ipq807x: fix kernel 5.15 cpufreq support

package/firmware/ipq-wifi/Makefile

@@ -57,6 +57,9 @@ ALLWIFIBOARDS:= \
 	p2w_r619ac \
 	qnap_301w \
 	qxwlan_e2600ac \
+	redmi_ax6 \
+	xiaomi_ax3600 \
+	xiaomi_ax9000 \
 	zte_mf263 \
 	zte_mf269 \
 	tplink_xtr10890
@@ -161,6 +164,9 @@ $(eval $(call generate-ipq-wifi-package,plasmacloud_pa2200,Plasma Cloud PA2200))
 $(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC))
 $(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w))
 $(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac,Qxwlan E2600AC))
+$(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6))
+$(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600))
+$(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000))
 $(eval $(call generate-ipq-wifi-package,zte_mf263,ZTE MF263))
 $(eval $(call generate-ipq-wifi-package,zte_mf269,ZTE MF269))
 $(eval $(call generate-ipq-wifi-package,tplink_xtr10890,TPLINK XTR10890))

target/linux/ipq807x/Makefile

@@ -16,7 +16,7 @@ DEFAULT_PACKAGES += \
 	kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
 	kmod-leds-gpio kmod-gpio-button-hotplug \
 	ath11k-firmware-ipq8074 kmod-ath11k-ahb \
-	autocore-arm htop wpad-openssl zram-swap uboot-envtools \
+	autocore-arm htop wpad-openssl uboot-envtools \
 	kmod-qca-nss-dp kmod-qca-nss-drv-64 \
 	kmod-qca-nss-drv-pppoe-64 kmod-qca-nss-ecm-64 \
 	kmod-qca-nss-drv-bridge-mgr-64 kmod-qca-nss-drv-vlan-mgr-64 \

target/linux/ipq807x/base-files/etc/board.d/01_leds

@@ -7,6 +7,10 @@ board=$(board_name)
 board_config_update
 
 case $board in
+xiaomi,ax3600|\
+redmi,ax6)
+	ucidef_set_led_netdev "wan" "WAN" "blue:network" "eth0"
+	;;
 qnap,301w)
 	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth0"
 	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth1"

target/linux/ipq807x/base-files/etc/board.d/02_network

@@ -14,6 +14,10 @@ ipq807x_setup_interfaces()
 	qnap,301w)
 		ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3 eth4" "eth5"
 		;;
+	redmi,ax6|\
+	xiaomi,ax3600)
+		ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0"
+		;;
 	zte,mf269)
 		ucidef_set_interfaces_lan_wan "eth0" "eth1"
 		;;

target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata

@@ -0,0 +1,20 @@
+#!/bin/sh
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions/caldata.sh
+
+board=$(board_name)
+
+case "$FIRMWARE" in
+"ath10k/cal-pci-0000:01:00.0.bin")
+	case "$board" in
+	xiaomi,ax3600)
+		caldata_extract "0:art" 0x33000 0x844
+		;;
+	esac
+	;;
+*)
+	exit 1
+	;;
+esac

target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata

@@ -9,7 +9,10 @@ board=$(board_name)
 case "$FIRMWARE" in
 "ath11k/IPQ8074/hw2.0/cal-ahb-c000000.wifi.bin")
 	case "$board" in
-	qnap,301w)
+	qnap,301w|\
+	redmi,ax6|\
+	xiaomi,ax3600|\
+	xiaomi,ax9000)
 		caldata_extract "0:art" 0x1000 0x20000
 		;;
 	zte,mf269)

target/linux/ipq807x/base-files/lib/upgrade/platform.sh

@@ -15,6 +15,34 @@ platform_do_upgrade() {
 		rootfsname="rootfs"
 		mmc_do_upgrade "$1"
 		;;
+	redmi,ax6|\
+	xiaomi,ax3600|\
+	xiaomi,ax9000)
+		part_num="$(fw_printenv -n flag_boot_rootfs)"
+		if [ "$part_num" -eq "1" ]; then
+			CI_UBIPART="rootfs_1"
+			target_num=1
+			# Reset fail flag for the current partition
+			# With both partition set to fail, the partition 2 (bit 1)
+			# is loaded
+			fw_setenv flag_try_sys2_failed 0
+		else
+			CI_UBIPART="rootfs"
+			target_num=0
+			# Reset fail flag for the current partition
+			# or uboot will skip the loading of this partition
+			fw_setenv flag_try_sys1_failed 0
+		fi
+
+		# Tell uboot to switch partition
+		fw_setenv flag_boot_rootfs $target_num
+		fw_setenv flag_last_success $target_num
+
+		# Reset success flag
+		fw_setenv flag_boot_success 0
+
+		nand_do_upgrade "$1"
+		;;
 	zte,mf269)
 		nand_do_upgrade "$1"
 		;;

target/linux/ipq807x/config-5.15

@@ -48,7 +48,6 @@ CONFIG_ARM_PSCI_CPUIDLE=y
 CONFIG_ARM_PSCI_FW=y
 # CONFIG_ARM_QCOM_CPUFREQ_HW is not set
 # CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
-CONFIG_ASN1=y
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BINARY_PRINTF=y
 CONFIG_BLK_DEV_LOOP=y
@@ -58,9 +57,7 @@ CONFIG_BLK_MQ_VIRTIO=y
 CONFIG_BLK_PM=y
 CONFIG_CAVIUM_TX2_ERRATUM_219=y
 CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLANG_VERSION=0
 CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
 CONFIG_COMMON_CLK=y
 CONFIG_COMMON_CLK_QCOM=y
 # CONFIG_COMPAT_32BIT_TIME is not set
@@ -87,27 +84,8 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_THERMAL=y
 CONFIG_CRC16=y
 CONFIG_CRC8=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
 CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLAKE2B=y
-CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20POLY1305=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_CURVE25519=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_DEV_QCE=y
 CONFIG_CRYPTO_DEV_QCE_AEAD=y
@@ -119,59 +97,17 @@ CONFIG_CRYPTO_DEV_QCE_SHA=y
 CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
 CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
 CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DH=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_ECDSA=y
-CONFIG_CRYPTO_ECRDSA=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
 CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_KEYWRAP=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
 CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
 CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_SM4=y
-CONFIG_CRYPTO_LRW=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_NHPOLY1305=y
-CONFIG_CRYPTO_NHPOLY1305_NEON=y
-CONFIG_CRYPTO_OFB=y
-CONFIG_CRYPTO_POLY1305=y
-CONFIG_CRYPTO_POLY1305_NEON=y
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
 CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
 CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA3=y
-CONFIG_CRYPTO_SHA3_ARM64=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA512_ARM64=y
-CONFIG_CRYPTO_SHA512_ARM64_CE=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_SM2=y
-CONFIG_CRYPTO_SM3=y
-CONFIG_CRYPTO_SM3_ARM64_CE=y
-CONFIG_CRYPTO_SM4_ARM64_CE=y
-CONFIG_CRYPTO_STREEBOG=y
 CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_XXHASH=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEV_COREDUMP=y
@@ -254,7 +190,6 @@ CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 # CONFIG_KPSS_XCC is not set
 CONFIG_LIBFDT=y
-CONFIG_LLD_VERSION=0
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_LTO_NONE=y
@@ -284,7 +219,6 @@ CONFIG_MMC_SDHCI_MSM=y
 # CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MPILIB=y
 # CONFIG_MSM_GCC_8660 is not set
 # CONFIG_MSM_GCC_8916 is not set
 # CONFIG_MSM_GCC_8939 is not set
@@ -315,6 +249,7 @@ CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SOCK_MSG=y
 CONFIG_NET_SWITCHDEV=y
 CONFIG_NLS=y
 CONFIG_NO_HZ_COMMON=y
@@ -332,7 +267,6 @@ CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
 CONFIG_PADATA=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCI=y
@@ -428,7 +362,6 @@ CONFIG_QCOM_Q6V5_COMMON=y
 # CONFIG_QCOM_Q6V5_PAS is not set
 CONFIG_QCOM_Q6V5_WCSS=y
 CONFIG_QCOM_QFPROM=y
-# CONFIG_QCOM_QMI_HELPERS is not set
 # CONFIG_QCOM_RMTFS_MEM is not set
 # CONFIG_QCOM_RPMH is not set
 CONFIG_QCOM_RPROC_COMMON=y
@@ -507,7 +440,6 @@ CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SGL_ALLOC=y
 CONFIG_SG_POOL=y
-# CONFIG_SHORTCUT_FE is not set
 CONFIG_SMP=y
 # CONFIG_SM_GCC_8150 is not set
 # CONFIG_SM_GCC_8250 is not set
@@ -558,7 +490,6 @@ CONFIG_VIRTIO=y
 CONFIG_VMAP_STACK=y
 CONFIG_WANT_DEV_COREDUMP=y
 CONFIG_WATCHDOG_CORE=y
-CONFIG_XOR_BLOCKS=y
 CONFIG_XPS=y
 CONFIG_XXHASH=y
 CONFIG_ZLIB_DEFLATE=y

target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+	model = "Xiaomi AX3600";
+	compatible = "xiaomi,ax3600", "qcom,ipq8074";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue: system-blue {
+			label = "blue:system";
+			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_yellow: system-yellow {
+			label = "yellow:system";
+			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-yellow {
+			label = "yellow:network";
+			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-blue {
+			label = "blue:network";
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		aiot {
+			label = "blue:aiot";
+			gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+};
+
+&qmp_pcie_phy0 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			status = "okay";
+
+			compatible = "qcom,ath10k";
+			reg = <0x00010000 0 0 0 0>;
+
+			qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
+		};
+	};
+};
+
+&wifi {
+	qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
+};

target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi

@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+#include "ipq8074.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ac-nss.dtsi"
+#include "ipq8074-memory-512m.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		led-boot = &led_system_yellow;
+		led-failsafe = &led_system_yellow;
+		led-running = &led_system_blue;
+		led-upgrade = &led_system_yellow;
+		/* Aliases as required by u-boot to patch MAC addresses */
+		ethernet1 = &dp2;
+		ethernet2 = &dp3;
+		ethernet3 = &dp4;
+		ethernet4 = &dp5;
+		label-mac-device = &dp2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_1";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	reserved-memory {
+		/delete-node/ tzapp@4a400000;
+		/delete-node/ q6_etr_dump@50f00000;
+		/delete-node/ m3_dump@51000000;
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "qcom,smem-part";
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	/*
+	 * Disable the reset GPIO temporarely as it
+	 * resets the 100Mbit LED configuration which
+	 * the bootloader writes.
+	 */
+	//reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	ethernet-phy@4 {
+		reg = <4>;
+	};
+};
+
+&ess_switch {
+	switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+	switch_lan_bmp = <0x1e>; /* lan port bitmap */
+	switch_wan_bmp = <0x20>; /* wan port bitmap */
+	switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+	switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+	switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+	bm_tick_mode = <0>; /* bm tick mode */
+	tm_tick_mode = <0>; /* tm tick mode */
+	qcom,port_phyinfo {
+		port@0 {
+			port_id = <1>;
+			phy_address = <0>;
+		};
+		port@1 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@2 {
+			port_id = <3>;
+			phy_address = <2>;
+		};
+		port@3 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@4 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+	};
+	port_scheduler_resource {
+		port@0 {
+			port_id = <0>;
+			ucast_queue = <0 143>;
+			mcast_queue = <256 271>;
+			l0sp = <0 35>;
+			l0cdrr = <0 47>;
+			l0edrr = <0 47>;
+			l1cdrr = <0 7>;
+			l1edrr = <0 7>;
+		};
+		port@1 {
+			port_id = <1>;
+			ucast_queue = <144 159>;
+			mcast_queue = <272 275>;
+			l0sp = <36 39>;
+			l0cdrr = <48 63>;
+			l0edrr = <48 63>;
+			l1cdrr = <8 11>;
+			l1edrr = <8 11>;
+		};
+		port@2 {
+			port_id = <2>;
+			ucast_queue = <160 175>;
+			mcast_queue = <276 279>;
+			l0sp = <40 43>;
+			l0cdrr = <64 79>;
+			l0edrr = <64 79>;
+			l1cdrr = <12 15>;
+			l1edrr = <12 15>;
+		};
+		port@3 {
+			port_id = <3>;
+			ucast_queue = <176 191>;
+			mcast_queue = <280 283>;
+			l0sp = <44 47>;
+			l0cdrr = <80 95>;
+			l0edrr = <80 95>;
+			l1cdrr = <16 19>;
+			l1edrr = <16 19>;
+		};
+		port@4 {
+			port_id = <4>;
+			ucast_queue = <192 207>;
+			mcast_queue = <284 287>;
+			l0sp = <48 51>;
+			l0cdrr = <96 111>;
+			l0edrr = <96 111>;
+			l1cdrr = <20 23>;
+			l1edrr = <20 23>;
+		};
+		port@5 {
+			port_id = <5>;
+			ucast_queue = <208 223>;
+			mcast_queue = <288 291>;
+			l0sp = <52 55>;
+			l0cdrr = <112 127>;
+			l0edrr = <112 127>;
+			l1cdrr = <24 27>;
+			l1edrr = <24 27>;
+		};
+		port@6 {
+			port_id = <6>;
+			ucast_queue = <224 239>;
+			mcast_queue = <292 295>;
+			l0sp = <56 59>;
+			l0cdrr = <128 143>;
+			l0edrr = <128 143>;
+			l1cdrr = <28 31>;
+			l1edrr = <28 31>;
+		};
+		port@7 {
+			port_id = <7>;
+			ucast_queue = <240 255>;
+			mcast_queue = <296 299>;
+			l0sp = <60 63>;
+			l0cdrr = <144 159>;
+			l0edrr = <144 159>;
+			l1cdrr = <32 35>;
+			l1edrr = <32 35>;
+		};
+	};
+	port_scheduler_config {
+		port@0 {
+			port_id = <0>;
+			l1scheduler {
+				group@0 {
+					sp = <0 1>; /*L0 SPs*/
+					/*cpri cdrr epri edrr*/
+					cfg = <0 0 0 0>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					/*unicast queues*/
+					ucast_queue = <0 4 8>;
+					/*multicast queues*/
+					mcast_queue = <256 260>;
+					/*sp cpri cdrr epri edrr*/
+					cfg = <0 0 0 0 0>;
+				};
+				group@1 {
+					ucast_queue = <1 5 9>;
+					mcast_queue = <257 261>;
+					cfg = <0 1 1 1 1>;
+				};
+				group@2 {
+					ucast_queue = <2 6 10>;
+					mcast_queue = <258 262>;
+					cfg = <0 2 2 2 2>;
+				};
+				group@3 {
+					ucast_queue = <3 7 11>;
+					mcast_queue = <259 263>;
+					cfg = <0 3 3 3 3>;
+				};
+			};
+		};
+		port@1 {
+			port_id = <1>;
+			l1scheduler {
+				group@0 {
+					sp = <36>;
+					cfg = <0 8 0 8>;
+				};
+				group@1 {
+					sp = <37>;
+					cfg = <1 9 1 9>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <144>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <272>;
+					mcast_loop_pri = <4>;
+					cfg = <36 0 48 0 48>;
+				};
+			};
+		};
+		port@2 {
+			port_id = <2>;
+			l1scheduler {
+				group@0 {
+					sp = <40>;
+					cfg = <0 12 0 12>;
+				};
+				group@1 {
+					sp = <41>;
+					cfg = <1 13 1 13>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <160>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <276>;
+					mcast_loop_pri = <4>;
+					cfg = <40 0 64 0 64>;
+				};
+			};
+		};
+		port@3 {
+			port_id = <3>;
+			l1scheduler {
+				group@0 {
+					sp = <44>;
+					cfg = <0 16 0 16>;
+				};
+				group@1 {
+					sp = <45>;
+					cfg = <1 17 1 17>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <176>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <280>;
+					mcast_loop_pri = <4>;
+					cfg = <44 0 80 0 80>;
+				};
+			};
+		};
+		port@4 {
+			port_id = <4>;
+			l1scheduler {
+				group@0 {
+					sp = <48>;
+					cfg = <0 20 0 20>;
+				};
+				group@1 {
+					sp = <49>;
+					cfg = <1 21 1 21>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <192>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <284>;
+					mcast_loop_pri = <4>;
+					cfg = <48 0 96 0 96>;
+				};
+			};
+		};
+		port@5 {
+			port_id = <5>;
+			l1scheduler {
+				group@0 {
+					sp = <52>;
+					cfg = <0 24 0 24>;
+				};
+				group@1 {
+					sp = <53>;
+					cfg = <1 25 1 25>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <208>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <288>;
+					mcast_loop_pri = <4>;
+					cfg = <52 0 112 0 112>;
+				};
+			};
+		};
+		port@6 {
+			port_id = <6>;
+			l1scheduler {
+				group@0 {
+					sp = <56>;
+					cfg = <0 28 0 28>;
+				};
+				group@1 {
+					sp = <57>;
+					cfg = <1 29 1 29>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <224>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <292>;
+					mcast_loop_pri = <4>;
+					cfg = <56 0 128 0 128>;
+				};
+			};
+		};
+		port@7 {
+			port_id = <7>;
+			l1scheduler {
+				group@0 {
+					sp = <60>;
+					cfg = <0 32 0 32>;
+				};
+				group@1 {
+					sp = <61>;
+					cfg = <1 33 1 33>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <240>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <296>;
+					cfg = <60 0 144 0 144>;
+				};
+			};
+		};
+	};
+};
+
+&soc {
+	dp2: dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <1>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp3: dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <2>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp4: dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <3>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp5: dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a001800 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <4>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,board_id = <658>;
+};

target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+	model = "Redmi AX6";
+	compatible = "redmi,ax6", "qcom,ipq8074";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue: system-blue {
+			label = "blue:system";
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_yellow: system-yellow {
+			label = "yellow:system";
+			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-blue {
+			label = "blue:network";
+			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-yellow {
+			label = "yellow:network";
+			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&wifi {
+	qcom,ath11k-calibration-variant = "Redmi-AX6";
+};

target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+	model = "Xiaomi AX3600";
+	compatible = "xiaomi,ax3600", "qcom,ipq8074";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue: system-blue {
+			label = "blue:system";
+			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_yellow: system-yellow {
+			label = "yellow:system";
+			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-yellow {
+			label = "yellow:network";
+			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-blue {
+			label = "blue:network";
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		aiot {
+			label = "blue:aiot";
+			gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+};
+
+&pcie_qmp0 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			status = "okay";
+
+			compatible = "qcom,ath10k";
+			reg = <0x00010000 0 0 0 0>;
+
+			qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
+		};
+	};
+};
+
+&wifi {
+	qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
+};

target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi

@@ -0,0 +1,494 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		led-boot = &led_system_yellow;
+		led-failsafe = &led_system_yellow;
+		led-running = &led_system_blue;
+		led-upgrade = &led_system_yellow;
+		/* Aliases as required by u-boot to patch MAC addresses */
+		ethernet1 = &dp2;
+		ethernet2 = &dp3;
+		ethernet3 = &dp4;
+		ethernet4 = &dp5;
+		label-mac-device = &dp2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_1";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "qcom,smem-part";
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	ethernet-phy@4 {
+		reg = <4>;
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+	switch_lan_bmp = <0x1e>; /* lan port bitmap */
+	switch_wan_bmp = <0x20>; /* wan port bitmap */
+	switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+	switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+	switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+	bm_tick_mode = <0>; /* bm tick mode */
+	tm_tick_mode = <0>; /* tm tick mode */
+
+	qcom,port_phyinfo {
+		port@0 {
+			port_id = <1>;
+			phy_address = <0>;
+		};
+		port@1 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@2 {
+			port_id = <3>;
+			phy_address = <2>;
+		};
+		port@3 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@4 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+	};
+
+	port_scheduler_resource {
+		port@0 {
+			port_id = <0>;
+			ucast_queue = <0 143>;
+			mcast_queue = <256 271>;
+			l0sp = <0 35>;
+			l0cdrr = <0 47>;
+			l0edrr = <0 47>;
+			l1cdrr = <0 7>;
+			l1edrr = <0 7>;
+		};
+		port@1 {
+			port_id = <1>;
+			ucast_queue = <144 159>;
+			mcast_queue = <272 275>;
+			l0sp = <36 39>;
+			l0cdrr = <48 63>;
+			l0edrr = <48 63>;
+			l1cdrr = <8 11>;
+			l1edrr = <8 11>;
+		};
+		port@2 {
+			port_id = <2>;
+			ucast_queue = <160 175>;
+			mcast_queue = <276 279>;
+			l0sp = <40 43>;
+			l0cdrr = <64 79>;
+			l0edrr = <64 79>;
+			l1cdrr = <12 15>;
+			l1edrr = <12 15>;
+		};
+		port@3 {
+			port_id = <3>;
+			ucast_queue = <176 191>;
+			mcast_queue = <280 283>;
+			l0sp = <44 47>;
+			l0cdrr = <80 95>;
+			l0edrr = <80 95>;
+			l1cdrr = <16 19>;
+			l1edrr = <16 19>;
+		};
+		port@4 {
+			port_id = <4>;
+			ucast_queue = <192 207>;
+			mcast_queue = <284 287>;
+			l0sp = <48 51>;
+			l0cdrr = <96 111>;
+			l0edrr = <96 111>;
+			l1cdrr = <20 23>;
+			l1edrr = <20 23>;
+		};
+		port@5 {
+			port_id = <5>;
+			ucast_queue = <208 223>;
+			mcast_queue = <288 291>;
+			l0sp = <52 55>;
+			l0cdrr = <112 127>;
+			l0edrr = <112 127>;
+			l1cdrr = <24 27>;
+			l1edrr = <24 27>;
+		};
+		port@6 {
+			port_id = <6>;
+			ucast_queue = <224 239>;
+			mcast_queue = <292 295>;
+			l0sp = <56 59>;
+			l0cdrr = <128 143>;
+			l0edrr = <128 143>;
+			l1cdrr = <28 31>;
+			l1edrr = <28 31>;
+		};
+		port@7 {
+			port_id = <7>;
+			ucast_queue = <240 255>;
+			mcast_queue = <296 299>;
+			l0sp = <60 63>;
+			l0cdrr = <144 159>;
+			l0edrr = <144 159>;
+			l1cdrr = <32 35>;
+			l1edrr = <32 35>;
+		};
+	};
+	port_scheduler_config {
+		port@0 {
+			port_id = <0>;
+			l1scheduler {
+				group@0 {
+					sp = <0 1>; /*L0 SPs*/
+					/*cpri cdrr epri edrr*/
+					cfg = <0 0 0 0>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					/*unicast queues*/
+					ucast_queue = <0 4 8>;
+					/*multicast queues*/
+					mcast_queue = <256 260>;
+					/*sp cpri cdrr epri edrr*/
+					cfg = <0 0 0 0 0>;
+				};
+				group@1 {
+					ucast_queue = <1 5 9>;
+					mcast_queue = <257 261>;
+					cfg = <0 1 1 1 1>;
+				};
+				group@2 {
+					ucast_queue = <2 6 10>;
+					mcast_queue = <258 262>;
+					cfg = <0 2 2 2 2>;
+				};
+				group@3 {
+					ucast_queue = <3 7 11>;
+					mcast_queue = <259 263>;
+					cfg = <0 3 3 3 3>;
+				};
+			};
+		};
+		port@1 {
+			port_id = <1>;
+			l1scheduler {
+				group@0 {
+					sp = <36>;
+					cfg = <0 8 0 8>;
+				};
+				group@1 {
+					sp = <37>;
+					cfg = <1 9 1 9>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <144>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <272>;
+					mcast_loop_pri = <4>;
+					cfg = <36 0 48 0 48>;
+				};
+			};
+		};
+		port@2 {
+			port_id = <2>;
+			l1scheduler {
+				group@0 {
+					sp = <40>;
+					cfg = <0 12 0 12>;
+				};
+				group@1 {
+					sp = <41>;
+					cfg = <1 13 1 13>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <160>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <276>;
+					mcast_loop_pri = <4>;
+					cfg = <40 0 64 0 64>;
+				};
+			};
+		};
+		port@3 {
+			port_id = <3>;
+			l1scheduler {
+				group@0 {
+					sp = <44>;
+					cfg = <0 16 0 16>;
+				};
+				group@1 {
+					sp = <45>;
+					cfg = <1 17 1 17>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <176>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <280>;
+					mcast_loop_pri = <4>;
+					cfg = <44 0 80 0 80>;
+				};
+			};
+		};
+		port@4 {
+			port_id = <4>;
+			l1scheduler {
+				group@0 {
+					sp = <48>;
+					cfg = <0 20 0 20>;
+				};
+				group@1 {
+					sp = <49>;
+					cfg = <1 21 1 21>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <192>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <284>;
+					mcast_loop_pri = <4>;
+					cfg = <48 0 96 0 96>;
+				};
+			};
+		};
+		port@5 {
+			port_id = <5>;
+			l1scheduler {
+				group@0 {
+					sp = <52>;
+					cfg = <0 24 0 24>;
+				};
+				group@1 {
+					sp = <53>;
+					cfg = <1 25 1 25>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <208>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <288>;
+					mcast_loop_pri = <4>;
+					cfg = <52 0 112 0 112>;
+				};
+			};
+		};
+		port@6 {
+			port_id = <6>;
+			l1scheduler {
+				group@0 {
+					sp = <56>;
+					cfg = <0 28 0 28>;
+				};
+				group@1 {
+					sp = <57>;
+					cfg = <1 29 1 29>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <224>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <292>;
+					mcast_loop_pri = <4>;
+					cfg = <56 0 128 0 128>;
+				};
+			};
+		};
+		port@7 {
+			port_id = <7>;
+			l1scheduler {
+				group@0 {
+					sp = <60>;
+					cfg = <0 32 0 32>;
+				};
+				group@1 {
+					sp = <61>;
+					cfg = <1 33 1 33>;
+				};
+			};
+			l0scheduler {
+				group@0 {
+					ucast_queue = <240>;
+					ucast_loop_pri = <16>;
+					mcast_queue = <296>;
+					cfg = <60 0 144 0 144>;
+				};
+			};
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+&soc {
+	dp2: dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <1>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp3: dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <2>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp4: dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <3>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp5: dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a001800 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <4>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,board_id = <658>;
+};

target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+	model = "Redmi AX6";
+	compatible = "redmi,ax6", "qcom,ipq8074";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_system_blue: system-blue {
+			label = "blue:system";
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_yellow: system-yellow {
+			label = "yellow:system";
+			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-blue {
+			label = "blue:network";
+			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+		};
+
+		network-yellow {
+			label = "yellow:network";
+			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&wifi {
+	qcom,ath11k-calibration-variant = "Redmi-AX6";
+};

target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts

@@ -11,8 +11,12 @@
 #include <dt-bindings/leds/common.h>
 
 / {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
 	model = "QNAP 301w";
 	compatible = "qnap,301w", "qcom,ipq8074";
+	interrupt-parent = <&intc>;
 
 	aliases {
 		serial0 = &blsp1_uart5;
@@ -363,46 +367,46 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	aqr113c_0: ethernet-phy@0 {
+	ethernet-phy@0 {
 		compatible ="ethernet-phy-ieee802.3-c45";
 		reg = <0>;
 		reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
 	};
 
-	aqr113c_8: ethernet-phy@8 {
+	ethernet-phy@8 {
 		compatible ="ethernet-phy-ieee802.3-c45";
 		reg = <8>;
 		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
 	};
 
-	qca8075_16: ethernet-phy@16 {
+	ethernet-phy@16 {
 		reg = <16>;
 	};
 
-	qca8075_17: ethernet-phy@17 {
+	ethernet-phy@17 {
 		reg = <17>;
 	};
 
-	qca8075_18: ethernet-phy@18 {
+	ethernet-phy@18 {
 		reg = <18>;
 	};
 
-	qca8075_19: ethernet-phy@19 {
+	ethernet-phy@19 {
 		reg = <19>;
 	};
+
 };
 
 &sdhc_1 {
-	status = "okay";
+		/* According to the stock dts from the QNAP gpl drop
-
+		 * the emmc has a problem with the hs400 > hs200 speed switch.
-	/* According to the stock dts from the QNAP gpl drop
+		 * Therefore remove the mmc-hs400-1_8v property
-	 * the emmc has a problem with the hs400 > hs200 speed switch.
+		*/
-	 * Therefore remove the mmc-hs400-1_8v property
+		/delete-property/ mmc-hs400-1_8v;
-	*/
+		mmc-hs200-1_8v;
-	/delete-property/ mmc-hs400-1_8v;
+		mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
+		vqmmc-supply = <&ldo11>;
-	mmc-ddr-1_8v;
+		status = "okay";
-	vqmmc-supply = <&l11>;
 };
 
 &switch {
@@ -734,8 +738,10 @@
 		reg = <0x3a001000 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-handle = <&qca8075_16>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <16>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	dp2: dp2 {
@@ -745,8 +751,10 @@
 		reg = <0x3a001200 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-handle = <&qca8075_17>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <17>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	dp3: dp3 {
@@ -756,8 +764,10 @@
 		reg = <0x3a001400 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-handle = <&qca8075_18>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <18>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	dp4: dp4 {
@@ -767,8 +777,10 @@
 		reg = <0x3a001600 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-handle = <&qca8075_19>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <19>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	dp5: dp5 {
@@ -778,8 +790,10 @@
 		reg = <0x3a001800 0x200>;
 		qcom,mactype = <1>;
 		local-mac-address = [000000000000];
-		phy-handle = <&aqr113c_8>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <8>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	dp6: dp6 {
@@ -789,13 +803,18 @@
 		reg = <0x3a007000 0x3fff>;
 		qcom,mactype = <1>;
 		local-mac-address = [000000000000];
-		phy-handle = <&aqr113c_0>;
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 };
 
 &wifi {
 	status = "okay";
-	
+	/* using board_id 0xff is intentionally
+	 * as the stock firmware is also using this default board_id
+	 */
+	qcom,board_id = <0xff>;
 	qcom,ath11k-calibration-variant = "QNAP-301w";
 };

target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi

@@ -1,7 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
-#include "pmp8074.dtsi"
-
 &soc {
 	apc_apm: apm@b111000 {
 		compatible = "qcom,ipq807x-apm";

target/linux/ipq807x/files-5.15/drivers/power/qcom/Kconfig

@@ -0,0 +1,7 @@
+config QCOM_APM
+       bool "Qualcomm Technologies Inc platform specific APM driver"
+       help
+	Platform specific driver to manage the power source of
+	memory arrays. Interfaces with regulator drivers to ensure
+	SRAM Vmin requirements are met across different performance
+	levels.

target/linux/ipq807x/files-5.15/drivers/power/qcom/Makefile

@@ -0,0 +1 @@
+obj-$(CONFIG_QCOM_APM)		+= apm.o

target/linux/ipq807x/files-5.15/drivers/power/qcom/apm.c

@@ -0,0 +1,944 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/power/qcom/apm.h>
+
+/*
+ *        VDD_APCC
+ * =============================================================
+ *       |      VDD_MX                  |                    |
+ *       |    ==========================|=============       |
+ *    ___|___   ___|___    ___|___   ___|___    ___|___   ___|___
+ *   |       | |       |  |       | |       |  |       | |       |
+ *   | APCC  | | MX HS |  | MX HS | | APCC  |  | MX HS | | APCC  |
+ *   |  HS   | |       |  |       | |  HS   |  |       | |  HS   |
+ *   |_______| |_______|  |_______| |_______|  |_______| |_______|
+ *       |_________|          |_________|         |__________|
+ *            |                    |                    |
+ *      ______|_____         ______|_____        _______|_____
+ *     |            |       |            |      |             |
+ *     |            |       |            |      |             |
+ *     |  CPU MEM   |       |   L2 MEM   |      |    L3 MEM   |
+ *     |   Arrays   |       |   Arrays   |      |    Arrays   |
+ *     |            |       |            |      |             |
+ *     |____________|       |____________|      |_____________|
+ *
+ */
+
+/* Register value definitions */
+#define APCS_GFMUXA_SEL_VAL            0x13
+#define APCS_GFMUXA_DESEL_VAL          0x03
+#define MSM_APM_MX_MODE_VAL            0x00
+#define MSM_APM_APCC_MODE_VAL          0x10
+#define MSM_APM_MX_DONE_VAL            0x00
+#define MSM_APM_APCC_DONE_VAL          0x03
+#define MSM_APM_OVERRIDE_SEL_VAL       0xb0
+#define MSM_APM_SEC_CLK_SEL_VAL        0x30
+#define SPM_EVENT_SET_VAL              0x01
+#define SPM_EVENT_CLEAR_VAL            0x00
+
+/* Register bit mask definitions */
+#define MSM_APM_CTL_STS_MASK            0x0f
+
+/* Register offset definitions */
+#define APCC_APM_MODE              0x00000098
+#define APCC_APM_CTL_STS           0x000000a8
+#define APCS_SPARE                 0x00000068
+#define APCS_VERSION               0x00000fd0
+
+#define HMSS_VERSION_1P2           0x10020000
+
+#define MSM_APM_SWITCH_TIMEOUT_US  10
+#define SPM_WAKEUP_DELAY_US        2
+#define SPM_EVENT_NUM              6
+
+#define MSM_APM_DRIVER_NAME        "qcom,msm-apm"
+
+enum {
+	MSM8996_ID,
+	MSM8953_ID,
+	IPQ807x_ID,
+};
+
+struct msm_apm_ctrl_dev {
+	struct list_head	list;
+	struct device		*dev;
+	enum msm_apm_supply	supply;
+	spinlock_t		lock;
+	void __iomem		*reg_base;
+	void __iomem		*apcs_csr_base;
+	void __iomem		**apcs_spm_events_addr;
+	void __iomem		*apc0_pll_ctl_addr;
+	void __iomem		*apc1_pll_ctl_addr;
+	u32			version;
+	struct dentry		*debugfs;
+	u32			msm_id;
+};
+
+#if defined(CONFIG_DEBUG_FS)
+static struct dentry *apm_debugfs_base;
+#endif
+
+static DEFINE_MUTEX(apm_ctrl_list_mutex);
+static LIST_HEAD(apm_ctrl_list);
+
+/*
+ * Get the resources associated with the APM controller from device tree
+ * and remap all I/O addresses that are relevant to this HW revision.
+ */
+static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
+				     struct msm_apm_ctrl_dev *ctrl)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	static const char *res_name[SPM_EVENT_NUM] = {
+		"apc0-l2-spm",
+		"apc1-l2-spm",
+		"apc0-cpu0-spm",
+		"apc0-cpu1-spm",
+		"apc1-cpu0-spm",
+		"apc1-cpu1-spm"
+	};
+	int i, ret = 0;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
+	if (!res) {
+		dev_err(dev, "Missing PM APCC Global register physical address");
+		return -EINVAL;
+	}
+	ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!ctrl->reg_base) {
+		dev_err(dev, "Failed to map PM APCC Global registers\n");
+		return -ENOMEM;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
+	if (!res) {
+		dev_err(dev, "Missing APCS CSR physical base address");
+		return -EINVAL;
+	}
+	ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!ctrl->apcs_csr_base) {
+		dev_err(dev, "Failed to map APCS CSR registers\n");
+		return -ENOMEM;
+	}
+
+	ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
+
+	if (ctrl->version >= HMSS_VERSION_1P2)
+		return ret;
+
+	ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
+						  SPM_EVENT_NUM
+						  * sizeof(void __iomem *),
+						  GFP_KERNEL);
+	if (!ctrl->apcs_spm_events_addr) {
+		dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < SPM_EVENT_NUM; i++) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+						   res_name[i]);
+		if (!res) {
+			dev_err(dev, "Missing address for %s\n", res_name[i]);
+			ret = -EINVAL;
+			goto free_events;
+		}
+
+		ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
+						resource_size(res));
+		if (!ctrl->apcs_spm_events_addr[i]) {
+			dev_err(dev, "Failed to map %s\n", res_name[i]);
+			ret = -ENOMEM;
+			goto free_events;
+		}
+
+		dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
+			&res->start, ctrl->apcs_spm_events_addr[i]);
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "apc0-pll-ctl");
+	if (!res) {
+		dev_err(dev, "Missing APC0 PLL CTL physical address\n");
+		ret = -EINVAL;
+		goto free_events;
+	}
+
+	ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
+					   res->start,
+					   resource_size(res));
+	if (!ctrl->apc0_pll_ctl_addr) {
+		dev_err(dev, "Failed to map APC0 PLL CTL register\n");
+		ret = -ENOMEM;
+		goto free_events;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "apc1-pll-ctl");
+	if (!res) {
+		dev_err(dev, "Missing APC1 PLL CTL physical address\n");
+		ret = -EINVAL;
+		goto free_events;
+	}
+
+	ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
+					   res->start,
+					   resource_size(res));
+	if (!ctrl->apc1_pll_ctl_addr) {
+		dev_err(dev, "Failed to map APC1 PLL CTL register\n");
+		ret = -ENOMEM;
+		goto free_events;
+	}
+
+	return ret;
+
+free_events:
+	devm_kfree(dev, ctrl->apcs_spm_events_addr);
+	return ret;
+}
+
+/* 8953 register offset definition */
+#define MSM8953_APM_DLY_CNTR	0x2ac
+
+/* Register field shift definitions */
+#define APM_CTL_SEL_SWITCH_DLY_SHIFT	0
+#define APM_CTL_RESUME_CLK_DLY_SHIFT	8
+#define APM_CTL_HALT_CLK_DLY_SHIFT	16
+#define APM_CTL_POST_HALT_DLY_SHIFT	24
+
+/* Register field mask definitions */
+#define APM_CTL_SEL_SWITCH_DLY_MASK	GENMASK(7, 0)
+#define APM_CTL_RESUME_CLK_DLY_MASK	GENMASK(15, 8)
+#define APM_CTL_HALT_CLK_DLY_MASK	GENMASK(23, 16)
+#define APM_CTL_POST_HALT_DLY_MASK	GENMASK(31, 24)
+
+/*
+ * Get the resources associated with the msm8953 APM controller from
+ * device tree, remap all I/O addresses, and program the initial
+ * register configuration required for the 8953 APM controller device.
+ */
+static int msm8953_apm_ctrl_init(struct platform_device *pdev,
+				     struct msm_apm_ctrl_dev *ctrl)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	u32 delay_counter, val = 0, regval = 0;
+	int rc = 0;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
+	if (!res) {
+		dev_err(dev, "Missing PM APCC Global register physical address\n");
+		return -ENODEV;
+	}
+	ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!ctrl->reg_base) {
+		dev_err(dev, "Failed to map PM APCC Global registers\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Initial APM register configuration required before starting
+	 * APM HW controller.
+	 */
+	regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR);
+	val = regval;
+
+	if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) {
+		rc = of_property_read_u32(dev->of_node,
+				"qcom,apm-post-halt-delay", &delay_counter);
+		if (rc < 0) {
+			dev_err(dev, "apm-post-halt-delay read failed, rc = %d",
+				rc);
+			return rc;
+		}
+
+		val &= ~APM_CTL_POST_HALT_DLY_MASK;
+		val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT)
+			& APM_CTL_POST_HALT_DLY_MASK;
+	}
+
+	if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) {
+		rc = of_property_read_u32(dev->of_node,
+				"qcom,apm-halt-clk-delay", &delay_counter);
+		if (rc < 0) {
+			dev_err(dev, "apm-halt-clk-delay read failed, rc = %d",
+				rc);
+			return rc;
+		}
+
+		val &= ~APM_CTL_HALT_CLK_DLY_MASK;
+		val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT)
+			& APM_CTL_HALT_CLK_DLY_MASK;
+	}
+
+	if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) {
+		rc = of_property_read_u32(dev->of_node,
+				"qcom,apm-resume-clk-delay", &delay_counter);
+		if (rc < 0) {
+			dev_err(dev, "apm-resume-clk-delay read failed, rc = %d",
+				rc);
+			return rc;
+		}
+
+		val &= ~APM_CTL_RESUME_CLK_DLY_MASK;
+		val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT)
+			& APM_CTL_RESUME_CLK_DLY_MASK;
+	}
+
+	if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) {
+		rc = of_property_read_u32(dev->of_node,
+				"qcom,apm-sel-switch-delay", &delay_counter);
+		if (rc < 0) {
+			dev_err(dev, "apm-sel-switch-delay read failed, rc = %d",
+				rc);
+			return rc;
+		}
+
+		val &= ~APM_CTL_SEL_SWITCH_DLY_MASK;
+		val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT)
+			& APM_CTL_SEL_SWITCH_DLY_MASK;
+	}
+
+	if (val != regval) {
+		writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR);
+		/* make sure write completes before return */
+		mb();
+	}
+
+	return rc;
+}
+
+static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
+	u32 regval;
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctrl_dev->lock, flags);
+
+	/* Perform revision-specific programming steps */
+	if (ctrl_dev->version < HMSS_VERSION_1P2) {
+		/* Clear SPM events */
+		for (i = 0; i < SPM_EVENT_NUM; i++)
+			writel_relaxed(SPM_EVENT_CLEAR_VAL,
+				       ctrl_dev->apcs_spm_events_addr[i]);
+
+		udelay(SPM_WAKEUP_DELAY_US);
+
+		/* Switch APC/CBF to GPLL0 clock */
+		writel_relaxed(APCS_GFMUXA_SEL_VAL,
+			       ctrl_dev->apcs_csr_base + APCS_SPARE);
+		ndelay(200);
+		writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
+			       ctrl_dev->apc0_pll_ctl_addr);
+		ndelay(200);
+		writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
+			       ctrl_dev->apc1_pll_ctl_addr);
+
+		/* Ensure writes complete before proceeding */
+		mb();
+	}
+
+	/* Switch arrays to MX supply and wait for its completion */
+	writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
+		       APCC_APM_MODE);
+
+	/* Ensure write above completes before delaying */
+	mb();
+
+	while (timeout > 0) {
+		regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
+		if ((regval & MSM_APM_CTL_STS_MASK) ==
+		    MSM_APM_MX_DONE_VAL)
+			break;
+
+		udelay(1);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		ret = -ETIMEDOUT;
+		dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
+			regval);
+	}
+
+	/* Perform revision-specific programming steps */
+	if (ctrl_dev->version < HMSS_VERSION_1P2) {
+		/* Switch APC/CBF clocks to original source */
+		writel_relaxed(APCS_GFMUXA_DESEL_VAL,
+			       ctrl_dev->apcs_csr_base + APCS_SPARE);
+		ndelay(200);
+		writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
+			       ctrl_dev->apc0_pll_ctl_addr);
+		ndelay(200);
+		writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
+			       ctrl_dev->apc1_pll_ctl_addr);
+
+		/* Complete clock source switch before SPM event sequence */
+		mb();
+
+		/* Set SPM events */
+		for (i = 0; i < SPM_EVENT_NUM; i++)
+			writel_relaxed(SPM_EVENT_SET_VAL,
+				       ctrl_dev->apcs_spm_events_addr[i]);
+	}
+
+	if (!ret) {
+		ctrl_dev->supply = MSM_APM_SUPPLY_MX;
+		dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
+	}
+
+	spin_unlock_irqrestore(&ctrl_dev->lock, flags);
+
+	return ret;
+}
+
+static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
+	u32 regval;
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctrl_dev->lock, flags);
+
+	/* Perform revision-specific programming steps */
+	if (ctrl_dev->version < HMSS_VERSION_1P2) {
+		/* Clear SPM events */
+		for (i = 0; i < SPM_EVENT_NUM; i++)
+			writel_relaxed(SPM_EVENT_CLEAR_VAL,
+				       ctrl_dev->apcs_spm_events_addr[i]);
+
+		udelay(SPM_WAKEUP_DELAY_US);
+
+		/* Switch APC/CBF to GPLL0 clock */
+		writel_relaxed(APCS_GFMUXA_SEL_VAL,
+			       ctrl_dev->apcs_csr_base + APCS_SPARE);
+		ndelay(200);
+		writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
+			       ctrl_dev->apc0_pll_ctl_addr);
+		ndelay(200);
+		writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
+			       ctrl_dev->apc1_pll_ctl_addr);
+
+		/* Ensure previous writes complete before proceeding */
+		mb();
+	}
+
+	/* Switch arrays to APCC supply and wait for its completion */
+	writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
+		       APCC_APM_MODE);
+
+	/* Ensure write above completes before delaying */
+	mb();
+
+	while (timeout > 0) {
+		regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
+		if ((regval & MSM_APM_CTL_STS_MASK) ==
+		    MSM_APM_APCC_DONE_VAL)
+			break;
+
+		udelay(1);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		ret = -ETIMEDOUT;
+		dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
+			regval);
+	}
+
+	/* Perform revision-specific programming steps */
+	if (ctrl_dev->version < HMSS_VERSION_1P2) {
+		/* Set SPM events */
+		for (i = 0; i < SPM_EVENT_NUM; i++)
+			writel_relaxed(SPM_EVENT_SET_VAL,
+				       ctrl_dev->apcs_spm_events_addr[i]);
+
+		/* Complete SPM event sequence before clock source switch */
+		mb();
+
+		/* Switch APC/CBF clocks to original source */
+		writel_relaxed(APCS_GFMUXA_DESEL_VAL,
+			       ctrl_dev->apcs_csr_base + APCS_SPARE);
+		ndelay(200);
+		writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
+			       ctrl_dev->apc0_pll_ctl_addr);
+		ndelay(200);
+		writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
+			       ctrl_dev->apc1_pll_ctl_addr);
+	}
+
+	if (!ret) {
+		ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
+		dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
+	}
+
+	spin_unlock_irqrestore(&ctrl_dev->lock, flags);
+
+	return ret;
+}
+
+/* 8953 register value definitions */
+#define MSM8953_APM_MX_MODE_VAL            0x00
+#define MSM8953_APM_APCC_MODE_VAL          0x02
+#define MSM8953_APM_MX_DONE_VAL            0x00
+#define MSM8953_APM_APCC_DONE_VAL          0x03
+
+/* 8953 register offset definitions */
+#define MSM8953_APCC_APM_MODE              0x000002a8
+#define MSM8953_APCC_APM_CTL_STS           0x000002b0
+
+/* 8953 constants */
+#define MSM8953_APM_SWITCH_TIMEOUT_US      500
+
+/* Register bit mask definitions */
+#define MSM8953_APM_CTL_STS_MASK           0x1f
+
+static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
+	u32 regval;
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctrl_dev->lock, flags);
+
+	/* Switch arrays to MX supply and wait for its completion */
+	writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base +
+		       MSM8953_APCC_APM_MODE);
+
+	/* Ensure write above completes before delaying */
+	mb();
+
+	while (timeout > 0) {
+		regval = readl_relaxed(ctrl_dev->reg_base +
+					MSM8953_APCC_APM_CTL_STS);
+		if ((regval & MSM8953_APM_CTL_STS_MASK) ==
+				MSM8953_APM_MX_DONE_VAL)
+			break;
+
+		udelay(1);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		ret = -ETIMEDOUT;
+		dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
+			regval);
+	} else {
+		ctrl_dev->supply = MSM_APM_SUPPLY_MX;
+		dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
+	}
+
+	spin_unlock_irqrestore(&ctrl_dev->lock, flags);
+
+	return ret;
+}
+
+static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
+	u32 regval;
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctrl_dev->lock, flags);
+
+	/* Switch arrays to APCC supply and wait for its completion */
+	writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
+		       MSM8953_APCC_APM_MODE);
+
+	/* Ensure write above completes before delaying */
+	mb();
+
+	while (timeout > 0) {
+		regval = readl_relaxed(ctrl_dev->reg_base +
+					MSM8953_APCC_APM_CTL_STS);
+		if ((regval & MSM8953_APM_CTL_STS_MASK) ==
+				MSM8953_APM_APCC_DONE_VAL)
+			break;
+
+		udelay(1);
+		timeout--;
+	}
+
+	if (timeout == 0) {
+		ret = -ETIMEDOUT;
+		dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
+			regval);
+	} else {
+		ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
+		dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
+	}
+
+	spin_unlock_irqrestore(&ctrl_dev->lock, flags);
+
+	return ret;
+}
+
+static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int ret = 0;
+
+	switch (ctrl_dev->msm_id) {
+	case MSM8996_ID:
+		ret = msm8996_apm_switch_to_mx(ctrl_dev);
+		break;
+	case MSM8953_ID:
+	case IPQ807x_ID:
+		ret = msm8953_apm_switch_to_mx(ctrl_dev);
+		break;
+	}
+
+	return ret;
+}
+
+static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	int ret = 0;
+
+	switch (ctrl_dev->msm_id) {
+	case MSM8996_ID:
+		ret = msm8996_apm_switch_to_apcc(ctrl_dev);
+		break;
+	case MSM8953_ID:
+	case IPQ807x_ID:
+		ret = msm8953_apm_switch_to_apcc(ctrl_dev);
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * msm_apm_get_supply() - Returns the supply that is currently
+ *			powering the memory arrays
+ * @ctrl_dev:                   Pointer to an MSM APM controller device
+ *
+ * Returns the supply currently selected by the APM.
+ */
+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	return ctrl_dev->supply;
+}
+EXPORT_SYMBOL(msm_apm_get_supply);
+
+/**
+ * msm_apm_set_supply() - Perform the necessary steps to switch the voltage
+ *                        source of the memory arrays to a given supply
+ * @ctrl_dev:                   Pointer to an MSM APM controller device
+ * @supply:                     Power rail to use as supply for the memory
+ *                              arrays
+ *
+ * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
+ * the supply is not supported.
+ */
+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
+		       enum msm_apm_supply supply)
+{
+	int ret;
+
+	switch (supply) {
+	case MSM_APM_SUPPLY_APCC:
+		ret = msm_apm_switch_to_apcc(ctrl_dev);
+		break;
+	case MSM_APM_SUPPLY_MX:
+		ret = msm_apm_switch_to_mx(ctrl_dev);
+		break;
+	default:
+		ret = -EPERM;
+		break;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(msm_apm_set_supply);
+
+/**
+ * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
+ *                          the device in device tree
+ * @dev:                    Pointer to the device
+ *
+ * The device must specify "qcom,apm-ctrl" property in its device tree
+ * node which points to an MSM APM controller device node.
+ *
+ * Returns an MSM APM controller handle if successful or ERR_PTR on any error.
+ * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
+ * returned.
+ */
+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
+{
+	struct msm_apm_ctrl_dev *ctrl_dev = NULL;
+	struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
+	struct device_node *ctrl_node;
+
+	if (!dev || !dev->of_node) {
+		pr_err("Invalid device node\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
+	if (!ctrl_node) {
+		pr_err("Could not find qcom,apm-ctrl property in %s\n",
+		       dev->of_node->full_name);
+		return ERR_PTR(-ENXIO);
+	}
+
+	mutex_lock(&apm_ctrl_list_mutex);
+	list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
+		if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
+			dev_found = ctrl_dev;
+			break;
+		}
+	}
+	mutex_unlock(&apm_ctrl_list_mutex);
+
+	of_node_put(ctrl_node);
+	return dev_found;
+}
+EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
+
+#if defined(CONFIG_DEBUG_FS)
+
+static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
+{
+	filep->private_data = inode->i_private;
+
+	return 0;
+}
+
+static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
+				   size_t count, loff_t *ppos)
+{
+	struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
+	char buf[10];
+	int len;
+
+	if (!ctrl_dev) {
+		pr_err("invalid apm ctrl handle\n");
+		return -ENODEV;
+	}
+
+	if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
+		len = snprintf(buf, sizeof(buf), "APCC\n");
+	else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
+		len = snprintf(buf, sizeof(buf), "MX\n");
+	else
+		len = snprintf(buf, sizeof(buf), "ERR\n");
+
+	return simple_read_from_buffer(ubuf, count, ppos, buf, len);
+}
+
+static const struct file_operations apm_supply_fops = {
+	.open = apm_supply_dbg_open,
+	.read = apm_supply_dbg_read,
+};
+
+static void apm_debugfs_base_init(void)
+{
+	apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
+
+	if (IS_ERR_OR_NULL(apm_debugfs_base))
+		pr_err("msm-apm debugfs base directory creation failed\n");
+}
+
+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	struct dentry *temp;
+
+	if (IS_ERR_OR_NULL(apm_debugfs_base)) {
+		pr_err("Base directory missing, cannot create apm debugfs nodes\n");
+		return;
+	}
+
+	ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
+					       apm_debugfs_base);
+	if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
+		pr_err("%s debugfs directory creation failed\n",
+		       dev_name(ctrl_dev->dev));
+		return;
+	}
+
+	temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
+				   ctrl_dev, &apm_supply_fops);
+	if (IS_ERR_OR_NULL(temp)) {
+		pr_err("supply mode creation failed\n");
+		return;
+	}
+}
+
+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
+{
+	if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
+		debugfs_remove_recursive(ctrl_dev->debugfs);
+}
+
+static void apm_debugfs_base_remove(void)
+{
+	debugfs_remove_recursive(apm_debugfs_base);
+}
+#else
+
+static void apm_debugfs_base_init(void)
+{}
+
+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
+{}
+
+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
+{}
+
+static void apm_debugfs_base_remove(void)
+{}
+
+#endif
+
+static struct of_device_id msm_apm_match_table[] = {
+	{
+		.compatible = "qcom,msm-apm",
+		.data = (void *)(uintptr_t)MSM8996_ID,
+	},
+	{
+		.compatible = "qcom,msm8953-apm",
+		.data = (void *)(uintptr_t)MSM8953_ID,
+	},
+	{
+		.compatible = "qcom,ipq807x-apm",
+		.data = (void *)(uintptr_t)IPQ807x_ID,
+	},
+	{}
+};
+
+static int msm_apm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct msm_apm_ctrl_dev *ctrl;
+	const struct of_device_id *match;
+	int ret = 0;
+
+	dev_dbg(dev, "probing MSM Array Power Mux driver\n");
+
+	if (!dev->of_node) {
+		dev_err(dev, "Device tree node is missing\n");
+		return -ENODEV;
+	}
+
+	match = of_match_device(msm_apm_match_table, dev);
+	if (!match)
+		return -ENODEV;
+
+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl) {
+		dev_err(dev, "MSM APM controller memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&ctrl->list);
+	spin_lock_init(&ctrl->lock);
+	ctrl->dev = dev;
+	ctrl->msm_id = (uintptr_t)match->data;
+	platform_set_drvdata(pdev, ctrl);
+
+	switch (ctrl->msm_id) {
+	case MSM8996_ID:
+		ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
+		if (ret) {
+			dev_err(dev, "Failed to add APM controller device\n");
+			return ret;
+		}
+		break;
+	case MSM8953_ID:
+	case IPQ807x_ID:
+		ret = msm8953_apm_ctrl_init(pdev, ctrl);
+		if (ret) {
+			dev_err(dev, "Failed to initialize APM controller device: ret=%d\n",
+				ret);
+			return ret;
+		}
+		break;
+	default:
+		dev_err(dev, "unable to add APM controller device for msm_id:%d\n",
+			ctrl->msm_id);
+		return -ENODEV;
+	}
+
+	apm_debugfs_init(ctrl);
+	mutex_lock(&apm_ctrl_list_mutex);
+	list_add_tail(&ctrl->list, &apm_ctrl_list);
+	mutex_unlock(&apm_ctrl_list_mutex);
+
+	dev_dbg(dev, "MSM Array Power Mux driver probe successful");
+
+	return ret;
+}
+
+static int msm_apm_remove(struct platform_device *pdev)
+{
+	struct msm_apm_ctrl_dev *ctrl_dev;
+
+	ctrl_dev = platform_get_drvdata(pdev);
+	if (ctrl_dev) {
+		mutex_lock(&apm_ctrl_list_mutex);
+		list_del(&ctrl_dev->list);
+		mutex_unlock(&apm_ctrl_list_mutex);
+		apm_debugfs_deinit(ctrl_dev);
+	}
+
+	return 0;
+}
+
+static struct platform_driver msm_apm_driver = {
+	.driver		= {
+		.name		= MSM_APM_DRIVER_NAME,
+		.of_match_table	= msm_apm_match_table,
+		.owner		= THIS_MODULE,
+	},
+	.probe		= msm_apm_probe,
+	.remove		= msm_apm_remove,
+};
+
+static int __init msm_apm_init(void)
+{
+	apm_debugfs_base_init();
+	return platform_driver_register(&msm_apm_driver);
+}
+
+static void __exit msm_apm_exit(void)
+{
+	platform_driver_unregister(&msm_apm_driver);
+	apm_debugfs_base_remove();
+}
+
+arch_initcall(msm_apm_init);
+module_exit(msm_apm_exit);
+
+MODULE_DESCRIPTION("MSM Array Power Mux driver");
+MODULE_LICENSE("GPL v2");

target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-npu-regulator.c

@@ -0,0 +1,695 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+
+#include "cpr3-regulator.h"
+
+#define IPQ807x_NPU_FUSE_CORNERS		2
+#define IPQ817x_NPU_FUSE_CORNERS		1
+#define IPQ807x_NPU_FUSE_STEP_VOLT		8000
+#define IPQ807x_NPU_VOLTAGE_FUSE_SIZE		6
+#define IPQ807x_NPU_CPR_CLOCK_RATE		19200000
+
+#define IPQ807x_NPU_CPR_TCSR_START		6
+#define IPQ807x_NPU_CPR_TCSR_END		7
+
+#define NPU_TSENS				5
+
+u32 g_valid_npu_fuse_count = IPQ807x_NPU_FUSE_CORNERS;
+/**
+ * struct cpr3_ipq807x_npu_fuses - NPU specific fuse data for IPQ807x
+ * @init_voltage:	Initial (i.e. open-loop) voltage fuse parameter value
+ *			for each fuse corner (raw, not converted to a voltage)
+ * This struct holds the values for all of the fuses read from memory.
+ */
+struct cpr3_ipq807x_npu_fuses {
+	u64	init_voltage[IPQ807x_NPU_FUSE_CORNERS];
+};
+
+/*
+ * Constants which define the name of each fuse corner.
+ */
+enum cpr3_ipq807x_npu_fuse_corner {
+	CPR3_IPQ807x_NPU_FUSE_CORNER_NOM	= 0,
+	CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO	= 1,
+};
+
+static const char * const cpr3_ipq807x_npu_fuse_corner_name[] = {
+	[CPR3_IPQ807x_NPU_FUSE_CORNER_NOM]	= "NOM",
+	[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]	= "TURBO",
+};
+
+/*
+ * IPQ807x NPU fuse parameter locations:
+ *
+ * Structs are organized with the following dimensions:
+ *	Outer: 0 to 1 for fuse corners from lowest to highest corner
+ *	Inner: large enough to hold the longest set of parameter segments which
+ *		fully defines a fuse parameter, +1 (for NULL termination).
+ *		Each segment corresponds to a contiguous group of bits from a
+ *		single fuse row.  These segments are concatentated together in
+ *		order to form the full fuse parameter value.  The segments for
+ *		a given parameter may correspond to different fuse rows.
+ */
+static struct cpr3_fuse_param
+ipq807x_npu_init_voltage_param[IPQ807x_NPU_FUSE_CORNERS][2] = {
+	{{73, 22, 27}, {} },
+	{{73, 16, 21}, {} },
+};
+
+/*
+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x
+ */
+static int
+ipq807x_npu_fuse_ref_volt [IPQ807x_NPU_FUSE_CORNERS] = {
+	912000,
+	992000,
+};
+
+/*
+ * IPQ9574 (Few parameters are changed, remaining are same as IPQ807x)
+ */
+#define IPQ9574_NPU_FUSE_CORNERS		2
+#define IPQ9574_NPU_FUSE_STEP_VOLT		10000
+#define IPQ9574_NPU_CPR_CLOCK_RATE		24000000
+
+/*
+ * fues parameters for IPQ9574
+ */
+static struct cpr3_fuse_param
+ipq9574_npu_init_voltage_param[IPQ9574_NPU_FUSE_CORNERS][2] = {
+	{{105, 12, 17}, {} },
+	{{105,  6, 11}, {} },
+};
+
+/*
+ * Open loop voltage fuse reference voltages in microvolts for IPQ9574
+ */
+static int
+ipq9574_npu_fuse_ref_volt [IPQ9574_NPU_FUSE_CORNERS] = {
+	862500,
+	987500,
+};
+
+struct cpr3_controller *g_ctrl;
+
+void cpr3_npu_temp_notify(int sensor, int temp, int low_notif)
+{
+	u32 prev_sensor_state;
+
+	if (sensor != NPU_TSENS)
+		return;
+
+	prev_sensor_state = g_ctrl->cur_sensor_state;
+	if (low_notif)
+		g_ctrl->cur_sensor_state |= BIT(sensor);
+	else
+		g_ctrl->cur_sensor_state &= ~BIT(sensor);
+
+	if (!prev_sensor_state && g_ctrl->cur_sensor_state)
+		cpr3_handle_temp_open_loop_adjustment(g_ctrl, true);
+	else if (prev_sensor_state && !g_ctrl->cur_sensor_state)
+		cpr3_handle_temp_open_loop_adjustment(g_ctrl, false);
+}
+
+/**
+ * cpr3_ipq807x_npu_read_fuse_data() - load NPU specific fuse parameter values
+ * @vreg:		Pointer to the CPR3 regulator
+ *
+ * This function allocates a cpr3_ipq807x_npu_fuses struct, fills it with
+ * values read out of hardware fuses, and finally copies common fuse values
+ * into the CPR3 regulator struct.
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_ipq807x_npu_read_fuse_data(struct cpr3_regulator *vreg)
+{
+	void __iomem *base = vreg->thread->ctrl->fuse_base;
+	struct cpr3_ipq807x_npu_fuses *fuse;
+	int i, rc;
+
+	fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
+	if (!fuse)
+		return -ENOMEM;
+
+	for (i = 0; i < g_valid_npu_fuse_count; i++) {
+		rc = cpr3_read_fuse_param(base,
+					  vreg->cpr3_regulator_data->init_voltage_param[i],
+					  &fuse->init_voltage[i]);
+		if (rc) {
+			cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
+				 i, rc);
+			return rc;
+		}
+	}
+
+	vreg->fuse_corner_count	= g_valid_npu_fuse_count;
+	vreg->platform_fuses	= fuse;
+
+	return 0;
+}
+
+/**
+ * cpr3_npu_parse_corner_data() - parse NPU corner data from device tree
+ *		properties of the CPR3 regulator's device node
+ * @vreg:		Pointer to the CPR3 regulator
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_npu_parse_corner_data(struct cpr3_regulator *vreg)
+{
+	int rc;
+
+	rc = cpr3_parse_common_corner_data(vreg);
+	if (rc) {
+		cpr3_err(vreg, "error reading corner data, rc=%d\n", rc);
+		return rc;
+	}
+
+	return rc;
+}
+
+/**
+ * cpr3_ipq807x_npu_calculate_open_loop_voltages() - calculate the open-loop
+ *		voltage for each corner of a CPR3 regulator
+ * @vreg:		Pointer to the CPR3 regulator
+ * @temp_correction:    Temperature based correction
+ *
+ * If open-loop voltage interpolation is allowed in device tree, then
+ * this function calculates the open-loop voltage for a given corner using
+ * linear interpolation.  This interpolation is performed using the processor
+ * frequencies of the lower and higher Fmax corners along with their fused
+ * open-loop voltages.
+ *
+ * If open-loop voltage interpolation is not allowed, then this function uses
+ * the Fmax fused open-loop voltage for all of the corners associated with a
+ * given fuse corner.
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_ipq807x_npu_calculate_open_loop_voltages(
+			struct cpr3_regulator *vreg, bool temp_correction)
+{
+	struct cpr3_ipq807x_npu_fuses *fuse = vreg->platform_fuses;
+	struct cpr3_controller *ctrl = vreg->thread->ctrl;
+	int i, j, rc = 0;
+	u64 freq_low, volt_low, freq_high, volt_high;
+	int *fuse_volt;
+	int *fmax_corner;
+
+	fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt),
+			    GFP_KERNEL);
+	fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner),
+			      GFP_KERNEL);
+	if (!fuse_volt || !fmax_corner) {
+		rc = -ENOMEM;
+		goto done;
+	}
+
+	for (i = 0; i < vreg->fuse_corner_count; i++) {
+		if (ctrl->cpr_global_setting == CPR_DISABLED)
+			fuse_volt[i] = vreg->cpr3_regulator_data->fuse_ref_volt[i];
+		else
+			fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(
+				vreg->cpr3_regulator_data->fuse_ref_volt[i],
+				vreg->cpr3_regulator_data->fuse_step_volt,
+				fuse->init_voltage[i],
+				IPQ807x_NPU_VOLTAGE_FUSE_SIZE);
+
+		/* Log fused open-loop voltage values for debugging purposes. */
+		cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n",
+			  cpr3_ipq807x_npu_fuse_corner_name[i],
+			  fuse_volt[i]);
+	}
+
+	rc = cpr3_determine_part_type(vreg,
+			fuse_volt[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]);
+	if (rc) {
+		cpr3_err(vreg,
+			"fused part type detection failed failed, rc=%d\n", rc);
+		goto done;
+	}
+
+	rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt);
+	if (rc) {
+		cpr3_err(vreg,
+			"fused open-loop voltage adjustment failed, rc=%d\n",
+			rc);
+		goto done;
+	}
+	if (temp_correction) {
+		rc = cpr3_determine_temp_base_open_loop_correction(vreg,
+								fuse_volt);
+		if (rc) {
+			cpr3_err(vreg,
+				"temp open-loop voltage adj. failed, rc=%d\n",
+				rc);
+			goto done;
+		}
+	}
+
+	for (i = 1; i < vreg->fuse_corner_count; i++) {
+		if (fuse_volt[i] < fuse_volt[i - 1]) {
+			cpr3_info(vreg,
+				"fuse corner %d voltage=%d uV < fuse corner %d \
+				voltage=%d uV; overriding: fuse corner %d \
+				voltage=%d\n",
+				  i, fuse_volt[i], i - 1, fuse_volt[i - 1],
+				  i, fuse_volt[i - 1]);
+			fuse_volt[i] = fuse_volt[i - 1];
+		}
+	}
+
+	/* Determine highest corner mapped to each fuse corner */
+	j = vreg->fuse_corner_count - 1;
+	for (i = vreg->corner_count - 1; i >= 0; i--) {
+		if (vreg->corner[i].cpr_fuse_corner == j) {
+			fmax_corner[j] = i;
+			j--;
+		}
+	}
+
+	if (j >= 0) {
+		cpr3_err(vreg, "invalid fuse corner mapping\n");
+		rc = -EINVAL;
+		goto done;
+	}
+
+	/*
+	 * Interpolation is not possible for corners mapped to the lowest fuse
+	 * corner so use the fuse corner value directly.
+	 */
+	for (i = 0; i <= fmax_corner[0]; i++)
+		vreg->corner[i].open_loop_volt = fuse_volt[0];
+
+	/* Interpolate voltages for the higher fuse corners. */
+	for (i = 1; i < vreg->fuse_corner_count; i++) {
+		freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq;
+		volt_low = fuse_volt[i - 1];
+		freq_high = vreg->corner[fmax_corner[i]].proc_freq;
+		volt_high = fuse_volt[i];
+
+		for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++)
+			vreg->corner[j].open_loop_volt = cpr3_interpolate(
+				freq_low, volt_low, freq_high, volt_high,
+				vreg->corner[j].proc_freq);
+	}
+
+done:
+	if (rc == 0) {
+		cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n");
+		for (i = 0; i < vreg->corner_count; i++)
+			cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i,
+				   vreg->corner[i].open_loop_volt);
+
+		rc = cpr3_adjust_open_loop_voltages(vreg);
+		if (rc)
+			cpr3_err(vreg,
+				"open-loop voltage adjustment failed, rc=%d\n",
+				 rc);
+	}
+
+	kfree(fuse_volt);
+	kfree(fmax_corner);
+	return rc;
+}
+
+/**
+ * cpr3_npu_print_settings() - print out NPU CPR configuration settings into
+ *		the kernel log for debugging purposes
+ * @vreg:		Pointer to the CPR3 regulator
+ */
+static void cpr3_npu_print_settings(struct cpr3_regulator *vreg)
+{
+	struct cpr3_corner *corner;
+	int i;
+
+	cpr3_debug(vreg,
+		"Corner: Frequency (Hz), Fuse Corner, Floor (uV), \
+		Open-Loop (uV), Ceiling (uV)\n");
+	for (i = 0; i < vreg->corner_count; i++) {
+		corner = &vreg->corner[i];
+		cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n",
+			   i, corner->proc_freq, corner->cpr_fuse_corner,
+			   corner->floor_volt, corner->open_loop_volt,
+			   corner->ceiling_volt);
+	}
+
+	if (vreg->thread->ctrl->apm)
+		cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n",
+			   vreg->thread->ctrl->apm_threshold_volt,
+			   vreg->thread->ctrl->apm_adj_volt);
+}
+
+/**
+ * cpr3_ipq807x_npu_calc_temp_based_ol_voltages() - Calculate the open loop
+ * voltages based on temperature based correction margins
+ * @vreg:               Pointer to the CPR3 regulator
+ */
+
+static int
+cpr3_ipq807x_npu_calc_temp_based_ol_voltages(struct cpr3_regulator *vreg,
+						bool temp_correction)
+{
+	int rc, i;
+
+	rc = cpr3_ipq807x_npu_calculate_open_loop_voltages(vreg,
+							temp_correction);
+	if (rc) {
+		cpr3_err(vreg,
+			"unable to calculate open-loop voltages, rc=%d\n", rc);
+		return rc;
+	}
+
+	rc = cpr3_limit_open_loop_voltages(vreg);
+	if (rc) {
+		cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n",
+			 rc);
+		return rc;
+	}
+
+	cpr3_open_loop_voltage_as_ceiling(vreg);
+
+	rc = cpr3_limit_floor_voltages(vreg);
+	if (rc) {
+		cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc);
+		return rc;
+	}
+
+	for (i = 0; i < vreg->corner_count; i++) {
+		if (temp_correction)
+			vreg->corner[i].cold_temp_open_loop_volt =
+				vreg->corner[i].open_loop_volt;
+		else
+			vreg->corner[i].normal_temp_open_loop_volt =
+				vreg->corner[i].open_loop_volt;
+	}
+
+	cpr3_npu_print_settings(vreg);
+
+	return rc;
+}
+
+/**
+ * cpr3_npu_init_thread() - perform steps necessary to initialize the
+ *		configuration data for a CPR3 thread
+ * @thread:		Pointer to the CPR3 thread
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_npu_init_thread(struct cpr3_thread *thread)
+{
+	int rc;
+
+	rc = cpr3_parse_common_thread_data(thread);
+	if (rc) {
+		cpr3_err(thread->ctrl,
+			"thread %u CPR thread data from DT- failed, rc=%d\n",
+			 thread->thread_id, rc);
+		return rc;
+	}
+
+	return 0;
+}
+
+/**
+ * cpr3_npu_init_regulator() - perform all steps necessary to initialize the
+ *		configuration data for a CPR3 regulator
+ * @vreg:		Pointer to the CPR3 regulator
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_npu_init_regulator(struct cpr3_regulator *vreg)
+{
+	struct cpr3_ipq807x_npu_fuses *fuse;
+	int rc, cold_temp = 0;
+	bool can_adj_cold_temp = cpr3_can_adjust_cold_temp(vreg);
+
+	rc = cpr3_ipq807x_npu_read_fuse_data(vreg);
+	if (rc) {
+		cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
+		return rc;
+	}
+
+	fuse = vreg->platform_fuses;
+
+	rc = cpr3_npu_parse_corner_data(vreg);
+	if (rc) {
+		cpr3_err(vreg,
+			"Cannot read CPR corner data from DT, rc=%d\n", rc);
+		return rc;
+	}
+
+	rc = cpr3_mem_acc_init(vreg);
+	if (rc) {
+		if (rc != -EPROBE_DEFER)
+			cpr3_err(vreg,
+			"Cannot initialize mem-acc regulator settings, rc=%d\n",
+			 rc);
+		return rc;
+	}
+
+	if (can_adj_cold_temp) {
+		rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, true);
+		if (rc) {
+			cpr3_err(vreg,
+			"unable to calculate open-loop voltages, rc=%d\n", rc);
+			return rc;
+		}
+	}
+
+	rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, false);
+	if (rc) {
+		cpr3_err(vreg,
+			"unable to calculate open-loop voltages, rc=%d\n", rc);
+		return rc;
+	}
+
+	if (can_adj_cold_temp) {
+		cpr3_info(vreg,
+		"Normal and Cold condition init done. Default to normal.\n");
+
+		rc = cpr3_get_cold_temp_threshold(vreg, &cold_temp);
+		if (rc) {
+			cpr3_err(vreg,
+			"Get cold temperature threshold failed, rc=%d\n", rc);
+			return rc;
+		}
+		register_low_temp_notif(NPU_TSENS, cold_temp,
+							cpr3_npu_temp_notify);
+	}
+
+	return rc;
+}
+
+/**
+ * cpr3_npu_init_controller() - perform NPU CPR3 controller specific
+ *		initializations
+ * @ctrl:		Pointer to the CPR3 controller
+ *
+ * Return: 0 on success, errno on failure
+ */
+static int cpr3_npu_init_controller(struct cpr3_controller *ctrl)
+{
+	int rc;
+
+	rc = cpr3_parse_open_loop_common_ctrl_data(ctrl);
+	if (rc) {
+		if (rc != -EPROBE_DEFER)
+			cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n",
+				 rc);
+		return rc;
+	}
+
+	ctrl->ctrl_type = CPR_CTRL_TYPE_CPR3;
+	ctrl->supports_hw_closed_loop = false;
+
+	return 0;
+}
+
+static const struct cpr3_reg_data ipq807x_cpr_npu = {
+	.cpr_valid_fuse_count = IPQ807x_NPU_FUSE_CORNERS,
+	.init_voltage_param = ipq807x_npu_init_voltage_param,
+	.fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
+	.fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
+	.cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
+};
+
+static const struct cpr3_reg_data ipq817x_cpr_npu = {
+	.cpr_valid_fuse_count = IPQ817x_NPU_FUSE_CORNERS,
+	.init_voltage_param = ipq807x_npu_init_voltage_param,
+	.fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
+	.fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
+	.cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
+};
+
+static const struct cpr3_reg_data ipq9574_cpr_npu = {
+	.cpr_valid_fuse_count = IPQ9574_NPU_FUSE_CORNERS,
+	.init_voltage_param = ipq9574_npu_init_voltage_param,
+	.fuse_ref_volt = ipq9574_npu_fuse_ref_volt,
+	.fuse_step_volt = IPQ9574_NPU_FUSE_STEP_VOLT,
+	.cpr_clk_rate = IPQ9574_NPU_CPR_CLOCK_RATE,
+};
+
+static struct of_device_id cpr3_regulator_match_table[] = {
+	{
+		.compatible = "qcom,cpr3-ipq807x-npu-regulator",
+		.data = &ipq807x_cpr_npu
+	},
+	{
+		.compatible = "qcom,cpr3-ipq817x-npu-regulator",
+		.data = &ipq817x_cpr_npu
+	},
+	{
+		.compatible = "qcom,cpr3-ipq9574-npu-regulator",
+		.data = &ipq9574_cpr_npu
+	},
+	{}
+};
+
+static int cpr3_npu_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cpr3_controller *ctrl;
+	int i, rc;
+	const struct of_device_id *match;
+	struct cpr3_reg_data *cpr_data;
+
+	if (!dev->of_node) {
+		dev_err(dev, "Device tree node is missing\n");
+		return -EINVAL;
+	}
+
+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl)
+		return -ENOMEM;
+	g_ctrl = ctrl;
+
+	match = of_match_device(cpr3_regulator_match_table, &pdev->dev);
+	if (!match)
+		return -ENODEV;
+
+	cpr_data = (struct cpr3_reg_data *)match->data;
+	g_valid_npu_fuse_count = cpr_data->cpr_valid_fuse_count;
+	dev_info(dev, "NPU CPR valid fuse count: %d\n", g_valid_npu_fuse_count);
+	ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate;
+
+	ctrl->dev = dev;
+	/* Set to false later if anything precludes CPR operation. */
+	ctrl->cpr_allowed_hw = true;
+
+	rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name",
+				     &ctrl->name);
+	if (rc) {
+		cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n",
+			 rc);
+		return rc;
+	}
+
+	rc = cpr3_map_fuse_base(ctrl, pdev);
+	if (rc) {
+		cpr3_err(ctrl, "could not map fuse base address\n");
+		return rc;
+	}
+
+	rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_NPU_CPR_TCSR_START,
+				    IPQ807x_NPU_CPR_TCSR_END);
+	if (rc) {
+		cpr3_err(ctrl, "could not read CPR tcsr rsetting\n");
+		return rc;
+	}
+
+	rc = cpr3_allocate_threads(ctrl, 0, 0);
+	if (rc) {
+		cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n",
+			 rc);
+		return rc;
+	}
+
+	if (ctrl->thread_count != 1) {
+		cpr3_err(ctrl, "expected 1 thread but found %d\n",
+			 ctrl->thread_count);
+		return -EINVAL;
+	}
+
+	rc = cpr3_npu_init_controller(ctrl);
+	if (rc) {
+		if (rc != -EPROBE_DEFER)
+			cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n",
+				 rc);
+		return rc;
+	}
+
+	rc = cpr3_npu_init_thread(&ctrl->thread[0]);
+	if (rc) {
+		cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc);
+		return rc;
+	}
+
+	for (i = 0; i < ctrl->thread[0].vreg_count; i++) {
+		ctrl->thread[0].vreg[i].cpr3_regulator_data = cpr_data;
+		rc = cpr3_npu_init_regulator(&ctrl->thread[0].vreg[i]);
+		if (rc) {
+			cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n",
+				 rc);
+			return rc;
+		}
+	}
+
+	platform_set_drvdata(pdev, ctrl);
+
+	return cpr3_open_loop_regulator_register(pdev, ctrl);
+}
+
+static int cpr3_npu_regulator_remove(struct platform_device *pdev)
+{
+	struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
+
+	return cpr3_open_loop_regulator_unregister(ctrl);
+}
+
+static struct platform_driver cpr3_npu_regulator_driver = {
+	.driver		= {
+		.name		= "qcom,cpr3-npu-regulator",
+		.of_match_table	= cpr3_regulator_match_table,
+		.owner		= THIS_MODULE,
+	},
+	.probe		= cpr3_npu_regulator_probe,
+	.remove		= cpr3_npu_regulator_remove,
+};
+
+static int cpr3_regulator_init(void)
+{
+	return platform_driver_register(&cpr3_npu_regulator_driver);
+}
+arch_initcall(cpr3_regulator_init);
+
+static void cpr3_regulator_exit(void)
+{
+	platform_driver_unregister(&cpr3_npu_regulator_driver);
+}
+module_exit(cpr3_regulator_exit);
+
+MODULE_DESCRIPTION("QCOM CPR3 NPU regulator driver");
+MODULE_LICENSE("Dual BSD/GPLv2");
+MODULE_ALIAS("platform:npu-ipq807x");

target/linux/ipq807x/files-5.15/include/linux/power/qcom/apm.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_POWER_QCOM_APM_H__
+#define __LINUX_POWER_QCOM_APM_H__
+
+#include <linux/device.h>
+#include <linux/err.h>
+
+/**
+ * enum msm_apm_supply - supported power rails to supply memory arrays
+ * %MSM_APM_SUPPLY_APCC:	to enable selection of VDD_APCC rail as supply
+ * %MSM_APM_SUPPLY_MX:		to enable selection of VDD_MX rail as supply
+ */
+enum msm_apm_supply {
+	MSM_APM_SUPPLY_APCC,
+	MSM_APM_SUPPLY_MX,
+};
+
+/* Handle used to identify an APM controller device  */
+struct msm_apm_ctrl_dev;
+
+#ifdef CONFIG_QCOM_APM
+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev);
+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
+		       enum msm_apm_supply supply);
+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev);
+
+#else
+static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
+{ return ERR_PTR(-EPERM); }
+static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
+		       enum msm_apm_supply supply)
+{ return -EPERM; }
+static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
+{ return -EPERM; }
+#endif
+#endif

target/linux/ipq807x/files-5.15/include/soc/qcom/socinfo.h

@@ -0,0 +1,463 @@
+/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_
+#define _ARCH_ARM_MACH_MSM_SOCINFO_H_
+
+#include <linux/of.h>
+
+#define CPU_IPQ8074 323
+#define CPU_IPQ8072 342
+#define CPU_IPQ8076 343
+#define CPU_IPQ8078 344
+#define CPU_IPQ8070 375
+#define CPU_IPQ8071 376
+
+#define CPU_IPQ8072A 389
+#define CPU_IPQ8074A 390
+#define CPU_IPQ8076A 391
+#define CPU_IPQ8078A 392
+#define CPU_IPQ8070A 395
+#define CPU_IPQ8071A 396
+
+#define CPU_IPQ8172  397
+#define CPU_IPQ8173  398
+#define CPU_IPQ8174  399
+
+#define CPU_IPQ6018 402
+#define CPU_IPQ6028 403
+#define CPU_IPQ6000 421
+#define CPU_IPQ6010 422
+#define CPU_IPQ6005 453
+
+#define CPU_IPQ5010 446
+#define CPU_IPQ5018 447
+#define CPU_IPQ5028 448
+#define CPU_IPQ5000 503
+#define CPU_IPQ0509 504
+#define CPU_IPQ0518 505
+
+#define CPU_IPQ9514 510
+#define CPU_IPQ9554 512
+#define CPU_IPQ9570 513
+#define CPU_IPQ9574 514
+#define CPU_IPQ9550 511
+#define CPU_IPQ9510 521
+
+static inline int read_ipq_soc_version_major(void)
+{
+	const int *prop;
+	prop = of_get_property(of_find_node_by_path("/"), "soc_version_major",
+				NULL);
+
+	if (!prop)
+		return -EINVAL;
+
+	return le32_to_cpu(*prop);
+}
+
+static inline int read_ipq_cpu_type(void)
+{
+	const int *prop;
+	prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL);
+	/*
+	 * Return Default CPU type if "cpu_type" property is not found in DTSI
+	 */
+	if (!prop)
+		return CPU_IPQ8074;
+
+	return le32_to_cpu(*prop);
+}
+
+static inline int cpu_is_ipq8070(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8070;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8071(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8071;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8072(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8072;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8074(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8074;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8076(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8076;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8078(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8078;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8072a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8072A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8074a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8074A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8076a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8076A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8078a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8078A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8070a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8070A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8071a(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8071A;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8172(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8172;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8173(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8173;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq8174(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ8174;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq6018(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ6018;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq6028(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ6028;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq6000(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ6000;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq6010(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ6010;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq6005(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ6005;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq5010(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ5010;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq5018(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ5018;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq5028(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ5028;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq5000(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ5000;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq0509(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ0509;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq0518(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ0518;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9514(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9514;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9554(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9554;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9570(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9570;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9574(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9574;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9550(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9550;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq9510(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return read_ipq_cpu_type() == CPU_IPQ9510;
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq807x(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq8072() || cpu_is_ipq8074() ||
+		cpu_is_ipq8076() || cpu_is_ipq8078() ||
+		cpu_is_ipq8070() || cpu_is_ipq8071() ||
+		cpu_is_ipq8072a() || cpu_is_ipq8074a() ||
+		cpu_is_ipq8076a() || cpu_is_ipq8078a() ||
+		cpu_is_ipq8070a() || cpu_is_ipq8071a() ||
+		cpu_is_ipq8172() || cpu_is_ipq8173() ||
+		cpu_is_ipq8174();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq60xx(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq6018() || cpu_is_ipq6028() ||
+		cpu_is_ipq6000() || cpu_is_ipq6010() ||
+		cpu_is_ipq6005();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq50xx(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq5010() || cpu_is_ipq5018() ||
+		cpu_is_ipq5028() || cpu_is_ipq5000() ||
+		cpu_is_ipq0509() || cpu_is_ipq0518();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_ipq95xx(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq9514() || cpu_is_ipq9554() ||
+		cpu_is_ipq9570() || cpu_is_ipq9574() ||
+		cpu_is_ipq9550() || cpu_is_ipq9510();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_nss_crypto_enabled(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
+		cpu_is_ipq50xx() || cpu_is_ipq9570() ||
+		cpu_is_ipq9550() || cpu_is_ipq9574() ||
+		cpu_is_ipq9554();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_internal_wifi_enabled(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
+		cpu_is_ipq50xx() || cpu_is_ipq9514() ||
+		cpu_is_ipq9554() || cpu_is_ipq9574();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_uniphy1_enabled(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
+		cpu_is_ipq9554() || cpu_is_ipq9570() ||
+		cpu_is_ipq9574() || cpu_is_ipq9550();
+#else
+	return 0;
+#endif
+}
+
+static inline int cpu_is_uniphy2_enabled(void)
+{
+#ifdef CONFIG_ARCH_QCOM
+	return  cpu_is_ipq807x() || cpu_is_ipq9570() ||
+		cpu_is_ipq9574();
+#else
+	return 0;
+#endif
+}
+
+#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */

target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch

@@ -12,11 +12,13 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/Makefile
 +++ b/arch/arm64/boot/dts/qcom/Makefile
-@@ -3,6 +3,9 @@ dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc.d
+@@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc.d
  dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 +dtb-$(CONFIG_ARCH_QCOM)	+= ipq8072-301w.dtb
++dtb-$(CONFIG_ARCH_QCOM)	+= ipq8071-ax6.dtb
++dtb-$(CONFIG_ARCH_QCOM)	+= ipq8071-ax3600.dtb
 +dtb-$(CONFIG_ARCH_QCOM)	+= ipq8071-mf269.dtb
 +dtb-$(CONFIG_ARCH_QCOM)	+= ipq8078-xtr10890.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb

target/linux/ipq807x/patches-5.15/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch

@@ -1,7 +1,7 @@
-From 3f3f712b16c7d374cfb079ca83684f12fda7884c Mon Sep 17 00:00:00 2001
+From 63750607afad67e57841689b01a9425822503e0c Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Sun, 5 Sep 2021 18:58:16 +0200
-Subject: [PATCH 01/44] arm64: dts: qcom: ipq8074: add SPMI bus
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add SPMI bus
 
 IPQ8074 uses SPMI for communication with the PMIC, so
 since its already supported add the DT node for it.

target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-Update-BAM-DMA-node-name-per-DT-schem.patch

@@ -1,27 +0,0 @@
-From e5698ba1e94af28e5f54943bcd6de278efc84500 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Tue, 31 Aug 2021 13:23:25 +0800
-Subject: [PATCH 02/44] arm64: dts: qcom: Update BAM DMA node name per DT
- schema
-
-Follow dma-controller.yaml schema to use `dma-controller` as node name
-of BAM DMA devices.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -212,7 +212,7 @@
- 			status = "disabled";
- 		};
- 
--		cryptobam: dma@704000 {
-+		cryptobam: dma-controller@704000 {
- 			compatible = "qcom,bam-v1.7.0";
- 			reg = <0x00704000 0x20000>;
- 			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;

target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch

@@ -1,7 +1,7 @@
-From 187368d2936edad6342151ae1ac34d95dc2de2c1 Mon Sep 17 00:00:00 2001
+From 9c0bd8e53774c38bd7859ad4af300a5062430925 Mon Sep 17 00:00:00 2001
 From: Chukun Pan <amadeus@jmu.edu.cn>
 Date: Fri, 1 Oct 2021 22:54:21 +0800
-Subject: [PATCH 03/44] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
 
 Add node to support the QUP5 I2C controller inside of IPQ8074.
 It is exactly the same as QUP2 controllers.

target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch

@@ -0,0 +1,134 @@
+From 82d61e19fccbf2fe7c018765b3799791916e7f31 Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@linaro.org>
+Date: Wed, 29 Sep 2021 11:42:46 +0800
+Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY
+ child node
+
+'#clock-cells' is a required property of QMP PHY child node, not itself.
+Move it to fix the dtbs_check warnings.
+
+There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
+child nodes already have the property.
+
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
+ arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++--
+ arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
+ arch/arm64/boot/dts/qcom/sm8350.dtsi  | 3 ---
+ 4 files changed, 5 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -91,7 +91,6 @@
+ 		ssphy_1: phy@58000 {
+ 			compatible = "qcom,ipq8074-qmp-usb3-phy";
+ 			reg = <0x00058000 0x1c4>;
+-			#clock-cells = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -112,6 +111,7 @@
+ 				      <0x00058800 0x1f8>,     /* PCS  */
+ 				      <0x00058600 0x044>;     /* PCS misc*/
+ 				#phy-cells = <0>;
++				#clock-cells = <1>;
+ 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
+ 				clock-names = "pipe0";
+ 				clock-output-names = "gcc_usb1_pipe_clk_src";
+@@ -134,7 +134,6 @@
+ 		ssphy_0: phy@78000 {
+ 			compatible = "qcom,ipq8074-qmp-usb3-phy";
+ 			reg = <0x00078000 0x1c4>;
+-			#clock-cells = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -155,6 +154,7 @@
+ 				      <0x00078800 0x1f8>,     /* PCS  */
+ 				      <0x00078600 0x044>;     /* PCS misc*/
+ 				#phy-cells = <0>;
++				#clock-cells = <1>;
+ 				clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ 				clock-names = "pipe0";
+ 				clock-output-names = "gcc_usb0_pipe_clk_src";
+--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
+@@ -582,7 +582,6 @@
+ 		pcie_phy: phy@34000 {
+ 			compatible = "qcom,msm8996-qmp-pcie-phy";
+ 			reg = <0x00034000 0x488>;
+-			#clock-cells = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -604,6 +603,7 @@
+ 				      <0x00035400 0x1dc>;
+ 				#phy-cells = <0>;
+ 
++				#clock-cells = <1>;
+ 				clock-output-names = "pcie_0_pipe_clk_src";
+ 				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ 				clock-names = "pipe0";
+@@ -2586,7 +2586,6 @@
+ 		usb3phy: phy@7410000 {
+ 			compatible = "qcom,msm8996-qmp-usb3-phy";
+ 			reg = <0x07410000 0x1c4>;
+-			#clock-cells = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -2607,6 +2606,7 @@
+ 				      <0x07410600 0x1a8>;
+ 				#phy-cells = <0>;
+ 
++				#clock-cells = <1>;
+ 				clock-output-names = "usb3_phy_pipe_clk_src";
+ 				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ 				clock-names = "pipe0";
+--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
+@@ -1985,7 +1985,6 @@
+ 			compatible = "qcom,msm8998-qmp-usb3-phy";
+ 			reg = <0x0c010000 0x18c>;
+ 			status = "disabled";
+-			#clock-cells = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -2006,6 +2005,7 @@
+ 				      <0xc010600 0x128>,
+ 				      <0xc010800 0x200>;
+ 				#phy-cells = <0>;
++				#clock-cells = <1>;
+ 				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ 				clock-names = "pipe0";
+ 				clock-output-names = "usb3_phy_pipe_clk_src";
+--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
+@@ -1070,7 +1070,6 @@
+ 			reg = <0 0x01d87000 0 0xe10>;
+ 			#address-cells = <2>;
+ 			#size-cells = <2>;
+-			#clock-cells = <1>;
+ 			ranges;
+ 			clock-names = "ref",
+ 				      "ref_aux";
+@@ -1205,7 +1204,6 @@
+ 			      <0 0x088e8000 0 0x20>;
+ 			reg-names = "reg-base", "dp_com";
+ 			status = "disabled";
+-			#clock-cells = <1>;
+ 			#address-cells = <2>;
+ 			#size-cells = <2>;
+ 			ranges;
+@@ -1238,7 +1236,6 @@
+ 			compatible = "qcom,sm8350-qmp-usb3-uni-phy";
+ 			reg = <0 0x088eb000 0 0x200>;
+ 			status = "disabled";
+-			#clock-cells = <1>;
+ 			#address-cells = <2>;
+ 			#size-cells = <2>;
+ 			ranges;

target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch

@@ -0,0 +1,273 @@
+From 1351512f29b4348e6b497f6343896c1033d409b4 Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@linaro.org>
+Date: Wed, 29 Sep 2021 11:42:47 +0800
+Subject: [PATCH] arm64: dts: qcom: Correct QMP PHY child node name
+
+Many child nodes of QMP PHY are named without following bindings schema
+and causing dtbs_check warnings like below.
+
+phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$'
+        arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
+        arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
+        arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
+        arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
+        arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
+        arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml
+
+Correct them to fix the warnings.
+
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi |  2 +-
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi |  4 ++--
+ arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++-----
+ arch/arm64/boot/dts/qcom/msm8998.dtsi |  6 +++---
+ arch/arm64/boot/dts/qcom/sdm845.dtsi  | 10 +++++-----
+ arch/arm64/boot/dts/qcom/sm8150.dtsi  |  6 +++---
+ arch/arm64/boot/dts/qcom/sm8250.dtsi  | 10 +++++-----
+ arch/arm64/boot/dts/qcom/sm8350.dtsi  |  2 +-
+ 8 files changed, 25 insertions(+), 25 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -401,7 +401,7 @@
+ 			reset-names = "phy",
+ 				      "common";
+ 
+-			pcie_phy0: lane@84200 {
++			pcie_phy0: phy@84200 {
+ 				reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
+ 				      <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
+ 				      <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -105,7 +105,7 @@
+ 			reset-names = "phy","common";
+ 			status = "disabled";
+ 
+-			usb1_ssphy: lane@58200 {
++			usb1_ssphy: phy@58200 {
+ 				reg = <0x00058200 0x130>,       /* Tx */
+ 				      <0x00058400 0x200>,     /* Rx */
+ 				      <0x00058800 0x1f8>,     /* PCS  */
+@@ -148,7 +148,7 @@
+ 			reset-names = "phy","common";
+ 			status = "disabled";
+ 
+-			usb0_ssphy: lane@78200 {
++			usb0_ssphy: phy@78200 {
+ 				reg = <0x00078200 0x130>,       /* Tx */
+ 				      <0x00078400 0x200>,     /* Rx */
+ 				      <0x00078800 0x1f8>,     /* PCS  */
+--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
+@@ -597,7 +597,7 @@
+ 			reset-names = "phy", "common", "cfg";
+ 			status = "disabled";
+ 
+-			pciephy_0: lane@35000 {
++			pciephy_0: phy@35000 {
+ 				reg = <0x00035000 0x130>,
+ 				      <0x00035200 0x200>,
+ 				      <0x00035400 0x1dc>;
+@@ -611,7 +611,7 @@
+ 				reset-names = "lane0";
+ 			};
+ 
+-			pciephy_1: lane@36000 {
++			pciephy_1: phy@36000 {
+ 				reg = <0x00036000 0x130>,
+ 				      <0x00036200 0x200>,
+ 				      <0x00036400 0x1dc>;
+@@ -624,7 +624,7 @@
+ 				reset-names = "lane1";
+ 			};
+ 
+-			pciephy_2: lane@37000 {
++			pciephy_2: phy@37000 {
+ 				reg = <0x00037000 0x130>,
+ 				      <0x00037200 0x200>,
+ 				      <0x00037400 0x1dc>;
+@@ -1746,7 +1746,7 @@
+ 			reset-names = "ufsphy";
+ 			status = "disabled";
+ 
+-			ufsphy_lane: lanes@627400 {
++			ufsphy_lane: phy@627400 {
+ 				reg = <0x627400 0x12c>,
+ 				      <0x627600 0x200>,
+ 				      <0x627c00 0x1b4>;
+@@ -2600,7 +2600,7 @@
+ 			reset-names = "phy", "common";
+ 			status = "disabled";
+ 
+-			ssusb_phy_0: lane@7410200 {
++			ssusb_phy_0: phy@7410200 {
+ 				reg = <0x07410200 0x200>,
+ 				      <0x07410400 0x130>,
+ 				      <0x07410600 0x1a8>;
+--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
+@@ -994,7 +994,7 @@
+ 			vdda-phy-supply = <&vreg_l1a_0p875>;
+ 			vdda-pll-supply = <&vreg_l2a_1p2>;
+ 
+-			pciephy: lane@1c06800 {
++			pciephy: phy@1c06800 {
+ 				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
+ 				#phy-cells = <0>;
+ 
+@@ -1066,7 +1066,7 @@
+ 			reset-names = "ufsphy";
+ 			resets = <&ufshc 0>;
+ 
+-			ufsphy_lanes: lanes@1da7400 {
++			ufsphy_lanes: phy@1da7400 {
+ 				reg = <0x01da7400 0x128>,
+ 				      <0x01da7600 0x1fc>,
+ 				      <0x01da7c00 0x1dc>,
+@@ -1998,7 +1998,7 @@
+ 				 <&gcc GCC_USB3PHY_PHY_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb1_ssphy: lane@c010200 {
++			usb1_ssphy: phy@c010200 {
+ 				reg = <0xc010200 0x128>,
+ 				      <0xc010400 0x200>,
+ 				      <0xc010c00 0x20c>,
+--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+@@ -2064,7 +2064,7 @@
+ 
+ 			status = "disabled";
+ 
+-			pcie0_lane: lanes@1c06200 {
++			pcie0_lane: phy@1c06200 {
+ 				reg = <0 0x01c06200 0 0x128>,
+ 				      <0 0x01c06400 0 0x1fc>,
+ 				      <0 0x01c06800 0 0x218>,
+@@ -2174,7 +2174,7 @@
+ 
+ 			status = "disabled";
+ 
+-			pcie1_lane: lanes@1c06200 {
++			pcie1_lane: phy@1c06200 {
+ 				reg = <0 0x01c0a800 0 0x800>,
+ 				      <0 0x01c0a800 0 0x800>,
+ 				      <0 0x01c0b800 0 0x400>;
+@@ -2302,7 +2302,7 @@
+ 			reset-names = "ufsphy";
+ 			status = "disabled";
+ 
+-			ufs_mem_phy_lanes: lanes@1d87400 {
++			ufs_mem_phy_lanes: phy@1d87400 {
+ 				reg = <0 0x01d87400 0 0x108>,
+ 				      <0 0x01d87600 0 0x1e0>,
+ 				      <0 0x01d87c00 0 0x1dc>,
+@@ -3699,7 +3699,7 @@
+ 				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_1_ssphy: lanes@88e9200 {
++			usb_1_ssphy: phy@88e9200 {
+ 				reg = <0 0x088e9200 0 0x128>,
+ 				      <0 0x088e9400 0 0x200>,
+ 				      <0 0x088e9c00 0 0x218>,
+@@ -3732,7 +3732,7 @@
+ 				 <&gcc GCC_USB3_PHY_SEC_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_2_ssphy: lane@88eb200 {
++			usb_2_ssphy: phy@88eb200 {
+ 				reg = <0 0x088eb200 0 0x128>,
+ 				      <0 0x088eb400 0 0x1fc>,
+ 				      <0 0x088eb800 0 0x218>,
+--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
+@@ -1692,7 +1692,7 @@
+ 			reset-names = "ufsphy";
+ 			status = "disabled";
+ 
+-			ufs_mem_phy_lanes: lanes@1d87400 {
++			ufs_mem_phy_lanes: phy@1d87400 {
+ 				reg = <0 0x01d87400 0 0x108>,
+ 				      <0 0x01d87600 0 0x1e0>,
+ 				      <0 0x01d87c00 0 0x1dc>,
+@@ -3010,7 +3010,7 @@
+ 				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_1_ssphy: lanes@88e9200 {
++			usb_1_ssphy: phy@88e9200 {
+ 				reg = <0 0x088e9200 0 0x200>,
+ 				      <0 0x088e9400 0 0x200>,
+ 				      <0 0x088e9c00 0 0x218>,
+@@ -3043,7 +3043,7 @@
+ 				 <&gcc GCC_USB3_PHY_SEC_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_2_ssphy: lane@88eb200 {
++			usb_2_ssphy: phy@88eb200 {
+ 				reg = <0 0x088eb200 0 0x200>,
+ 				      <0 0x088eb400 0 0x200>,
+ 				      <0 0x088eb800 0 0x800>,
+--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
+@@ -1463,7 +1463,7 @@
+ 
+ 			status = "disabled";
+ 
+-			pcie0_lane: lanes@1c06200 {
++			pcie0_lane: phy@1c06200 {
+ 				reg = <0 0x1c06200 0 0x170>, /* tx */
+ 				      <0 0x1c06400 0 0x200>, /* rx */
+ 				      <0 0x1c06800 0 0x1f0>, /* pcs */
+@@ -1567,7 +1567,7 @@
+ 
+ 			status = "disabled";
+ 
+-			pcie1_lane: lanes@1c0e200 {
++			pcie1_lane: phy@1c0e200 {
+ 				reg = <0 0x1c0e200 0 0x170>, /* tx0 */
+ 				      <0 0x1c0e400 0 0x200>, /* rx0 */
+ 				      <0 0x1c0ea00 0 0x1f0>, /* pcs */
+@@ -1673,7 +1673,7 @@
+ 
+ 			status = "disabled";
+ 
+-			pcie2_lane: lanes@1c16200 {
++			pcie2_lane: phy@1c16200 {
+ 				reg = <0 0x1c16200 0 0x170>, /* tx0 */
+ 				      <0 0x1c16400 0 0x200>, /* rx0 */
+ 				      <0 0x1c16a00 0 0x1f0>, /* pcs */
+@@ -1750,7 +1750,7 @@
+ 			reset-names = "ufsphy";
+ 			status = "disabled";
+ 
+-			ufs_mem_phy_lanes: lanes@1d87400 {
++			ufs_mem_phy_lanes: phy@1d87400 {
+ 				reg = <0 0x01d87400 0 0x108>,
+ 				      <0 0x01d87600 0 0x1e0>,
+ 				      <0 0x01d87c00 0 0x1dc>,
+@@ -2330,7 +2330,7 @@
+ 				 <&gcc GCC_USB3_PHY_SEC_BCR>;
+ 			reset-names = "phy", "common";
+ 
+-			usb_2_ssphy: lanes@88eb200 {
++			usb_2_ssphy: phy@88eb200 {
+ 				reg = <0 0x088eb200 0 0x200>,
+ 				      <0 0x088eb400 0 0x200>,
+ 				      <0 0x088eb800 0 0x800>;
+--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
+@@ -1080,7 +1080,7 @@
+ 			reset-names = "ufsphy";
+ 			status = "disabled";
+ 
+-			ufs_mem_phy_lanes: lanes@1d87400 {
++			ufs_mem_phy_lanes: phy@1d87400 {
+ 				reg = <0 0x01d87400 0 0x108>,
+ 				      <0 0x01d87600 0 0x1e0>,
+ 				      <0 0x01d87c00 0 0x1dc>,

target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch

@@ -1,53 +0,0 @@
-From 4ef751128de689e12e3eccb5d4e2562ef8b42758 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Wed, 29 Sep 2021 11:42:46 +0800
-Subject: [PATCH 04/44] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP
- PHY child node
-
-'#clock-cells' is a required property of QMP PHY child node, not itself.
-Move it to fix the dtbs_check warnings.
-
-There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
-child nodes already have the property.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -91,7 +91,6 @@
- 		ssphy_1: phy@58000 {
- 			compatible = "qcom,ipq8074-qmp-usb3-phy";
- 			reg = <0x00058000 0x1c4>;
--			#clock-cells = <1>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
- 			ranges;
-@@ -112,6 +111,7 @@
- 				      <0x00058800 0x1f8>,     /* PCS  */
- 				      <0x00058600 0x044>;     /* PCS misc*/
- 				#phy-cells = <0>;
-+				#clock-cells = <1>;
- 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
- 				clock-names = "pipe0";
- 				clock-output-names = "gcc_usb1_pipe_clk_src";
-@@ -134,7 +134,6 @@
- 		ssphy_0: phy@78000 {
- 			compatible = "qcom,ipq8074-qmp-usb3-phy";
- 			reg = <0x00078000 0x1c4>;
--			#clock-cells = <1>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
- 			ranges;
-@@ -155,6 +154,7 @@
- 				      <0x00078800 0x1f8>,     /* PCS  */
- 				      <0x00078600 0x044>;     /* PCS misc*/
- 				#phy-cells = <0>;
-+				#clock-cells = <1>;
- 				clocks = <&gcc GCC_USB0_PIPE_CLK>;
- 				clock-names = "pipe0";
- 				clock-output-names = "gcc_usb0_pipe_clk_src";

target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch

@@ -1,45 +0,0 @@
-From 616ad8e9f89e9f57597cf856697fe1c35cf84e5d Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Wed, 29 Sep 2021 11:42:47 +0800
-Subject: [PATCH 05/44] arm64: dts: qcom: Correct QMP PHY child node name
-
-Many child nodes of QMP PHY are named without following bindings schema
-and causing dtbs_check warnings like below.
-
-phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$'
-        arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
-        arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
-        arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
-        arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
-        arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
-        arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml
-
-Correct them to fix the warnings.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -105,7 +105,7 @@
- 			reset-names = "phy","common";
- 			status = "disabled";
- 
--			usb1_ssphy: lane@58200 {
-+			usb1_ssphy: phy@58200 {
- 				reg = <0x00058200 0x130>,       /* Tx */
- 				      <0x00058400 0x200>,     /* Rx */
- 				      <0x00058800 0x1f8>,     /* PCS  */
-@@ -148,7 +148,7 @@
- 			reset-names = "phy","common";
- 			status = "disabled";
- 
--			usb0_ssphy: lane@78200 {
-+			usb0_ssphy: phy@78200 {
- 				reg = <0x00078200 0x130>,       /* Tx */
- 				      <0x00078400 0x200>,     /* Rx */
- 				      <0x00078800 0x1f8>,     /* PCS  */

target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch

@@ -1,7 +1,7 @@
-From 2a38228b9ac3f8cb4fdae411abbdd5226b687880 Mon Sep 17 00:00:00 2001
+From 942bcd33ed455ad40b71a59901bd926bbf4a500e Mon Sep 17 00:00:00 2001
 From: Shawn Guo <shawn.guo@linaro.org>
 Date: Wed, 29 Sep 2021 11:42:51 +0800
-Subject: [PATCH 06/44] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
+Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
 
 IPQ8074 PCIe PHY nodes are broken in the many ways:
 

target/linux/ipq807x/patches-5.15/0006-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch

@@ -1,7 +1,7 @@
-From 9757a0d4e05b807074f6868ed594a9bf0111d74d Mon Sep 17 00:00:00 2001
+From d201f67714a302b12ad3d78b982963342939629c Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Thu, 7 Oct 2021 13:58:46 +0200
-Subject: [PATCH 07/44] arm64: dts: qcom: ipq8074: add MDIO bus
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add MDIO bus
 
 IPQ8074 uses an IPQ4019 compatible MDIO controller that is already
 supported in the kernel, so add the DT node in order to use it.

target/linux/ipq807x/patches-5.15/0007-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch

@@ -1,7 +1,7 @@
-From 70835efbc6c9dbc4e652aa60a250ecb1a2160a9b Mon Sep 17 00:00:00 2001
+From adfde5bbb4afd5e47371b74a0a4c9ec02fcc8d58 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Sun, 5 Sep 2021 19:11:31 +0200
-Subject: [PATCH 41/44] soc: qcom: socinfo: Add IPQ8074 family ID-s
+Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 family ID-s
 
 IPQ8074 family SoC ID-s are missing, so lets add them based on
 the downstream driver.

target/linux/ipq807x/patches-5.15/0008-v5.16-soc-qcom-smem-Support-reserved-memory-description.patch

@@ -1,166 +0,0 @@
-From 00abf58f0ec5ce9dd947792f65e9d01284a4e9c8 Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Thu, 30 Sep 2021 11:21:10 -0700
-Subject: [PATCH 08/44] soc: qcom: smem: Support reserved-memory description
-
-Practically all modern Qualcomm platforms has a single reserved-memory
-region for SMEM. So rather than having to describe SMEM in the form of a
-node with a reference to a reserved-memory node, allow the SMEM device
-to be instantiated directly from the reserved-memory node.
-
-The current means of falling back to dereferencing the "memory-region"
-is kept as a fallback, if it's determined that the SMEM node is a
-reserved-memory node.
-
-The "qcom,smem" compatible is added to the reserved_mem_matches list, to
-allow the reserved-memory device to be probed.
-
-In order to retain the readability of the code, the resolution of
-resources is split from the actual ioremapping.
-
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
-Link: https://lore.kernel.org/r/20210930182111.57353-4-bjorn.andersson@linaro.org
----
- drivers/of/platform.c   |  1 +
- drivers/soc/qcom/smem.c | 57 ++++++++++++++++++++++++++++-------------
- 2 files changed, 40 insertions(+), 18 deletions(-)
-
---- a/drivers/of/platform.c
-+++ b/drivers/of/platform.c
-@@ -509,6 +509,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_po
- static const struct of_device_id reserved_mem_matches[] = {
- 	{ .compatible = "qcom,rmtfs-mem" },
- 	{ .compatible = "qcom,cmd-db" },
-+	{ .compatible = "qcom,smem" },
- 	{ .compatible = "ramoops" },
- 	{ .compatible = "nvmem-rmem" },
- 	{}
---- a/drivers/soc/qcom/smem.c
-+++ b/drivers/soc/qcom/smem.c
-@@ -9,6 +9,7 @@
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-+#include <linux/of_reserved_mem.h>
- #include <linux/platform_device.h>
- #include <linux/sizes.h>
- #include <linux/slab.h>
-@@ -240,7 +241,7 @@ static const u8 SMEM_INFO_MAGIC[] = { 0x
-  * @size:	size of the memory region
-  */
- struct smem_region {
--	u32 aux_base;
-+	phys_addr_t aux_base;
- 	void __iomem *virt_base;
- 	size_t size;
- };
-@@ -499,7 +500,7 @@ static void *qcom_smem_get_global(struct
- 	for (i = 0; i < smem->num_regions; i++) {
- 		region = &smem->regions[i];
- 
--		if (region->aux_base == aux_base || !aux_base) {
-+		if ((u32)region->aux_base == aux_base || !aux_base) {
- 			if (size != NULL)
- 				*size = le32_to_cpu(entry->size);
- 			return region->virt_base + le32_to_cpu(entry->offset);
-@@ -664,7 +665,7 @@ phys_addr_t qcom_smem_virt_to_phys(void
- 		if (p < region->virt_base + region->size) {
- 			u64 offset = p - region->virt_base;
- 
--			return (phys_addr_t)region->aux_base + offset;
-+			return region->aux_base + offset;
- 		}
- 	}
- 
-@@ -863,12 +864,12 @@ qcom_smem_enumerate_partitions(struct qc
- 	return 0;
- }
- 
--static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev,
--				const char *name, int i)
-+static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name,
-+				 struct smem_region *region)
- {
-+	struct device *dev = smem->dev;
- 	struct device_node *np;
- 	struct resource r;
--	resource_size_t size;
- 	int ret;
- 
- 	np = of_parse_phandle(dev->of_node, name, 0);
-@@ -881,13 +882,9 @@ static int qcom_smem_map_memory(struct q
- 	of_node_put(np);
- 	if (ret)
- 		return ret;
--	size = resource_size(&r);
- 
--	smem->regions[i].virt_base = devm_ioremap_wc(dev, r.start, size);
--	if (!smem->regions[i].virt_base)
--		return -ENOMEM;
--	smem->regions[i].aux_base = (u32)r.start;
--	smem->regions[i].size = size;
-+	region->aux_base = r.start;
-+	region->size = resource_size(&r);
- 
- 	return 0;
- }
-@@ -895,12 +892,14 @@ static int qcom_smem_map_memory(struct q
- static int qcom_smem_probe(struct platform_device *pdev)
- {
- 	struct smem_header *header;
-+	struct reserved_mem *rmem;
- 	struct qcom_smem *smem;
- 	size_t array_size;
- 	int num_regions;
- 	int hwlock_id;
- 	u32 version;
- 	int ret;
-+	int i;
- 
- 	num_regions = 1;
- 	if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL))
-@@ -914,13 +913,35 @@ static int qcom_smem_probe(struct platfo
- 	smem->dev = &pdev->dev;
- 	smem->num_regions = num_regions;
- 
--	ret = qcom_smem_map_memory(smem, &pdev->dev, "memory-region", 0);
--	if (ret)
--		return ret;
--
--	if (num_regions > 1 && (ret = qcom_smem_map_memory(smem, &pdev->dev,
--					"qcom,rpm-msg-ram", 1)))
--		return ret;
-+	rmem = of_reserved_mem_lookup(pdev->dev.of_node);
-+	if (rmem) {
-+		smem->regions[0].aux_base = rmem->base;
-+		smem->regions[0].size = rmem->size;
-+	} else {
-+		/*
-+		 * Fall back to the memory-region reference, if we're not a
-+		 * reserved-memory node.
-+		 */
-+		ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	if (num_regions > 1) {
-+		ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	for (i = 0; i < num_regions; i++) {
-+		smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev,
-+							     smem->regions[i].aux_base,
-+							     smem->regions[i].size);
-+		if (!smem->regions[i].virt_base) {
-+			dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base);
-+			return -ENOMEM;
-+		}
-+	}
- 
- 	header = smem->regions[0].virt_base;
- 	if (le32_to_cpu(header->initialized) != 1 ||

target/linux/ipq807x/patches-5.15/0010-v5.18-arm64-dts-qcom-ipq8074-add-the-reserved-memory-node.patch

@@ -1,30 +0,0 @@
-From d58eeedd46d47db44a5932f7d74efae881d54c9b Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Fri, 7 Jan 2022 18:24:38 +0530
-Subject: [PATCH 10/44] arm64: dts: qcom: ipq8074: add the reserved-memory node
-
-On IPQ8074, 4MB of memory is needed for TZ. So mark that region
-as reserved.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-[bjorn: Squash with existing reserved-memory node]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -88,6 +88,11 @@
- 
- 			hwlocks = <&tcsr_mutex 0>;
- 		};
-+
-+		memory@4ac00000 {
-+			no-map;
-+			reg = <0x0 0x4ac00000 0x0 0x00400000>;
-+		};
- 	};
- 
- 	firmware {

target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-ipq8074-add-SMEM-support.patch

@@ -1,21 +1,21 @@
-From 0064ce4f52ed8fc010c1794114205daa9f598828 Mon Sep 17 00:00:00 2001
+From f63c96c02671c00871d180fb5b436e53f4847d3c Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Thu, 6 Jan 2022 22:25:12 +0100
-Subject: [PATCH 09/44] arm64: dts: qcom: ipq8074: add SMEM support
+Subject: [PATCH] arm64: dts: ipq8074: add SMEM support
 
 IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already
 supported by the kernel add the required DT nodes.
 
 Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
 ---
  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index 91436f0a653a..adce47affbef 100644
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -76,6 +76,20 @@
+@@ -76,6 +76,20 @@ psci {
  		method = "smc";
  	};
  
@@ -36,7 +36,7 @@ Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
  	firmware {
  		scm {
  			compatible = "qcom,scm-ipq8074", "qcom,scm";
-@@ -331,6 +345,12 @@
+@@ -331,6 +345,12 @@ gcc: gcc@1800000 {
  			#reset-cells = <0x1>;
  		};
  
@@ -49,3 +49,6 @@ Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
  		spmi_bus: spmi@200f000 {
  			compatible = "qcom,spmi-pmic-arb";
  			reg = <0x0200f000 0x001000>,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0012-v5.18-arm64-dts-qcom-ipq8074-drop-the-clock-frequency-prop.patch

@@ -1,26 +0,0 @@
-From 2e21d1f48dc0d0cdbd53ac33b9859c7cb575eecc Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Wed, 2 Feb 2022 22:05:08 +0530
-Subject: [PATCH 12/44] arm64: dts: qcom: ipq8074: drop the clock-frequency
- property
-
-Drop the clock-frequency property from the MMIO timer node, since it
-is already configured by the bootloader.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -670,7 +670,6 @@
- 			ranges;
- 			compatible = "arm,armv7-timer-mem";
- 			reg = <0x0b120000 0x1000>;
--			clock-frequency = <19200000>;
- 
- 			frame@b120000 {
- 				frame-number = <0>;

target/linux/ipq807x/patches-5.15/0013-v5.19-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-sc.patch

@@ -1,62 +0,0 @@
-From 4647475f588c85138ddf47a17305dd41834e1105 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 5 Apr 2022 08:34:43 +0200
-Subject: [PATCH 13/44] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT
- schema
-
-The DT schema expects dma channels in tx-rx order.  No functional
-change.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -471,8 +471,8 @@
- 				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- 			clock-names = "iface", "core";
- 			clock-frequency = <400000>;
--			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
--			dma-names = "rx", "tx";
-+			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
-+			dma-names = "tx", "rx";
- 			pinctrl-0 = <&i2c_0_pins>;
- 			pinctrl-names = "default";
- 			status = "disabled";
-@@ -488,8 +488,8 @@
- 				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- 			clock-names = "iface", "core";
- 			clock-frequency = <100000>;
--			dmas = <&blsp_dma 17>, <&blsp_dma 16>;
--			dma-names = "rx", "tx";
-+			dmas = <&blsp_dma 16>, <&blsp_dma 17>;
-+			dma-names = "tx", "rx";
- 			status = "disabled";
- 		};
- 
-@@ -503,8 +503,8 @@
- 				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- 			clock-names = "iface", "core";
- 			clock-frequency = <400000>;
--			dmas = <&blsp_dma 21>, <&blsp_dma 20>;
--			dma-names = "rx", "tx";
-+			dmas = <&blsp_dma 20>, <&blsp_dma 21>;
-+			dma-names = "tx", "rx";
- 			status = "disabled";
- 		};
- 
-@@ -518,8 +518,8 @@
- 				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- 			clock-names = "iface", "core";
- 			clock-frequency = <100000>;
--			dmas = <&blsp_dma 23>, <&blsp_dma 22>;
--			dma-names = "rx", "tx";
-+			dmas = <&blsp_dma 22>, <&blsp_dma 23>;
-+			dma-names = "tx", "rx";
- 			status = "disabled";
- 		};
- 

target/linux/ipq807x/patches-5.15/0014-v5.19-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schem.patch

@@ -1,69 +0,0 @@
-From 553f1ea4128453cead2d38d5773ec6044c6e7626 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 5 Apr 2022 08:34:44 +0200
-Subject: [PATCH 14/44] arm64: dts: qcom: align clocks in I2C/SPI with DT
- schema
-
-The DT schema expects clocks core-iface order.  No functional change.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -467,9 +467,9 @@
- 			#size-cells = <0>;
- 			reg = <0x078b6000 0x600>;
- 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
--			clock-names = "iface", "core";
-+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
- 			clock-frequency = <400000>;
- 			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
- 			dma-names = "tx", "rx";
-@@ -484,9 +484,9 @@
- 			#size-cells = <0>;
- 			reg = <0x078b7000 0x600>;
- 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
--			clock-names = "iface", "core";
-+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
- 			clock-frequency = <100000>;
- 			dmas = <&blsp_dma 16>, <&blsp_dma 17>;
- 			dma-names = "tx", "rx";
-@@ -499,9 +499,9 @@
- 			#size-cells = <0>;
- 			reg = <0x78b9000 0x600>;
- 			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
--			clock-names = "iface", "core";
-+			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
- 			clock-frequency = <400000>;
- 			dmas = <&blsp_dma 20>, <&blsp_dma 21>;
- 			dma-names = "tx", "rx";
-@@ -514,9 +514,9 @@
- 			#size-cells = <0>;
- 			reg = <0x078ba000 0x600>;
- 			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
--			clock-names = "iface", "core";
-+			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
- 			clock-frequency = <100000>;
- 			dmas = <&blsp_dma 22>, <&blsp_dma 23>;
- 			dma-names = "tx", "rx";

target/linux/ipq807x/patches-5.15/0015-v5.19-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addr.patch

@@ -1,37 +0,0 @@
-From 04e91eb95f7a0a9dceed2c1fcb47fbbe7f96ec52 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:16 +0200
-Subject: [PATCH 15/44] arm64: dts: qcom: correct DWC3 node names and unit
- addresses
-
-Align DWC3 USB node names with DT schema ("usb" is expected) and correct
-the unit addresses to match the "reg" property.  This also implies
-overriding nodes by label, instead of full path.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -578,7 +578,7 @@
- 			resets = <&gcc GCC_USB0_BCR>;
- 			status = "disabled";
- 
--			dwc_0: dwc3@8a00000 {
-+			dwc_0: usb@8a00000 {
- 				compatible = "snps,dwc3";
- 				reg = <0x8a00000 0xcd00>;
- 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-@@ -618,7 +618,7 @@
- 			resets = <&gcc GCC_USB1_BCR>;
- 			status = "disabled";
- 
--			dwc_1: dwc3@8c00000 {
-+			dwc_1: usb@8c00000 {
- 				compatible = "snps,dwc3";
- 				reg = <0x8c00000 0xcd00>;
- 				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

target/linux/ipq807x/patches-5.15/0016-v5.19-arm64-dts-qcom-ipq8074-add-dedicated-qcom-ipq8074-dw.patch

@@ -1,36 +0,0 @@
-From 65b572a6c5bad2c9f3c784ff42d4eddedcfd85cd Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:17 +0200
-Subject: [PATCH 16/44] arm64: dts: qcom: ipq8074: add dedicated
- qcom,ipq8074-dwc3 compatible
-
-Add dedicated compatible for DWC3 USB node name to allow more accurate
-DT schema matching.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-8-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -553,7 +553,7 @@
- 		};
- 
- 		usb_0: usb@8af8800 {
--			compatible = "qcom,dwc3";
-+			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
- 			reg = <0x08af8800 0x400>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
-@@ -593,7 +593,7 @@
- 		};
- 
- 		usb_1: usb@8cf8800 {
--			compatible = "qcom,dwc3";
-+			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
- 			reg = <0x08cf8800 0x400>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;

target/linux/ipq807x/patches-5.15/0017-v5.19-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch

@@ -1,39 +0,0 @@
-From e8949160470080b4c24139cfb88accc25e589f70 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:22 +0200
-Subject: [PATCH 17/44] arm64: dts: qcom: align DWC3 USB clocks with DT schema
-
-Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
-No functional impact expected.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -563,8 +563,8 @@
- 				<&gcc GCC_USB0_MASTER_CLK>,
- 				<&gcc GCC_USB0_SLEEP_CLK>,
- 				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
--			clock-names = "sys_noc_axi",
--				"master",
-+			clock-names = "cfg_noc",
-+				"core",
- 				"sleep",
- 				"mock_utmi";
- 
-@@ -603,8 +603,8 @@
- 				<&gcc GCC_USB1_MASTER_CLK>,
- 				<&gcc GCC_USB1_SLEEP_CLK>,
- 				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
--			clock-names = "sys_noc_axi",
--				"master",
-+			clock-names = "cfg_noc",
-+				"core",
- 				"sleep",
- 				"mock_utmi";
- 

target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-adjust-whitespace-around.patch

@@ -1,36 +0,0 @@
-From af38dc1085f574d575c886c0800645c8b7d4b874 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Thu, 26 May 2022 22:42:47 +0200
-Subject: [PATCH 18/44] arm64: dts: qcom: adjust whitespace around '='
-
-Fix whitespace coding style: use single space instead of tabs or
-multiple spaces around '=' sign in property assignment.  No functional
-changes (same DTB).
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -119,7 +119,7 @@
- 				<&xo>;
- 			clock-names = "aux", "cfg_ahb", "ref";
- 
--			resets =  <&gcc GCC_USB1_PHY_BCR>,
-+			resets = <&gcc GCC_USB1_PHY_BCR>,
- 				<&gcc GCC_USB3PHY_1_PHY_BCR>;
- 			reset-names = "phy","common";
- 			status = "disabled";
-@@ -162,7 +162,7 @@
- 				<&xo>;
- 			clock-names = "aux", "cfg_ahb", "ref";
- 
--			resets =  <&gcc GCC_USB0_PHY_BCR>,
-+			resets = <&gcc GCC_USB0_PHY_BCR>,
- 				<&gcc GCC_USB3PHY_0_PHY_BCR>;
- 			reset-names = "phy","common";
- 			status = "disabled";

target/linux/ipq807x/patches-5.15/0019-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch

@@ -1,34 +0,0 @@
-From 0d7e4bd5d554ac7471724f80aa67b664f3539f47 Mon Sep 17 00:00:00 2001
-From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Date: Sun, 15 May 2022 03:24:19 +0530
-Subject: [PATCH 19/44] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
-
-Since the Qualcomm sdhci-msm device-tree binding has been converted
-to yaml format, 'make dtbs_check' reports issues with
-inconsistent 'sdhci@' convention used for specifying the
-sdhci nodes. The generic mmc bindings expect 'mmc@' format
-instead.
-
-Fix the same.
-
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
-Cc: Rob Herring <robh@kernel.org>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-[bjorn: Moved non-arm64 changes to separate commit]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -375,7 +375,7 @@
- 			cell-index = <0>;
- 		};
- 
--		sdhc_1: sdhci@7824900 {
-+		sdhc_1: mmc@7824900 {
- 			compatible = "qcom,sdhci-msm-v4";
- 			reg = <0x7824900 0x500>, <0x7824000 0x800>;
- 			reg-names = "hc_mem", "core_mem";

target/linux/ipq807x/patches-5.15/0020-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch

@@ -1,47 +0,0 @@
-From d923ec8397673773a3d22dc3ac0c5fccd22cd405 Mon Sep 17 00:00:00 2001
-From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Date: Sun, 15 May 2022 03:24:22 +0530
-Subject: [PATCH 20/44] arm64: dts: qcom: Fix ordering of 'clocks' &
- 'clock-names' for sdhci nodes
-
-Since the Qualcomm sdhci-msm device-tree binding has been converted
-to yaml format, 'make dtbs_check' reports a number of issues with
-ordering of 'clocks' & 'clock-names' for sdhci nodes:
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
-  clock-names:0: 'iface' was expected
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
-  clock-names:1: 'core' was expected
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
-  clock-names:2: 'xo' was expected
-
-Fix the same by updating the offending 'dts' files.
-
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
-Cc: Rob Herring <robh@kernel.org>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -384,10 +384,10 @@
- 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- 			interrupt-names = "hc_irq", "pwr_irq";
- 
--			clocks = <&xo>,
--				 <&gcc GCC_SDCC1_AHB_CLK>,
--				 <&gcc GCC_SDCC1_APPS_CLK>;
--			clock-names = "xo", "iface", "core";
-+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
-+				 <&gcc GCC_SDCC1_APPS_CLK>,
-+				 <&xo>;
-+			clock-names = "iface", "core", "xo";
- 			max-frequency = <384000000>;
- 			mmc-ddr-1_8v;
- 			mmc-hs200-1_8v;

target/linux/ipq807x/patches-5.15/0021-v6.0-dt-bindings-clock-qcom-ipq8074-add-PPE-crypto-clock.patch

@@ -1,25 +0,0 @@
-From f56aefe67c7652d38293afa83333c9228a9fbc35 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:41 +0200
-Subject: [PATCH 21/44] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock
-
-Add binding for the PPE crypto clock in IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -233,6 +233,7 @@
- #define GCC_PCIE0_AXI_S_BRIDGE_CLK		224
- #define GCC_PCIE0_RCHNG_CLK_SRC			225
- #define GCC_PCIE0_RCHNG_CLK			226
-+#define GCC_CRYPTO_PPE_CLK			227
- 
- #define GCC_BLSP1_BCR				0
- #define GCC_BLSP1_QUP1_BCR			1

target/linux/ipq807x/patches-5.15/0023-v6.0-dt-bindings-clock-qcom-ipq8074-add-USB-GDSCs.patch

@@ -1,25 +0,0 @@
-From c0823201046e5a79823e3ff5fa4f0a9b5fcda14d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:45 +0200
-Subject: [PATCH 23/44] dt-bindings: clock: qcom: ipq8074: add USB GDSCs
-
-Add bindings for the USB GDSCs found in IPQ8074 GCC.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -368,4 +368,7 @@
- #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
- #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
- 
-+#define USB0_GDSC				0
-+#define USB1_GDSC				1
-+
- #endif

target/linux/ipq807x/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch

@@ -1,79 +0,0 @@
-From 248fb3267c23749059baa231e21650a68771abef Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:46 +0200
-Subject: [PATCH 24/44] clk: qcom: ipq8074: add USB GDSCs
-
-Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
----
- drivers/clk/qcom/Kconfig       |  1 +
- drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
- 2 files changed, 25 insertions(+)
-
---- a/drivers/clk/qcom/Kconfig
-+++ b/drivers/clk/qcom/Kconfig
-@@ -166,6 +166,7 @@ config IPQ_LCC_806X
- 
- config IPQ_GCC_8074
- 	tristate "IPQ8074 Global Clock Controller"
-+	select QCOM_GDSC
- 	help
- 	  Support for global clock controller on ipq8074 devices.
- 	  Say Y if you want to use peripheral devices such as UART, SPI,
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -22,6 +22,7 @@
- #include "clk-alpha-pll.h"
- #include "clk-regmap-divider.h"
- #include "clk-regmap-mux.h"
-+#include "gdsc.h"
- #include "reset.h"
- 
- enum {
-@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s
- 	},
- };
- 
-+static struct gdsc usb0_gdsc = {
-+	.gdscr = 0x3e078,
-+	.pd = {
-+		.name = "usb0_gdsc",
-+	},
-+	.pwrsts = PWRSTS_OFF_ON,
-+};
-+
-+static struct gdsc usb1_gdsc = {
-+	.gdscr = 0x3f078,
-+	.pd = {
-+		.name = "usb1_gdsc",
-+	},
-+	.pwrsts = PWRSTS_OFF_ON,
-+};
-+
- static const struct alpha_pll_config ubi32_pll_config = {
- 	.l = 0x4e,
- 	.config_ctl_val = 0x200d4aa8,
-@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i
- 	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
- };
- 
-+static struct gdsc *gcc_ipq8074_gdscs[] = {
-+	[USB0_GDSC] = &usb0_gdsc,
-+	[USB1_GDSC] = &usb1_gdsc,
-+};
-+
- static const struct of_device_id gcc_ipq8074_match_table[] = {
- 	{ .compatible = "qcom,gcc-ipq8074" },
- 	{ }
-@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq
- 	.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
- 	.clk_hws = gcc_ipq8074_hws,
- 	.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
-+	.gdscs = gcc_ipq8074_gdscs,
-+	.num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
- };
- 
- static int gcc_ipq8074_probe(struct platform_device *pdev)

target/linux/ipq807x/patches-5.15/0025-v6.0-arm64-dts-qcom-ipq8074-add-USB-power-domains.patch

@@ -1,43 +0,0 @@
-From e8516c04110438230314ddbe94879ecb4a5db5df Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:48 +0200
-Subject: [PATCH 25/44] arm64: dts: qcom: ipq8074: add USB power domains
-
-Add USB power domains provided by GCC GDSCs.
-Add the required #power-domain-cells to the GCC as well.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-11-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -347,6 +347,7 @@
- 			compatible = "qcom,gcc-ipq8074";
- 			reg = <0x01800000 0x80000>;
- 			#clock-cells = <0x1>;
-+			#power-domain-cells = <1>;
- 			#reset-cells = <0x1>;
- 		};
- 
-@@ -575,6 +576,8 @@
- 						<133330000>,
- 						<19200000>;
- 
-+			power-domains = <&gcc USB0_GDSC>;
-+
- 			resets = <&gcc GCC_USB0_BCR>;
- 			status = "disabled";
- 
-@@ -615,6 +618,8 @@
- 						<133330000>,
- 						<19200000>;
- 
-+			power-domains = <&gcc USB1_GDSC>;
-+
- 			resets = <&gcc GCC_USB1_BCR>;
- 			status = "disabled";
- 

target/linux/ipq807x/patches-5.15/0026-v6.0-arm64-dts-qcom-ipq8074-move-ARMv8-timer-out-of-SoC-n.patch

@@ -1,51 +0,0 @@
-From 510f246cf8f6af8c0d7a46d22448b812fd9a14a4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 13:33:18 +0200
-Subject: [PATCH 26/44] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC
- node
-
-The ARM timer is usually considered not part of SoC node, just like
-other ARM designed blocks (PMU, PSCI).  This fixes dtbs_check warning:
-
-arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
-	From schema: dtschema/schemas/simple-bus.yaml
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-[bjorn: Moved node after "soc" for alphabetical ordering]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -653,14 +653,6 @@
- 			};
- 		};
- 
--		timer {
--			compatible = "arm,armv8-timer";
--			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
--		};
--
- 		watchdog: watchdog@b017000 {
- 			compatible = "qcom,kpss-wdt";
- 			reg = <0xb017000 0x1000>;
-@@ -852,4 +844,12 @@
- 			status = "disabled";
- 		};
- 	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+	};
- };

target/linux/ipq807x/patches-5.15/0027-v6.0-arm64-dts-qcom-ipq8074-add-reset-to-SDHCI.patch

@@ -1,27 +0,0 @@
-From 8cef5828706a1584b4dadf3f4b707a392bc8c231 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 16:35:54 +0200
-Subject: [PATCH 27/44] arm64: dts: qcom: ipq8074: add reset to SDHCI
-
-Add reset to SDHCI controller so it can be reset to avoid timeout issues
-after software reset due to bootloader set configuration.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -389,6 +389,7 @@
- 				 <&gcc GCC_SDCC1_APPS_CLK>,
- 				 <&xo>;
- 			clock-names = "iface", "core", "xo";
-+			resets = <&gcc GCC_SDCC1_BCR>;
- 			max-frequency = <384000000>;
- 			mmc-ddr-1_8v;
- 			mmc-hs200-1_8v;

target/linux/ipq807x/patches-5.15/0028-v6.0-arm64-dts-qcom-ipq8074-drop-USB-PHY-clock-index.patch

@@ -1,36 +0,0 @@
-From 2bf80b5de7c2598972af28adc09e8e667b528d11 Mon Sep 17 00:00:00 2001
-From: Johan Hovold <johan+linaro@kernel.org>
-Date: Tue, 5 Jul 2022 13:40:22 +0200
-Subject: [PATCH 28/44] arm64: dts: qcom: ipq8074: drop USB PHY clock index
-
-The QMP USB PHY provides a single clock so drop the redundant clock
-index.
-
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -130,7 +130,7 @@
- 				      <0x00058800 0x1f8>,     /* PCS  */
- 				      <0x00058600 0x044>;     /* PCS misc*/
- 				#phy-cells = <0>;
--				#clock-cells = <1>;
-+				#clock-cells = <0>;
- 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
- 				clock-names = "pipe0";
- 				clock-output-names = "gcc_usb1_pipe_clk_src";
-@@ -173,7 +173,7 @@
- 				      <0x00078800 0x1f8>,     /* PCS  */
- 				      <0x00078600 0x044>;     /* PCS misc*/
- 				#phy-cells = <0>;
--				#clock-cells = <1>;
-+				#clock-cells = <0>;
- 				clocks = <&gcc GCC_USB0_PIPE_CLK>;
- 				clock-names = "pipe0";
- 				clock-output-names = "gcc_usb0_pipe_clk_src";

target/linux/ipq807x/patches-5.15/0029-v6.0-arm64-dts-qcom-ipq8074-add-APCS-node.patch

@@ -1,37 +0,0 @@
-From 73ea147a5caa82c94486076186af2c7dc1894a97 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 7 Jul 2022 19:37:33 +0200
-Subject: [PATCH 29/44] arm64: dts: qcom: ipq8074: add APCS node
-
-APCS now has support for providing the APSS clocks as the child device
-for IPQ8074.
-
-So, add the required DT node for it as it will later be used as the CPU
-clocksource.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-[bjorn: Sorted node based on address]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -662,6 +662,14 @@
- 			timeout-sec = <30>;
- 		};
- 
-+		apcs_glb: mailbox@b111000 {
-+			compatible = "qcom,ipq8074-apcs-apps-global";
-+			reg = <0x0b111000 0x6000>;
-+
-+			#clock-cells = <1>;
-+			#mbox-cells = <1>;
-+		};
-+
- 		timer@b120000 {
- 			#address-cells = <1>;
- 			#size-cells = <1>;

target/linux/ipq807x/patches-5.15/0030-v6.0-arm64-dts-qcom-ipq8074-add-size-address-cells-to-DTS.patch

@@ -1,55 +0,0 @@
-From 254bf23fe2e0c73d75a0bf4f37579e15433b75e0 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 8 Jul 2022 15:38:45 +0200
-Subject: [PATCH 30/44] arm64: dts: qcom: ipq8074: add #size/address-cells to
- DTSI
-
-Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating
-the same properties in board DTS files.
-
-Remove the mentioned properties from current board DTS files.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 2 --
- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi      | 3 +++
- 3 files changed, 3 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -5,8 +5,6 @@
- #include "ipq8074.dtsi"
- 
- / {
--	#address-cells = <0x2>;
--	#size-cells = <0x2>;
- 	model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
- 	compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
- 	interrupt-parent = <&intc>;
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-@@ -7,9 +7,6 @@
- #include "ipq8074.dtsi"
- 
- / {
--	#address-cells = <0x2>;
--	#size-cells = <0x2>;
--
- 	interrupt-parent = <&intc>;
- 
- 	aliases {
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -7,6 +7,9 @@
- #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
- 
- / {
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
- 	model = "Qualcomm Technologies, Inc. IPQ8074";
- 	compatible = "qcom,ipq8074";
- 

target/linux/ipq807x/patches-5.15/0031-v6.0-arm64-dts-qcom-ipq8074-add-interrupt-parent-to-DTSI.patch

@@ -1,50 +0,0 @@
-From 520877b4d26ba4e6d08b5e9579f166ca2a934e81 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 8 Jul 2022 15:38:46 +0200
-Subject: [PATCH 31/44] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI
-
-Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board
-DTS file.
-
-Remove interrupt-parent from existing board DTS files.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 1 -
- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 --
- arch/arm64/boot/dts/qcom/ipq8074.dtsi      | 1 +
- 3 files changed, 1 insertion(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -7,7 +7,6 @@
- / {
- 	model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
- 	compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
--	interrupt-parent = <&intc>;
- 
- 	aliases {
- 		serial0 = &blsp1_uart5;
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-@@ -7,8 +7,6 @@
- #include "ipq8074.dtsi"
- 
- / {
--	interrupt-parent = <&intc>;
--
- 	aliases {
- 		serial0 = &blsp1_uart5;
- 	};
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -12,6 +12,7 @@
- 
- 	model = "Qualcomm Technologies, Inc. IPQ8074";
- 	compatible = "qcom,ipq8074";
-+	interrupt-parent = <&intc>;
- 
- 	clocks {
- 		sleep_clk: sleep_clk {

target/linux/ipq807x/patches-5.15/0032-v6.0-regulator-qcom_spmi-add-support-for-HT_P150.patch

@@ -1,58 +0,0 @@
-From 8928dcb644461e72608dbea26af4d072868ae41b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:54 +0200
-Subject: [PATCH 32/44] regulator: qcom_spmi: add support for HT_P150
-
-HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout
-found in PMP8074 and PMS405 PMIC-s.
-
-Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V
-but the actual MAX output voltage depends on the exact LDO in each of
-the PMIC-s.
-
-It has a max current of 150mA, voltage step of 8mV.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-4-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -164,6 +164,7 @@ enum spmi_regulator_subtype {
- 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3	= 0x0f,
- 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4	= 0x10,
- 	SPMI_REGULATOR_SUBTYPE_HFS430		= 0x0a,
-+	SPMI_REGULATOR_SUBTYPE_HT_P150		= 0x35,
- };
- 
- enum spmi_common_regulator_registers {
-@@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_
- 	SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
- };
- 
-+static struct spmi_voltage_range ht_p150_ranges[] = {
-+	SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
-+};
-+
- static DEFINE_SPMI_SET_POINTS(pldo);
- static DEFINE_SPMI_SET_POINTS(nldo1);
- static DEFINE_SPMI_SET_POINTS(nldo2);
-@@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660);
- static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
- static DEFINE_SPMI_SET_POINTS(ht_nldo);
- static DEFINE_SPMI_SET_POINTS(hfs430);
-+static DEFINE_SPMI_SET_POINTS(ht_p150);
- 
- static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
- 				 int len)
-@@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_h
- 
- static const struct spmi_regulator_mapping supported_regulators[] = {
- 	/*           type subtype dig_min dig_max ltype ops setpoints hpm_min */
-+	SPMI_VREG(LDO,   HT_P150,  0, INF, HFS430, hfs430, ht_p150, 10000),
- 	SPMI_VREG(BUCK,  GP_CTL,   0, INF, SMPS,   smps,   smps,   100000),
- 	SPMI_VREG(BUCK,  HFS430,   0, INF, HFS430, hfs430, hfs430,  10000),
- 	SPMI_VREG(LDO,   N300,     0, INF, LDO,    ldo,    nldo1,   10000),

target/linux/ipq807x/patches-5.15/0033-v6.0-regulator-qcom_spmi-add-support-for-HT_P600.patch

@@ -1,59 +0,0 @@
-From 2ba036ce8e99673073adc5ac62e7768a47725567 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:55 +0200
-Subject: [PATCH 33/44] regulator: qcom_spmi: add support for HT_P600
-
-HT_P600 is a LDO PMOS regulator based on LV P600 using HFS430 layout
-found in PMP8074 and PMS405 PMIC-s.
-
-Both PMP8074 and PMS405 define the programmable range as 1.704 to 1.896V
-but the actual MAX output voltage depends on the exact LDO in each of
-the PMIC-s.
-Their usual voltage that they are used is 1.8V.
-
-It has a max current of 600mA, voltage step of 8mV.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-5-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -165,6 +165,7 @@ enum spmi_regulator_subtype {
- 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4	= 0x10,
- 	SPMI_REGULATOR_SUBTYPE_HFS430		= 0x0a,
- 	SPMI_REGULATOR_SUBTYPE_HT_P150		= 0x35,
-+	SPMI_REGULATOR_SUBTYPE_HT_P600		= 0x3d,
- };
- 
- enum spmi_common_regulator_registers {
-@@ -549,6 +550,10 @@ static struct spmi_voltage_range ht_p150
- 	SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
- };
- 
-+static struct spmi_voltage_range ht_p600_ranges[] = {
-+	SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
-+};
-+
- static DEFINE_SPMI_SET_POINTS(pldo);
- static DEFINE_SPMI_SET_POINTS(nldo1);
- static DEFINE_SPMI_SET_POINTS(nldo2);
-@@ -570,6 +575,7 @@ static DEFINE_SPMI_SET_POINTS(ht_lvpldo)
- static DEFINE_SPMI_SET_POINTS(ht_nldo);
- static DEFINE_SPMI_SET_POINTS(hfs430);
- static DEFINE_SPMI_SET_POINTS(ht_p150);
-+static DEFINE_SPMI_SET_POINTS(ht_p600);
- 
- static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
- 				 int len)
-@@ -1464,6 +1470,7 @@ static const struct regulator_ops spmi_h
- 
- static const struct spmi_regulator_mapping supported_regulators[] = {
- 	/*           type subtype dig_min dig_max ltype ops setpoints hpm_min */
-+	SPMI_VREG(LDO,   HT_P600,  0, INF, HFS430, hfs430, ht_p600, 10000),
- 	SPMI_VREG(LDO,   HT_P150,  0, INF, HFS430, hfs430, ht_p150, 10000),
- 	SPMI_VREG(BUCK,  GP_CTL,   0, INF, SMPS,   smps,   smps,   100000),
- 	SPMI_VREG(BUCK,  HFS430,   0, INF, HFS430, hfs430, hfs430,  10000),

target/linux/ipq807x/patches-5.15/0034-v6.0-regulator-qcom_spmi-add-support-for-PMP8074-regulato.patch

@@ -1,69 +0,0 @@
-From 933b687758646242fc7410edb06da70fe7540cdc Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:57 +0200
-Subject: [PATCH 34/44] regulator: qcom_spmi: add support for PMP8074
- regulators
-
-PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s.
-
-It features 5 HF-SMPS and 13 LDO regulators.
-
-HF-SMPS regulators are Buck HFS430 regulators.
-L1, L2 and L3 are HT_N1200_ST subtype LDO regulators.
-L4 is HT_N300_ST subtype LDO regulator.
-L5 and L6 are HT_P600 subtype LDO regulators.
-L7, L11, L12 and L13 are HT_P150 subtype LDO regulators.
-L10 is HT_P50 subtype LDO regulator.
-
-This commit adds support for all of the buck regulators and LDO-s except
-for L10 as I dont have documentation on its output voltage range.
-
-S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores
-and L11 is the SDIO/eMMC I/O voltage regulator required for high speeds.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-7-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -2101,6 +2101,28 @@ static const struct spmi_regulator_data
- 	{ }
- };
- 
-+static const struct spmi_regulator_data pmp8074_regulators[] = {
-+	{ "s1", 0x1400, "vdd_s1"},
-+	{ "s2", 0x1700, "vdd_s2"},
-+	{ "s3", 0x1a00, "vdd_s3"},
-+	{ "s4", 0x1d00, "vdd_s4"},
-+	{ "s5", 0x2000, "vdd_s5"},
-+	{ "l1", 0x4000, "vdd_l1_l2"},
-+	{ "l2", 0x4100, "vdd_l1_l2"},
-+	{ "l3", 0x4200, "vdd_l3_l8"},
-+	{ "l4", 0x4300, "vdd_l4"},
-+	{ "l5", 0x4400, "vdd_l5_l6_l15"},
-+	{ "l6", 0x4500, "vdd_l5_l6_l15"},
-+	{ "l7", 0x4600, "vdd_l7"},
-+	{ "l8", 0x4700, "vdd_l3_l8"},
-+	{ "l9", 0x4800, "vdd_l9"},
-+	/* l10 is currently unsupported HT_P50 */
-+	{ "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
-+	{ "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
-+	{ "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
-+	{ }
-+};
-+
- static const struct spmi_regulator_data pms405_regulators[] = {
- 	{ "s3", 0x1a00, "vdd_s3"},
- 	{ }
-@@ -2117,6 +2139,7 @@ static const struct of_device_id qcom_sp
- 	{ .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
- 	{ .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
- 	{ .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
-+	{ .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
- 	{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
- 	{ }
- };

target/linux/ipq807x/patches-5.15/0035-v6.0-pinctrl-qcom-pmic-gpio-add-support-for-PMP8074.patch

@@ -1,25 +0,0 @@
-From 55545dc54f015387dccfb3c8fe20115c5f21b8a7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Jul 2022 22:34:05 +0200
-Subject: [PATCH 35/44] pinctrl: qcom-pmic-gpio: add support for PMP8074
-
-PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
-+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
-@@ -1167,6 +1167,8 @@ static const struct of_device_id pmic_gp
- 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
- 	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
- 	{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
-+	/* pmp8074 has 12 GPIOs with holes on 1 and 12 */
-+	{ .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
- 	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
- 	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
- 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */

target/linux/ipq807x/patches-5.15/0036-v5.16-mfd-qcom-spmi-pmic-Sort-compatibles-in-the-driver.patch

@@ -1,60 +0,0 @@
-From f76d65737cff6f41f0fab7a46a742d89c08fd652 Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Sun, 17 Oct 2021 09:12:16 -0700
-Subject: [PATCH 36/44] mfd: qcom-spmi-pmic: Sort compatibles in the driver
-
-Sort the compatibles in the driver, to make it easier to validate that
-the DT binding and driver are in sync.
-
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20211017161218.2378176-2-bjorn.andersson@linaro.org
----
- drivers/mfd/qcom-spmi-pmic.c | 30 +++++++++++++++---------------
- 1 file changed, 15 insertions(+), 15 deletions(-)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -40,27 +40,27 @@
- #define PM660_SUBTYPE		0x1B
- 
- static const struct of_device_id pmic_spmi_id_table[] = {
--	{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
--	{ .compatible = "qcom,pm8941",    .data = (void *)PM8941_SUBTYPE },
--	{ .compatible = "qcom,pm8841",    .data = (void *)PM8841_SUBTYPE },
-+	{ .compatible = "qcom,pm660",     .data = (void *)PM660_SUBTYPE },
-+	{ .compatible = "qcom,pm660l",    .data = (void *)PM660L_SUBTYPE },
-+	{ .compatible = "qcom,pm8004",    .data = (void *)PM8004_SUBTYPE },
-+	{ .compatible = "qcom,pm8005",    .data = (void *)PM8005_SUBTYPE },
- 	{ .compatible = "qcom,pm8019",    .data = (void *)PM8019_SUBTYPE },
--	{ .compatible = "qcom,pm8226",    .data = (void *)PM8226_SUBTYPE },
- 	{ .compatible = "qcom,pm8110",    .data = (void *)PM8110_SUBTYPE },
--	{ .compatible = "qcom,pma8084",   .data = (void *)PMA8084_SUBTYPE },
--	{ .compatible = "qcom,pmi8962",   .data = (void *)PMI8962_SUBTYPE },
--	{ .compatible = "qcom,pmd9635",   .data = (void *)PMD9635_SUBTYPE },
--	{ .compatible = "qcom,pm8994",    .data = (void *)PM8994_SUBTYPE },
--	{ .compatible = "qcom,pmi8994",   .data = (void *)PMI8994_SUBTYPE },
--	{ .compatible = "qcom,pm8916",    .data = (void *)PM8916_SUBTYPE },
--	{ .compatible = "qcom,pm8004",    .data = (void *)PM8004_SUBTYPE },
-+	{ .compatible = "qcom,pm8226",    .data = (void *)PM8226_SUBTYPE },
-+	{ .compatible = "qcom,pm8841",    .data = (void *)PM8841_SUBTYPE },
- 	{ .compatible = "qcom,pm8909",    .data = (void *)PM8909_SUBTYPE },
-+	{ .compatible = "qcom,pm8916",    .data = (void *)PM8916_SUBTYPE },
-+	{ .compatible = "qcom,pm8941",    .data = (void *)PM8941_SUBTYPE },
- 	{ .compatible = "qcom,pm8950",    .data = (void *)PM8950_SUBTYPE },
--	{ .compatible = "qcom,pmi8950",   .data = (void *)PMI8950_SUBTYPE },
-+	{ .compatible = "qcom,pm8994",    .data = (void *)PM8994_SUBTYPE },
- 	{ .compatible = "qcom,pm8998",    .data = (void *)PM8998_SUBTYPE },
-+	{ .compatible = "qcom,pma8084",   .data = (void *)PMA8084_SUBTYPE },
-+	{ .compatible = "qcom,pmd9635",   .data = (void *)PMD9635_SUBTYPE },
-+	{ .compatible = "qcom,pmi8950",   .data = (void *)PMI8950_SUBTYPE },
-+	{ .compatible = "qcom,pmi8962",   .data = (void *)PMI8962_SUBTYPE },
-+	{ .compatible = "qcom,pmi8994",   .data = (void *)PMI8994_SUBTYPE },
- 	{ .compatible = "qcom,pmi8998",   .data = (void *)PMI8998_SUBTYPE },
--	{ .compatible = "qcom,pm8005",    .data = (void *)PM8005_SUBTYPE },
--	{ .compatible = "qcom,pm660l",    .data = (void *)PM660L_SUBTYPE },
--	{ .compatible = "qcom,pm660",     .data = (void *)PM660_SUBTYPE },
-+	{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
- 	{ }
- };
- 

target/linux/ipq807x/patches-5.15/0037-v5.16-mfd-qcom-spmi-pmic-Add-missing-PMICs-supported-by-so.patch

@@ -1,66 +0,0 @@
-From b4f85660d09360b2ef9f04e51890fbf9935bf759 Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Sun, 17 Oct 2021 09:12:18 -0700
-Subject: [PATCH 37/44] mfd: qcom-spmi-pmic: Add missing PMICs supported by
- socinfo
-
-The Qualcomm socinfo driver has eight more PMICs described, add these to
-the SPMI PMIC driver as well.
-
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20211017161218.2378176-4-bjorn.andersson@linaro.org
----
- drivers/mfd/qcom-spmi-pmic.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -31,6 +31,8 @@
- #define PM8916_SUBTYPE		0x0b
- #define PM8004_SUBTYPE		0x0c
- #define PM8909_SUBTYPE		0x0d
-+#define PM8028_SUBTYPE		0x0e
-+#define PM8901_SUBTYPE		0x0f
- #define PM8950_SUBTYPE		0x10
- #define PMI8950_SUBTYPE		0x11
- #define PM8998_SUBTYPE		0x14
-@@ -38,6 +40,13 @@
- #define PM8005_SUBTYPE		0x18
- #define PM660L_SUBTYPE		0x1A
- #define PM660_SUBTYPE		0x1B
-+#define PM8150_SUBTYPE		0x1E
-+#define PM8150L_SUBTYPE		0x1f
-+#define PM8150B_SUBTYPE		0x20
-+#define PMK8002_SUBTYPE		0x21
-+#define PM8009_SUBTYPE		0x24
-+#define PM8150C_SUBTYPE		0x26
-+#define SMB2351_SUBTYPE		0x29
- 
- static const struct of_device_id pmic_spmi_id_table[] = {
- 	{ .compatible = "qcom,pm660",     .data = (void *)PM660_SUBTYPE },
-@@ -45,9 +54,15 @@ static const struct of_device_id pmic_sp
- 	{ .compatible = "qcom,pm8004",    .data = (void *)PM8004_SUBTYPE },
- 	{ .compatible = "qcom,pm8005",    .data = (void *)PM8005_SUBTYPE },
- 	{ .compatible = "qcom,pm8019",    .data = (void *)PM8019_SUBTYPE },
-+	{ .compatible = "qcom,pm8028",    .data = (void *)PM8028_SUBTYPE },
- 	{ .compatible = "qcom,pm8110",    .data = (void *)PM8110_SUBTYPE },
-+	{ .compatible = "qcom,pm8150",    .data = (void *)PM8150_SUBTYPE },
-+	{ .compatible = "qcom,pm8150b",   .data = (void *)PM8150B_SUBTYPE },
-+	{ .compatible = "qcom,pm8150c",   .data = (void *)PM8150C_SUBTYPE },
-+	{ .compatible = "qcom,pm8150l",   .data = (void *)PM8150L_SUBTYPE },
- 	{ .compatible = "qcom,pm8226",    .data = (void *)PM8226_SUBTYPE },
- 	{ .compatible = "qcom,pm8841",    .data = (void *)PM8841_SUBTYPE },
-+	{ .compatible = "qcom,pm8901",    .data = (void *)PM8901_SUBTYPE },
- 	{ .compatible = "qcom,pm8909",    .data = (void *)PM8909_SUBTYPE },
- 	{ .compatible = "qcom,pm8916",    .data = (void *)PM8916_SUBTYPE },
- 	{ .compatible = "qcom,pm8941",    .data = (void *)PM8941_SUBTYPE },
-@@ -60,6 +75,8 @@ static const struct of_device_id pmic_sp
- 	{ .compatible = "qcom,pmi8962",   .data = (void *)PMI8962_SUBTYPE },
- 	{ .compatible = "qcom,pmi8994",   .data = (void *)PMI8994_SUBTYPE },
- 	{ .compatible = "qcom,pmi8998",   .data = (void *)PMI8998_SUBTYPE },
-+	{ .compatible = "qcom,pmk8002",   .data = (void *)PMK8002_SUBTYPE },
-+	{ .compatible = "qcom,smb2351",   .data = (void *)SMB2351_SUBTYPE },
- 	{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
- 	{ }
- };

target/linux/ipq807x/patches-5.15/0038-v6.0-iio-adc-qcom-spmi-adc5-add-ADC5_VREF_VADC-to-rev2-AD.patch

@@ -1,27 +0,0 @@
-From 1aa9a70ca9a1d3bb5139030fd9fc340d8525a7d7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:13 +0200
-Subject: [PATCH 38/44] iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2
- ADC5
-
-Add support for ADC5_VREF_VADC channel to rev2 ADC5 channel list.
-This channel measures the VADC reference LDO output.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220818221815.346233-3-robimarko@gmail.com
-Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
----
- drivers/iio/adc/qcom-spmi-adc5.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/iio/adc/qcom-spmi-adc5.c
-+++ b/drivers/iio/adc/qcom-spmi-adc5.c
-@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_c
- 					SCALE_HW_CALIB_DEFAULT)
- 	[ADC5_1P25VREF]		= ADC5_CHAN_VOLT("vref_1p25", 0,
- 					SCALE_HW_CALIB_DEFAULT)
-+	[ADC5_VREF_VADC]	= ADC5_CHAN_VOLT("vref_vadc", 0,
-+					SCALE_HW_CALIB_DEFAULT)
- 	[ADC5_VPH_PWR]		= ADC5_CHAN_VOLT("vph_pwr", 1,
- 					SCALE_HW_CALIB_DEFAULT)
- 	[ADC5_VBAT_SNS]		= ADC5_CHAN_VOLT("vbat_sns", 1,

target/linux/ipq807x/patches-5.15/0039-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch

@@ -1,47 +0,0 @@
-From 8454872e52992108308e44aa974b441558fa1fc9 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 23 Aug 2022 22:43:51 +0200
-Subject: [PATCH 39/44] phy: qcom-qmp-pcie: make pipe clock rate configurable
-
-IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
-like every other PCIe QMP PHY does, so make it configurable as part of the
-qmp_phy_cfg.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
-@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
- 	/* true, if PHY has secondary tx/rx lanes to be configured */
- 	bool is_dual_lane_phy;
- 
-+	/* QMP PHY pipe clock interface rate */
-+	unsigned long pipe_clock_rate;
-+
- 	/* true, if PCS block has no separate SW_RESET register */
- 	bool no_pcs_sw_reset;
- };
-@@ -5138,8 +5141,15 @@ static int phy_pipe_clk_register(struct
- 
- 	init.ops = &clk_fixed_rate_ops;
- 
--	/* controllers using QMP phys use 125MHz pipe clock interface */
--	fixed->fixed_rate = 125000000;
-+	/*
-+	 * Controllers using QMP PHY-s use 125MHz pipe clock interface
-+	 * unless other frequency is specified in the PHY config.
-+	 */
-+	if (qmp->phys[0]->cfg->pipe_clock_rate)
-+		fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
-+	else
-+		fixed->fixed_rate = 125000000;
-+
- 	fixed->hw.init = &init;
- 
- 	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);

target/linux/ipq807x/patches-5.15/0040-v6.0-phy-qcom-qmp-pcie-add-IPQ8074-PCIe-Gen3-QMP-PHY-supp.patch

@@ -1,201 +0,0 @@
-From 6702bed8d48e29bd51c4b702b0baf18c5b1814c1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 23 Aug 2022 22:47:40 +0200
-Subject: [PATCH 40/44] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY
- support
-
-IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
-Gen2 one is already supported, so add the support for the Gen3 one.
-It uses the same register layout as IPQ6018.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++
- 1 file changed, 160 insertions(+)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
-@@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq
- 	QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
- };
- 
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
-+	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
-+	QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+	QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+	QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
-+	QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
-+	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
-+	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
-+	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
-+	QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
-+	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
-+	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
-+	QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+	QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+	QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+};
-+
- static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
- 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
- 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-@@ -3167,6 +3294,36 @@ static const struct qmp_phy_cfg ipq8074_
- 	.pwrdn_delay_max	= 1005,		/* us */
- };
- 
-+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
-+	.type			= PHY_TYPE_PCIE,
-+	.nlanes			= 1,
-+
-+	.serdes_tbl		= ipq8074_pcie_gen3_serdes_tbl,
-+	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
-+	.tx_tbl			= ipq8074_pcie_gen3_tx_tbl,
-+	.tx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
-+	.rx_tbl			= ipq8074_pcie_gen3_rx_tbl,
-+	.rx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
-+	.pcs_tbl		= ipq8074_pcie_gen3_pcs_tbl,
-+	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
-+	.clk_list		= ipq8074_pciephy_clk_l,
-+	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+	.reset_list		= ipq8074_pciephy_reset_l,
-+	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+	.vreg_list		= NULL,
-+	.num_vregs		= 0,
-+	.regs			= ipq_pciephy_gen3_regs_layout,
-+
-+	.start_ctrl		= SERDES_START | PCS_START,
-+	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+	.has_pwrdn_delay	= true,
-+	.pwrdn_delay_min	= 995,		/* us */
-+	.pwrdn_delay_max	= 1005,		/* us */
-+
-+	.pipe_clock_rate	= 250000000,
-+};
-+
- static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
- 	.type			= PHY_TYPE_PCIE,
- 	.nlanes			= 1,
-@@ -5543,6 +5700,9 @@ static const struct of_device_id qcom_qm
- 		.compatible = "qcom,ipq8074-qmp-pcie-phy",
- 		.data = &ipq8074_pciephy_cfg,
- 	}, {
-+		.compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
-+		.data = &ipq8074_pciephy_gen3_cfg,
-+	}, {
- 		.compatible = "qcom,ipq6018-qmp-pcie-phy",
- 		.data = &ipq6018_pciephy_cfg,
- 	}, {

target/linux/ipq807x/patches-5.15/0045-v5.17-mtd-parsers-qcom-Don-t-print-error-message-on-EPROBE.patch

@@ -1,32 +0,0 @@
-From 9fbfce710333c5ee674a5cad4cbb12ea5f969769 Mon Sep 17 00:00:00 2001
-From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
-Date: Mon, 3 Jan 2022 03:03:16 +0000
-Subject: [PATCH] mtd: parsers: qcom: Don't print error message on
- -EPROBE_DEFER
-
-Its possible for the main smem driver to not be loaded by the time we come
-along to parse the smem partition description but, this is a perfectly
-normal thing.
-
-No need to print out an error message in this case.
-
-Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
-Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220103030316.58301-3-bryan.odonoghue@linaro.org
----
- drivers/mtd/parsers/qcomsmempart.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/parsers/qcomsmempart.c
-+++ b/drivers/mtd/parsers/qcomsmempart.c
-@@ -75,7 +75,8 @@ static int parse_qcomsmem_part(struct mt
- 	pr_debug("Parsing partition table info from SMEM\n");
- 	ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
- 	if (IS_ERR(ptable)) {
--		pr_err("Error reading partition table header\n");
-+		if (PTR_ERR(ptable) != -EPROBE_DEFER)
-+			pr_err("Error reading partition table header\n");
- 		return PTR_ERR(ptable);
- 	}
- 

target/linux/ipq807x/patches-5.15/0101-arm64-dts-ipq8074-add-reserved-memory-nodes.patch

@@ -1,7 +1,7 @@
-From 2dc8319c43ccc511a38f441ab4f7aa120af9a9fb Mon Sep 17 00:00:00 2001
+From 4b6d5caa1747bbe0eca15d4d20f028748c544cd0 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Wed, 22 Dec 2021 12:23:34 +0100
-Subject: [PATCH 100/137] arm64: dts: ipq8074: add reserved memory nodes
+Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
 
 IPQ8074 has multiple reserved memory ranges, if they are not defined
 then weird things tend to happen, board hangs and resets when PCI or
@@ -14,12 +14,14 @@ devices with lower ammounts can override the Q6 node.
 
 Signed-off-by: Robert Marko <robimarko@gmail.com>
 ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 40 +++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
+ 1 file changed, 40 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index adce47affbef..94de2bd6596f 100644
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -85,6 +85,26 @@
+@@ -81,6 +81,31 @@ reserved-memory {
  		#size-cells = <2>;
  		ranges;
  
@@ -42,13 +44,18 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 +			no-map;
 +			reg = <0x0 0x4aa00000 0x0 0x00100000>;
 +		};
++
++		tz@4ac00000 {
++			no-map;
++			reg = <0x0 0x4ac00000 0x0 0x00400000>;
++		};
 +
  		smem@4ab00000 {
  			compatible = "qcom,smem";
  			reg = <0x0 0x4ab00000 0x0 0x00100000>;
-@@ -97,6 +117,21 @@
+@@ -88,6 +113,21 @@ smem@4ab00000 {
- 			no-map;
+ 
- 			reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ 			hwlocks = <&tcsr_mutex 0>;
  		};
 +
 +		q6_region: wcnss@4b000000 {
@@ -68,3 +75,6 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  	};
  
  	firmware {
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch

@@ -1,49 +0,0 @@
-From 9d38e110e23ce0b858ccd67a8a819dc187529a33 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 8 Jul 2022 23:24:25 +0200
-Subject: [PATCH 101/137] clk: qcom: clk-rcg2: add rcg2 mux ops
-
-An RCG may act as a mux that switch between 2 parents.
-This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
-the CPU cluster clock just switches between XO and the PLL that feeds it.
-
-Add the required ops to add support for this special configuration and use
-the generic mux function to determine the rate.
-
-This way we dont have to keep a essentially dummy frequency table to use
-RCG2 as a mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
----
- drivers/clk/qcom/clk-rcg.h  | 1 +
- drivers/clk/qcom/clk-rcg2.c | 7 +++++++
- 2 files changed, 8 insertions(+)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
- 
- extern const struct clk_ops clk_rcg2_ops;
- extern const struct clk_ops clk_rcg2_floor_ops;
-+extern const struct clk_ops clk_rcg2_mux_closest_ops;
- extern const struct clk_ops clk_edp_pixel_ops;
- extern const struct clk_ops clk_byte_ops;
- extern const struct clk_ops clk_byte2_ops;
---- a/drivers/clk/qcom/clk-rcg2.c
-+++ b/drivers/clk/qcom/clk-rcg2.c
-@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
- };
- EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
- 
-+const struct clk_ops clk_rcg2_mux_closest_ops = {
-+	.determine_rate = __clk_mux_determine_rate_closest,
-+	.get_parent = clk_rcg2_get_parent,
-+	.set_parent = clk_rcg2_set_parent,
-+};
-+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
-+
- struct frac_entry {
- 	int num;
- 	int den;

target/linux/ipq807x/patches-5.15/0102-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch

@@ -1,61 +0,0 @@
-From d2b31da4eae2175ff86f28f596b54abde08d382f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 9 Jul 2022 00:18:45 +0200
-Subject: [PATCH 102/137] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
-
-While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
-IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
-currently broken.
-
-More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
-clock.
-However after debugging why it was always stuck at 800Mhz, it was figured
-out that its not regmap_mux compatible at all.
-It is a simple mux but it uses RCG2 register layout and control bits, so
-utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
-having to provide a dummy frequency table.
-
-While we are here, use ARRAY_SIZE for number of parents.
-
-Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
-
-Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
----
- drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq6018.c
-+++ b/drivers/clk/qcom/apss-ipq6018.c
-@@ -16,7 +16,7 @@
- #include "clk-regmap.h"
- #include "clk-branch.h"
- #include "clk-alpha-pll.h"
--#include "clk-regmap-mux.h"
-+#include "clk-rcg.h"
- 
- enum {
- 	P_XO,
-@@ -33,16 +33,15 @@ static const struct parent_map parents_a
- 	{ P_APSS_PLL_EARLY, 5 },
- };
- 
--static struct clk_regmap_mux apcs_alias0_clk_src = {
--	.reg = 0x0050,
--	.width = 3,
--	.shift = 7,
-+static struct clk_rcg2 apcs_alias0_clk_src = {
-+	.cmd_rcgr = 0x0050,
-+	.hid_width = 5,
- 	.parent_map = parents_apcs_alias0_clk_src_map,
- 	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "apcs_alias0_clk_src",
- 		.parent_data = parents_apcs_alias0_clk_src,
--		.num_parents = 2,
--		.ops = &clk_regmap_mux_closest_ops,
-+		.num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
-+		.ops = &clk_rcg2_mux_closest_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	},
- };

target/linux/ipq807x/patches-5.15/0103-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch

@@ -0,0 +1,377 @@
+From 6fe752e3927ee9d9cad6ad197d5fe58c23a61935 Mon Sep 17 00:00:00 2001
+From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
+Date: Wed, 29 Jul 2020 21:00:04 +0530
+Subject: [PATCH] phy: qcom-qmp: Add IPQ8074 PCIe Gen3 QMP PHY support
+
+IPQ8074 has two PCIe ports, One Gen2 and one Gen3 port.
+Since support for Gen2 PHY is already available, add support for
+PCIe Gen3 PHY.
+
+Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
+Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
+Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 ++++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp.c       | 171 +++++++++++++++++++++-
+ 2 files changed, 308 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
+new file mode 100644
+index 000000000000..070bde355836
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
+@@ -0,0 +1,139 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++/*
++ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
++ */
++
++#ifndef PHY_QCOM_PCIE_H
++#define PHY_QCOM_PCIE_H
++
++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */
++#define QSERDES_PLL_BG_TIMER				0x00c
++#define QSERDES_PLL_SSC_PER1				0x01c
++#define QSERDES_PLL_SSC_PER2				0x020
++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0		0x024
++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0		0x028
++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1		0x02c
++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1		0x030
++#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN			0x03c
++#define QSERDES_PLL_CLK_ENABLE1				0x040
++#define QSERDES_PLL_SYS_CLK_CTRL			0x044
++#define QSERDES_PLL_SYSCLK_BUF_ENABLE			0x048
++#define QSERDES_PLL_PLL_IVCO				0x050
++#define QSERDES_PLL_LOCK_CMP1_MODE0			0x054
++#define QSERDES_PLL_LOCK_CMP2_MODE0			0x058
++#define QSERDES_PLL_LOCK_CMP1_MODE1			0x060
++#define QSERDES_PLL_LOCK_CMP2_MODE1			0x064
++#define QSERDES_PLL_BG_TRIM				0x074
++#define QSERDES_PLL_CLK_EP_DIV_MODE0			0x078
++#define QSERDES_PLL_CLK_EP_DIV_MODE1			0x07c
++#define QSERDES_PLL_CP_CTRL_MODE0			0x080
++#define QSERDES_PLL_CP_CTRL_MODE1			0x084
++#define QSERDES_PLL_PLL_RCTRL_MODE0			0x088
++#define QSERDES_PLL_PLL_RCTRL_MODE1			0x08C
++#define QSERDES_PLL_PLL_CCTRL_MODE0			0x090
++#define QSERDES_PLL_PLL_CCTRL_MODE1			0x094
++#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x0a4
++#define QSERDES_PLL_SYSCLK_EN_SEL			0x0a8
++#define QSERDES_PLL_RESETSM_CNTRL			0x0b0
++#define QSERDES_PLL_LOCK_CMP_EN				0x0c4
++#define QSERDES_PLL_DEC_START_MODE0			0x0cc
++#define QSERDES_PLL_DEC_START_MODE1			0x0d0
++#define QSERDES_PLL_DIV_FRAC_START1_MODE0		0x0d8
++#define QSERDES_PLL_DIV_FRAC_START2_MODE0		0x0dc
++#define QSERDES_PLL_DIV_FRAC_START3_MODE0		0x0e0
++#define QSERDES_PLL_DIV_FRAC_START1_MODE1		0x0e4
++#define QSERDES_PLL_DIV_FRAC_START2_MODE1		0x0e8
++#define QSERDES_PLL_DIV_FRAC_START3_MODE1		0x0eC
++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0		0x100
++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0		0x104
++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1		0x108
++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1		0x10c
++#define QSERDES_PLL_VCO_TUNE_MAP			0x120
++#define QSERDES_PLL_VCO_TUNE1_MODE0			0x124
++#define QSERDES_PLL_VCO_TUNE2_MODE0			0x128
++#define QSERDES_PLL_VCO_TUNE1_MODE1			0x12c
++#define QSERDES_PLL_VCO_TUNE2_MODE1			0x130
++#define QSERDES_PLL_VCO_TUNE_TIMER1			0x13c
++#define QSERDES_PLL_VCO_TUNE_TIMER2			0x140
++#define QSERDES_PLL_CLK_SELECT				0x16c
++#define QSERDES_PLL_HSCLK_SEL				0x170
++#define QSERDES_PLL_CORECLK_DIV				0x17c
++#define QSERDES_PLL_CORE_CLK_EN				0x184
++#define QSERDES_PLL_CMN_CONFIG				0x18c
++#define QSERDES_PLL_SVS_MODE_CLK_SEL			0x194
++#define QSERDES_PLL_CORECLK_DIV_MODE1			0x1b4
++
++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */
++#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX		0x03c
++#define QSERDES_TX0_HIGHZ_DRVR_EN			0x058
++#define QSERDES_TX0_LANE_MODE_1				0x084
++#define QSERDES_TX0_RCV_DETECT_LVL_2			0x09c
++
++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */
++#define QSERDES_RX0_UCDR_FO_GAIN			0x008
++#define QSERDES_RX0_UCDR_SO_GAIN			0x014
++#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE	0x034
++#define QSERDES_RX0_UCDR_PI_CONTROLS			0x044
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2		0x0ec
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3		0x0f0
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4		0x0f4
++#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW			0x0f8
++#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH		0x0fc
++#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x110
++#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2		0x114
++#define QSERDES_RX0_SIGDET_ENABLES			0x118
++#define QSERDES_RX0_SIGDET_CNTRL			0x11c
++#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL		0x124
++#define QSERDES_RX0_RX_MODE_00_LOW			0x170
++#define QSERDES_RX0_RX_MODE_00_HIGH			0x174
++#define QSERDES_RX0_RX_MODE_00_HIGH2			0x178
++#define QSERDES_RX0_RX_MODE_00_HIGH3			0x17c
++#define QSERDES_RX0_RX_MODE_00_HIGH4			0x180
++#define QSERDES_RX0_RX_MODE_01_LOW			0x184
++#define QSERDES_RX0_RX_MODE_01_HIGH			0x188
++#define QSERDES_RX0_RX_MODE_01_HIGH2			0x18c
++#define QSERDES_RX0_RX_MODE_01_HIGH3			0x190
++#define QSERDES_RX0_RX_MODE_01_HIGH4			0x194
++#define QSERDES_RX0_RX_MODE_10_LOW			0x198
++#define QSERDES_RX0_RX_MODE_10_HIGH			0x19c
++#define QSERDES_RX0_RX_MODE_10_HIGH2			0x1a0
++#define QSERDES_RX0_RX_MODE_10_HIGH3			0x1a4
++#define QSERDES_RX0_RX_MODE_10_HIGH4			0x1a8
++#define QSERDES_RX0_DFE_EN_TIMER			0x1b4
++
++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS registers */
++
++#define PCS_COM_FLL_CNTRL1				0x098
++#define PCS_COM_FLL_CNTRL2				0x09c
++#define PCS_COM_FLL_CNT_VAL_L				0x0a0
++#define PCS_COM_FLL_CNT_VAL_H_TOL			0x0a4
++#define PCS_COM_FLL_MAN_CODE				0x0a8
++#define PCS_COM_REFGEN_REQ_CONFIG1			0x0dc
++#define PCS_COM_G12S1_TXDEEMPH_M3P5DB			0x16c
++#define PCS_COM_RX_SIGDET_LVL				0x188
++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4
++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8
++#define PCS_COM_RX_DCC_CAL_CONFIG			0x1d8
++#define PCS_COM_EQ_CONFIG5				0x1ec
++
++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS Misc registers */
++
++#define PCS_PCIE_POWER_STATE_CONFIG2			0x40c
++#define PCS_PCIE_POWER_STATE_CONFIG4			0x414
++#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE			0x41c
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L		0x440
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H		0x444
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L		0x448
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H		0x44c
++#define PCS_PCIE_OSC_DTCT_CONFIG2			0x45c
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2			0x478
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4			0x480
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5			0x484
++#define PCS_PCIE_OSC_DTCT_ACTIONS			0x490
++#define PCS_PCIE_EQ_CONFIG1				0x4a0
++#define PCS_PCIE_EQ_CONFIG2				0x4a4
++#define PCS_PCIE_PRESET_P10_PRE				0x4bc
++#define PCS_PCIE_PRESET_P10_POST			0x4e0
++
++#endif
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
+index 06b04606dd7e..7d139754889a 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
+@@ -23,6 +23,7 @@
+ #include <dt-bindings/phy/phy.h>
+ 
+ #include "phy-qcom-qmp.h"
++#include "phy-qcom-pcie3-qmp.h"
+ 
+ /* QPHY_SW_RESET bit */
+ #define SW_RESET				BIT(0)
+@@ -812,6 +813,132 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
+ 	QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
+ };
+ 
++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++	QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
++	QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
++	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
++	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
++	QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++	QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++	QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++};
+ static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+ 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+@@ -3194,6 +3321,36 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
+ 	.pwrdn_delay_max	= 1005,		/* us */
+ };
+ 
++static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
++	.type			= PHY_TYPE_PCIE,
++	.nlanes			= 1,
++
++	.serdes_tbl		= ipq8074_pcie_gen3_serdes_tbl,
++	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
++	.tx_tbl			= ipq8074_pcie_gen3_tx_tbl,
++	.tx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
++	.rx_tbl			= ipq8074_pcie_gen3_rx_tbl,
++	.rx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
++	.pcs_tbl		= ipq8074_pcie_gen3_pcs_tbl,
++	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
++	.clk_list		= ipq8074_pciephy_clk_l,
++	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),
++	.reset_list		= ipq8074_pciephy_reset_l,
++	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),
++	.vreg_list		= NULL,
++	.num_vregs		= 0,
++	.regs			= qmp_v4_usb3phy_regs_layout,
++
++	.start_ctrl		= SERDES_START | PCS_START,
++	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
++
++	.has_phy_com_ctrl	= false,
++	.has_lane_rst		= false,
++	.has_pwrdn_delay	= true,
++	.pwrdn_delay_min	= 995,		/* us */
++	.pwrdn_delay_max	= 1005,		/* us */
++};
++
+ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
+ 	.type = PHY_TYPE_PCIE,
+ 	.nlanes = 1,
+@@ -5138,8 +5295,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
+ 
+ 	init.ops = &clk_fixed_rate_ops;
+ 
+-	/* controllers using QMP phys use 125MHz pipe clock interface */
+-	fixed->fixed_rate = 125000000;
++	/*
++	 * controllers using QMP phys use 125MHz pipe clock interface unless
++	 * other frequency is specified in dts
++	 */
++	ret = of_property_read_u32(np, "clock-output-rate",
++				   (u32 *)&fixed->fixed_rate);
++	if (ret)
++		fixed->fixed_rate = 125000000;
++
+ 	fixed->hw.init = &init;
+ 
+ 	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
+@@ -5529,6 +5693,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ 	}, {
+ 		.compatible = "qcom,ipq6018-qmp-usb3-phy",
+ 		.data = &ipq8074_usb3phy_cfg,
++	}, {
++		.compatible = "qcom,ipq8074-qmp-pcie-gen3-phy",
++		.data = &ipq8074_pciephy_gen3_cfg,
+ 	}, {
+ 		.compatible = "qcom,sc7180-qmp-usb3-phy",
+ 		.data = &sc7180_usb3phy_cfg,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch

@@ -1,21 +1,21 @@
-From 4f0959ded385c8ed518659aa08cedbd83ae0726a Mon Sep 17 00:00:00 2001
+From 110bec39320cbfd23ac869af4aa231cda9c5f74a Mon Sep 17 00:00:00 2001
 From: Kathiravan T <quic_kathirav@quicinc.com>
 Date: Tue, 8 Feb 2022 21:05:24 +0530
-Subject: [PATCH 11/44] arm64: dts: qcom: ipq8074: enable the GICv2m support
+Subject: [PATCH] arm64: dts: qcom: ipq8074: enable the GICv2m support
 
 GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
 which supports upto 32 MSI interrupts. Lets add support for the same.
 
 Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
 ---
  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index 452a81d288f4..777c6267e777 100644
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -634,9 +634,18 @@
+@@ -669,9 +669,18 @@ dwc_1: dwc3@8c00000 {
  
  		intc: interrupt-controller@b000000 {
  			compatible = "qcom,msm-qgic2";
@@ -34,3 +34,6 @@ Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@
  		};
  
  		timer {
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0104-clk-qcom-apss-ipq-pll-use-OF-match-data-for-Alpha-PL.patch

@@ -1,68 +0,0 @@
-From 8878f39722eeacbb40babe82ad763d8d20214018 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 9 Jul 2022 00:32:04 +0200
-Subject: [PATCH 104/137] clk: qcom: apss-ipq-pll: use OF match data for Alpha
- PLL config
-
-Convert the driver to use OF match data for providing the Alpha PLL config
-per compatible.
-This is required for IPQ8074 support since it uses a different Alpha PLL
-config.
-
-While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make
-it clear that it is for IPQ6018 only.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/apss-ipq-pll.c | 12 +++++++++---
- 1 file changed, 9 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -2,6 +2,7 @@
- // Copyright (c) 2018, The Linux Foundation. All rights reserved.
- #include <linux/clk-provider.h>
- #include <linux/module.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
- 
-@@ -36,7 +37,7 @@ static struct clk_alpha_pll ipq_pll = {
- 	},
- };
- 
--static const struct alpha_pll_config ipq_pll_config = {
-+static const struct alpha_pll_config ipq6018_pll_config = {
- 	.l = 0x37,
- 	.config_ctl_val = 0x04141200,
- 	.config_ctl_hi_val = 0x0,
-@@ -54,6 +55,7 @@ static const struct regmap_config ipq_pl
- 
- static int apss_ipq_pll_probe(struct platform_device *pdev)
- {
-+	const struct alpha_pll_config *ipq_pll_config;
- 	struct device *dev = &pdev->dev;
- 	struct regmap *regmap;
- 	void __iomem *base;
-@@ -67,7 +69,11 @@ static int apss_ipq_pll_probe(struct pla
- 	if (IS_ERR(regmap))
- 		return PTR_ERR(regmap);
- 
--	clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
-+	ipq_pll_config = of_device_get_match_data(&pdev->dev);
-+	if (!ipq_pll_config)
-+		return -ENODEV;
-+
-+	clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
- 
- 	ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
- 	if (ret)
-@@ -78,7 +84,7 @@ static int apss_ipq_pll_probe(struct pla
- }
- 
- static const struct of_device_id apss_ipq_pll_match_table[] = {
--	{ .compatible = "qcom,ipq6018-a53pll" },
-+	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch

@@ -1,8 +1,8 @@
-From 66dafdaad281e0a0eb2045ffb1f8dcf72e25989f Mon Sep 17 00:00:00 2001
+From dae5693368998da74d3a460da739677c02c9c6af Mon Sep 17 00:00:00 2001
 From: Baruch Siach <baruch.siach@siklu.com>
 Date: Mon, 7 Feb 2022 16:51:24 +0200
-Subject: [PATCH 42/44] PCI: dwc: tegra: move GEN3_RELATED DBI register to
+Subject: [PATCH] PCI: dwc: tegra: move GEN3_RELATED DBI register to common
- common header
+ header
 
 These are common dwc macros that will be used for other platforms.
 
@@ -13,6 +13,8 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  drivers/pci/controller/dwc/pcie-tegra194.c   | 6 ------
  2 files changed, 6 insertions(+), 6 deletions(-)
 
+diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
+index 7d6e9b7576be..ea87809ee298 100644
 --- a/drivers/pci/controller/dwc/pcie-designware.h
 +++ b/drivers/pci/controller/dwc/pcie-designware.h
 @@ -74,6 +74,12 @@
@@ -28,6 +30,8 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  #define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
  #define PORT_MLTI_UPCFG_SUPPORT		BIT(7)
  
+diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
+index 904976913081..846c9d154f49 100644
 --- a/drivers/pci/controller/dwc/pcie-tegra194.c
 +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
 @@ -193,12 +193,6 @@
@@ -43,3 +47,6 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT	0x8D0
  #define AMBA_ERROR_RESPONSE_CRS_SHIFT		3
  #define AMBA_ERROR_RESPONSE_CRS_MASK		GENMASK(1, 0)
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0105-clk-qcom-apss-ipq-pll-update-IPQ6018-Alpha-PLL-confi.patch

@@ -1,38 +0,0 @@
-From 426edd7e45e9eaf18c433739ceeb51e6f2f8e190 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Jul 2022 22:40:52 +0200
-Subject: [PATCH 105/137] clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL
- config
-
-Update the IPQ6018 Alpha PLL config to the latest one from the downstream
-5.4 kernel[1].
-
-This one should match the production SoC-s.
-
-Tested on IPQ6018 CP01-C1 reference board.
-
-[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/apss-ipq-pll.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -39,10 +39,14 @@ static struct clk_alpha_pll ipq_pll = {
- 
- static const struct alpha_pll_config ipq6018_pll_config = {
- 	.l = 0x37,
--	.config_ctl_val = 0x04141200,
--	.config_ctl_hi_val = 0x0,
-+	.config_ctl_val = 0x240d4828,
-+	.config_ctl_hi_val = 0x6,
- 	.early_output_mask = BIT(3),
-+	.aux2_output_mask = BIT(2),
-+	.aux_output_mask = BIT(1),
- 	.main_output_mask = BIT(0),
-+	.test_ctl_val = 0x1c0000C0,
-+	.test_ctl_hi_val = 0x4000,
- };
- 
- static const struct regmap_config ipq_pll_regmap_config = {

target/linux/ipq807x/patches-5.15/0106-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch

@@ -1,8 +1,7 @@
-From 55299da8c17f23249497ee8868a5a268c6e3fbcc Mon Sep 17 00:00:00 2001
+From 70261569da66997eb4c6057b136af417ed06716e Mon Sep 17 00:00:00 2001
 From: Baruch Siach <baruch.siach@siklu.com>
 Date: Mon, 7 Feb 2022 16:51:25 +0200
-Subject: [PATCH 43/44] PCI: qcom: Define slot capabilities using
+Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
- PCI_EXP_SLTCAP_*
 
 The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
 PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
@@ -13,6 +12,8 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
  1 file changed, 13 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
+index 8a7a300163e5..f5101258d73b 100644
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
 @@ -69,7 +69,18 @@
@@ -35,7 +36,7 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  
  #define PCIE20_PARF_Q2A_FLUSH			0x1AC
  
-@@ -1125,7 +1136,7 @@ static int qcom_pcie_post_init_2_3_3(str
+@@ -1102,7 +1113,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
  
  	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
  	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
@@ -44,3 +45,6 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  
  	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
  	val &= ~PCI_EXP_LNKCAP_ASPMS;
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0106-clk-qcom-apss-ipq-pll-add-support-for-IPQ8074.patch

@@ -1,51 +0,0 @@
-From c633afe32123157370f21aeaf3d705ca584fc754 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Jul 2022 14:23:08 +0200
-Subject: [PATCH 106/137] clk: qcom: apss-ipq-pll: add support for IPQ8074
-
-Add support for IPQ8074 since it uses the same PLL setup, however it uses
-slightly different Alpha PLL config.
-
-Alpha PLL config was obtained by dumping PLL registers from a running
-device.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
-Changes in v2:
-* Drop hardcoded compatible check for IPQ6018 to do the PLL config and
-utilize match data provided by previous commit
-* Add IPQ8074 Alpha PLL config using match data
-* Update commit description to reflect changes
----
- drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -49,6 +49,18 @@ static const struct alpha_pll_config ipq
- 	.test_ctl_hi_val = 0x4000,
- };
- 
-+static const struct alpha_pll_config ipq8074_pll_config = {
-+	.l = 0x48,
-+	.config_ctl_val = 0x200d4828,
-+	.config_ctl_hi_val = 0x6,
-+	.early_output_mask = BIT(3),
-+	.aux2_output_mask = BIT(2),
-+	.aux_output_mask = BIT(1),
-+	.main_output_mask = BIT(0),
-+	.test_ctl_val = 0x1c000000,
-+	.test_ctl_hi_val = 0x4000,
-+};
-+
- static const struct regmap_config ipq_pll_regmap_config = {
- 	.reg_bits		= 32,
- 	.reg_stride		= 4,
-@@ -89,6 +101,7 @@ static int apss_ipq_pll_probe(struct pla
- 
- static const struct of_device_id apss_ipq_pll_match_table[] = {
- 	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
-+	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-IPQ60xx-support.patch

@@ -1,7 +1,7 @@
-From b9d02fcefdf166671356a08dd621429e63541b22 Mon Sep 17 00:00:00 2001
+From 5d15adca10588019810505a07ed3f6758e4413be Mon Sep 17 00:00:00 2001
 From: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
 Date: Thu, 10 Feb 2022 18:02:47 +0100
-Subject: [PATCH 44/44] PCI: qcom: Add IPQ60xx support
+Subject: [PATCH] PCI: qcom: Add IPQ60xx support
 
 IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
 platform.
@@ -21,6 +21,8 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  drivers/pci/controller/dwc/pcie-qcom.c       | 135 +++++++++++++++++++
  2 files changed, 136 insertions(+)
 
+diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
+index ea87809ee298..279c3778a13b 100644
 --- a/drivers/pci/controller/dwc/pcie-designware.h
 +++ b/drivers/pci/controller/dwc/pcie-designware.h
 @@ -76,6 +76,7 @@
@@ -31,6 +33,8 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
  #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
  #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
+diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
+index f5101258d73b..05359cfc0e34 100644
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
 @@ -52,6 +52,10 @@
@@ -64,7 +68,7 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  };
  
  struct qcom_pcie;
-@@ -1276,6 +1286,121 @@ static void qcom_pcie_post_deinit_2_7_0(
+@@ -1277,6 +1287,121 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
  	clk_disable_unprepare(res->pipe_clk);
  }
  
@@ -186,7 +190,7 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  static int qcom_pcie_link_up(struct dw_pcie *pci)
  {
  	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
-@@ -1467,6 +1592,15 @@ static const struct qcom_pcie_ops ops_1_
+@@ -1467,6 +1592,15 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
  	.config_sid = qcom_pcie_config_sid_sm8250,
  };
  
@@ -202,7 +206,7 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  static const struct dw_pcie_ops dw_pcie_ops = {
  	.link_up = qcom_pcie_link_up,
  	.start_link = qcom_pcie_start_link,
-@@ -1565,6 +1699,7 @@ static const struct of_device_id qcom_pc
+@@ -1566,6 +1700,7 @@ static const struct of_device_id qcom_pcie_match[] = {
  	{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
  	{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
  	{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
@@ -210,3 +214,6 @@ Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  	{ }
  };
  
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0107-arm64-dts-qcom-ipq8074-correct-APCS-register-space-s.patch

@@ -1,31 +0,0 @@
-From f3d524334069e69554eaecd8adf75284dff7c9d9 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 18 Aug 2022 23:15:43 +0200
-Subject: [PATCH 107/137] arm64: dts: qcom: ipq8074: correct APCS register
- space size
-
-APCS DTS addition that was merged, was not supposed to get merged as it
-was part of patch series that was superseded by 2 more patch series
-that resolved issues with this one and greatly simplified things.
-
-Since it already got merged, start by correcting the register space
-size as APCS will not be providing regmap for PLL and it will conflict
-with the standalone A53 PLL node.
-
-Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -703,7 +703,7 @@
- 
- 		apcs_glb: mailbox@b111000 {
- 			compatible = "qcom,ipq8074-apcs-apps-global";
--			reg = <0x0b111000 0x6000>;
-+			reg = <0x0b111000 0x1000>;
- 
- 			#clock-cells = <1>;
- 			#mbox-cells = <1>;

target/linux/ipq807x/patches-5.15/0108-PCI-qcom-add-IPQ8074-Gen3-support.patch

@@ -1,7 +1,7 @@
-From f086c5659cd54946b618ae4c695a8c05096f267a Mon Sep 17 00:00:00 2001
+From 4e93203281f4b0c82bf36afd5f316e37991d6456 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Mon, 20 Dec 2021 15:01:36 +0100
-Subject: [PATCH 111/137] PCI: qcom: add IPQ8074 Gen3 support
+Subject: [PATCH] PCI: qcom: add IPQ8074 Gen3 support
 
 IPQ8074 has one Gen2 and one Gen3 port, Gen3 port is the same one as
 in IPQ6018, so reuse the support but just add the missing clocks.
@@ -11,6 +11,8 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  drivers/pci/controller/dwc/pcie-qcom.c | 9 ++++++---
  1 file changed, 6 insertions(+), 3 deletions(-)
 
+diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
+index 05359cfc0e34..5556859eed18 100644
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
 @@ -184,7 +184,7 @@ struct qcom_pcie_resources_2_7_0 {
@@ -22,7 +24,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  	struct reset_control *rst;
  };
  
-@@ -1296,8 +1296,10 @@ static int qcom_pcie_get_resources_2_9_0
+@@ -1297,8 +1297,10 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
  	res->clks[0].id = "iface";
  	res->clks[1].id = "axi_m";
  	res->clks[2].id = "axi_s";
@@ -35,7 +37,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  
  	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
  	if (ret < 0)
-@@ -1700,6 +1702,7 @@ static const struct of_device_id qcom_pc
+@@ -1701,6 +1703,7 @@ static const struct of_device_id qcom_pcie_match[] = {
  	{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
  	{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
  	{ .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 },
@@ -43,3 +45,6 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  	{ }
  };
  
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch

@@ -1,30 +0,0 @@
-From be028f5f79b8af6ea16ffeea486e216acdf80789 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 18 Aug 2022 23:21:06 +0200
-Subject: [PATCH 108/137] arm64: dts: qcom: ipq8074: add A53 PLL node
-
-Add the required node for A53 PLL which will be used to provide the CPU
-clock via APCS for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -709,6 +709,14 @@
- 			#mbox-cells = <1>;
- 		};
- 
-+		a53pll: clock@b116000 {
-+			compatible = "qcom,ipq8074-a53pll";
-+			reg = <0x0b116000 0x40>;
-+			#clock-cells = <0>;
-+			clocks = <&xo>;
-+			clock-names = "xo";
-+		};
-+
- 		timer@b120000 {
- 			#address-cells = <1>;
- 			#size-cells = <1>;

target/linux/ipq807x/patches-5.15/0109-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-support.patch

@@ -1,50 +0,0 @@
-From ded0538937e9edf8b217d2082fd30af3bf7bd10b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 28 Dec 2021 20:59:18 +0100
-Subject: [PATCH 109/137] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock
- support
-
-IPQ8074 has the APSS clock controller utilizing the same register space as
-the APCS, so provide access to the APSS utilizing a child device like
-IPQ6018.
-
-IPQ6018 and IPQ8074 use the same controller and driver, so just utilize
-IPQ6018 match data for IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
----
-Changes in v7:
-* Dont max_register modifications
-* Drop custom IPQ8074 match data and use IPQ6018 one as they share the
-controller and driver
-
-Changes in v5:
-* Use lower case hex for max_register
-* Update the APSS clock name to match the new one without commas
----
- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 6 +-----
- 1 file changed, 1 insertion(+), 5 deletions(-)
-
---- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-@@ -33,10 +33,6 @@ static const struct qcom_apcs_ipc_data i
- 	.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
- };
- 
--static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
--	.offset = 8, .clk_name = NULL
--};
--
- static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
- 	.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
- };
-@@ -160,7 +156,7 @@ static int qcom_apcs_ipc_remove(struct p
- /* .data is the offset of the ipc register within the global block */
- static const struct of_device_id qcom_apcs_ipc_of_match[] = {
- 	{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
--	{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
-+	{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
- 	{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
- 	{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
- 	{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },

target/linux/ipq807x/patches-5.15/0110-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch

@@ -1,7 +1,7 @@
-From 184c9b73285f05ebc013205d54ed11cd968cb38e Mon Sep 17 00:00:00 2001
+From 9e280276de874970d03cdc124d8bfa7afbb6aef1 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
 Date: Mon, 20 Dec 2021 15:08:04 +0100
-Subject: [PATCH 112/137] arm64: dts: ipq8074: fix PCI related DT nodes
+Subject: [PATCH] arm64: dts: ipq8074: fix PCI related DT nodes
 
 Currently present PCI PHY and PCI controller nodes are not working
 and are incorrect for the v2 of IPQ8074 which is the only version
@@ -11,12 +11,14 @@ So, correct the PCI related nodes.
 
 Signed-off-by: Robert Marko <robimarko@gmail.com>
 ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 93 +++++++++++++++------------
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 73 +++++++++++++++------------
- 1 file changed, 52 insertions(+), 41 deletions(-)
+ 1 file changed, 42 insertions(+), 31 deletions(-)
 
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index 777c6267e777..2f553b82ca12 100644
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -232,59 +232,61 @@
+@@ -228,9 +228,9 @@ qusb_phy_0: phy@79000 {
  			status = "disabled";
  		};
  
@@ -24,24 +26,13 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 -			compatible = "qcom,ipq8074-qmp-pcie-phy";
 -			reg = <0x00086000 0x1000>;
 +		pcie_qmp0: phy@84000 {
-+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
++			compatible = "qcom,ipq8074-qmp-pcie-gen3-phy";
 +			reg = <0x00084000 0x1bc>;
  			#address-cells = <1>;
  			#size-cells = <1>;
  			ranges;
- 
+@@ -244,21 +244,22 @@ pcie_qmp0: phy@86000 {
- 			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ 				      "common";
--				<&gcc GCC_PCIE0_AHB_CLK>;
-+				 <&gcc GCC_PCIE0_AHB_CLK>;
- 			clock-names = "aux", "cfg_ahb";
-+
- 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
--				<&gcc GCC_PCIE0PHY_PHY_BCR>;
--			reset-names = "phy",
--				      "common";
-+				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+			reset-names = "phy", "common";
-+
  			status = "disabled";
  
 -			pcie_phy0: phy@86200 {
@@ -56,8 +47,8 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  				#clock-cells = <0>;
  				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  				clock-names = "pipe0";
--				clock-output-names = "pcie_0_pipe_clk";
+ 				clock-output-names = "pcie_0_pipe_clk";
-+				clock-output-names = "gcc_pcie0_pipe_clk_src";
++				clock-output-rate = <250000000>;
  			};
  		};
  
@@ -68,19 +59,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#address-cells = <1>;
  			#size-cells = <1>;
  			ranges;
- 
+@@ -273,14 +274,15 @@ pcie_qmp1: phy@8e000 {
- 			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
--				<&gcc GCC_PCIE1_AHB_CLK>;
-+				 <&gcc GCC_PCIE1_AHB_CLK>;
- 			clock-names = "aux", "cfg_ahb";
-+
- 			resets = <&gcc GCC_PCIE1_PHY_BCR>,
--				<&gcc GCC_PCIE1PHY_PHY_BCR>;
--			reset-names = "phy",
--				      "common";
-+				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
-+			reset-names = "phy", "common";
-+
  			status = "disabled";
  
  			pcie_phy1: phy@8e200 {
@@ -93,12 +72,12 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  				#clock-cells = <0>;
  				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
  				clock-names = "pipe0";
--				clock-output-names = "pcie_1_pipe_clk";
+ 				clock-output-names = "pcie_1_pipe_clk";
-+				clock-output-names = "gcc_pcie1_pipe_clk_src";
++				clock-output-rate = <125000000>;
  			};
  		};
  
-@@ -686,7 +688,7 @@
+@@ -676,7 +678,7 @@ intc: interrupt-controller@b000000 {
  			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
  			ranges = <0 0xb00a000 0xffd>;
  
@@ -107,7 +86,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  				compatible = "arm,gic-v2m-frame";
  				msi-controller;
  				reg = <0x0 0xffd>;
-@@ -787,6 +789,7 @@
+@@ -769,6 +771,7 @@ pcie1: pci@10000000 {
  			linux,pci-domain = <1>;
  			bus-range = <0x00 0xff>;
  			num-lanes = <1>;
@@ -115,7 +94,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#address-cells = <3>;
  			#size-cells = <2>;
  
-@@ -794,12 +797,12 @@
+@@ -776,12 +779,12 @@ pcie1: pci@10000000 {
  			phy-names = "pciephy";
  
  			ranges = <0x81000000 0 0x10200000 0x10200000
@@ -133,7 +112,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#interrupt-cells = <1>;
  			interrupt-map-mask = <0 0 0 0x7>;
  			interrupt-map = <0 0 0 1 &intc 0 142
-@@ -839,16 +842,18 @@
+@@ -821,16 +824,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  		};
  
  		pcie0: pci@20000000 {
@@ -158,7 +137,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#address-cells = <3>;
  			#size-cells = <2>;
  
-@@ -856,12 +861,12 @@
+@@ -838,12 +843,12 @@ pcie0: pci@20000000 {
  			phy-names = "pciephy";
  
  			ranges = <0x81000000 0 0x20200000 0x20200000
@@ -176,7 +155,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#interrupt-cells = <1>;
  			interrupt-map-mask = <0 0 0 0x7>;
  			interrupt-map = <0 0 0 1 &intc 0 75
-@@ -877,27 +882,33 @@
+@@ -859,27 +864,33 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  				 <&gcc GCC_PCIE0_AXI_M_CLK>,
  				 <&gcc GCC_PCIE0_AXI_S_CLK>,
  				 <&gcc GCC_PCIE0_AHB_CLK>,
@@ -214,3 +193,6 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			status = "disabled";
  		};
  	};
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0110-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch

@@ -1,29 +0,0 @@
-From 0a36a586424feabf9ce9436379f9d061b7844155 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 18 Aug 2022 23:25:00 +0200
-Subject: [PATCH 110/137] arm64: dts: qcom: ipq8074: add clocks to APCS
-
-APCS now has support for providing the APSS clocks as the child device
-for IPQ8074.
-
-So, add the A53 PLL and XO clocks in order to use APCS as the CPU
-clocksource for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -704,8 +704,9 @@
- 		apcs_glb: mailbox@b111000 {
- 			compatible = "qcom,ipq8074-apcs-apps-global";
- 			reg = <0x0b111000 0x1000>;
--
- 			#clock-cells = <1>;
-+			clocks = <&a53pll>, <&xo>;
-+			clock-names = "pll", "xo";
- 			#mbox-cells = <1>;
- 		};
- 

target/linux/ipq807x/patches-5.15/0111-remoteproc-qcom-Add-PRNG-proxy-clock.patch

@@ -1,7 +1,7 @@
-From 84e13a5267e43bb0a6a1f764211fda7769dc9cbe Mon Sep 17 00:00:00 2001
+From ddc957c5eee78cf41d04040b6de3e3437830b473 Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:05 +0530
-Subject: [PATCH 113/137] remoteproc: qcom: Add PRNG proxy clock
+Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
 
 PRNG clock is needed by the secure PIL, support for the same
 is added in subsequent patches.
@@ -13,6 +13,8 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
  1 file changed, 47 insertions(+), 18 deletions(-)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index 20d50ec7eff1..0e5484020296 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
 @@ -91,19 +91,6 @@ enum {
@@ -65,7 +67,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
  {
  	int ret;
-@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
+@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc *rproc)
  	struct q6v5_wcss *wcss = rproc->priv;
  	int ret;
  
@@ -78,7 +80,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	qcom_q6v5_prepare(&wcss->q6v5);
  
  	/* Release Q6 and WCSS reset */
-@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc *
+@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc *rproc)
  			return ret;
  	}
  
@@ -86,7 +88,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	qcom_q6v5_unprepare(&wcss->q6v5);
  
  	return 0;
-@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(stru
+@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
  	return 0;
  }
  
@@ -109,7 +111,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  {
  	int ret;
  
-@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q
+@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
  	return 0;
  }
  
@@ -118,7 +120,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  {
  	wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
  	if (IS_ERR(wcss->cx_supply))
-@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  	if (ret)
  		goto free_rproc;
  
@@ -136,7 +138,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  		if (ret)
  			goto free_rproc;
  	}
-@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platf
+@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
  }
  
  static const struct wcss_data wcss_ipq8074_res_init = {
@@ -144,7 +146,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	.firmware_name = "IPQ8074/q6_fw.mdt",
  	.crash_reason_smem = WCSS_CRASH_REASON,
  	.aon_reset_required = true,
-@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq80
+@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq8074_res_init = {
  };
  
  static const struct wcss_data wcss_qcs404_res_init = {
@@ -153,3 +155,6 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	.crash_reason_smem = WCSS_CRASH_REASON,
  	.firmware_name = "wcnss.mdt",
  	.version = WCSS_QCS404,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0112-remoteproc-qcom-Add-secure-PIL-support.patch

@@ -1,7 +1,7 @@
-From cb3b9e284104fd7fe4aa92a37df005577aed2c40 Mon Sep 17 00:00:00 2001
+From 3151bf7eb1350e3dd8a51424942d7365673a6e25 Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:06 +0530
-Subject: [PATCH 114/137] remoteproc: qcom: Add secure PIL support
+Subject: [PATCH] remoteproc: qcom: Add secure PIL support
 
 IPQ8074 uses secure PIL. Hence, adding the support for the same.
 
@@ -12,6 +12,8 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
  1 file changed, 40 insertions(+), 3 deletions(-)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index 0e5484020296..7d173b7816b8 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
 @@ -18,6 +18,7 @@
@@ -48,7 +50,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  };
  
  static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
+@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc *rproc)
  
  	qcom_q6v5_prepare(&wcss->q6v5);
  
@@ -64,7 +66,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	/* Release Q6 and WCSS reset */
  	ret = reset_control_deassert(wcss->wcss_reset);
  	if (ret) {
-@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
+@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc *rproc)
  	if (ret)
  		goto wcss_q6_reset;
  
@@ -72,7 +74,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
  	if (ret == -ETIMEDOUT)
  		dev_err(wcss->dev, "start timed out\n");
-@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc *
+@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc *rproc)
  	struct q6v5_wcss *wcss = rproc->priv;
  	int ret;
  
@@ -88,7 +90,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	/* WCSS powerdown */
  	if (wcss->requires_force_stop) {
  		ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
-@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc *
+@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc *rproc)
  			return ret;
  	}
  
@@ -96,7 +98,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	clk_disable_unprepare(wcss->prng_clk);
  	qcom_q6v5_unprepare(&wcss->q6v5);
  
-@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc *
+@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
  	struct q6v5_wcss *wcss = rproc->priv;
  	int ret;
  
@@ -115,7 +117,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	if (ret)
  		return ret;
  
-@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  	if (!desc)
  		return -EINVAL;
  
@@ -125,7 +127,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
  			    desc->firmware_name, sizeof(*wcss));
  	if (!rproc) {
-@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  
  	wcss->version = desc->version;
  	wcss->requires_force_stop = desc->requires_force_stop;
@@ -133,7 +135,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  
  	ret = q6v5_wcss_init_mmio(wcss, pdev);
  	if (ret)
-@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq80
+@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq8074_res_init = {
  	.wcss_q6_reset_required = true,
  	.ops = &q6v5_wcss_ipq8074_ops,
  	.requires_force_stop = true,
@@ -141,3 +143,6 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  };
  
  static const struct wcss_data wcss_qcs404_res_init = {
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch

@@ -1,8 +1,7 @@
-From bcb2c37f265924ac43642f1f97c964dd546b3cb5 Mon Sep 17 00:00:00 2001
+From 0915eaecd5e06227c9e4e3a4a931c45942e7b4ed Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:07 +0530
-Subject: [PATCH 115/137] remoteproc: qcom: Add support for split q6 + m3 wlan
+Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
- firmware
 
 IPQ8074 supports split firmware for q6 and m3 as well.
 So add support for loading the m3 firmware before q6.
@@ -16,6 +15,8 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
  1 file changed, 29 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index 7d173b7816b8..60ed0c046693 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
 @@ -139,6 +139,7 @@ struct q6v5_wcss {
@@ -36,7 +37,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	unsigned int crash_reason_smem;
  	u32 version;
  	bool aon_reset_required;
-@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct r
+@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *i
  static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
  {
  	struct q6v5_wcss *wcss = rproc->priv;
@@ -66,7 +67,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	if (wcss->need_mem_protection)
  		ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
  				    WCNSS_PAS_ID, wcss->mem_region,
-@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  		return -EPROBE_DEFER;
  
  	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
@@ -75,7 +76,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	if (!rproc) {
  		dev_err(&pdev->dev, "failed to allocate rproc\n");
  		return -ENOMEM;
-@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  	wcss->version = desc->version;
  	wcss->requires_force_stop = desc->requires_force_stop;
  	wcss->need_mem_protection = desc->need_mem_protection;
@@ -83,7 +84,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  
  	ret = q6v5_wcss_init_mmio(wcss, pdev);
  	if (ret)
-@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platf
+@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
  
  static const struct wcss_data wcss_ipq8074_res_init = {
  	.init_clock = ipq8074_init_clock,
@@ -93,7 +94,7 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	.crash_reason_smem = WCSS_CRASH_REASON,
  	.aon_reset_required = true,
  	.wcss_q6_reset_required = true,
-@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs40
+@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs404_res_init = {
  	.init_clock = qcs404_init_clock,
  	.init_regulator = qcs404_init_regulator,
  	.crash_reason_smem = WCSS_CRASH_REASON,
@@ -102,3 +103,6 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	.version = WCSS_QCS404,
  	.aon_reset_required = false,
  	.wcss_q6_reset_required = false,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-ssr-subdevice-identifier.patch

@@ -1,7 +1,7 @@
-From 5b717749ce49853f495ebac227c72013622b0810 Mon Sep 17 00:00:00 2001
+From a0774816e1e76c47fe47a4e0fa7e0a84811dd62f Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:08 +0530
-Subject: [PATCH 116/137] remoteproc: qcom: Add ssr subdevice identifier
+Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
 
 Add name for ssr subdevice on IPQ8074 SoC.
 
@@ -12,9 +12,11 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index 60ed0c046693..e32efdc660d2 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq80
+@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq8074_res_init = {
  	.crash_reason_smem = WCSS_CRASH_REASON,
  	.aon_reset_required = true,
  	.wcss_q6_reset_required = true,
@@ -22,3 +24,6 @@ Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  	.ops = &q6v5_wcss_ipq8074_ops,
  	.requires_force_stop = true,
  	.need_mem_protection = true,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch

@@ -1,8 +1,7 @@
-From 3bc5b97ecbb003e413ae76b332b0ccdba05ef6bc Mon Sep 17 00:00:00 2001
+From e99af92362058cfec70569057c1b15da9a1acb5f Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:09 +0530
-Subject: [PATCH 117/137] remoteproc: qcom: Update regmap offsets for halt
+Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
- register
 
 Fixed issue in reading halt-regs parameter from device-tree.
 
@@ -12,6 +11,8 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
  1 file changed, 14 insertions(+), 8 deletions(-)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index e32efdc660d2..16fc5a33adaf 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
 @@ -86,7 +86,7 @@
@@ -31,7 +32,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  	const char *ssr_name;
  	const char *sysmon_name;
  	int ssctl_id;
-@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q
+@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,
  		}
  	}
  
@@ -49,7 +50,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  	}
  
  	return 0;
-@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6
+@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
  		return -EINVAL;
  	}
  
@@ -62,7 +63,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  
  	return 0;
  }
-@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq80
+@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq8074_res_init = {
  	.crash_reason_smem = WCSS_CRASH_REASON,
  	.aon_reset_required = true,
  	.wcss_q6_reset_required = true,
@@ -70,7 +71,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  	.ssr_name = "q6wcss",
  	.ops = &q6v5_wcss_ipq8074_ops,
  	.requires_force_stop = true,
-@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs40
+@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs404_res_init = {
  	.version = WCSS_QCS404,
  	.aon_reset_required = false,
  	.wcss_q6_reset_required = false,
@@ -78,3 +79,6 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  	.ssr_name = "mpss",
  	.sysmon_name = "wcnss",
  	.ssctl_id = 0x12,
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0116-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch

@@ -1,7 +1,7 @@
-From aa0c4a764d290cceba0a27fd5d81b30b54c5c81f Mon Sep 17 00:00:00 2001
+From 25e8ae5b960f45e9e19aa24cc023603375f44db0 Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:10 +0530
-Subject: [PATCH 128/137] dt-bindings: clock: qcom: Add reset for WCSSAON
+Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
 
 Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
 
@@ -14,13 +14,17 @@ Acked-by: Stephen Boyd <sboyd@kernel.org>
  include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+index 8e2bec1c91bf..9b1c42bc430c 100644
 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
 +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -367,6 +367,7 @@
+@@ -366,5 +366,6 @@
  #define GCC_PCIE1_AHB_ARES			129
  #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
  #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
 +#define GCC_WCSSAON_RESET			132
  
- #define USB0_GDSC				0
+ #endif
- #define USB1_GDSC				1
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch

@@ -1,7 +1,7 @@
-From 1377fc72a67c8684237fa9b1f246257fd073b2b1 Mon Sep 17 00:00:00 2001
+From 1a279695f52e8ab438fde5dbfbb762da8980e037 Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:11 +0530
-Subject: [PATCH 129/137] clk: qcom: Add WCSSAON reset
+Subject: [PATCH] clk: qcom: Add WCSSAON reset
 
 Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
 
@@ -13,13 +13,18 @@ Acked-by: Stephen Boyd <sboyd@kernel.org>
  drivers/clk/qcom/gcc-ipq8074.c | 1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
+index b09d99343e09..4d6e8c47515f 100644
 --- a/drivers/clk/qcom/gcc-ipq8074.c
 +++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4826,6 +4826,7 @@ static const struct qcom_reset_map gcc_i
+@@ -4744,6 +4744,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
  	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
  	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
  	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
 +	[GCC_WCSSAON_RESET] = { 0x59010, 0 },
  };
  
- static struct gdsc *gcc_ipq8074_gdscs[] = {
+ static const struct of_device_id gcc_ipq8074_match_table[] = {
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0118-drivers-thermal-tsens-Add-support-for-combined-inter.patch

@@ -1,138 +0,0 @@
-From 24a47e4619d90266188d26be04c0c29854294f06 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 28 Apr 2022 14:58:16 +0200
-Subject: [PATCH 118/137] drivers: thermal: tsens: Add support for combined
- interrupt
-
-Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
-signaling both up/low and critical trips.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
-Changes in v7:
-* Rebase to apply on next-20220818
-
-Changes in v6:
-* Check critical IRQ handler return, simplify up/low return
----
- drivers/thermal/qcom/tsens-8960.c |  1 +
- drivers/thermal/qcom/tsens-v0_1.c |  1 +
- drivers/thermal/qcom/tsens-v1.c   |  1 +
- drivers/thermal/qcom/tsens-v2.c   |  1 +
- drivers/thermal/qcom/tsens.c      | 38 ++++++++++++++++++++++++++-----
- drivers/thermal/qcom/tsens.h      |  2 ++
- 6 files changed, 38 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/qcom/tsens-8960.c
-+++ b/drivers/thermal/qcom/tsens-8960.c
-@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
- static struct tsens_features tsens_8960_feat = {
- 	.ver_major	= VER_0,
- 	.crit_int	= 0,
-+	.combo_int	= 0,
- 	.adc		= 1,
- 	.srot_split	= 0,
- 	.max_sensors	= 11,
---- a/drivers/thermal/qcom/tsens-v0_1.c
-+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_p
- static struct tsens_features tsens_v0_1_feat = {
- 	.ver_major	= VER_0_1,
- 	.crit_int	= 0,
-+	.combo_int	= 0,
- 	.adc		= 1,
- 	.srot_split	= 1,
- 	.max_sensors	= 11,
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_p
- static struct tsens_features tsens_v1_feat = {
- 	.ver_major	= VER_1_X,
- 	.crit_int	= 0,
-+	.combo_int	= 0,
- 	.adc		= 1,
- 	.srot_split	= 1,
- 	.max_sensors	= 11,
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -31,6 +31,7 @@
- static struct tsens_features tsens_v2_feat = {
- 	.ver_major	= VER_2_X,
- 	.crit_int	= 1,
-+	.combo_int	= 0,
- 	.adc		= 0,
- 	.srot_split	= 1,
- 	.max_sensors	= 16,
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -531,6 +531,27 @@ static irqreturn_t tsens_irq_thread(int
- 	return IRQ_HANDLED;
- }
- 
-+/**
-+ * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts
-+ * @irq: irq number
-+ * @data: tsens controller private data
-+ *
-+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
-+ * critical handler first and then the up/low one.
-+ *
-+ * Return: IRQ_HANDLED
-+ */
-+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
-+{
-+	irqreturn_t ret;
-+
-+	ret = tsens_critical_irq_thread(irq, data);
-+	if (ret != IRQ_HANDLED)
-+		return ret;
-+
-+	return tsens_irq_thread(irq, data);
-+}
-+
- static int tsens_set_trips(void *_sensor, int low, int high)
- {
- 	struct tsens_sensor *s = _sensor;
-@@ -1075,13 +1096,18 @@ static int tsens_register(struct tsens_p
- 				   tsens_mC_to_hw(priv->sensor, 0));
- 	}
- 
--	ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
--	if (ret < 0)
--		return ret;
-+	if (priv->feat->combo_int) {
-+		ret = tsens_register_irq(priv, "combined",
-+					 tsens_combined_irq_thread);
-+	} else {
-+		ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
-+		if (ret < 0)
-+			return ret;
- 
--	if (priv->feat->crit_int)
--		ret = tsens_register_irq(priv, "critical",
--					 tsens_critical_irq_thread);
-+		if (priv->feat->crit_int)
-+			ret = tsens_register_irq(priv, "critical",
-+						 tsens_critical_irq_thread);
-+	}
- 
- 	return ret;
- }
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -495,6 +495,7 @@ enum regfield_ids {
-  * struct tsens_features - Features supported by the IP
-  * @ver_major: Major number of IP version
-  * @crit_int: does the IP support critical interrupts?
-+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
-  * @adc:      do the sensors only output adc code (instead of temperature)?
-  * @srot_split: does the IP neatly splits the register space into SROT and TM,
-  *              with SROT only being available to secure boot firmware?
-@@ -504,6 +505,7 @@ enum regfield_ids {
- struct tsens_features {
- 	unsigned int ver_major;
- 	unsigned int crit_int:1;
-+	unsigned int combo_int:1;
- 	unsigned int adc:1;
- 	unsigned int srot_split:1;
- 	unsigned int has_watchdog:1;

target/linux/ipq807x/patches-5.15/0118-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch

@@ -1,7 +1,7 @@
-From d9965ec6f02f71609d837d33d4bae20fb7dec1fd Mon Sep 17 00:00:00 2001
+From 76126149a2a76a0cf9895224dbb4dacf69ebb06a Mon Sep 17 00:00:00 2001
 From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
 Date: Fri, 17 Apr 2020 16:37:10 +0530
-Subject: [PATCH 130/137] remoteproc: wcss: disable auto boot for IPQ8074
+Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
 
 auto boot is disabled for IPQ8074 the wifi driver brings up the wcss.
 
@@ -11,6 +11,8 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
  drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
+index 16fc5a33adaf..92c240976f55 100644
 --- a/drivers/remoteproc/qcom_q6v5_wcss.c
 +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
 @@ -161,6 +161,7 @@ struct wcss_data {
@@ -21,7 +23,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
  };
  
  static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platfo
+@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
  						      desc->sysmon_name,
  						      desc->ssctl_id);
  
@@ -29,7 +31,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
  	ret = rproc_add(rproc);
  	if (ret)
  		goto free_rproc;
-@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq80
+@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq8074_res_init = {
  	.ops = &q6v5_wcss_ipq8074_ops,
  	.requires_force_stop = true,
  	.need_mem_protection = true,
@@ -37,7 +39,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
  };
  
  static const struct wcss_data wcss_qcs404_res_init = {
-@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs40
+@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs404_res_init = {
  	.ssctl_id = 0x12,
  	.ops = &q6v5_wcss_qcs404_ops,
  	.requires_force_stop = false,
@@ -45,3 +47,6 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
  };
  
  static const struct of_device_id q6v5_wcss_of_match[] = {
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0119-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch

@@ -1,7 +1,7 @@
-From 45dfcd1ecf0910e4e45fec5f26f2fc80a47732f9 Mon Sep 17 00:00:00 2001
+From 1078ef8be64de03a2dbd78d17c87af0472748079 Mon Sep 17 00:00:00 2001
 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
 Date: Sat, 30 Jan 2021 10:50:13 +0530
-Subject: [PATCH 131/137] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
+Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
 
 Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
 Also enables smp2p and mailboxes required for IPC.
@@ -11,12 +11,14 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
 Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
 Signed-off-by: Robert Marko <robimarko@gmail.com>
 ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 88 +++++++++++++++++++++++++++
- 1 file changed, 81 insertions(+)
+ 1 file changed, 88 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+index 2f553b82ca12..947064465fc0 100644
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -153,6 +153,32 @@
+@@ -136,6 +136,32 @@ scm {
  		};
  	};
  
@@ -49,7 +51,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  	soc: soc {
  		#address-cells = <0x1>;
  		#size-cells = <0x1>;
-@@ -421,6 +447,11 @@
+@@ -393,6 +419,11 @@ tcsr_mutex: hwlock@1905000 {
  			#hwlock-cells = <1>;
  		};
  
@@ -61,11 +63,18 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  		spmi_bus: spmi@200f000 {
  			compatible = "qcom,spmi-pmic-arb";
  			reg = <0x0200f000 0x001000>,
-@@ -934,6 +965,56 @@
+@@ -893,5 +924,62 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  				      "axi_s_sticky";
  			status = "disabled";
  		};
 +
++		apcs_glb: mailbox@b111000 {
++			compatible = "qcom,ipq8074-apcs-apps-global";
++			reg = <0x0b111000 0x1000>;
++
++			#mbox-cells = <1>;
++		};
++
 +		q6v5_wcss: q6v5_wcss@cd00000 {
 +			compatible = "qcom,ipq8074-wcss-pil";
 +			reg = <0x0cd00000 0x4040>,
@@ -116,5 +125,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 +			};
 +		};
  	};
- 
+ };
- 	timer {
+-- 
+2.35.1
+