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51 lines
1.8 KiB
Diff
51 lines
1.8 KiB
Diff
From 70261569da66997eb4c6057b136af417ed06716e Mon Sep 17 00:00:00 2001
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From: Baruch Siach <baruch.siach@siklu.com>
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Date: Mon, 7 Feb 2022 16:51:25 +0200
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Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
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The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
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PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
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describe its meaning.
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Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
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1 file changed, 13 insertions(+), 2 deletions(-)
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diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
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index 8a7a300163e5..f5101258d73b 100644
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -69,7 +69,18 @@
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#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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#define CFG_BRIDGE_SB_INIT BIT(0)
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-#define PCIE_CAP_LINK1_VAL 0x2FD7F
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+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
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+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
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+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
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+ PCI_EXP_SLTCAP_PCP | \
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+ PCI_EXP_SLTCAP_MRLSP | \
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+ PCI_EXP_SLTCAP_AIP | \
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+ PCI_EXP_SLTCAP_PIP | \
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+ PCI_EXP_SLTCAP_HPS | \
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+ PCI_EXP_SLTCAP_HPC | \
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+ PCI_EXP_SLTCAP_EIP | \
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+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
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+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
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#define PCIE20_PARF_Q2A_FLUSH 0x1AC
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@@ -1102,7 +1113,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
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writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
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writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
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- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
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val &= ~PCI_EXP_LNKCAP_ASPMS;
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--
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2.35.1
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