diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 416a03413..5ea8a8afa 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -57,6 +57,9 @@ ALLWIFIBOARDS:= \ p2w_r619ac \ qnap_301w \ qxwlan_e2600ac \ + redmi_ax6 \ + xiaomi_ax3600 \ + xiaomi_ax9000 \ zte_mf263 \ zte_mf269 \ tplink_xtr10890 @@ -161,6 +164,9 @@ $(eval $(call generate-ipq-wifi-package,plasmacloud_pa2200,Plasma Cloud PA2200)) $(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC)) $(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w)) $(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac,Qxwlan E2600AC)) +$(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6)) +$(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600)) +$(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000)) $(eval $(call generate-ipq-wifi-package,zte_mf263,ZTE MF263)) $(eval $(call generate-ipq-wifi-package,zte_mf269,ZTE MF269)) $(eval $(call generate-ipq-wifi-package,tplink_xtr10890,TPLINK XTR10890)) diff --git a/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 b/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 new file mode 100644 index 000000000..98ed9c6f6 Binary files /dev/null and b/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 b/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 new file mode 100644 index 000000000..db8ef4cef Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 b/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 new file mode 100644 index 000000000..af4405cd5 Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 b/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 new file mode 100644 index 000000000..babfaa2a9 Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 differ diff --git a/target/linux/ipq807x/Makefile b/target/linux/ipq807x/Makefile index c8af6c42c..697ad9217 100644 --- a/target/linux/ipq807x/Makefile +++ b/target/linux/ipq807x/Makefile @@ -16,7 +16,7 @@ DEFAULT_PACKAGES += \ kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \ kmod-leds-gpio kmod-gpio-button-hotplug \ ath11k-firmware-ipq8074 kmod-ath11k-ahb \ - autocore-arm htop wpad-openssl zram-swap uboot-envtools \ + autocore-arm htop wpad-openssl uboot-envtools \ kmod-qca-nss-dp kmod-qca-nss-drv-64 \ kmod-qca-nss-drv-pppoe-64 kmod-qca-nss-ecm-64 \ kmod-qca-nss-drv-bridge-mgr-64 kmod-qca-nss-drv-vlan-mgr-64 \ diff --git a/target/linux/ipq807x/base-files/etc/board.d/01_leds b/target/linux/ipq807x/base-files/etc/board.d/01_leds index 1966a95c0..e63ef959c 100644 --- a/target/linux/ipq807x/base-files/etc/board.d/01_leds +++ b/target/linux/ipq807x/base-files/etc/board.d/01_leds @@ -7,6 +7,10 @@ board=$(board_name) board_config_update case $board in +xiaomi,ax3600|\ +redmi,ax6) + ucidef_set_led_netdev "wan" "WAN" "blue:network" "eth0" + ;; qnap,301w) ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth0" ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth1" diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network index cbd229347..40c2d1de1 100644 --- a/target/linux/ipq807x/base-files/etc/board.d/02_network +++ b/target/linux/ipq807x/base-files/etc/board.d/02_network @@ -14,6 +14,10 @@ ipq807x_setup_interfaces() qnap,301w) ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3 eth4" "eth5" ;; + redmi,ax6|\ + xiaomi,ax3600) + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0" + ;; zte,mf269) ucidef_set_interfaces_lan_wan "eth0" "eth1" ;; diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 000000000..e5daf2dba --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,20 @@ +#!/bin/sh + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh + +board=$(board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:01:00.0.bin") + case "$board" in + xiaomi,ax3600) + caldata_extract "0:art" 0x33000 0x844 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index 4a91b83d8..cf200be88 100644 --- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -9,7 +9,10 @@ board=$(board_name) case "$FIRMWARE" in "ath11k/IPQ8074/hw2.0/cal-ahb-c000000.wifi.bin") case "$board" in - qnap,301w) + qnap,301w|\ + redmi,ax6|\ + xiaomi,ax3600|\ + xiaomi,ax9000) caldata_extract "0:art" 0x1000 0x20000 ;; zte,mf269) diff --git a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh index a164a73de..09b243a2d 100644 --- a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh @@ -15,6 +15,34 @@ platform_do_upgrade() { rootfsname="rootfs" mmc_do_upgrade "$1" ;; + redmi,ax6|\ + xiaomi,ax3600|\ + xiaomi,ax9000) + part_num="$(fw_printenv -n flag_boot_rootfs)" + if [ "$part_num" -eq "1" ]; then + CI_UBIPART="rootfs_1" + target_num=1 + # Reset fail flag for the current partition + # With both partition set to fail, the partition 2 (bit 1) + # is loaded + fw_setenv flag_try_sys2_failed 0 + else + CI_UBIPART="rootfs" + target_num=0 + # Reset fail flag for the current partition + # or uboot will skip the loading of this partition + fw_setenv flag_try_sys1_failed 0 + fi + + # Tell uboot to switch partition + fw_setenv flag_boot_rootfs $target_num + fw_setenv flag_last_success $target_num + + # Reset success flag + fw_setenv flag_boot_success 0 + + nand_do_upgrade "$1" + ;; zte,mf269) nand_do_upgrade "$1" ;; diff --git a/target/linux/ipq807x/config-5.15 b/target/linux/ipq807x/config-5.15 index 232a70f47..3b42ef0c5 100644 --- a/target/linux/ipq807x/config-5.15 +++ b/target/linux/ipq807x/config-5.15 @@ -48,7 +48,6 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set # CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set -CONFIG_ASN1=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_BINARY_PRINTF=y CONFIG_BLK_DEV_LOOP=y @@ -58,9 +57,7 @@ CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y CONFIG_CAVIUM_TX2_ERRATUM_219=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLANG_VERSION=0 CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_QCOM=y # CONFIG_COMPAT_32BIT_TIME is not set @@ -87,27 +84,8 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRC16=y CONFIG_CRC8=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_BS=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=y -CONFIG_CRYPTO_CHACHA20=y -CONFIG_CRYPTO_CHACHA20POLY1305=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_CURVE25519=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DEV_QCE=y CONFIG_CRYPTO_DEV_QCE_AEAD=y @@ -119,59 +97,17 @@ CONFIG_CRYPTO_DEV_QCE_SHA=y CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DH=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_ECDSA=y -CONFIG_CRYPTO_ECRDSA=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_KEYWRAP=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_SM4=y -CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_NHPOLY1305=y -CONFIG_CRYPTO_NHPOLY1305_NEON=y -CONFIG_CRYPTO_OFB=y -CONFIG_CRYPTO_POLY1305=y -CONFIG_CRYPTO_POLY1305_NEON=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA3_ARM64=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_SM2=y -CONFIG_CRYPTO_SM3=y -CONFIG_CRYPTO_SM3_ARM64_CE=y -CONFIG_CRYPTO_SM4_ARM64_CE=y -CONFIG_CRYPTO_STREEBOG=y CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_XXHASH=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEV_COREDUMP=y @@ -254,7 +190,6 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y # CONFIG_KPSS_XCC is not set CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LTO_NONE=y @@ -284,7 +219,6 @@ CONFIG_MMC_SDHCI_MSM=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MPILIB=y # CONFIG_MSM_GCC_8660 is not set # CONFIG_MSM_GCC_8916 is not set # CONFIG_MSM_GCC_8939 is not set @@ -315,6 +249,7 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NET_SWITCHDEV=y CONFIG_NLS=y CONFIG_NO_HZ_COMMON=y @@ -332,7 +267,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OID_REGISTRY=y CONFIG_PADATA=y CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y @@ -428,7 +362,6 @@ CONFIG_QCOM_Q6V5_COMMON=y # CONFIG_QCOM_Q6V5_PAS is not set CONFIG_QCOM_Q6V5_WCSS=y CONFIG_QCOM_QFPROM=y -# CONFIG_QCOM_QMI_HELPERS is not set # CONFIG_QCOM_RMTFS_MEM is not set # CONFIG_QCOM_RPMH is not set CONFIG_QCOM_RPROC_COMMON=y @@ -507,7 +440,6 @@ CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y -# CONFIG_SHORTCUT_FE is not set CONFIG_SMP=y # CONFIG_SM_GCC_8150 is not set # CONFIG_SM_GCC_8250 is not set @@ -558,7 +490,6 @@ CONFIG_VIRTIO=y CONFIG_VMAP_STACK=y CONFIG_WANT_DEV_COREDUMP=y CONFIG_WATCHDOG_CORE=y -CONFIG_XOR_BLOCKS=y CONFIG_XPS=y CONFIG_XXHASH=y CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts new file mode 100644 index 000000000..0e5b1906e --- /dev/null +++ b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +/dts-v1/; + +#include "ipq8071-ax3600.dtsi" + +/ { + model = "Xiaomi AX3600"; + compatible = "xiaomi,ax3600", "qcom,ipq8074"; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + aiot { + label = "blue:aiot"; + gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&qmp_pcie_phy0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + status = "okay"; + + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath10k-calibration-variant = "Xiaomi-AX3600"; + }; + }; +}; + +&wifi { + qcom,ath11k-calibration-variant = "Xiaomi-AX3600"; +}; diff --git a/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi new file mode 100644 index 000000000..4d93bda5c --- /dev/null +++ b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +#include "ipq8074.dtsi" +#include "ipq8074-ac-cpu.dtsi" +#include "ipq8074-ac-nss.dtsi" +#include "ipq8074-memory-512m.dtsi" +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + /* Aliases as required by u-boot to patch MAC addresses */ + ethernet1 = &dp2; + ethernet2 = &dp3; + ethernet3 = &dp4; + ethernet4 = &dp5; + label-mac-device = &dp2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reserved-memory { + /delete-node/ tzapp@4a400000; + /delete-node/ q6_etr_dump@50f00000; + /delete-node/ m3_dump@51000000; + }; +}; + +&tlmm { + mdio_pins: mdio-pins { + mdc { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + /* + * Disable the reset GPIO temporarely as it + * resets the 100Mbit LED configuration which + * the bootloader writes. + */ + //reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&ess_switch { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x1e>; /* lan port bitmap */ + switch_wan_bmp = <0x20>; /* wan port bitmap */ + switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + port@1 { + port_id = <2>; + phy_address = <1>; + }; + port@2 { + port_id = <3>; + phy_address = <2>; + }; + port@3 { + port_id = <4>; + phy_address = <3>; + }; + port@4 { + port_id = <5>; + phy_address = <4>; + }; + }; + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 143>; + mcast_queue = <256 271>; + l0sp = <0 35>; + l0cdrr = <0 47>; + l0edrr = <0 47>; + l1cdrr = <0 7>; + l1edrr = <0 7>; + }; + port@1 { + port_id = <1>; + ucast_queue = <144 159>; + mcast_queue = <272 275>; + l0sp = <36 39>; + l0cdrr = <48 63>; + l0edrr = <48 63>; + l1cdrr = <8 11>; + l1edrr = <8 11>; + }; + port@2 { + port_id = <2>; + ucast_queue = <160 175>; + mcast_queue = <276 279>; + l0sp = <40 43>; + l0cdrr = <64 79>; + l0edrr = <64 79>; + l1cdrr = <12 15>; + l1edrr = <12 15>; + }; + port@3 { + port_id = <3>; + ucast_queue = <176 191>; + mcast_queue = <280 283>; + l0sp = <44 47>; + l0cdrr = <80 95>; + l0edrr = <80 95>; + l1cdrr = <16 19>; + l1edrr = <16 19>; + }; + port@4 { + port_id = <4>; + ucast_queue = <192 207>; + mcast_queue = <284 287>; + l0sp = <48 51>; + l0cdrr = <96 111>; + l0edrr = <96 111>; + l1cdrr = <20 23>; + l1edrr = <20 23>; + }; + port@5 { + port_id = <5>; + ucast_queue = <208 223>; + mcast_queue = <288 291>; + l0sp = <52 55>; + l0cdrr = <112 127>; + l0edrr = <112 127>; + l1cdrr = <24 27>; + l1edrr = <24 27>; + }; + port@6 { + port_id = <6>; + ucast_queue = <224 239>; + mcast_queue = <292 295>; + l0sp = <56 59>; + l0cdrr = <128 143>; + l0edrr = <128 143>; + l1cdrr = <28 31>; + l1edrr = <28 31>; + }; + port@7 { + port_id = <7>; + ucast_queue = <240 255>; + mcast_queue = <296 299>; + l0sp = <60 63>; + l0cdrr = <144 159>; + l0edrr = <144 159>; + l1cdrr = <32 35>; + l1edrr = <32 35>; + }; + }; + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + sp = <0 1>; /*L0 SPs*/ + /*cpri cdrr epri edrr*/ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /*unicast queues*/ + ucast_queue = <0 4 8>; + /*multicast queues*/ + mcast_queue = <256 260>; + /*sp cpri cdrr epri edrr*/ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <1 5 9>; + mcast_queue = <257 261>; + cfg = <0 1 1 1 1>; + }; + group@2 { + ucast_queue = <2 6 10>; + mcast_queue = <258 262>; + cfg = <0 2 2 2 2>; + }; + group@3 { + ucast_queue = <3 7 11>; + mcast_queue = <259 263>; + cfg = <0 3 3 3 3>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <36>; + cfg = <0 8 0 8>; + }; + group@1 { + sp = <37>; + cfg = <1 9 1 9>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <144>; + ucast_loop_pri = <16>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <36 0 48 0 48>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <40>; + cfg = <0 12 0 12>; + }; + group@1 { + sp = <41>; + cfg = <1 13 1 13>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <160>; + ucast_loop_pri = <16>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <40 0 64 0 64>; + }; + }; + }; + port@3 { + port_id = <3>; + l1scheduler { + group@0 { + sp = <44>; + cfg = <0 16 0 16>; + }; + group@1 { + sp = <45>; + cfg = <1 17 1 17>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <176>; + ucast_loop_pri = <16>; + mcast_queue = <280>; + mcast_loop_pri = <4>; + cfg = <44 0 80 0 80>; + }; + }; + }; + port@4 { + port_id = <4>; + l1scheduler { + group@0 { + sp = <48>; + cfg = <0 20 0 20>; + }; + group@1 { + sp = <49>; + cfg = <1 21 1 21>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <192>; + ucast_loop_pri = <16>; + mcast_queue = <284>; + mcast_loop_pri = <4>; + cfg = <48 0 96 0 96>; + }; + }; + }; + port@5 { + port_id = <5>; + l1scheduler { + group@0 { + sp = <52>; + cfg = <0 24 0 24>; + }; + group@1 { + sp = <53>; + cfg = <1 25 1 25>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <208>; + ucast_loop_pri = <16>; + mcast_queue = <288>; + mcast_loop_pri = <4>; + cfg = <52 0 112 0 112>; + }; + }; + }; + port@6 { + port_id = <6>; + l1scheduler { + group@0 { + sp = <56>; + cfg = <0 28 0 28>; + }; + group@1 { + sp = <57>; + cfg = <1 29 1 29>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <224>; + ucast_loop_pri = <16>; + mcast_queue = <292>; + mcast_loop_pri = <4>; + cfg = <56 0 128 0 128>; + }; + }; + }; + port@7 { + port_id = <7>; + l1scheduler { + group@0 { + sp = <60>; + cfg = <0 32 0 32>; + }; + group@1 { + sp = <61>; + cfg = <1 33 1 33>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <240>; + ucast_loop_pri = <16>; + mcast_queue = <296>; + cfg = <60 0 144 0 144>; + }; + }; + }; + }; +}; + +&soc { + dp2: dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a001200 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <1>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp3: dp3 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <3>; + reg = <0x3a001400 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <2>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp4: dp4 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <4>; + reg = <0x3a001600 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <3>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp5: dp5 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <5>; + reg = <0x3a001800 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <4>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; +}; + +&wifi { + status = "okay"; + + qcom,board_id = <658>; +}; diff --git a/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts new file mode 100644 index 000000000..c66fb95bc --- /dev/null +++ b/target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Zhijun You */ + +/dts-v1/; + +#include "ipq8071-ax3600.dtsi" + +/ { + model = "Redmi AX6"; + compatible = "redmi,ax6", "qcom,ipq8074"; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&wifi { + qcom,ath11k-calibration-variant = "Redmi-AX6"; +}; diff --git a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts new file mode 100644 index 000000000..3af5a3471 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +/dts-v1/; + +#include "ipq8071-ax3600.dtsi" + +/ { + model = "Xiaomi AX3600"; + compatible = "xiaomi,ax3600", "qcom,ipq8074"; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + aiot { + label = "blue:aiot"; + gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&pcie_qmp0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + status = "okay"; + + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath10k-calibration-variant = "Xiaomi-AX3600"; + }; + }; +}; + +&wifi { + qcom,ath11k-calibration-variant = "Xiaomi-AX3600"; +}; diff --git a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi new file mode 100644 index 000000000..2c29da383 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +#include "ipq8074-512m.dtsi" +#include "ipq8074-ac-cpu.dtsi" +#include "ipq8074-ess.dtsi" +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + /* Aliases as required by u-boot to patch MAC addresses */ + ethernet1 = &dp2; + ethernet2 = &dp3; + ethernet3 = &dp4; + ethernet4 = &dp5; + label-mac-device = &dp2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&tlmm { + mdio_pins: mdio-pins { + mdc { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&switch { + status = "okay"; + + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x1e>; /* lan port bitmap */ + switch_wan_bmp = <0x20>; /* wan port bitmap */ + switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + port@1 { + port_id = <2>; + phy_address = <1>; + }; + port@2 { + port_id = <3>; + phy_address = <2>; + }; + port@3 { + port_id = <4>; + phy_address = <3>; + }; + port@4 { + port_id = <5>; + phy_address = <4>; + }; + }; + + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 143>; + mcast_queue = <256 271>; + l0sp = <0 35>; + l0cdrr = <0 47>; + l0edrr = <0 47>; + l1cdrr = <0 7>; + l1edrr = <0 7>; + }; + port@1 { + port_id = <1>; + ucast_queue = <144 159>; + mcast_queue = <272 275>; + l0sp = <36 39>; + l0cdrr = <48 63>; + l0edrr = <48 63>; + l1cdrr = <8 11>; + l1edrr = <8 11>; + }; + port@2 { + port_id = <2>; + ucast_queue = <160 175>; + mcast_queue = <276 279>; + l0sp = <40 43>; + l0cdrr = <64 79>; + l0edrr = <64 79>; + l1cdrr = <12 15>; + l1edrr = <12 15>; + }; + port@3 { + port_id = <3>; + ucast_queue = <176 191>; + mcast_queue = <280 283>; + l0sp = <44 47>; + l0cdrr = <80 95>; + l0edrr = <80 95>; + l1cdrr = <16 19>; + l1edrr = <16 19>; + }; + port@4 { + port_id = <4>; + ucast_queue = <192 207>; + mcast_queue = <284 287>; + l0sp = <48 51>; + l0cdrr = <96 111>; + l0edrr = <96 111>; + l1cdrr = <20 23>; + l1edrr = <20 23>; + }; + port@5 { + port_id = <5>; + ucast_queue = <208 223>; + mcast_queue = <288 291>; + l0sp = <52 55>; + l0cdrr = <112 127>; + l0edrr = <112 127>; + l1cdrr = <24 27>; + l1edrr = <24 27>; + }; + port@6 { + port_id = <6>; + ucast_queue = <224 239>; + mcast_queue = <292 295>; + l0sp = <56 59>; + l0cdrr = <128 143>; + l0edrr = <128 143>; + l1cdrr = <28 31>; + l1edrr = <28 31>; + }; + port@7 { + port_id = <7>; + ucast_queue = <240 255>; + mcast_queue = <296 299>; + l0sp = <60 63>; + l0cdrr = <144 159>; + l0edrr = <144 159>; + l1cdrr = <32 35>; + l1edrr = <32 35>; + }; + }; + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + sp = <0 1>; /*L0 SPs*/ + /*cpri cdrr epri edrr*/ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /*unicast queues*/ + ucast_queue = <0 4 8>; + /*multicast queues*/ + mcast_queue = <256 260>; + /*sp cpri cdrr epri edrr*/ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <1 5 9>; + mcast_queue = <257 261>; + cfg = <0 1 1 1 1>; + }; + group@2 { + ucast_queue = <2 6 10>; + mcast_queue = <258 262>; + cfg = <0 2 2 2 2>; + }; + group@3 { + ucast_queue = <3 7 11>; + mcast_queue = <259 263>; + cfg = <0 3 3 3 3>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <36>; + cfg = <0 8 0 8>; + }; + group@1 { + sp = <37>; + cfg = <1 9 1 9>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <144>; + ucast_loop_pri = <16>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <36 0 48 0 48>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <40>; + cfg = <0 12 0 12>; + }; + group@1 { + sp = <41>; + cfg = <1 13 1 13>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <160>; + ucast_loop_pri = <16>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <40 0 64 0 64>; + }; + }; + }; + port@3 { + port_id = <3>; + l1scheduler { + group@0 { + sp = <44>; + cfg = <0 16 0 16>; + }; + group@1 { + sp = <45>; + cfg = <1 17 1 17>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <176>; + ucast_loop_pri = <16>; + mcast_queue = <280>; + mcast_loop_pri = <4>; + cfg = <44 0 80 0 80>; + }; + }; + }; + port@4 { + port_id = <4>; + l1scheduler { + group@0 { + sp = <48>; + cfg = <0 20 0 20>; + }; + group@1 { + sp = <49>; + cfg = <1 21 1 21>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <192>; + ucast_loop_pri = <16>; + mcast_queue = <284>; + mcast_loop_pri = <4>; + cfg = <48 0 96 0 96>; + }; + }; + }; + port@5 { + port_id = <5>; + l1scheduler { + group@0 { + sp = <52>; + cfg = <0 24 0 24>; + }; + group@1 { + sp = <53>; + cfg = <1 25 1 25>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <208>; + ucast_loop_pri = <16>; + mcast_queue = <288>; + mcast_loop_pri = <4>; + cfg = <52 0 112 0 112>; + }; + }; + }; + port@6 { + port_id = <6>; + l1scheduler { + group@0 { + sp = <56>; + cfg = <0 28 0 28>; + }; + group@1 { + sp = <57>; + cfg = <1 29 1 29>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <224>; + ucast_loop_pri = <16>; + mcast_queue = <292>; + mcast_loop_pri = <4>; + cfg = <56 0 128 0 128>; + }; + }; + }; + port@7 { + port_id = <7>; + l1scheduler { + group@0 { + sp = <60>; + cfg = <0 32 0 32>; + }; + group@1 { + sp = <61>; + cfg = <1 33 1 33>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <240>; + ucast_loop_pri = <16>; + mcast_queue = <296>; + cfg = <60 0 144 0 144>; + }; + }; + }; + }; +}; + +&edma { + status = "okay"; +}; + +&soc { + dp2: dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a001200 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <1>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp3: dp3 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <3>; + reg = <0x3a001400 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <2>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp4: dp4 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <4>; + reg = <0x3a001600 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <3>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp5: dp5 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <5>; + reg = <0x3a001800 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <4>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; +}; + +&wifi { + status = "okay"; + + qcom,board_id = <658>; +}; diff --git a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts new file mode 100644 index 000000000..c66fb95bc --- /dev/null +++ b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Zhijun You */ + +/dts-v1/; + +#include "ipq8071-ax3600.dtsi" + +/ { + model = "Redmi AX6"; + compatible = "redmi,ax6", "qcom,ipq8074"; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&wifi { + qcom,ath11k-calibration-variant = "Redmi-AX6"; +}; diff --git a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts index 16d6dcdde..d00951824 100644 --- a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts +++ b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts @@ -11,8 +11,12 @@ #include / { + #address-cells = <2>; + #size-cells = <2>; + model = "QNAP 301w"; compatible = "qnap,301w", "qcom,ipq8074"; + interrupt-parent = <&intc>; aliases { serial0 = &blsp1_uart5; @@ -363,46 +367,46 @@ pinctrl-names = "default"; reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; - aqr113c_0: ethernet-phy@0 { + ethernet-phy@0 { compatible ="ethernet-phy-ieee802.3-c45"; reg = <0>; reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; }; - aqr113c_8: ethernet-phy@8 { + ethernet-phy@8 { compatible ="ethernet-phy-ieee802.3-c45"; reg = <8>; reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; }; - qca8075_16: ethernet-phy@16 { + ethernet-phy@16 { reg = <16>; }; - qca8075_17: ethernet-phy@17 { + ethernet-phy@17 { reg = <17>; }; - qca8075_18: ethernet-phy@18 { + ethernet-phy@18 { reg = <18>; }; - qca8075_19: ethernet-phy@19 { + ethernet-phy@19 { reg = <19>; }; + }; &sdhc_1 { - status = "okay"; - - /* According to the stock dts from the QNAP gpl drop - * the emmc has a problem with the hs400 > hs200 speed switch. - * Therefore remove the mmc-hs400-1_8v property - */ - /delete-property/ mmc-hs400-1_8v; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - vqmmc-supply = <&l11>; + /* According to the stock dts from the QNAP gpl drop + * the emmc has a problem with the hs400 > hs200 speed switch. + * Therefore remove the mmc-hs400-1_8v property + */ + /delete-property/ mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + vqmmc-supply = <&ldo11>; + status = "okay"; }; &switch { @@ -734,8 +738,10 @@ reg = <0x3a001000 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; - phy-handle = <&qca8075_16>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <16>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; dp2: dp2 { @@ -745,8 +751,10 @@ reg = <0x3a001200 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; - phy-handle = <&qca8075_17>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <17>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; dp3: dp3 { @@ -756,8 +764,10 @@ reg = <0x3a001400 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; - phy-handle = <&qca8075_18>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <18>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; dp4: dp4 { @@ -767,8 +777,10 @@ reg = <0x3a001600 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; - phy-handle = <&qca8075_19>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <19>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; dp5: dp5 { @@ -778,8 +790,10 @@ reg = <0x3a001800 0x200>; qcom,mactype = <1>; local-mac-address = [000000000000]; - phy-handle = <&aqr113c_8>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <8>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; dp6: dp6 { @@ -789,13 +803,18 @@ reg = <0x3a007000 0x3fff>; qcom,mactype = <1>; local-mac-address = [000000000000]; - phy-handle = <&aqr113c_0>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <0>; phy-mode = "sgmii"; + mdio-bus = <&mdio>; }; }; &wifi { status = "okay"; - + /* using board_id 0xff is intentionally + * as the stock firmware is also using this default board_id + */ + qcom,board_id = <0xff>; qcom,ath11k-calibration-variant = "QNAP-301w"; }; diff --git a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi index e351a2e75..e692cc942 100644 --- a/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi +++ b/target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -#include "pmp8074.dtsi" - &soc { apc_apm: apm@b111000 { compatible = "qcom,ipq807x-apm"; diff --git a/target/linux/ipq807x/files-5.15/drivers/power/qcom/Kconfig b/target/linux/ipq807x/files-5.15/drivers/power/qcom/Kconfig new file mode 100644 index 000000000..01993a617 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/power/qcom/Kconfig @@ -0,0 +1,7 @@ +config QCOM_APM + bool "Qualcomm Technologies Inc platform specific APM driver" + help + Platform specific driver to manage the power source of + memory arrays. Interfaces with regulator drivers to ensure + SRAM Vmin requirements are met across different performance + levels. diff --git a/target/linux/ipq807x/files-5.15/drivers/power/qcom/Makefile b/target/linux/ipq807x/files-5.15/drivers/power/qcom/Makefile new file mode 100644 index 000000000..43a288e62 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/power/qcom/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_QCOM_APM) += apm.o diff --git a/target/linux/ipq807x/files-5.15/drivers/power/qcom/apm.c b/target/linux/ipq807x/files-5.15/drivers/power/qcom/apm.c new file mode 100644 index 000000000..bd93358e3 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/power/qcom/apm.c @@ -0,0 +1,944 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * VDD_APCC + * ============================================================= + * | VDD_MX | | + * | ==========================|============= | + * ___|___ ___|___ ___|___ ___|___ ___|___ ___|___ + * | | | | | | | | | | | | + * | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC | + * | HS | | | | | | HS | | | | HS | + * |_______| |_______| |_______| |_______| |_______| |_______| + * |_________| |_________| |__________| + * | | | + * ______|_____ ______|_____ _______|_____ + * | | | | | | + * | | | | | | + * | CPU MEM | | L2 MEM | | L3 MEM | + * | Arrays | | Arrays | | Arrays | + * | | | | | | + * |____________| |____________| |_____________| + * + */ + +/* Register value definitions */ +#define APCS_GFMUXA_SEL_VAL 0x13 +#define APCS_GFMUXA_DESEL_VAL 0x03 +#define MSM_APM_MX_MODE_VAL 0x00 +#define MSM_APM_APCC_MODE_VAL 0x10 +#define MSM_APM_MX_DONE_VAL 0x00 +#define MSM_APM_APCC_DONE_VAL 0x03 +#define MSM_APM_OVERRIDE_SEL_VAL 0xb0 +#define MSM_APM_SEC_CLK_SEL_VAL 0x30 +#define SPM_EVENT_SET_VAL 0x01 +#define SPM_EVENT_CLEAR_VAL 0x00 + +/* Register bit mask definitions */ +#define MSM_APM_CTL_STS_MASK 0x0f + +/* Register offset definitions */ +#define APCC_APM_MODE 0x00000098 +#define APCC_APM_CTL_STS 0x000000a8 +#define APCS_SPARE 0x00000068 +#define APCS_VERSION 0x00000fd0 + +#define HMSS_VERSION_1P2 0x10020000 + +#define MSM_APM_SWITCH_TIMEOUT_US 10 +#define SPM_WAKEUP_DELAY_US 2 +#define SPM_EVENT_NUM 6 + +#define MSM_APM_DRIVER_NAME "qcom,msm-apm" + +enum { + MSM8996_ID, + MSM8953_ID, + IPQ807x_ID, +}; + +struct msm_apm_ctrl_dev { + struct list_head list; + struct device *dev; + enum msm_apm_supply supply; + spinlock_t lock; + void __iomem *reg_base; + void __iomem *apcs_csr_base; + void __iomem **apcs_spm_events_addr; + void __iomem *apc0_pll_ctl_addr; + void __iomem *apc1_pll_ctl_addr; + u32 version; + struct dentry *debugfs; + u32 msm_id; +}; + +#if defined(CONFIG_DEBUG_FS) +static struct dentry *apm_debugfs_base; +#endif + +static DEFINE_MUTEX(apm_ctrl_list_mutex); +static LIST_HEAD(apm_ctrl_list); + +/* + * Get the resources associated with the APM controller from device tree + * and remap all I/O addresses that are relevant to this HW revision. + */ +static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev, + struct msm_apm_ctrl_dev *ctrl) +{ + struct device *dev = &pdev->dev; + struct resource *res; + static const char *res_name[SPM_EVENT_NUM] = { + "apc0-l2-spm", + "apc1-l2-spm", + "apc0-cpu0-spm", + "apc0-cpu1-spm", + "apc1-cpu0-spm", + "apc1-cpu1-spm" + }; + int i, ret = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb"); + if (!res) { + dev_err(dev, "Missing PM APCC Global register physical address"); + return -EINVAL; + } + ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!ctrl->reg_base) { + dev_err(dev, "Failed to map PM APCC Global registers\n"); + return -ENOMEM; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr"); + if (!res) { + dev_err(dev, "Missing APCS CSR physical base address"); + return -EINVAL; + } + ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!ctrl->apcs_csr_base) { + dev_err(dev, "Failed to map APCS CSR registers\n"); + return -ENOMEM; + } + + ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION); + + if (ctrl->version >= HMSS_VERSION_1P2) + return ret; + + ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev, + SPM_EVENT_NUM + * sizeof(void __iomem *), + GFP_KERNEL); + if (!ctrl->apcs_spm_events_addr) { + dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n"); + return -ENOMEM; + } + + for (i = 0; i < SPM_EVENT_NUM; i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + res_name[i]); + if (!res) { + dev_err(dev, "Missing address for %s\n", res_name[i]); + ret = -EINVAL; + goto free_events; + } + + ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start, + resource_size(res)); + if (!ctrl->apcs_spm_events_addr[i]) { + dev_err(dev, "Failed to map %s\n", res_name[i]); + ret = -ENOMEM; + goto free_events; + } + + dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i], + &res->start, ctrl->apcs_spm_events_addr[i]); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "apc0-pll-ctl"); + if (!res) { + dev_err(dev, "Missing APC0 PLL CTL physical address\n"); + ret = -EINVAL; + goto free_events; + } + + ctrl->apc0_pll_ctl_addr = devm_ioremap(dev, + res->start, + resource_size(res)); + if (!ctrl->apc0_pll_ctl_addr) { + dev_err(dev, "Failed to map APC0 PLL CTL register\n"); + ret = -ENOMEM; + goto free_events; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "apc1-pll-ctl"); + if (!res) { + dev_err(dev, "Missing APC1 PLL CTL physical address\n"); + ret = -EINVAL; + goto free_events; + } + + ctrl->apc1_pll_ctl_addr = devm_ioremap(dev, + res->start, + resource_size(res)); + if (!ctrl->apc1_pll_ctl_addr) { + dev_err(dev, "Failed to map APC1 PLL CTL register\n"); + ret = -ENOMEM; + goto free_events; + } + + return ret; + +free_events: + devm_kfree(dev, ctrl->apcs_spm_events_addr); + return ret; +} + +/* 8953 register offset definition */ +#define MSM8953_APM_DLY_CNTR 0x2ac + +/* Register field shift definitions */ +#define APM_CTL_SEL_SWITCH_DLY_SHIFT 0 +#define APM_CTL_RESUME_CLK_DLY_SHIFT 8 +#define APM_CTL_HALT_CLK_DLY_SHIFT 16 +#define APM_CTL_POST_HALT_DLY_SHIFT 24 + +/* Register field mask definitions */ +#define APM_CTL_SEL_SWITCH_DLY_MASK GENMASK(7, 0) +#define APM_CTL_RESUME_CLK_DLY_MASK GENMASK(15, 8) +#define APM_CTL_HALT_CLK_DLY_MASK GENMASK(23, 16) +#define APM_CTL_POST_HALT_DLY_MASK GENMASK(31, 24) + +/* + * Get the resources associated with the msm8953 APM controller from + * device tree, remap all I/O addresses, and program the initial + * register configuration required for the 8953 APM controller device. + */ +static int msm8953_apm_ctrl_init(struct platform_device *pdev, + struct msm_apm_ctrl_dev *ctrl) +{ + struct device *dev = &pdev->dev; + struct resource *res; + u32 delay_counter, val = 0, regval = 0; + int rc = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb"); + if (!res) { + dev_err(dev, "Missing PM APCC Global register physical address\n"); + return -ENODEV; + } + ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!ctrl->reg_base) { + dev_err(dev, "Failed to map PM APCC Global registers\n"); + return -ENOMEM; + } + + /* + * Initial APM register configuration required before starting + * APM HW controller. + */ + regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR); + val = regval; + + if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) { + rc = of_property_read_u32(dev->of_node, + "qcom,apm-post-halt-delay", &delay_counter); + if (rc < 0) { + dev_err(dev, "apm-post-halt-delay read failed, rc = %d", + rc); + return rc; + } + + val &= ~APM_CTL_POST_HALT_DLY_MASK; + val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT) + & APM_CTL_POST_HALT_DLY_MASK; + } + + if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) { + rc = of_property_read_u32(dev->of_node, + "qcom,apm-halt-clk-delay", &delay_counter); + if (rc < 0) { + dev_err(dev, "apm-halt-clk-delay read failed, rc = %d", + rc); + return rc; + } + + val &= ~APM_CTL_HALT_CLK_DLY_MASK; + val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT) + & APM_CTL_HALT_CLK_DLY_MASK; + } + + if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) { + rc = of_property_read_u32(dev->of_node, + "qcom,apm-resume-clk-delay", &delay_counter); + if (rc < 0) { + dev_err(dev, "apm-resume-clk-delay read failed, rc = %d", + rc); + return rc; + } + + val &= ~APM_CTL_RESUME_CLK_DLY_MASK; + val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT) + & APM_CTL_RESUME_CLK_DLY_MASK; + } + + if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) { + rc = of_property_read_u32(dev->of_node, + "qcom,apm-sel-switch-delay", &delay_counter); + if (rc < 0) { + dev_err(dev, "apm-sel-switch-delay read failed, rc = %d", + rc); + return rc; + } + + val &= ~APM_CTL_SEL_SWITCH_DLY_MASK; + val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT) + & APM_CTL_SEL_SWITCH_DLY_MASK; + } + + if (val != regval) { + writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR); + /* make sure write completes before return */ + mb(); + } + + return rc; +} + +static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int i, timeout = MSM_APM_SWITCH_TIMEOUT_US; + u32 regval; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&ctrl_dev->lock, flags); + + /* Perform revision-specific programming steps */ + if (ctrl_dev->version < HMSS_VERSION_1P2) { + /* Clear SPM events */ + for (i = 0; i < SPM_EVENT_NUM; i++) + writel_relaxed(SPM_EVENT_CLEAR_VAL, + ctrl_dev->apcs_spm_events_addr[i]); + + udelay(SPM_WAKEUP_DELAY_US); + + /* Switch APC/CBF to GPLL0 clock */ + writel_relaxed(APCS_GFMUXA_SEL_VAL, + ctrl_dev->apcs_csr_base + APCS_SPARE); + ndelay(200); + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, + ctrl_dev->apc0_pll_ctl_addr); + ndelay(200); + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, + ctrl_dev->apc1_pll_ctl_addr); + + /* Ensure writes complete before proceeding */ + mb(); + } + + /* Switch arrays to MX supply and wait for its completion */ + writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base + + APCC_APM_MODE); + + /* Ensure write above completes before delaying */ + mb(); + + while (timeout > 0) { + regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS); + if ((regval & MSM_APM_CTL_STS_MASK) == + MSM_APM_MX_DONE_VAL) + break; + + udelay(1); + timeout--; + } + + if (timeout == 0) { + ret = -ETIMEDOUT; + dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n", + regval); + } + + /* Perform revision-specific programming steps */ + if (ctrl_dev->version < HMSS_VERSION_1P2) { + /* Switch APC/CBF clocks to original source */ + writel_relaxed(APCS_GFMUXA_DESEL_VAL, + ctrl_dev->apcs_csr_base + APCS_SPARE); + ndelay(200); + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, + ctrl_dev->apc0_pll_ctl_addr); + ndelay(200); + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, + ctrl_dev->apc1_pll_ctl_addr); + + /* Complete clock source switch before SPM event sequence */ + mb(); + + /* Set SPM events */ + for (i = 0; i < SPM_EVENT_NUM; i++) + writel_relaxed(SPM_EVENT_SET_VAL, + ctrl_dev->apcs_spm_events_addr[i]); + } + + if (!ret) { + ctrl_dev->supply = MSM_APM_SUPPLY_MX; + dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n"); + } + + spin_unlock_irqrestore(&ctrl_dev->lock, flags); + + return ret; +} + +static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int i, timeout = MSM_APM_SWITCH_TIMEOUT_US; + u32 regval; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&ctrl_dev->lock, flags); + + /* Perform revision-specific programming steps */ + if (ctrl_dev->version < HMSS_VERSION_1P2) { + /* Clear SPM events */ + for (i = 0; i < SPM_EVENT_NUM; i++) + writel_relaxed(SPM_EVENT_CLEAR_VAL, + ctrl_dev->apcs_spm_events_addr[i]); + + udelay(SPM_WAKEUP_DELAY_US); + + /* Switch APC/CBF to GPLL0 clock */ + writel_relaxed(APCS_GFMUXA_SEL_VAL, + ctrl_dev->apcs_csr_base + APCS_SPARE); + ndelay(200); + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, + ctrl_dev->apc0_pll_ctl_addr); + ndelay(200); + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, + ctrl_dev->apc1_pll_ctl_addr); + + /* Ensure previous writes complete before proceeding */ + mb(); + } + + /* Switch arrays to APCC supply and wait for its completion */ + writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base + + APCC_APM_MODE); + + /* Ensure write above completes before delaying */ + mb(); + + while (timeout > 0) { + regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS); + if ((regval & MSM_APM_CTL_STS_MASK) == + MSM_APM_APCC_DONE_VAL) + break; + + udelay(1); + timeout--; + } + + if (timeout == 0) { + ret = -ETIMEDOUT; + dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n", + regval); + } + + /* Perform revision-specific programming steps */ + if (ctrl_dev->version < HMSS_VERSION_1P2) { + /* Set SPM events */ + for (i = 0; i < SPM_EVENT_NUM; i++) + writel_relaxed(SPM_EVENT_SET_VAL, + ctrl_dev->apcs_spm_events_addr[i]); + + /* Complete SPM event sequence before clock source switch */ + mb(); + + /* Switch APC/CBF clocks to original source */ + writel_relaxed(APCS_GFMUXA_DESEL_VAL, + ctrl_dev->apcs_csr_base + APCS_SPARE); + ndelay(200); + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, + ctrl_dev->apc0_pll_ctl_addr); + ndelay(200); + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, + ctrl_dev->apc1_pll_ctl_addr); + } + + if (!ret) { + ctrl_dev->supply = MSM_APM_SUPPLY_APCC; + dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n"); + } + + spin_unlock_irqrestore(&ctrl_dev->lock, flags); + + return ret; +} + +/* 8953 register value definitions */ +#define MSM8953_APM_MX_MODE_VAL 0x00 +#define MSM8953_APM_APCC_MODE_VAL 0x02 +#define MSM8953_APM_MX_DONE_VAL 0x00 +#define MSM8953_APM_APCC_DONE_VAL 0x03 + +/* 8953 register offset definitions */ +#define MSM8953_APCC_APM_MODE 0x000002a8 +#define MSM8953_APCC_APM_CTL_STS 0x000002b0 + +/* 8953 constants */ +#define MSM8953_APM_SWITCH_TIMEOUT_US 500 + +/* Register bit mask definitions */ +#define MSM8953_APM_CTL_STS_MASK 0x1f + +static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int timeout = MSM8953_APM_SWITCH_TIMEOUT_US; + u32 regval; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&ctrl_dev->lock, flags); + + /* Switch arrays to MX supply and wait for its completion */ + writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base + + MSM8953_APCC_APM_MODE); + + /* Ensure write above completes before delaying */ + mb(); + + while (timeout > 0) { + regval = readl_relaxed(ctrl_dev->reg_base + + MSM8953_APCC_APM_CTL_STS); + if ((regval & MSM8953_APM_CTL_STS_MASK) == + MSM8953_APM_MX_DONE_VAL) + break; + + udelay(1); + timeout--; + } + + if (timeout == 0) { + ret = -ETIMEDOUT; + dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n", + regval); + } else { + ctrl_dev->supply = MSM_APM_SUPPLY_MX; + dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n"); + } + + spin_unlock_irqrestore(&ctrl_dev->lock, flags); + + return ret; +} + +static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int timeout = MSM8953_APM_SWITCH_TIMEOUT_US; + u32 regval; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&ctrl_dev->lock, flags); + + /* Switch arrays to APCC supply and wait for its completion */ + writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base + + MSM8953_APCC_APM_MODE); + + /* Ensure write above completes before delaying */ + mb(); + + while (timeout > 0) { + regval = readl_relaxed(ctrl_dev->reg_base + + MSM8953_APCC_APM_CTL_STS); + if ((regval & MSM8953_APM_CTL_STS_MASK) == + MSM8953_APM_APCC_DONE_VAL) + break; + + udelay(1); + timeout--; + } + + if (timeout == 0) { + ret = -ETIMEDOUT; + dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n", + regval); + } else { + ctrl_dev->supply = MSM_APM_SUPPLY_APCC; + dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n"); + } + + spin_unlock_irqrestore(&ctrl_dev->lock, flags); + + return ret; +} + +static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int ret = 0; + + switch (ctrl_dev->msm_id) { + case MSM8996_ID: + ret = msm8996_apm_switch_to_mx(ctrl_dev); + break; + case MSM8953_ID: + case IPQ807x_ID: + ret = msm8953_apm_switch_to_mx(ctrl_dev); + break; + } + + return ret; +} + +static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) +{ + int ret = 0; + + switch (ctrl_dev->msm_id) { + case MSM8996_ID: + ret = msm8996_apm_switch_to_apcc(ctrl_dev); + break; + case MSM8953_ID: + case IPQ807x_ID: + ret = msm8953_apm_switch_to_apcc(ctrl_dev); + break; + } + + return ret; +} + +/** + * msm_apm_get_supply() - Returns the supply that is currently + * powering the memory arrays + * @ctrl_dev: Pointer to an MSM APM controller device + * + * Returns the supply currently selected by the APM. + */ +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev) +{ + return ctrl_dev->supply; +} +EXPORT_SYMBOL(msm_apm_get_supply); + +/** + * msm_apm_set_supply() - Perform the necessary steps to switch the voltage + * source of the memory arrays to a given supply + * @ctrl_dev: Pointer to an MSM APM controller device + * @supply: Power rail to use as supply for the memory + * arrays + * + * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if + * the supply is not supported. + */ +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, + enum msm_apm_supply supply) +{ + int ret; + + switch (supply) { + case MSM_APM_SUPPLY_APCC: + ret = msm_apm_switch_to_apcc(ctrl_dev); + break; + case MSM_APM_SUPPLY_MX: + ret = msm_apm_switch_to_mx(ctrl_dev); + break; + default: + ret = -EPERM; + break; + } + + return ret; +} +EXPORT_SYMBOL(msm_apm_set_supply); + +/** + * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to + * the device in device tree + * @dev: Pointer to the device + * + * The device must specify "qcom,apm-ctrl" property in its device tree + * node which points to an MSM APM controller device node. + * + * Returns an MSM APM controller handle if successful or ERR_PTR on any error. + * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is + * returned. + */ +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev) +{ + struct msm_apm_ctrl_dev *ctrl_dev = NULL; + struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER); + struct device_node *ctrl_node; + + if (!dev || !dev->of_node) { + pr_err("Invalid device node\n"); + return ERR_PTR(-EINVAL); + } + + ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0); + if (!ctrl_node) { + pr_err("Could not find qcom,apm-ctrl property in %s\n", + dev->of_node->full_name); + return ERR_PTR(-ENXIO); + } + + mutex_lock(&apm_ctrl_list_mutex); + list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) { + if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) { + dev_found = ctrl_dev; + break; + } + } + mutex_unlock(&apm_ctrl_list_mutex); + + of_node_put(ctrl_node); + return dev_found; +} +EXPORT_SYMBOL(msm_apm_ctrl_dev_get); + +#if defined(CONFIG_DEBUG_FS) + +static int apm_supply_dbg_open(struct inode *inode, struct file *filep) +{ + filep->private_data = inode->i_private; + + return 0; +} + +static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data; + char buf[10]; + int len; + + if (!ctrl_dev) { + pr_err("invalid apm ctrl handle\n"); + return -ENODEV; + } + + if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC) + len = snprintf(buf, sizeof(buf), "APCC\n"); + else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX) + len = snprintf(buf, sizeof(buf), "MX\n"); + else + len = snprintf(buf, sizeof(buf), "ERR\n"); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations apm_supply_fops = { + .open = apm_supply_dbg_open, + .read = apm_supply_dbg_read, +}; + +static void apm_debugfs_base_init(void) +{ + apm_debugfs_base = debugfs_create_dir("msm-apm", NULL); + + if (IS_ERR_OR_NULL(apm_debugfs_base)) + pr_err("msm-apm debugfs base directory creation failed\n"); +} + +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev) +{ + struct dentry *temp; + + if (IS_ERR_OR_NULL(apm_debugfs_base)) { + pr_err("Base directory missing, cannot create apm debugfs nodes\n"); + return; + } + + ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev), + apm_debugfs_base); + if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) { + pr_err("%s debugfs directory creation failed\n", + dev_name(ctrl_dev->dev)); + return; + } + + temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs, + ctrl_dev, &apm_supply_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("supply mode creation failed\n"); + return; + } +} + +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev) +{ + if (!IS_ERR_OR_NULL(ctrl_dev->debugfs)) + debugfs_remove_recursive(ctrl_dev->debugfs); +} + +static void apm_debugfs_base_remove(void) +{ + debugfs_remove_recursive(apm_debugfs_base); +} +#else + +static void apm_debugfs_base_init(void) +{} + +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev) +{} + +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev) +{} + +static void apm_debugfs_base_remove(void) +{} + +#endif + +static struct of_device_id msm_apm_match_table[] = { + { + .compatible = "qcom,msm-apm", + .data = (void *)(uintptr_t)MSM8996_ID, + }, + { + .compatible = "qcom,msm8953-apm", + .data = (void *)(uintptr_t)MSM8953_ID, + }, + { + .compatible = "qcom,ipq807x-apm", + .data = (void *)(uintptr_t)IPQ807x_ID, + }, + {} +}; + +static int msm_apm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct msm_apm_ctrl_dev *ctrl; + const struct of_device_id *match; + int ret = 0; + + dev_dbg(dev, "probing MSM Array Power Mux driver\n"); + + if (!dev->of_node) { + dev_err(dev, "Device tree node is missing\n"); + return -ENODEV; + } + + match = of_match_device(msm_apm_match_table, dev); + if (!match) + return -ENODEV; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) { + dev_err(dev, "MSM APM controller memory allocation failed\n"); + return -ENOMEM; + } + + INIT_LIST_HEAD(&ctrl->list); + spin_lock_init(&ctrl->lock); + ctrl->dev = dev; + ctrl->msm_id = (uintptr_t)match->data; + platform_set_drvdata(pdev, ctrl); + + switch (ctrl->msm_id) { + case MSM8996_ID: + ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl); + if (ret) { + dev_err(dev, "Failed to add APM controller device\n"); + return ret; + } + break; + case MSM8953_ID: + case IPQ807x_ID: + ret = msm8953_apm_ctrl_init(pdev, ctrl); + if (ret) { + dev_err(dev, "Failed to initialize APM controller device: ret=%d\n", + ret); + return ret; + } + break; + default: + dev_err(dev, "unable to add APM controller device for msm_id:%d\n", + ctrl->msm_id); + return -ENODEV; + } + + apm_debugfs_init(ctrl); + mutex_lock(&apm_ctrl_list_mutex); + list_add_tail(&ctrl->list, &apm_ctrl_list); + mutex_unlock(&apm_ctrl_list_mutex); + + dev_dbg(dev, "MSM Array Power Mux driver probe successful"); + + return ret; +} + +static int msm_apm_remove(struct platform_device *pdev) +{ + struct msm_apm_ctrl_dev *ctrl_dev; + + ctrl_dev = platform_get_drvdata(pdev); + if (ctrl_dev) { + mutex_lock(&apm_ctrl_list_mutex); + list_del(&ctrl_dev->list); + mutex_unlock(&apm_ctrl_list_mutex); + apm_debugfs_deinit(ctrl_dev); + } + + return 0; +} + +static struct platform_driver msm_apm_driver = { + .driver = { + .name = MSM_APM_DRIVER_NAME, + .of_match_table = msm_apm_match_table, + .owner = THIS_MODULE, + }, + .probe = msm_apm_probe, + .remove = msm_apm_remove, +}; + +static int __init msm_apm_init(void) +{ + apm_debugfs_base_init(); + return platform_driver_register(&msm_apm_driver); +} + +static void __exit msm_apm_exit(void) +{ + platform_driver_unregister(&msm_apm_driver); + apm_debugfs_base_remove(); +} + +arch_initcall(msm_apm_init); +module_exit(msm_apm_exit); + +MODULE_DESCRIPTION("MSM Array Power Mux driver"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-npu-regulator.c b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-npu-regulator.c new file mode 100644 index 000000000..e808073c0 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-npu-regulator.c @@ -0,0 +1,695 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cpr3-regulator.h" + +#define IPQ807x_NPU_FUSE_CORNERS 2 +#define IPQ817x_NPU_FUSE_CORNERS 1 +#define IPQ807x_NPU_FUSE_STEP_VOLT 8000 +#define IPQ807x_NPU_VOLTAGE_FUSE_SIZE 6 +#define IPQ807x_NPU_CPR_CLOCK_RATE 19200000 + +#define IPQ807x_NPU_CPR_TCSR_START 6 +#define IPQ807x_NPU_CPR_TCSR_END 7 + +#define NPU_TSENS 5 + +u32 g_valid_npu_fuse_count = IPQ807x_NPU_FUSE_CORNERS; +/** + * struct cpr3_ipq807x_npu_fuses - NPU specific fuse data for IPQ807x + * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value + * for each fuse corner (raw, not converted to a voltage) + * This struct holds the values for all of the fuses read from memory. + */ +struct cpr3_ipq807x_npu_fuses { + u64 init_voltage[IPQ807x_NPU_FUSE_CORNERS]; +}; + +/* + * Constants which define the name of each fuse corner. + */ +enum cpr3_ipq807x_npu_fuse_corner { + CPR3_IPQ807x_NPU_FUSE_CORNER_NOM = 0, + CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO = 1, +}; + +static const char * const cpr3_ipq807x_npu_fuse_corner_name[] = { + [CPR3_IPQ807x_NPU_FUSE_CORNER_NOM] = "NOM", + [CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO] = "TURBO", +}; + +/* + * IPQ807x NPU fuse parameter locations: + * + * Structs are organized with the following dimensions: + * Outer: 0 to 1 for fuse corners from lowest to highest corner + * Inner: large enough to hold the longest set of parameter segments which + * fully defines a fuse parameter, +1 (for NULL termination). + * Each segment corresponds to a contiguous group of bits from a + * single fuse row. These segments are concatentated together in + * order to form the full fuse parameter value. The segments for + * a given parameter may correspond to different fuse rows. + */ +static struct cpr3_fuse_param +ipq807x_npu_init_voltage_param[IPQ807x_NPU_FUSE_CORNERS][2] = { + {{73, 22, 27}, {} }, + {{73, 16, 21}, {} }, +}; + +/* + * Open loop voltage fuse reference voltages in microvolts for IPQ807x + */ +static int +ipq807x_npu_fuse_ref_volt [IPQ807x_NPU_FUSE_CORNERS] = { + 912000, + 992000, +}; + +/* + * IPQ9574 (Few parameters are changed, remaining are same as IPQ807x) + */ +#define IPQ9574_NPU_FUSE_CORNERS 2 +#define IPQ9574_NPU_FUSE_STEP_VOLT 10000 +#define IPQ9574_NPU_CPR_CLOCK_RATE 24000000 + +/* + * fues parameters for IPQ9574 + */ +static struct cpr3_fuse_param +ipq9574_npu_init_voltage_param[IPQ9574_NPU_FUSE_CORNERS][2] = { + {{105, 12, 17}, {} }, + {{105, 6, 11}, {} }, +}; + +/* + * Open loop voltage fuse reference voltages in microvolts for IPQ9574 + */ +static int +ipq9574_npu_fuse_ref_volt [IPQ9574_NPU_FUSE_CORNERS] = { + 862500, + 987500, +}; + +struct cpr3_controller *g_ctrl; + +void cpr3_npu_temp_notify(int sensor, int temp, int low_notif) +{ + u32 prev_sensor_state; + + if (sensor != NPU_TSENS) + return; + + prev_sensor_state = g_ctrl->cur_sensor_state; + if (low_notif) + g_ctrl->cur_sensor_state |= BIT(sensor); + else + g_ctrl->cur_sensor_state &= ~BIT(sensor); + + if (!prev_sensor_state && g_ctrl->cur_sensor_state) + cpr3_handle_temp_open_loop_adjustment(g_ctrl, true); + else if (prev_sensor_state && !g_ctrl->cur_sensor_state) + cpr3_handle_temp_open_loop_adjustment(g_ctrl, false); +} + +/** + * cpr3_ipq807x_npu_read_fuse_data() - load NPU specific fuse parameter values + * @vreg: Pointer to the CPR3 regulator + * + * This function allocates a cpr3_ipq807x_npu_fuses struct, fills it with + * values read out of hardware fuses, and finally copies common fuse values + * into the CPR3 regulator struct. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_ipq807x_npu_read_fuse_data(struct cpr3_regulator *vreg) +{ + void __iomem *base = vreg->thread->ctrl->fuse_base; + struct cpr3_ipq807x_npu_fuses *fuse; + int i, rc; + + fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); + if (!fuse) + return -ENOMEM; + + for (i = 0; i < g_valid_npu_fuse_count; i++) { + rc = cpr3_read_fuse_param(base, + vreg->cpr3_regulator_data->init_voltage_param[i], + &fuse->init_voltage[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", + i, rc); + return rc; + } + } + + vreg->fuse_corner_count = g_valid_npu_fuse_count; + vreg->platform_fuses = fuse; + + return 0; +} + +/** + * cpr3_npu_parse_corner_data() - parse NPU corner data from device tree + * properties of the CPR3 regulator's device node + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr3_npu_parse_corner_data(struct cpr3_regulator *vreg) +{ + int rc; + + rc = cpr3_parse_common_corner_data(vreg); + if (rc) { + cpr3_err(vreg, "error reading corner data, rc=%d\n", rc); + return rc; + } + + return rc; +} + +/** + * cpr3_ipq807x_npu_calculate_open_loop_voltages() - calculate the open-loop + * voltage for each corner of a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * @temp_correction: Temperature based correction + * + * If open-loop voltage interpolation is allowed in device tree, then + * this function calculates the open-loop voltage for a given corner using + * linear interpolation. This interpolation is performed using the processor + * frequencies of the lower and higher Fmax corners along with their fused + * open-loop voltages. + * + * If open-loop voltage interpolation is not allowed, then this function uses + * the Fmax fused open-loop voltage for all of the corners associated with a + * given fuse corner. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_ipq807x_npu_calculate_open_loop_voltages( + struct cpr3_regulator *vreg, bool temp_correction) +{ + struct cpr3_ipq807x_npu_fuses *fuse = vreg->platform_fuses; + struct cpr3_controller *ctrl = vreg->thread->ctrl; + int i, j, rc = 0; + u64 freq_low, volt_low, freq_high, volt_high; + int *fuse_volt; + int *fmax_corner; + + fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt), + GFP_KERNEL); + fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), + GFP_KERNEL); + if (!fuse_volt || !fmax_corner) { + rc = -ENOMEM; + goto done; + } + + for (i = 0; i < vreg->fuse_corner_count; i++) { + if (ctrl->cpr_global_setting == CPR_DISABLED) + fuse_volt[i] = vreg->cpr3_regulator_data->fuse_ref_volt[i]; + else + fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( + vreg->cpr3_regulator_data->fuse_ref_volt[i], + vreg->cpr3_regulator_data->fuse_step_volt, + fuse->init_voltage[i], + IPQ807x_NPU_VOLTAGE_FUSE_SIZE); + + /* Log fused open-loop voltage values for debugging purposes. */ + cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", + cpr3_ipq807x_npu_fuse_corner_name[i], + fuse_volt[i]); + } + + rc = cpr3_determine_part_type(vreg, + fuse_volt[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]); + if (rc) { + cpr3_err(vreg, + "fused part type detection failed failed, rc=%d\n", rc); + goto done; + } + + rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt); + if (rc) { + cpr3_err(vreg, + "fused open-loop voltage adjustment failed, rc=%d\n", + rc); + goto done; + } + if (temp_correction) { + rc = cpr3_determine_temp_base_open_loop_correction(vreg, + fuse_volt); + if (rc) { + cpr3_err(vreg, + "temp open-loop voltage adj. failed, rc=%d\n", + rc); + goto done; + } + } + + for (i = 1; i < vreg->fuse_corner_count; i++) { + if (fuse_volt[i] < fuse_volt[i - 1]) { + cpr3_info(vreg, + "fuse corner %d voltage=%d uV < fuse corner %d \ + voltage=%d uV; overriding: fuse corner %d \ + voltage=%d\n", + i, fuse_volt[i], i - 1, fuse_volt[i - 1], + i, fuse_volt[i - 1]); + fuse_volt[i] = fuse_volt[i - 1]; + } + } + + /* Determine highest corner mapped to each fuse corner */ + j = vreg->fuse_corner_count - 1; + for (i = vreg->corner_count - 1; i >= 0; i--) { + if (vreg->corner[i].cpr_fuse_corner == j) { + fmax_corner[j] = i; + j--; + } + } + + if (j >= 0) { + cpr3_err(vreg, "invalid fuse corner mapping\n"); + rc = -EINVAL; + goto done; + } + + /* + * Interpolation is not possible for corners mapped to the lowest fuse + * corner so use the fuse corner value directly. + */ + for (i = 0; i <= fmax_corner[0]; i++) + vreg->corner[i].open_loop_volt = fuse_volt[0]; + + /* Interpolate voltages for the higher fuse corners. */ + for (i = 1; i < vreg->fuse_corner_count; i++) { + freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; + volt_low = fuse_volt[i - 1]; + freq_high = vreg->corner[fmax_corner[i]].proc_freq; + volt_high = fuse_volt[i]; + + for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) + vreg->corner[j].open_loop_volt = cpr3_interpolate( + freq_low, volt_low, freq_high, volt_high, + vreg->corner[j].proc_freq); + } + +done: + if (rc == 0) { + cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n"); + for (i = 0; i < vreg->corner_count; i++) + cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i, + vreg->corner[i].open_loop_volt); + + rc = cpr3_adjust_open_loop_voltages(vreg); + if (rc) + cpr3_err(vreg, + "open-loop voltage adjustment failed, rc=%d\n", + rc); + } + + kfree(fuse_volt); + kfree(fmax_corner); + return rc; +} + +/** + * cpr3_npu_print_settings() - print out NPU CPR configuration settings into + * the kernel log for debugging purposes + * @vreg: Pointer to the CPR3 regulator + */ +static void cpr3_npu_print_settings(struct cpr3_regulator *vreg) +{ + struct cpr3_corner *corner; + int i; + + cpr3_debug(vreg, + "Corner: Frequency (Hz), Fuse Corner, Floor (uV), \ + Open-Loop (uV), Ceiling (uV)\n"); + for (i = 0; i < vreg->corner_count; i++) { + corner = &vreg->corner[i]; + cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n", + i, corner->proc_freq, corner->cpr_fuse_corner, + corner->floor_volt, corner->open_loop_volt, + corner->ceiling_volt); + } + + if (vreg->thread->ctrl->apm) + cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n", + vreg->thread->ctrl->apm_threshold_volt, + vreg->thread->ctrl->apm_adj_volt); +} + +/** + * cpr3_ipq807x_npu_calc_temp_based_ol_voltages() - Calculate the open loop + * voltages based on temperature based correction margins + * @vreg: Pointer to the CPR3 regulator + */ + +static int +cpr3_ipq807x_npu_calc_temp_based_ol_voltages(struct cpr3_regulator *vreg, + bool temp_correction) +{ + int rc, i; + + rc = cpr3_ipq807x_npu_calculate_open_loop_voltages(vreg, + temp_correction); + if (rc) { + cpr3_err(vreg, + "unable to calculate open-loop voltages, rc=%d\n", rc); + return rc; + } + + rc = cpr3_limit_open_loop_voltages(vreg); + if (rc) { + cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n", + rc); + return rc; + } + + cpr3_open_loop_voltage_as_ceiling(vreg); + + rc = cpr3_limit_floor_voltages(vreg); + if (rc) { + cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc); + return rc; + } + + for (i = 0; i < vreg->corner_count; i++) { + if (temp_correction) + vreg->corner[i].cold_temp_open_loop_volt = + vreg->corner[i].open_loop_volt; + else + vreg->corner[i].normal_temp_open_loop_volt = + vreg->corner[i].open_loop_volt; + } + + cpr3_npu_print_settings(vreg); + + return rc; +} + +/** + * cpr3_npu_init_thread() - perform steps necessary to initialize the + * configuration data for a CPR3 thread + * @thread: Pointer to the CPR3 thread + * + * Return: 0 on success, errno on failure + */ +static int cpr3_npu_init_thread(struct cpr3_thread *thread) +{ + int rc; + + rc = cpr3_parse_common_thread_data(thread); + if (rc) { + cpr3_err(thread->ctrl, + "thread %u CPR thread data from DT- failed, rc=%d\n", + thread->thread_id, rc); + return rc; + } + + return 0; +} + +/** + * cpr3_npu_init_regulator() - perform all steps necessary to initialize the + * configuration data for a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr3_npu_init_regulator(struct cpr3_regulator *vreg) +{ + struct cpr3_ipq807x_npu_fuses *fuse; + int rc, cold_temp = 0; + bool can_adj_cold_temp = cpr3_can_adjust_cold_temp(vreg); + + rc = cpr3_ipq807x_npu_read_fuse_data(vreg); + if (rc) { + cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); + return rc; + } + + fuse = vreg->platform_fuses; + + rc = cpr3_npu_parse_corner_data(vreg); + if (rc) { + cpr3_err(vreg, + "Cannot read CPR corner data from DT, rc=%d\n", rc); + return rc; + } + + rc = cpr3_mem_acc_init(vreg); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(vreg, + "Cannot initialize mem-acc regulator settings, rc=%d\n", + rc); + return rc; + } + + if (can_adj_cold_temp) { + rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, true); + if (rc) { + cpr3_err(vreg, + "unable to calculate open-loop voltages, rc=%d\n", rc); + return rc; + } + } + + rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, false); + if (rc) { + cpr3_err(vreg, + "unable to calculate open-loop voltages, rc=%d\n", rc); + return rc; + } + + if (can_adj_cold_temp) { + cpr3_info(vreg, + "Normal and Cold condition init done. Default to normal.\n"); + + rc = cpr3_get_cold_temp_threshold(vreg, &cold_temp); + if (rc) { + cpr3_err(vreg, + "Get cold temperature threshold failed, rc=%d\n", rc); + return rc; + } + register_low_temp_notif(NPU_TSENS, cold_temp, + cpr3_npu_temp_notify); + } + + return rc; +} + +/** + * cpr3_npu_init_controller() - perform NPU CPR3 controller specific + * initializations + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_npu_init_controller(struct cpr3_controller *ctrl) +{ + int rc; + + rc = cpr3_parse_open_loop_common_ctrl_data(ctrl); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n", + rc); + return rc; + } + + ctrl->ctrl_type = CPR_CTRL_TYPE_CPR3; + ctrl->supports_hw_closed_loop = false; + + return 0; +} + +static const struct cpr3_reg_data ipq807x_cpr_npu = { + .cpr_valid_fuse_count = IPQ807x_NPU_FUSE_CORNERS, + .init_voltage_param = ipq807x_npu_init_voltage_param, + .fuse_ref_volt = ipq807x_npu_fuse_ref_volt, + .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE, +}; + +static const struct cpr3_reg_data ipq817x_cpr_npu = { + .cpr_valid_fuse_count = IPQ817x_NPU_FUSE_CORNERS, + .init_voltage_param = ipq807x_npu_init_voltage_param, + .fuse_ref_volt = ipq807x_npu_fuse_ref_volt, + .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE, +}; + +static const struct cpr3_reg_data ipq9574_cpr_npu = { + .cpr_valid_fuse_count = IPQ9574_NPU_FUSE_CORNERS, + .init_voltage_param = ipq9574_npu_init_voltage_param, + .fuse_ref_volt = ipq9574_npu_fuse_ref_volt, + .fuse_step_volt = IPQ9574_NPU_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ9574_NPU_CPR_CLOCK_RATE, +}; + +static struct of_device_id cpr3_regulator_match_table[] = { + { + .compatible = "qcom,cpr3-ipq807x-npu-regulator", + .data = &ipq807x_cpr_npu + }, + { + .compatible = "qcom,cpr3-ipq817x-npu-regulator", + .data = &ipq817x_cpr_npu + }, + { + .compatible = "qcom,cpr3-ipq9574-npu-regulator", + .data = &ipq9574_cpr_npu + }, + {} +}; + +static int cpr3_npu_regulator_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cpr3_controller *ctrl; + int i, rc; + const struct of_device_id *match; + struct cpr3_reg_data *cpr_data; + + if (!dev->of_node) { + dev_err(dev, "Device tree node is missing\n"); + return -EINVAL; + } + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + g_ctrl = ctrl; + + match = of_match_device(cpr3_regulator_match_table, &pdev->dev); + if (!match) + return -ENODEV; + + cpr_data = (struct cpr3_reg_data *)match->data; + g_valid_npu_fuse_count = cpr_data->cpr_valid_fuse_count; + dev_info(dev, "NPU CPR valid fuse count: %d\n", g_valid_npu_fuse_count); + ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate; + + ctrl->dev = dev; + /* Set to false later if anything precludes CPR operation. */ + ctrl->cpr_allowed_hw = true; + + rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name", + &ctrl->name); + if (rc) { + cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n", + rc); + return rc; + } + + rc = cpr3_map_fuse_base(ctrl, pdev); + if (rc) { + cpr3_err(ctrl, "could not map fuse base address\n"); + return rc; + } + + rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_NPU_CPR_TCSR_START, + IPQ807x_NPU_CPR_TCSR_END); + if (rc) { + cpr3_err(ctrl, "could not read CPR tcsr rsetting\n"); + return rc; + } + + rc = cpr3_allocate_threads(ctrl, 0, 0); + if (rc) { + cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n", + rc); + return rc; + } + + if (ctrl->thread_count != 1) { + cpr3_err(ctrl, "expected 1 thread but found %d\n", + ctrl->thread_count); + return -EINVAL; + } + + rc = cpr3_npu_init_controller(ctrl); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n", + rc); + return rc; + } + + rc = cpr3_npu_init_thread(&ctrl->thread[0]); + if (rc) { + cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc); + return rc; + } + + for (i = 0; i < ctrl->thread[0].vreg_count; i++) { + ctrl->thread[0].vreg[i].cpr3_regulator_data = cpr_data; + rc = cpr3_npu_init_regulator(&ctrl->thread[0].vreg[i]); + if (rc) { + cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n", + rc); + return rc; + } + } + + platform_set_drvdata(pdev, ctrl); + + return cpr3_open_loop_regulator_register(pdev, ctrl); +} + +static int cpr3_npu_regulator_remove(struct platform_device *pdev) +{ + struct cpr3_controller *ctrl = platform_get_drvdata(pdev); + + return cpr3_open_loop_regulator_unregister(ctrl); +} + +static struct platform_driver cpr3_npu_regulator_driver = { + .driver = { + .name = "qcom,cpr3-npu-regulator", + .of_match_table = cpr3_regulator_match_table, + .owner = THIS_MODULE, + }, + .probe = cpr3_npu_regulator_probe, + .remove = cpr3_npu_regulator_remove, +}; + +static int cpr3_regulator_init(void) +{ + return platform_driver_register(&cpr3_npu_regulator_driver); +} +arch_initcall(cpr3_regulator_init); + +static void cpr3_regulator_exit(void) +{ + platform_driver_unregister(&cpr3_npu_regulator_driver); +} +module_exit(cpr3_regulator_exit); + +MODULE_DESCRIPTION("QCOM CPR3 NPU regulator driver"); +MODULE_LICENSE("Dual BSD/GPLv2"); +MODULE_ALIAS("platform:npu-ipq807x"); diff --git a/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.c b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.c new file mode 100644 index 000000000..d5d8a1a0b --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.c @@ -0,0 +1,5112 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpr3-regulator.h" + +#define CPR3_REGULATOR_CORNER_INVALID (-1) +#define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0) + +/* CPR3 registers */ +#define CPR3_REG_CPR_CTL 0x4 +#define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0) +#define CPR3_CPR_CTL_LOOP_ENABLE BIT(0) +#define CPR3_CPR_CTL_LOOP_DISABLE 0 +#define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1) +#define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1 +#define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6) +#define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1 +#define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3 +#define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9) +#define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9 + +#define CPR3_REG_CPR_STATUS 0x8 +#define CPR3_CPR_STATUS_BUSY_MASK BIT(0) +#define CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK BIT(1) + +/* + * This register is not present on controllers that support HW closed-loop + * except CPR4 APSS controller. + */ +#define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC + +#define CPR3_REG_CPR_STEP_QUOT 0x14 +#define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0) +#define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0 +#define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6) +#define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6 + +#define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro)) + +#define CPR3_REG_SENSOR_BYPASS_WRITE(sensor) (0xE0 + 0x4 * ((sensor) / 32)) +#define CPR3_REG_SENSOR_BYPASS_WRITE_BANK(bank) (0xE0 + 0x4 * (bank)) + +#define CPR3_REG_SENSOR_MASK_WRITE(sensor) (0x120 + 0x4 * ((sensor) / 32)) +#define CPR3_REG_SENSOR_MASK_WRITE_BANK(bank) (0x120 + 0x4 * (bank)) +#define CPR3_REG_SENSOR_MASK_READ(sensor) (0x140 + 0x4 * ((sensor) / 32)) + +#define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor)) + +#define CPR3_REG_CONT_CMD 0x800 +#define CPR3_CONT_CMD_ACK 0x1 +#define CPR3_CONT_CMD_NACK 0x0 + +#define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread)) +#define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0) +#define CPR3_THRESH_CONS_DOWN_SHIFT 0 +#define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4) +#define CPR3_THRESH_CONS_UP_SHIFT 4 +#define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8) +#define CPR3_THRESH_DOWN_THRESH_SHIFT 8 +#define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13) +#define CPR3_THRESH_UP_THRESH_SHIFT 13 + +#define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread)) + +#define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread)) +#define CPR3_RESULT0_BUSY_MASK BIT(0) +#define CPR3_RESULT0_STEP_DN_MASK BIT(1) +#define CPR3_RESULT0_STEP_UP_MASK BIT(2) +#define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3) +#define CPR3_RESULT0_ERROR_STEPS_SHIFT 3 +#define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8) +#define CPR3_RESULT0_ERROR_SHIFT 8 +#define CPR3_RESULT0_NEGATIVE_MASK BIT(20) + +#define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread)) +#define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0) +#define CPR3_RESULT1_QUOT_MIN_SHIFT 0 +#define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12) +#define CPR3_RESULT1_QUOT_MAX_SHIFT 12 +#define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24) +#define CPR3_RESULT1_RO_MIN_SHIFT 24 +#define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28) +#define CPR3_RESULT1_RO_MAX_SHIFT 28 + +#define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread)) +#define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0) +#define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0 +#define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6) +#define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6 +#define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16) +#define CPR3_RESULT2_SENSOR_MIN_SHIFT 16 +#define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24) +#define CPR3_RESULT2_SENSOR_MAX_SHIFT 24 + +#define CPR3_REG_IRQ_EN 0x81C +#define CPR3_REG_IRQ_CLEAR 0x820 +#define CPR3_REG_IRQ_STATUS 0x824 +#define CPR3_IRQ_UP BIT(3) +#define CPR3_IRQ_MID BIT(2) +#define CPR3_IRQ_DOWN BIT(1) + +#define CPR3_REG_TARGET_QUOT(thread, ro) \ + (0x840 + 0x440 * (thread) + 0x4 * (ro)) + +/* Registers found only on controllers that support HW closed-loop. */ +#define CPR3_REG_PD_THROTTLE 0xE8 +#define CPR3_PD_THROTTLE_DISABLE 0x0 + +#define CPR3_REG_HW_CLOSED_LOOP 0x3000 +#define CPR3_HW_CLOSED_LOOP_ENABLE 0x0 +#define CPR3_HW_CLOSED_LOOP_DISABLE 0x1 + +#define CPR3_REG_CPR_TIMER_MID_CONT 0x3004 +#define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008 + +#define CPR3_REG_LAST_MEASUREMENT 0x7F8 +#define CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT 0 +#define CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT 4 +#define CPR3_LAST_MEASUREMENT_THREAD_DN(thread) \ + (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT) +#define CPR3_LAST_MEASUREMENT_THREAD_UP(thread) \ + (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT) +#define CPR3_LAST_MEASUREMENT_AGGR_DN BIT(8) +#define CPR3_LAST_MEASUREMENT_AGGR_MID BIT(9) +#define CPR3_LAST_MEASUREMENT_AGGR_UP BIT(10) +#define CPR3_LAST_MEASUREMENT_VALID BIT(11) +#define CPR3_LAST_MEASUREMENT_SAW_ERROR BIT(12) +#define CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK GENMASK(23, 16) +#define CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT 16 + +/* CPR4 controller specific registers and bit definitions */ +#define CPR4_REG_CPR_TIMER_CLAMP 0x10 +#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27) + +#define CPR4_REG_MISC 0x700 +#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20) +#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20 +#define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24) +#define CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT 24 +#define CPR4_MISC_TEMP_SENSOR_ID_END_MASK GENMASK(31, 28) +#define CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT 28 + +#define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4 +#define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0) +#define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0 +#define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5) +#define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5 + +#define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8 +#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18) +#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT 18 + +#define CPR4_REG_MARGIN_TEMP_CORE(core) (0x7AC + 0x4 * (core)) +#define CPR4_MARGIN_TEMP_CORE_ADJ_MASK GENMASK(7, 0) +#define CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT 8 + +#define CPR4_REG_MARGIN_TEMP_POINT0N1 0x7F0 +#define CPR4_MARGIN_TEMP_POINT0_MASK GENMASK(11, 0) +#define CPR4_MARGIN_TEMP_POINT0_SHIFT 0 +#define CPR4_MARGIN_TEMP_POINT1_MASK GENMASK(23, 12) +#define CPR4_MARGIN_TEMP_POINT1_SHIFT 12 +#define CPR4_REG_MARGIN_TEMP_POINT2 0x7F4 +#define CPR4_MARGIN_TEMP_POINT2_MASK GENMASK(11, 0) +#define CPR4_MARGIN_TEMP_POINT2_SHIFT 0 + +#define CPR4_REG_MARGIN_ADJ_CTL 0x7F8 +#define CPR4_MARGIN_ADJ_CTL_BOOST_EN BIT(0) +#define CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN BIT(1) +#define CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN BIT(2) +#define CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN BIT(3) +#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK BIT(4) +#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE BIT(4) +#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE 0 +#define CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN BIT(7) +#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN BIT(8) +#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK GENMASK(16, 12) +#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT 12 +#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK GENMASK(21, 19) +#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT 19 +#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK GENMASK(25, 22) +#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT 22 +#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26) +#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26 + +#define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread)) +#define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31) +#define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0) + +/* + * The amount of time to wait for the CPR controller to become idle when + * performing an aging measurement. + */ +#define CPR3_AGING_MEASUREMENT_TIMEOUT_NS 5000000 + +/* + * The number of individual aging measurements to perform which are then + * averaged together in order to determine the final aging adjustment value. + */ +#define CPR3_AGING_MEASUREMENT_ITERATIONS 16 + +/* + * Aging measurements for the aged and unaged ring oscillators take place a few + * microseconds apart. If the vdd-supply voltage fluctuates between the two + * measurements, then the difference between them will be incorrect. The + * difference could end up too high or too low. This constant defines the + * number of lowest and highest measurements to ignore when averaging. + */ +#define CPR3_AGING_MEASUREMENT_FILTER 3 + +/* + * The number of times to attempt the full aging measurement sequence before + * declaring a measurement failure. + */ +#define CPR3_AGING_RETRY_COUNT 5 + +/* + * The maximum time to wait in microseconds for a CPR register write to + * complete. + */ +#define CPR3_REGISTER_WRITE_DELAY_US 200 + +static DEFINE_MUTEX(cpr3_controller_list_mutex); +static LIST_HEAD(cpr3_controller_list); +static struct dentry *cpr3_debugfs_base; + +/** + * cpr3_read() - read four bytes from the memory address specified + * @ctrl: Pointer to the CPR3 controller + * @offset: Offset in bytes from the CPR3 controller's base address + * + * Return: memory address value + */ +static inline u32 cpr3_read(struct cpr3_controller *ctrl, u32 offset) +{ + if (!ctrl->cpr_enabled) { + cpr3_err(ctrl, "CPR register reads are not possible when CPR clocks are disabled\n"); + return 0; + } + + return readl_relaxed(ctrl->cpr_ctrl_base + offset); +} + +/** + * cpr3_write() - write four bytes to the memory address specified + * @ctrl: Pointer to the CPR3 controller + * @offset: Offset in bytes from the CPR3 controller's base address + * @value: Value to write to the memory address + * + * Return: none + */ +static inline void cpr3_write(struct cpr3_controller *ctrl, u32 offset, + u32 value) +{ + if (!ctrl->cpr_enabled) { + cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); + return; + } + + writel_relaxed(value, ctrl->cpr_ctrl_base + offset); +} + +/** + * cpr3_masked_write() - perform a read-modify-write sequence so that only + * masked bits are modified + * @ctrl: Pointer to the CPR3 controller + * @offset: Offset in bytes from the CPR3 controller's base address + * @mask: Mask identifying the bits that should be modified + * @value: Value to write to the memory address + * + * Return: none + */ +static inline void cpr3_masked_write(struct cpr3_controller *ctrl, u32 offset, + u32 mask, u32 value) +{ + u32 reg_val, orig_val; + + if (!ctrl->cpr_enabled) { + cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); + return; + } + + reg_val = orig_val = readl_relaxed(ctrl->cpr_ctrl_base + offset); + reg_val &= ~mask; + reg_val |= value & mask; + + if (reg_val != orig_val) + writel_relaxed(reg_val, ctrl->cpr_ctrl_base + offset); +} + +/** + * cpr3_ctrl_loop_enable() - enable the CPR sensing loop for a given controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: none + */ +static inline void cpr3_ctrl_loop_enable(struct cpr3_controller *ctrl) +{ + if (ctrl->cpr_enabled && !(ctrl->aggr_corner.sdelta + && ctrl->aggr_corner.sdelta->allow_boost)) + cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_ENABLE); +} + +/** + * cpr3_ctrl_loop_disable() - disable the CPR sensing loop for a given + * controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: none + */ +static inline void cpr3_ctrl_loop_disable(struct cpr3_controller *ctrl) +{ + if (ctrl->cpr_enabled) + cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_DISABLE); +} + +/** + * cpr3_clock_enable() - prepare and enable all clocks used by this CPR3 + * controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_clock_enable(struct cpr3_controller *ctrl) +{ + int rc; + + rc = clk_prepare_enable(ctrl->bus_clk); + if (rc) { + cpr3_err(ctrl, "failed to enable bus clock, rc=%d\n", rc); + return rc; + } + + rc = clk_prepare_enable(ctrl->iface_clk); + if (rc) { + cpr3_err(ctrl, "failed to enable interface clock, rc=%d\n", rc); + clk_disable_unprepare(ctrl->bus_clk); + return rc; + } + + rc = clk_prepare_enable(ctrl->core_clk); + if (rc) { + cpr3_err(ctrl, "failed to enable core clock, rc=%d\n", rc); + clk_disable_unprepare(ctrl->iface_clk); + clk_disable_unprepare(ctrl->bus_clk); + return rc; + } + + return 0; +} + +/** + * cpr3_clock_disable() - disable and unprepare all clocks used by this CPR3 + * controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: none + */ +static void cpr3_clock_disable(struct cpr3_controller *ctrl) +{ + clk_disable_unprepare(ctrl->core_clk); + clk_disable_unprepare(ctrl->iface_clk); + clk_disable_unprepare(ctrl->bus_clk); +} + +/** + * cpr3_ctrl_clear_cpr4_config() - clear the CPR4 register configuration + * programmed for current aggregated corner of a given controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static inline int cpr3_ctrl_clear_cpr4_config(struct cpr3_controller *ctrl) +{ + struct cpr4_sdelta *aggr_sdelta = ctrl->aggr_corner.sdelta; + bool cpr_enabled = ctrl->cpr_enabled; + int i, rc = 0; + + if (!aggr_sdelta || !(aggr_sdelta->allow_core_count_adj + || aggr_sdelta->allow_temp_adj || aggr_sdelta->allow_boost)) + /* cpr4 features are not enabled */ + return 0; + + /* Ensure that CPR clocks are enabled before writing to registers. */ + if (!cpr_enabled) { + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); + return rc; + } + ctrl->cpr_enabled = true; + } + + /* + * Clear feature enable configuration made for current + * aggregated corner. + */ + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK + | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_BOOST_EN + | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, 0); + + cpr3_masked_write(ctrl, CPR4_REG_MISC, + CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, + 0 << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); + + for (i = 0; i <= aggr_sdelta->max_core_count; i++) { + /* Clear voltage margin adjustments programmed in TEMP_COREi */ + cpr3_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE(i), 0); + } + + /* Turn off CPR clocks if they were off before this function call. */ + if (!cpr_enabled) { + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + } + + return 0; +} + +/** + * cpr3_closed_loop_enable() - enable logical CPR closed-loop operation + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_closed_loop_enable(struct cpr3_controller *ctrl) +{ + int rc; + + if (!ctrl->cpr_allowed_hw || !ctrl->cpr_allowed_sw) { + cpr3_err(ctrl, "cannot enable closed-loop CPR operation because it is disallowed\n"); + return -EPERM; + } else if (ctrl->cpr_enabled) { + /* Already enabled */ + return 0; + } else if (ctrl->cpr_suspended) { + /* + * CPR must remain disabled as the system is entering suspend. + */ + return 0; + } + + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "unable to enable CPR clocks, rc=%d\n", rc); + return rc; + } + + ctrl->cpr_enabled = true; + cpr3_debug(ctrl, "CPR closed-loop operation enabled\n"); + + return 0; +} + +/** + * cpr3_closed_loop_disable() - disable logical CPR closed-loop operation + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static inline int cpr3_closed_loop_disable(struct cpr3_controller *ctrl) +{ + if (!ctrl->cpr_enabled) { + /* Already disabled */ + return 0; + } + + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + cpr3_debug(ctrl, "CPR closed-loop operation disabled\n"); + + return 0; +} + +/** + * cpr3_regulator_get_gcnt() - returns the GCNT register value corresponding + * to the clock rate and sensor time of the CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: GCNT value + */ +static u32 cpr3_regulator_get_gcnt(struct cpr3_controller *ctrl) +{ + u64 temp; + unsigned int remainder; + u32 gcnt; + + temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->sensor_time; + remainder = do_div(temp, 1000000000); + if (remainder) + temp++; + /* + * GCNT == 0 corresponds to a single ref clock measurement interval so + * offset GCNT values by 1. + */ + gcnt = temp - 1; + + return gcnt; +} + +/** + * cpr3_regulator_init_thread() - performs hardware initialization of CPR + * thread registers + * @thread: Pointer to the CPR3 thread + * + * CPR interface/bus clocks must be enabled before calling this function. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_init_thread(struct cpr3_thread *thread) +{ + u32 reg; + + reg = (thread->consecutive_up << CPR3_THRESH_CONS_UP_SHIFT) + & CPR3_THRESH_CONS_UP_MASK; + reg |= (thread->consecutive_down << CPR3_THRESH_CONS_DOWN_SHIFT) + & CPR3_THRESH_CONS_DOWN_MASK; + reg |= (thread->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT) + & CPR3_THRESH_UP_THRESH_MASK; + reg |= (thread->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT) + & CPR3_THRESH_DOWN_THRESH_MASK; + + cpr3_write(thread->ctrl, CPR3_REG_THRESH(thread->thread_id), reg); + + /* + * Mask all RO's initially so that unused thread doesn't contribute + * to closed-loop voltage. + */ + cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), + CPR3_RO_MASK); + + return 0; +} + +/** + * cpr4_regulator_init_temp_points() - performs hardware initialization of CPR4 + * registers to track tsen temperature data and also specify the + * temperature band range values to apply different voltage margins + * @ctrl: Pointer to the CPR3 controller + * + * CPR interface/bus clocks must be enabled before calling this function. + * + * Return: 0 on success, errno on failure + */ +static int cpr4_regulator_init_temp_points(struct cpr3_controller *ctrl) +{ + if (!ctrl->allow_temp_adj) + return 0; + + cpr3_masked_write(ctrl, CPR4_REG_MISC, + CPR4_MISC_TEMP_SENSOR_ID_START_MASK, + ctrl->temp_sensor_id_start + << CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT); + + cpr3_masked_write(ctrl, CPR4_REG_MISC, + CPR4_MISC_TEMP_SENSOR_ID_END_MASK, + ctrl->temp_sensor_id_end + << CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT2, + CPR4_MARGIN_TEMP_POINT2_MASK, + (ctrl->temp_band_count == 4 ? ctrl->temp_points[2] : 0x7FF) + << CPR4_MARGIN_TEMP_POINT2_SHIFT); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, + CPR4_MARGIN_TEMP_POINT1_MASK, + (ctrl->temp_band_count >= 3 ? ctrl->temp_points[1] : 0x7FF) + << CPR4_MARGIN_TEMP_POINT1_SHIFT); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, + CPR4_MARGIN_TEMP_POINT0_MASK, + (ctrl->temp_band_count >= 2 ? ctrl->temp_points[0] : 0x7FF) + << CPR4_MARGIN_TEMP_POINT0_SHIFT); + return 0; +} + +/** + * cpr3_regulator_init_cpr4() - performs hardware initialization at the + * controller and thread level required for CPR4 operation. + * @ctrl: Pointer to the CPR3 controller + * + * CPR interface/bus clocks must be enabled before calling this function. + * This function allocates sdelta structures and sdelta tables for aggregated + * corners of the controller and its threads. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_init_cpr4(struct cpr3_controller *ctrl) +{ + struct cpr3_thread *thread; + struct cpr3_regulator *vreg; + struct cpr4_sdelta *sdelta; + int i, j, ctrl_max_core_count, thread_max_core_count, rc = 0; + bool ctrl_valid_sdelta, thread_valid_sdelta; + u32 pmic_step_size = 1; + int thread_id = 0; + u64 temp; + + if (ctrl->supports_hw_closed_loop) { + if (ctrl->saw_use_unit_mV) + pmic_step_size = ctrl->step_volt / 1000; + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK, + (pmic_step_size + << CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT)); + + cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, + CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK, + (ctrl->down_error_step_limit + << CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT)); + + cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, + CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK, + (ctrl->up_error_step_limit + << CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT)); + + /* + * Enable thread aggregation regardless of which threads are + * enabled or disabled. + */ + cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP, + CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN, + CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN); + + switch (ctrl->thread_count) { + case 0: + /* Disable both threads */ + cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(0), + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); + + cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(1), + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); + break; + case 1: + /* Disable unused thread */ + thread_id = ctrl->thread[0].thread_id ? 0 : 1; + cpr3_masked_write(ctrl, + CPR4_REG_CPR_MASK_THREAD(thread_id), + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, + CPR4_CPR_MASK_THREAD_DISABLE_THREAD + | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); + break; + } + } + + if (!ctrl->allow_core_count_adj && !ctrl->allow_temp_adj + && !ctrl->allow_boost) { + /* + * Skip below configuration as none of the features + * are enabled. + */ + return rc; + } + + if (ctrl->supports_hw_closed_loop) + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN, + CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK, + ctrl->step_quot_fixed + << CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN, + (ctrl->use_dynamic_step_quot + ? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0)); + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK, + ctrl->initial_temp_band + << CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT); + + rc = cpr4_regulator_init_temp_points(ctrl); + if (rc) { + cpr3_err(ctrl, "initialize temp points failed, rc=%d\n", rc); + return rc; + } + + if (ctrl->voltage_settling_time) { + /* + * Configure the settling timer used to account for + * one VDD supply step. + */ + temp = (u64)ctrl->cpr_clock_rate + * (u64)ctrl->voltage_settling_time; + do_div(temp, 1000000000); + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS, + CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK, + temp + << CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT); + } + + /* + * Allocate memory for cpr4_sdelta structure and sdelta table for + * controller aggregated corner by finding the maximum core count + * used by any cpr3 regulators. + */ + ctrl_max_core_count = 1; + ctrl_valid_sdelta = false; + for (i = 0; i < ctrl->thread_count; i++) { + thread = &ctrl->thread[i]; + + /* + * Allocate memory for cpr4_sdelta structure and sdelta table + * for thread aggregated corner by finding the maximum core + * count used by any cpr3 regulators of the thread. + */ + thread_max_core_count = 1; + thread_valid_sdelta = false; + for (j = 0; j < thread->vreg_count; j++) { + vreg = &thread->vreg[j]; + thread_max_core_count = max(thread_max_core_count, + vreg->max_core_count); + thread_valid_sdelta |= (vreg->allow_core_count_adj + | vreg->allow_temp_adj + | vreg->allow_boost); + } + if (thread_valid_sdelta) { + sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), + GFP_KERNEL); + if (!sdelta) + return -ENOMEM; + + sdelta->table = devm_kcalloc(ctrl->dev, + thread_max_core_count + * ctrl->temp_band_count, + sizeof(*sdelta->table), + GFP_KERNEL); + if (!sdelta->table) + return -ENOMEM; + + sdelta->boost_table = devm_kcalloc(ctrl->dev, + ctrl->temp_band_count, + sizeof(*sdelta->boost_table), + GFP_KERNEL); + if (!sdelta->boost_table) + return -ENOMEM; + + thread->aggr_corner.sdelta = sdelta; + } + + ctrl_valid_sdelta |= thread_valid_sdelta; + ctrl_max_core_count = max(ctrl_max_core_count, + thread_max_core_count); + } + + if (ctrl_valid_sdelta) { + sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), GFP_KERNEL); + if (!sdelta) + return -ENOMEM; + + sdelta->table = devm_kcalloc(ctrl->dev, ctrl_max_core_count + * ctrl->temp_band_count, + sizeof(*sdelta->table), GFP_KERNEL); + if (!sdelta->table) + return -ENOMEM; + + sdelta->boost_table = devm_kcalloc(ctrl->dev, + ctrl->temp_band_count, + sizeof(*sdelta->boost_table), + GFP_KERNEL); + if (!sdelta->boost_table) + return -ENOMEM; + + ctrl->aggr_corner.sdelta = sdelta; + } + + return 0; +} + +/** + * cpr3_write_temp_core_margin() - programs hardware SDELTA registers with + * the voltage margin adjustments that need to be applied for + * different online core-count and temperature bands. + * @ctrl: Pointer to the CPR3 controller + * @addr: SDELTA register address + * @temp_core_adj: Array of voltage margin values for different temperature + * bands. + * + * CPR interface/bus clocks must be enabled before calling this function. + * + * Return: none + */ +static void cpr3_write_temp_core_margin(struct cpr3_controller *ctrl, + int addr, int *temp_core_adj) +{ + int i, margin_steps; + u32 reg = 0; + + for (i = 0; i < ctrl->temp_band_count; i++) { + margin_steps = max(min(temp_core_adj[i], 127), -128); + reg |= (margin_steps & CPR4_MARGIN_TEMP_CORE_ADJ_MASK) << + (i * CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT); + } + + cpr3_write(ctrl, addr, reg); + cpr3_debug(ctrl, "sdelta offset=0x%08x, val=0x%08x\n", addr, reg); +} + +/** + * cpr3_controller_program_sdelta() - programs hardware SDELTA registers with + * the voltage margin adjustments that need to be applied at + * different online core-count and temperature bands. Also, + * programs hardware register configuration for per-online-core + * and per-temperature based adjustments. + * @ctrl: Pointer to the CPR3 controller + * + * CPR interface/bus clocks must be enabled before calling this function. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_controller_program_sdelta(struct cpr3_controller *ctrl) +{ + struct cpr3_corner *corner = &ctrl->aggr_corner; + struct cpr4_sdelta *sdelta = corner->sdelta; + int i, index, max_core_count, rc = 0; + bool cpr_enabled = ctrl->cpr_enabled; + + if (!sdelta) + /* cpr4_sdelta not defined for current aggregated corner */ + return 0; + + if (ctrl->supports_hw_closed_loop && ctrl->cpr_enabled) { + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, + (ctrl->use_hw_closed_loop && !sdelta->allow_boost) + ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0); + } + + if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj + && !sdelta->allow_boost) { + /* + * Per-online-core, per-temperature and voltage boost + * adjustments are disabled for this aggregation corner. + */ + return 0; + } + + /* Ensure that CPR clocks are enabled before writing to registers. */ + if (!cpr_enabled) { + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); + return rc; + } + ctrl->cpr_enabled = true; + } + + max_core_count = sdelta->max_core_count; + + if (sdelta->allow_core_count_adj || sdelta->allow_temp_adj) { + if (sdelta->allow_core_count_adj) { + /* Program TEMP_CORE0 to same margins as TEMP_CORE1 */ + cpr3_write_temp_core_margin(ctrl, + CPR4_REG_MARGIN_TEMP_CORE(0), + &sdelta->table[0]); + } + + for (i = 0; i < max_core_count; i++) { + index = i * sdelta->temp_band_count; + /* + * Program TEMP_COREi with voltage margin adjustments + * that need to be applied when the number of cores + * becomes i. + */ + cpr3_write_temp_core_margin(ctrl, + CPR4_REG_MARGIN_TEMP_CORE( + sdelta->allow_core_count_adj + ? i + 1 : max_core_count), + &sdelta->table[index]); + } + } + + if (sdelta->allow_boost) { + /* Program only boost_num_cores row of SDELTA */ + cpr3_write_temp_core_margin(ctrl, + CPR4_REG_MARGIN_TEMP_CORE(sdelta->boost_num_cores), + &sdelta->boost_table[0]); + } + + if (!sdelta->allow_core_count_adj && !sdelta->allow_boost) { + cpr3_masked_write(ctrl, CPR4_REG_MISC, + CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, + max_core_count + << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); + } + + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK + | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN + | CPR4_MARGIN_ADJ_CTL_BOOST_EN, + max_core_count << CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT + | ((sdelta->allow_core_count_adj || sdelta->allow_boost) + ? CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN : 0) + | ((sdelta->allow_temp_adj && ctrl->supports_hw_closed_loop) + ? CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN : 0) + | (((ctrl->use_hw_closed_loop && !sdelta->allow_boost) + || !ctrl->supports_hw_closed_loop) + ? CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN : 0) + | (sdelta->allow_boost + ? CPR4_MARGIN_ADJ_CTL_BOOST_EN : 0)); + + /* + * Ensure that all previous CPR register writes have completed before + * continuing. + */ + mb(); + + /* Turn off CPR clocks if they were off before this function call. */ + if (!cpr_enabled) { + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + } + + return 0; +} + +/** + * cpr3_regulator_init_ctrl() - performs hardware initialization of CPR + * controller registers + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_init_ctrl(struct cpr3_controller *ctrl) +{ + int i, j, k, m, rc; + u32 ro_used = 0; + u32 gcnt, cont_dly, up_down_dly, val; + u64 temp; + char *mode; + + if (ctrl->core_clk) { + rc = clk_set_rate(ctrl->core_clk, ctrl->cpr_clock_rate); + if (rc) { + cpr3_err(ctrl, "clk_set_rate(core_clk, %u) failed, rc=%d\n", + ctrl->cpr_clock_rate, rc); + return rc; + } + } + + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); + return rc; + } + ctrl->cpr_enabled = true; + + /* Find all RO's used by any corner of any regulator. */ + for (i = 0; i < ctrl->thread_count; i++) + for (j = 0; j < ctrl->thread[i].vreg_count; j++) + for (k = 0; k < ctrl->thread[i].vreg[j].corner_count; + k++) + for (m = 0; m < CPR3_RO_COUNT; m++) + if (ctrl->thread[i].vreg[j].corner[k]. + target_quot[m]) + ro_used |= BIT(m); + + /* Configure the GCNT of the RO's that will be used */ + gcnt = cpr3_regulator_get_gcnt(ctrl); + for (i = 0; i < CPR3_RO_COUNT; i++) + if (ro_used & BIT(i)) + cpr3_write(ctrl, CPR3_REG_GCNT(i), gcnt); + + /* Configure the loop delay time */ + temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->loop_time; + do_div(temp, 1000000000); + cont_dly = temp; + if (ctrl->supports_hw_closed_loop + && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly); + else + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, cont_dly); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + temp = (u64)ctrl->cpr_clock_rate * + (u64)ctrl->up_down_delay_time; + do_div(temp, 1000000000); + up_down_dly = temp; + if (ctrl->supports_hw_closed_loop) + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, + up_down_dly); + cpr3_debug(ctrl, "up_down_dly=%u, up_down_delay_time=%u ns\n", + up_down_dly, ctrl->up_down_delay_time); + } + + cpr3_debug(ctrl, "cpr_clock_rate=%u HZ, sensor_time=%u ns, loop_time=%u ns, gcnt=%u, cont_dly=%u\n", + ctrl->cpr_clock_rate, ctrl->sensor_time, ctrl->loop_time, + gcnt, cont_dly); + + /* Configure CPR sensor operation */ + val = (ctrl->idle_clocks << CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT) + & CPR3_CPR_CTL_IDLE_CLOCKS_MASK; + val |= (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) + & CPR3_CPR_CTL_COUNT_MODE_MASK; + val |= (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT) + & CPR3_CPR_CTL_COUNT_REPEAT_MASK; + cpr3_write(ctrl, CPR3_REG_CPR_CTL, val); + + cpr3_debug(ctrl, "idle_clocks=%u, count_mode=%u, count_repeat=%u; CPR_CTL=0x%08X\n", + ctrl->idle_clocks, ctrl->count_mode, ctrl->count_repeat, val); + + /* Configure CPR default step quotients */ + val = (ctrl->step_quot_init_min << CPR3_CPR_STEP_QUOT_MIN_SHIFT) + & CPR3_CPR_STEP_QUOT_MIN_MASK; + val |= (ctrl->step_quot_init_max << CPR3_CPR_STEP_QUOT_MAX_SHIFT) + & CPR3_CPR_STEP_QUOT_MAX_MASK; + cpr3_write(ctrl, CPR3_REG_CPR_STEP_QUOT, val); + + cpr3_debug(ctrl, "step_quot_min=%u, step_quot_max=%u; STEP_QUOT=0x%08X\n", + ctrl->step_quot_init_min, ctrl->step_quot_init_max, val); + + /* Configure the CPR sensor ownership */ + for (i = 0; i < ctrl->sensor_count; i++) + cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(i), + ctrl->sensor_owner[i]); + + /* Configure per-thread registers */ + for (i = 0; i < ctrl->thread_count; i++) { + rc = cpr3_regulator_init_thread(&ctrl->thread[i]); + if (rc) { + cpr3_err(ctrl, "CPR thread register initialization failed, rc=%d\n", + rc); + return rc; + } + } + + if (ctrl->supports_hw_closed_loop) { + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, + ctrl->use_hw_closed_loop + ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE + : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); + } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, + ctrl->use_hw_closed_loop + ? CPR3_HW_CLOSED_LOOP_ENABLE + : CPR3_HW_CLOSED_LOOP_DISABLE); + + cpr3_debug(ctrl, "PD_THROTTLE=0x%08X\n", + ctrl->proc_clock_throttle); + } + + if ((ctrl->use_hw_closed_loop || + ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) && + ctrl->vdd_limit_regulator) { + rc = regulator_enable(ctrl->vdd_limit_regulator); + if (rc) { + cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", + rc); + return rc; + } + } + } + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_regulator_init_cpr4(ctrl); + if (rc) { + cpr3_err(ctrl, "CPR4-specific controller initialization failed, rc=%d\n", + rc); + return rc; + } + } + + /* Ensure that all register writes complete before disabling clocks. */ + wmb(); + + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + + if (!ctrl->cpr_allowed_sw || !ctrl->cpr_allowed_hw) + mode = "open-loop"; + else if (ctrl->supports_hw_closed_loop) + mode = ctrl->use_hw_closed_loop + ? "HW closed-loop" : "SW closed-loop"; + else + mode = "closed-loop"; + + cpr3_info(ctrl, "Default CPR mode = %s", mode); + + return 0; +} + +/** + * cpr3_regulator_set_target_quot() - configure the target quotient for each + * RO of the CPR3 thread and set the RO mask + * @thread: Pointer to the CPR3 thread + * + * Return: none + */ +static void cpr3_regulator_set_target_quot(struct cpr3_thread *thread) +{ + u32 new_quot, last_quot; + int i; + + if (thread->aggr_corner.ro_mask == CPR3_RO_MASK + && thread->last_closed_loop_aggr_corner.ro_mask == CPR3_RO_MASK) { + /* Avoid writing target quotients since all RO's are masked. */ + return; + } else if (thread->aggr_corner.ro_mask == CPR3_RO_MASK) { + cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), + CPR3_RO_MASK); + thread->last_closed_loop_aggr_corner.ro_mask = CPR3_RO_MASK; + /* + * Only the RO_MASK register needs to be written since all + * RO's are masked. + */ + return; + } else if (thread->aggr_corner.ro_mask + != thread->last_closed_loop_aggr_corner.ro_mask) { + cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), + thread->aggr_corner.ro_mask); + } + + for (i = 0; i < CPR3_RO_COUNT; i++) { + new_quot = thread->aggr_corner.target_quot[i]; + last_quot = thread->last_closed_loop_aggr_corner.target_quot[i]; + if (new_quot != last_quot) + cpr3_write(thread->ctrl, + CPR3_REG_TARGET_QUOT(thread->thread_id, i), + new_quot); + } + + thread->last_closed_loop_aggr_corner = thread->aggr_corner; + + return; +} + +/** + * cpr3_update_vreg_closed_loop_volt() - update the last known settled + * closed loop voltage for a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * @vdd_volt: Last known settled voltage in microvolts for the + * VDD supply + * @reg_last_measurement: Value read from the LAST_MEASUREMENT register + * + * Return: none + */ +static void cpr3_update_vreg_closed_loop_volt(struct cpr3_regulator *vreg, + int vdd_volt, u32 reg_last_measurement) +{ + bool step_dn, step_up, aggr_step_up, aggr_step_dn, aggr_step_mid; + bool valid, pd_valid, saw_error; + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct cpr3_corner *corner; + u32 id; + + if (vreg->last_closed_loop_corner == CPR3_REGULATOR_CORNER_INVALID) + return; + else + corner = &vreg->corner[vreg->last_closed_loop_corner]; + + if (vreg->thread->last_closed_loop_aggr_corner.ro_mask + == CPR3_RO_MASK || !vreg->aggregated) { + return; + } else if (!ctrl->cpr_enabled || !ctrl->last_corner_was_closed_loop) { + return; + } else if (ctrl->thread_count == 1 + && vdd_volt >= corner->floor_volt + && vdd_volt <= corner->ceiling_volt) { + corner->last_volt = vdd_volt; + cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", + vreg->last_closed_loop_corner, corner->last_volt, + vreg->last_closed_loop_corner, + corner->ceiling_volt, + vreg->last_closed_loop_corner, + corner->floor_volt); + return; + } else if (!ctrl->supports_hw_closed_loop) { + return; + } else if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPR3) { + corner->last_volt = vdd_volt; + cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", + vreg->last_closed_loop_corner, corner->last_volt, + vreg->last_closed_loop_corner, + corner->ceiling_volt, + vreg->last_closed_loop_corner, + corner->floor_volt); + return; + } + + /* CPR clocks are on and HW closed loop is supported */ + valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); + if (!valid) { + cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X valid bit not set\n", + reg_last_measurement); + return; + } + + id = vreg->thread->thread_id; + + step_dn + = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_DN(id)); + step_up + = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_UP(id)); + aggr_step_dn = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_DN); + aggr_step_mid + = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_MID); + aggr_step_up = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_UP); + saw_error = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_SAW_ERROR); + pd_valid + = !((((reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) + >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT) + & vreg->pd_bypass_mask) == vreg->pd_bypass_mask); + + if (!pd_valid) { + cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X, all power domains bypassed\n", + reg_last_measurement); + return; + } else if (step_dn && step_up) { + cpr3_err(vreg, "both up and down status bits set, CPR_LAST_VALID_MEASUREMENT=0x%X\n", + reg_last_measurement); + return; + } else if (aggr_step_dn && step_dn && vdd_volt < corner->last_volt + && vdd_volt >= corner->floor_volt) { + corner->last_volt = vdd_volt; + } else if (aggr_step_up && step_up && vdd_volt > corner->last_volt + && vdd_volt <= corner->ceiling_volt) { + corner->last_volt = vdd_volt; + } else if (aggr_step_mid + && vdd_volt >= corner->floor_volt + && vdd_volt <= corner->ceiling_volt) { + corner->last_volt = vdd_volt; + } else if (saw_error && (vdd_volt == corner->ceiling_volt + || vdd_volt == corner->floor_volt)) { + corner->last_volt = vdd_volt; + } else { + cpr3_debug(vreg, "last_volt not updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, vdd_volt=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", + vreg->last_closed_loop_corner, corner->last_volt, + vreg->last_closed_loop_corner, + corner->ceiling_volt, + vreg->last_closed_loop_corner, corner->floor_volt, + vdd_volt, reg_last_measurement); + return; + } + + cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", + vreg->last_closed_loop_corner, corner->last_volt, + vreg->last_closed_loop_corner, corner->ceiling_volt, + vreg->last_closed_loop_corner, corner->floor_volt, + reg_last_measurement); +} + +/** + * cpr3_regulator_mem_acc_bhs_used() - determines if mem-acc regulators powered + * through a BHS are associated with the CPR3 controller or any of + * the CPR3 regulators it controls. + * @ctrl: Pointer to the CPR3 controller + * + * This function determines if the CPR3 controller or any of its CPR3 regulators + * need to manage mem-acc regulators that are currently powered through a BHS + * and whose corner selection is based upon a particular voltage threshold. + * + * Return: true or false + */ +static bool cpr3_regulator_mem_acc_bhs_used(struct cpr3_controller *ctrl) +{ + struct cpr3_regulator *vreg; + int i, j; + + if (!ctrl->mem_acc_threshold_volt) + return false; + + if (ctrl->mem_acc_regulator) + return true; + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + + if (vreg->mem_acc_regulator) + return true; + } + } + + return false; +} + +/** + * cpr3_regulator_config_bhs_mem_acc() - configure the mem-acc regulator + * settings for hardware blocks currently powered through the BHS. + * @ctrl: Pointer to the CPR3 controller + * @new_volt: New voltage in microvolts that VDD supply needs to + * end up at + * @last_volt: Pointer to the last known voltage in microvolts for the + * VDD supply + * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max + * corner aggregated from all CPR3 threads managed by the + * CPR3 controller + * + * This function programs the mem-acc regulator corners for CPR3 regulators + * whose LDO regulators are in bypassed state. The function also handles + * CPR3 controllers which utilize mem-acc regulators that operate independently + * from the LDO hardware and that must be programmed when the VDD supply + * crosses a particular voltage threshold. + * + * Return: 0 on success, errno on failure. If the VDD supply voltage is + * modified, last_volt is updated to reflect the new voltage setpoint. + */ +static int cpr3_regulator_config_bhs_mem_acc(struct cpr3_controller *ctrl, + int new_volt, int *last_volt, + struct cpr3_corner *aggr_corner) +{ + struct cpr3_regulator *vreg; + int i, j, rc, mem_acc_corn, safe_volt; + int mem_acc_volt = ctrl->mem_acc_threshold_volt; + int ref_volt; + + if (!cpr3_regulator_mem_acc_bhs_used(ctrl)) + return 0; + + ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : + new_volt; + + if (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || + (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt))) { + if (ref_volt < *last_volt) + safe_volt = max(mem_acc_volt, aggr_corner->last_volt); + else + safe_volt = max(mem_acc_volt, *last_volt); + + rc = regulator_set_voltage(ctrl->vdd_regulator, safe_volt, + new_volt < *last_volt ? + ctrl->aggr_corner.ceiling_volt : + new_volt); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", + safe_volt, rc); + return rc; + } + + *last_volt = safe_volt; + + mem_acc_corn = ref_volt < mem_acc_volt ? + ctrl->mem_acc_corner_map[CPR3_MEM_ACC_LOW_CORNER] : + ctrl->mem_acc_corner_map[CPR3_MEM_ACC_HIGH_CORNER]; + + if (ctrl->mem_acc_regulator) { + rc = regulator_set_voltage(ctrl->mem_acc_regulator, + mem_acc_corn, mem_acc_corn); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", + mem_acc_corn, rc); + return rc; + } + } + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + + if (!vreg->mem_acc_regulator) + continue; + + rc = regulator_set_voltage( + vreg->mem_acc_regulator, mem_acc_corn, + mem_acc_corn); + if (rc) { + cpr3_err(vreg, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", + mem_acc_corn, rc); + return rc; + } + } + } + } + + return 0; +} + +/** + * cpr3_regulator_switch_apm_mode() - switch the mode of the APM controller + * associated with a given CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * @new_volt: New voltage in microvolts that VDD supply needs to + * end up at + * @last_volt: Pointer to the last known voltage in microvolts for the + * VDD supply + * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max + * corner aggregated from all CPR3 threads managed by the + * CPR3 controller + * + * This function requests a switch of the APM mode while guaranteeing + * any LDO regulator hardware requirements are satisfied. The function must + * be called once it is known a new VDD supply setpoint crosses the APM + * voltage threshold. + * + * Return: 0 on success, errno on failure. If the VDD supply voltage is + * modified, last_volt is updated to reflect the new voltage setpoint. + */ +static int cpr3_regulator_switch_apm_mode(struct cpr3_controller *ctrl, + int new_volt, int *last_volt, + struct cpr3_corner *aggr_corner) +{ + struct regulator *vdd = ctrl->vdd_regulator; + int apm_volt = ctrl->apm_threshold_volt; + int orig_last_volt = *last_volt; + int rc; + + rc = regulator_set_voltage(vdd, apm_volt, apm_volt); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", + apm_volt, rc); + return rc; + } + + *last_volt = apm_volt; + + rc = msm_apm_set_supply(ctrl->apm, new_volt >= apm_volt + ? ctrl->apm_high_supply : ctrl->apm_low_supply); + if (rc) { + cpr3_err(ctrl, "APM switch failed, rc=%d\n", rc); + /* Roll back the voltage. */ + regulator_set_voltage(vdd, orig_last_volt, INT_MAX); + *last_volt = orig_last_volt; + return rc; + } + return 0; +} + +/** + * cpr3_regulator_config_voltage_crossings() - configure APM and mem-acc + * settings depending upon a new VDD supply setpoint + * + * @ctrl: Pointer to the CPR3 controller + * @new_volt: New voltage in microvolts that VDD supply needs to + * end up at + * @last_volt: Pointer to the last known voltage in microvolts for the + * VDD supply + * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max + * corner aggregated from all CPR3 threads managed by the + * CPR3 controller + * + * This function handles the APM and mem-acc regulator reconfiguration if + * the new VDD supply voltage will result in crossing their respective voltage + * thresholds. + * + * Return: 0 on success, errno on failure. If the VDD supply voltage is + * modified, last_volt is updated to reflect the new voltage setpoint. + */ +static int cpr3_regulator_config_voltage_crossings(struct cpr3_controller *ctrl, + int new_volt, int *last_volt, + struct cpr3_corner *aggr_corner) +{ + bool apm_crossing = false, mem_acc_crossing = false; + bool mem_acc_bhs_used; + int apm_volt = ctrl->apm_threshold_volt; + int mem_acc_volt = ctrl->mem_acc_threshold_volt; + int ref_volt, rc; + + if (ctrl->apm && apm_volt > 0 + && ((*last_volt < apm_volt && apm_volt <= new_volt) + || (*last_volt >= apm_volt && apm_volt > new_volt))) + apm_crossing = true; + + mem_acc_bhs_used = cpr3_regulator_mem_acc_bhs_used(ctrl); + + ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : + new_volt; + + if (mem_acc_bhs_used && + (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || + (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt)))) + mem_acc_crossing = true; + + if (apm_crossing && mem_acc_crossing) { + if ((new_volt < *last_volt && apm_volt >= mem_acc_volt) || + (new_volt >= *last_volt && apm_volt < mem_acc_volt)) { + rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, + last_volt, + aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to switch APM mode\n"); + return rc; + } + + rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, + last_volt, aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); + return rc; + } + } else { + rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, + last_volt, aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); + return rc; + } + + rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, + last_volt, + aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to switch APM mode\n"); + return rc; + } + } + } else if (apm_crossing) { + rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, last_volt, + aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to switch APM mode\n"); + return rc; + } + } else if (mem_acc_crossing) { + rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, + last_volt, aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); + return rc; + } + } + + return 0; +} + +/** + * cpr3_regulator_config_mem_acc() - configure the corner of the mem-acc + * regulator associated with the CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max + * corner aggregated from all CPR3 threads managed by the + * CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_config_mem_acc(struct cpr3_controller *ctrl, + struct cpr3_corner *aggr_corner) +{ + int rc; + + if (ctrl->mem_acc_regulator && aggr_corner->mem_acc_volt) { + rc = regulator_set_voltage(ctrl->mem_acc_regulator, + aggr_corner->mem_acc_volt, + aggr_corner->mem_acc_volt); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", + aggr_corner->mem_acc_volt, rc); + return rc; + } + } + + return 0; +} + +/** + * cpr3_regulator_scale_vdd_voltage() - scale the CPR controlled VDD supply + * voltage to the new level while satisfying any other hardware + * requirements + * @ctrl: Pointer to the CPR3 controller + * @new_volt: New voltage in microvolts that VDD supply needs to end + * up at + * @last_volt: Last known voltage in microvolts for the VDD supply + * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max + * corner aggregated from all CPR3 threads managed by the + * CPR3 controller + * + * This function scales the CPR controlled VDD supply voltage from its + * current level to the new voltage that is specified. If the supply is + * configured to use the APM and the APM threshold is crossed as a result of + * the voltage scaling, then this function also stops at the APM threshold, + * switches the APM source, and finally sets the final new voltage. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_scale_vdd_voltage(struct cpr3_controller *ctrl, + int new_volt, int last_volt, + struct cpr3_corner *aggr_corner) +{ + struct regulator *vdd = ctrl->vdd_regulator; + int rc; + + if (new_volt < last_volt) { + rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); + if (rc) + return rc; + } else { + /* Increasing VDD voltage */ + if (ctrl->system_regulator) { + rc = regulator_set_voltage(ctrl->system_regulator, + aggr_corner->system_volt, INT_MAX); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", + aggr_corner->system_volt, rc); + return rc; + } + } + } + + rc = cpr3_regulator_config_voltage_crossings(ctrl, new_volt, &last_volt, + aggr_corner); + if (rc) { + cpr3_err(ctrl, "unable to handle voltage threshold crossing configurations, rc=%d\n", + rc); + return rc; + } + + /* + * Subtract a small amount from the min_uV parameter so that the + * set voltage request is not dropped by the framework due to being + * duplicate. This is needed in order to switch from hardware + * closed-loop to open-loop successfully. + */ + rc = regulator_set_voltage(vdd, new_volt - (ctrl->cpr_enabled ? 0 : 1), + aggr_corner->ceiling_volt); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", + new_volt, rc); + return rc; + } + + if (new_volt == last_volt && ctrl->supports_hw_closed_loop + && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + /* + * CPR4 features enforce voltage reprogramming when the last + * set voltage and new set voltage are same. This way, we can + * ensure that SAW PMIC STATUS register is updated with newly + * programmed voltage. + */ + rc = regulator_sync_voltage(vdd); + if (rc) { + cpr3_err(ctrl, "regulator_sync_voltage(vdd) == %d failed, rc=%d\n", + new_volt, rc); + return rc; + } + } + + if (new_volt >= last_volt) { + rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); + if (rc) + return rc; + } else { + /* Decreasing VDD voltage */ + if (ctrl->system_regulator) { + rc = regulator_set_voltage(ctrl->system_regulator, + aggr_corner->system_volt, INT_MAX); + if (rc) { + cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", + aggr_corner->system_volt, rc); + return rc; + } + } + } + + return 0; +} + +/** + * cpr3_regulator_get_dynamic_floor_volt() - returns the current dynamic floor + * voltage based upon static configurations and the state of all + * power domains during the last CPR measurement + * @ctrl: Pointer to the CPR3 controller + * @reg_last_measurement: Value read from the LAST_MEASUREMENT register + * + * When using HW closed-loop, the dynamic floor voltage is always returned + * regardless of the current state of the power domains. + * + * Return: dynamic floor voltage in microvolts or 0 if dynamic floor is not + * currently required + */ +static int cpr3_regulator_get_dynamic_floor_volt(struct cpr3_controller *ctrl, + u32 reg_last_measurement) +{ + int dynamic_floor_volt = 0; + struct cpr3_regulator *vreg; + bool valid, pd_valid; + u32 bypass_bits; + int i, j; + + if (!ctrl->supports_hw_closed_loop) + return 0; + + if (likely(!ctrl->use_hw_closed_loop)) { + valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); + bypass_bits + = (reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) + >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT; + } else { + /* + * Ensure that the dynamic floor voltage is always used for + * HW closed-loop since the conditions below cannot be evaluated + * after each CPR measurement. + */ + valid = false; + bypass_bits = 0; + } + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + + if (!vreg->uses_dynamic_floor) + continue; + + pd_valid = !((bypass_bits & vreg->pd_bypass_mask) + == vreg->pd_bypass_mask); + + if (!valid || !pd_valid) + dynamic_floor_volt = max(dynamic_floor_volt, + vreg->corner[ + vreg->dynamic_floor_corner].last_volt); + } + } + + return dynamic_floor_volt; +} + +/** + * cpr3_regulator_max_sdelta_diff() - returns the maximum voltage difference in + * microvolts that can result from different operating conditions + * for the specified sdelta struct + * @sdelta: Pointer to the sdelta structure + * @step_volt: Step size in microvolts between available set + * points of the VDD supply. + * + * Return: voltage difference between the highest and lowest adjustments if + * sdelta and sdelta->table are valid, else 0. + */ +static int cpr3_regulator_max_sdelta_diff(const struct cpr4_sdelta *sdelta, + int step_volt) +{ + int i, j, index, sdelta_min = INT_MAX, sdelta_max = INT_MIN; + + if (!sdelta || !sdelta->table) + return 0; + + for (i = 0; i < sdelta->max_core_count; i++) { + for (j = 0; j < sdelta->temp_band_count; j++) { + index = i * sdelta->temp_band_count + j; + sdelta_min = min(sdelta_min, sdelta->table[index]); + sdelta_max = max(sdelta_max, sdelta->table[index]); + } + } + + return (sdelta_max - sdelta_min) * step_volt; +} + +/** + * cpr3_regulator_aggregate_sdelta() - check open-loop voltages of current + * aggregated corner and current corner of a given regulator + * and adjust the sdelta strucuture data of aggregate corner. + * @aggr_corner: Pointer to accumulated aggregated corner which + * is both an input and an output + * @corner: Pointer to the corner to be aggregated with + * aggr_corner + * @step_volt: Step size in microvolts between available set + * points of the VDD supply. + * + * Return: none + */ +static void cpr3_regulator_aggregate_sdelta( + struct cpr3_corner *aggr_corner, + const struct cpr3_corner *corner, int step_volt) +{ + struct cpr4_sdelta *aggr_sdelta, *sdelta; + int aggr_core_count, core_count, temp_band_count; + u32 aggr_index, index; + int i, j, sdelta_size, cap_steps, adjust_sdelta; + + aggr_sdelta = aggr_corner->sdelta; + sdelta = corner->sdelta; + + if (aggr_corner->open_loop_volt < corner->open_loop_volt) { + /* + * Found the new dominant regulator as its open-loop requirement + * is higher than previous dominant regulator. Calculate cap + * voltage to limit the SDELTA values to make sure the runtime + * (Core-count/temp) adjustments do not violate other + * regulators' voltage requirements. Use cpr4_sdelta values of + * new dominant regulator. + */ + aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, + (corner->open_loop_volt - + aggr_corner->open_loop_volt)); + + /* Clear old data in the sdelta table */ + sdelta_size = aggr_sdelta->max_core_count + * aggr_sdelta->temp_band_count; + + if (aggr_sdelta->allow_core_count_adj + || aggr_sdelta->allow_temp_adj) + memset(aggr_sdelta->table, 0, sdelta_size + * sizeof(*aggr_sdelta->table)); + + if (sdelta->allow_temp_adj || sdelta->allow_core_count_adj) { + /* Copy new data in sdelta table */ + sdelta_size = sdelta->max_core_count + * sdelta->temp_band_count; + if (sdelta->table) + memcpy(aggr_sdelta->table, sdelta->table, + sdelta_size * sizeof(*sdelta->table)); + } + + if (sdelta->allow_boost) { + memcpy(aggr_sdelta->boost_table, sdelta->boost_table, + sdelta->temp_band_count + * sizeof(*sdelta->boost_table)); + aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; + } else if (aggr_sdelta->allow_boost) { + for (i = 0; i < aggr_sdelta->temp_band_count; i++) { + adjust_sdelta = (corner->open_loop_volt + - aggr_corner->open_loop_volt) + / step_volt; + aggr_sdelta->boost_table[i] += adjust_sdelta; + aggr_sdelta->boost_table[i] + = min(aggr_sdelta->boost_table[i], 0); + } + } + + aggr_corner->open_loop_volt = corner->open_loop_volt; + aggr_sdelta->allow_temp_adj = sdelta->allow_temp_adj; + aggr_sdelta->allow_core_count_adj + = sdelta->allow_core_count_adj; + aggr_sdelta->max_core_count = sdelta->max_core_count; + aggr_sdelta->temp_band_count = sdelta->temp_band_count; + } else if (aggr_corner->open_loop_volt > corner->open_loop_volt) { + /* + * Adjust the cap voltage if the open-loop requirement of new + * regulator is the next highest. + */ + aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, + (aggr_corner->open_loop_volt + - corner->open_loop_volt)); + + if (sdelta->allow_boost) { + for (i = 0; i < aggr_sdelta->temp_band_count; i++) { + adjust_sdelta = (aggr_corner->open_loop_volt + - corner->open_loop_volt) + / step_volt; + aggr_sdelta->boost_table[i] = + sdelta->boost_table[i] + adjust_sdelta; + aggr_sdelta->boost_table[i] + = min(aggr_sdelta->boost_table[i], 0); + } + aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; + } + } else { + /* + * Found another dominant regulator with same open-loop + * requirement. Make cap voltage to '0'. Disable core-count + * adjustments as we couldn't support for both regulators. + * Keep enable temp based adjustments if enabled for both + * regulators and choose mininum margin adjustment values + * between them. + */ + aggr_sdelta->cap_volt = 0; + aggr_sdelta->allow_core_count_adj = false; + + if (aggr_sdelta->allow_temp_adj + && sdelta->allow_temp_adj) { + aggr_core_count = aggr_sdelta->max_core_count - 1; + core_count = sdelta->max_core_count - 1; + temp_band_count = sdelta->temp_band_count; + for (j = 0; j < temp_band_count; j++) { + aggr_index = aggr_core_count * temp_band_count + + j; + index = core_count * temp_band_count + j; + aggr_sdelta->table[aggr_index] = + min(aggr_sdelta->table[aggr_index], + sdelta->table[index]); + } + } else { + aggr_sdelta->allow_temp_adj = false; + } + + if (sdelta->allow_boost) { + memcpy(aggr_sdelta->boost_table, sdelta->boost_table, + sdelta->temp_band_count + * sizeof(*sdelta->boost_table)); + aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; + } + } + + /* Keep non-dominant clients boost enable state */ + aggr_sdelta->allow_boost |= sdelta->allow_boost; + if (aggr_sdelta->allow_boost) + aggr_sdelta->allow_core_count_adj = false; + + if (aggr_sdelta->cap_volt && !(aggr_sdelta->cap_volt == INT_MAX)) { + core_count = aggr_sdelta->max_core_count; + temp_band_count = aggr_sdelta->temp_band_count; + /* + * Convert cap voltage from uV to PMIC steps and use to limit + * sdelta margin adjustments. + */ + cap_steps = aggr_sdelta->cap_volt / step_volt; + for (i = 0; i < core_count; i++) + for (j = 0; j < temp_band_count; j++) { + index = i * temp_band_count + j; + aggr_sdelta->table[index] = + min(aggr_sdelta->table[index], + cap_steps); + } + } +} + +/** + * cpr3_regulator_aggregate_corners() - aggregate two corners together + * @aggr_corner: Pointer to accumulated aggregated corner which + * is both an input and an output + * @corner: Pointer to the corner to be aggregated with + * aggr_corner + * @aggr_quot: Flag indicating that target quotients should be + * aggregated as well. + * @step_volt: Step size in microvolts between available set + * points of the VDD supply. + * + * Return: none + */ +static void cpr3_regulator_aggregate_corners(struct cpr3_corner *aggr_corner, + const struct cpr3_corner *corner, bool aggr_quot, + int step_volt) +{ + int i; + + aggr_corner->ceiling_volt + = max(aggr_corner->ceiling_volt, corner->ceiling_volt); + aggr_corner->floor_volt + = max(aggr_corner->floor_volt, corner->floor_volt); + aggr_corner->last_volt + = max(aggr_corner->last_volt, corner->last_volt); + aggr_corner->system_volt + = max(aggr_corner->system_volt, corner->system_volt); + aggr_corner->mem_acc_volt + = max(aggr_corner->mem_acc_volt, corner->mem_acc_volt); + aggr_corner->irq_en |= corner->irq_en; + aggr_corner->use_open_loop |= corner->use_open_loop; + + if (aggr_quot) { + aggr_corner->ro_mask &= corner->ro_mask; + + for (i = 0; i < CPR3_RO_COUNT; i++) + aggr_corner->target_quot[i] + = max(aggr_corner->target_quot[i], + corner->target_quot[i]); + } + + if (aggr_corner->sdelta && corner->sdelta + && (aggr_corner->sdelta->table + || aggr_corner->sdelta->boost_table)) { + cpr3_regulator_aggregate_sdelta(aggr_corner, corner, step_volt); + } else { + aggr_corner->open_loop_volt + = max(aggr_corner->open_loop_volt, + corner->open_loop_volt); + } +} + +/** + * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller + * to reflect the corners used by all CPR3 regulators as well as + * the CPR operating mode + * @ctrl: Pointer to the CPR3 controller + * + * This function aggregates the CPR parameters for all CPR3 regulators + * associated with the VDD supply. Upon success, it sets the aggregated last + * known good voltage. + * + * The VDD supply voltage will not be physically configured unless this + * condition is met by at least one of the regulators of the controller: + * regulator->vreg_enabled == true && + * regulator->current_corner != CPR3_REGULATOR_CORNER_INVALID + * + * CPR registers for the controller and each thread are updated as long as + * ctrl->cpr_enabled == true. + * + * Note, CPR3 controller lock must be held by the caller. + * + * Return: 0 on success, errno on failure + */ +static int _cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) +{ + struct cpr3_corner aggr_corner = {}; + struct cpr3_thread *thread; + struct cpr3_regulator *vreg; + struct cpr4_sdelta *sdelta; + bool valid = false; + bool thread_valid; + int i, j, rc, new_volt, vdd_volt, dynamic_floor_volt, last_corner_volt; + u32 reg_last_measurement = 0, sdelta_size; + int *sdelta_table, *boost_table; + + last_corner_volt = 0; + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + return rc; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + vdd_volt = regulator_get_voltage(ctrl->vdd_regulator); + if (vdd_volt < 0) { + cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", + vdd_volt); + return vdd_volt; + } + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + /* + * Save aggregated corner open-loop voltage which was programmed + * during last corner switch which is used when programming new + * aggregated corner open-loop voltage. + */ + last_corner_volt = ctrl->aggr_corner.open_loop_volt; + } + + if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop && + ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) + reg_last_measurement + = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); + + aggr_corner.sdelta = ctrl->aggr_corner.sdelta; + if (aggr_corner.sdelta) { + sdelta = aggr_corner.sdelta; + sdelta_table = sdelta->table; + if (sdelta_table) { + sdelta_size = sdelta->max_core_count * + sdelta->temp_band_count; + memset(sdelta_table, 0, sdelta_size + * sizeof(*sdelta_table)); + } + + boost_table = sdelta->boost_table; + if (boost_table) + memset(boost_table, 0, sdelta->temp_band_count + * sizeof(*boost_table)); + + memset(sdelta, 0, sizeof(*sdelta)); + sdelta->table = sdelta_table; + sdelta->cap_volt = INT_MAX; + sdelta->boost_table = boost_table; + } + + /* Aggregate the requests of all threads */ + for (i = 0; i < ctrl->thread_count; i++) { + thread = &ctrl->thread[i]; + thread_valid = false; + + sdelta = thread->aggr_corner.sdelta; + if (sdelta) { + sdelta_table = sdelta->table; + if (sdelta_table) { + sdelta_size = sdelta->max_core_count * + sdelta->temp_band_count; + memset(sdelta_table, 0, sdelta_size + * sizeof(*sdelta_table)); + } + + boost_table = sdelta->boost_table; + if (boost_table) + memset(boost_table, 0, sdelta->temp_band_count + * sizeof(*boost_table)); + + memset(sdelta, 0, sizeof(*sdelta)); + sdelta->table = sdelta_table; + sdelta->cap_volt = INT_MAX; + sdelta->boost_table = boost_table; + } + + memset(&thread->aggr_corner, 0, sizeof(thread->aggr_corner)); + thread->aggr_corner.sdelta = sdelta; + thread->aggr_corner.ro_mask = CPR3_RO_MASK; + + for (j = 0; j < thread->vreg_count; j++) { + vreg = &thread->vreg[j]; + + if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop) + cpr3_update_vreg_closed_loop_volt(vreg, + vdd_volt, reg_last_measurement); + + if (!vreg->vreg_enabled + || vreg->current_corner + == CPR3_REGULATOR_CORNER_INVALID) { + /* Cannot participate in aggregation. */ + vreg->aggregated = false; + continue; + } else { + vreg->aggregated = true; + thread_valid = true; + } + + cpr3_regulator_aggregate_corners(&thread->aggr_corner, + &vreg->corner[vreg->current_corner], + true, ctrl->step_volt); + } + + valid |= thread_valid; + + if (thread_valid) + cpr3_regulator_aggregate_corners(&aggr_corner, + &thread->aggr_corner, + false, ctrl->step_volt); + } + + if (valid && ctrl->cpr_allowed_hw && ctrl->cpr_allowed_sw) { + rc = cpr3_closed_loop_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); + return rc; + } + } else { + rc = cpr3_closed_loop_disable(ctrl); + if (rc) { + cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); + return rc; + } + } + + /* No threads are enabled with a valid corner so exit. */ + if (!valid) + return 0; + + /* + * When using CPR hardware closed-loop, the voltage may vary anywhere + * between the floor and ceiling voltage without software notification. + * Therefore, it is required that the floor to ceiling range for the + * aggregated corner not intersect the APM threshold voltage. Adjust + * the floor to ceiling range if this requirement is violated. + * + * The following algorithm is applied in the case that + * floor < threshold <= ceiling: + * if open_loop >= threshold - adj, then floor = threshold + * else ceiling = threshold - step + * where adj = an adjustment factor to ensure sufficient voltage margin + * and step = VDD output step size + * + * The open-loop and last known voltages are also bounded by the new + * floor or ceiling value as needed. + */ + if (ctrl->use_hw_closed_loop + && aggr_corner.ceiling_volt >= ctrl->apm_threshold_volt + && aggr_corner.floor_volt < ctrl->apm_threshold_volt) { + + if (aggr_corner.open_loop_volt + >= ctrl->apm_threshold_volt - ctrl->apm_adj_volt) + aggr_corner.floor_volt = ctrl->apm_threshold_volt; + else + aggr_corner.ceiling_volt + = ctrl->apm_threshold_volt - ctrl->step_volt; + + aggr_corner.last_volt + = max(aggr_corner.last_volt, aggr_corner.floor_volt); + aggr_corner.last_volt + = min(aggr_corner.last_volt, aggr_corner.ceiling_volt); + aggr_corner.open_loop_volt + = max(aggr_corner.open_loop_volt, aggr_corner.floor_volt); + aggr_corner.open_loop_volt + = min(aggr_corner.open_loop_volt, aggr_corner.ceiling_volt); + } + + if (ctrl->use_hw_closed_loop + && aggr_corner.ceiling_volt >= ctrl->mem_acc_threshold_volt + && aggr_corner.floor_volt < ctrl->mem_acc_threshold_volt) { + aggr_corner.floor_volt = ctrl->mem_acc_threshold_volt; + aggr_corner.last_volt = max(aggr_corner.last_volt, + aggr_corner.floor_volt); + aggr_corner.open_loop_volt = max(aggr_corner.open_loop_volt, + aggr_corner.floor_volt); + } + + if (ctrl->use_hw_closed_loop) { + dynamic_floor_volt + = cpr3_regulator_get_dynamic_floor_volt(ctrl, + reg_last_measurement); + if (aggr_corner.floor_volt < dynamic_floor_volt) { + aggr_corner.floor_volt = dynamic_floor_volt; + aggr_corner.last_volt = max(aggr_corner.last_volt, + aggr_corner.floor_volt); + aggr_corner.open_loop_volt + = max(aggr_corner.open_loop_volt, + aggr_corner.floor_volt); + aggr_corner.ceiling_volt = max(aggr_corner.ceiling_volt, + aggr_corner.floor_volt); + } + } + + if (ctrl->cpr_enabled && ctrl->last_corner_was_closed_loop) { + /* + * Always program open-loop voltage for CPR4 controllers which + * support hardware closed-loop. Storing the last closed loop + * voltage in corner structure can still help with debugging. + */ + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) + new_volt = aggr_corner.last_volt; + else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 + && ctrl->supports_hw_closed_loop) + new_volt = aggr_corner.open_loop_volt; + else + new_volt = min(aggr_corner.last_volt + + cpr3_regulator_max_sdelta_diff(aggr_corner.sdelta, + ctrl->step_volt), + aggr_corner.ceiling_volt); + + aggr_corner.last_volt = new_volt; + } else { + new_volt = aggr_corner.open_loop_volt; + aggr_corner.last_volt = aggr_corner.open_loop_volt; + } + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 + && ctrl->supports_hw_closed_loop) { + /* + * Store last aggregated corner open-loop voltage in vdd_volt + * which is used when programming current aggregated corner + * required voltage. + */ + vdd_volt = last_corner_volt; + } + + cpr3_debug(ctrl, "setting new voltage=%d uV\n", new_volt); + rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, + vdd_volt, &aggr_corner); + if (rc) { + cpr3_err(ctrl, "vdd voltage scaling failed, rc=%d\n", rc); + return rc; + } + + /* Only update registers if CPR is enabled. */ + if (ctrl->cpr_enabled) { + if (ctrl->use_hw_closed_loop) { + /* Hardware closed-loop */ + + /* Set ceiling and floor limits in hardware */ + rc = regulator_set_voltage(ctrl->vdd_limit_regulator, + aggr_corner.floor_volt, + aggr_corner.ceiling_volt); + if (rc) { + cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", + rc); + return rc; + } + } else { + /* Software closed-loop */ + + /* + * Disable UP or DOWN interrupts when at ceiling or + * floor respectively. + */ + if (new_volt == aggr_corner.floor_volt) + aggr_corner.irq_en &= ~CPR3_IRQ_DOWN; + if (new_volt == aggr_corner.ceiling_volt) + aggr_corner.irq_en &= ~CPR3_IRQ_UP; + + cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, + CPR3_IRQ_UP | CPR3_IRQ_DOWN); + cpr3_write(ctrl, CPR3_REG_IRQ_EN, aggr_corner.irq_en); + } + + for (i = 0; i < ctrl->thread_count; i++) { + cpr3_regulator_set_target_quot(&ctrl->thread[i]); + + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + + if (vreg->vreg_enabled) + vreg->last_closed_loop_corner + = vreg->current_corner; + } + } + + if (ctrl->proc_clock_throttle) { + if (aggr_corner.ceiling_volt > aggr_corner.floor_volt + && (ctrl->use_hw_closed_loop + || new_volt < aggr_corner.ceiling_volt)) + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + ctrl->proc_clock_throttle); + else + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + CPR3_PD_THROTTLE_DISABLE); + } + + /* + * Ensure that all CPR register writes complete before + * re-enabling CPR loop operation. + */ + wmb(); + } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 + && ctrl->vdd_limit_regulator) { + /* Set ceiling and floor limits in hardware */ + rc = regulator_set_voltage(ctrl->vdd_limit_regulator, + aggr_corner.floor_volt, + aggr_corner.ceiling_volt); + if (rc) { + cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", + rc); + return rc; + } + } + + ctrl->aggr_corner = aggr_corner; + + if (ctrl->allow_core_count_adj || ctrl->allow_temp_adj + || ctrl->allow_boost) { + rc = cpr3_controller_program_sdelta(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to program sdelta, rc=%d\n", rc); + return rc; + } + } + + /* + * Only enable the CPR controller if it is possible to set more than + * one vdd-supply voltage. + */ + if (aggr_corner.ceiling_volt > aggr_corner.floor_volt && + !aggr_corner.use_open_loop) + cpr3_ctrl_loop_enable(ctrl); + + ctrl->last_corner_was_closed_loop = ctrl->cpr_enabled; + cpr3_debug(ctrl, "CPR configuration updated\n"); + + return 0; +} + +/** + * cpr3_regulator_wait_for_idle() - wait for the CPR controller to no longer be + * busy + * @ctrl: Pointer to the CPR3 controller + * @max_wait_ns: Max wait time in nanoseconds + * + * Return: 0 on success or -ETIMEDOUT if the controller was still busy after + * the maximum delay time + */ +static int cpr3_regulator_wait_for_idle(struct cpr3_controller *ctrl, + s64 max_wait_ns) +{ + ktime_t start, end; + s64 time_ns; + u32 reg; + + /* + * Ensure that all previous CPR register writes have completed before + * checking the status register. + */ + mb(); + + start = ktime_get(); + do { + end = ktime_get(); + time_ns = ktime_to_ns(ktime_sub(end, start)); + if (time_ns > max_wait_ns) { + cpr3_err(ctrl, "CPR controller still busy after %lld us\n", + div_s64(time_ns, 1000)); + return -ETIMEDOUT; + } + usleep_range(50, 100); + reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); + } while (reg & CPR3_CPR_STATUS_BUSY_MASK); + + return 0; +} + +/** + * cmp_int() - int comparison function to be passed into the sort() function + * which leads to ascending sorting + * @a: First int value + * @b: Second int value + * + * Return: >0 if a > b, 0 if a == b, <0 if a < b + */ +static int cmp_int(const void *a, const void *b) +{ + return *(int *)a - *(int *)b; +} + +/** + * cpr3_regulator_measure_aging() - measure the quotient difference for the + * specified CPR aging sensor + * @ctrl: Pointer to the CPR3 controller + * @aging_sensor: Aging sensor to measure + * + * Note that vdd-supply must be configured to the aging reference voltage before + * calling this function. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_measure_aging(struct cpr3_controller *ctrl, + struct cpr3_aging_sensor_info *aging_sensor) +{ + u32 mask, reg, result, quot_min, quot_max, sel_min, sel_max; + u32 quot_min_scaled, quot_max_scaled; + u32 gcnt, gcnt_ref, gcnt0_restore, gcnt1_restore, irq_restore; + u32 ro_mask_restore, cont_dly_restore, up_down_dly_restore = 0; + int quot_delta, quot_delta_scaled, quot_delta_scaled_sum; + int *quot_delta_results; + int rc, rc2, i, aging_measurement_count, filtered_count; + bool is_aging_measurement; + + quot_delta_results = kcalloc(CPR3_AGING_MEASUREMENT_ITERATIONS, + sizeof(*quot_delta_results), GFP_KERNEL); + if (!quot_delta_results) + return -ENOMEM; + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + kfree(quot_delta_results); + return rc; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + /* Enable up, down, and mid CPR interrupts */ + irq_restore = cpr3_read(ctrl, CPR3_REG_IRQ_EN); + cpr3_write(ctrl, CPR3_REG_IRQ_EN, + CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); + + /* Ensure that the aging sensor is assigned to CPR thread 0 */ + cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), 0); + + /* Switch from HW to SW closed-loop if necessary */ + if (ctrl->supports_hw_closed_loop) { + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); + } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, + CPR3_HW_CLOSED_LOOP_DISABLE); + } + } + + /* Configure the GCNT for RO0 and RO1 that are used for aging */ + gcnt0_restore = cpr3_read(ctrl, CPR3_REG_GCNT(0)); + gcnt1_restore = cpr3_read(ctrl, CPR3_REG_GCNT(1)); + gcnt_ref = cpr3_regulator_get_gcnt(ctrl); + gcnt = gcnt_ref * 3 / 2; + cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt); + cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt); + + /* Unmask all RO's */ + ro_mask_restore = cpr3_read(ctrl, CPR3_REG_RO_MASK(0)); + cpr3_write(ctrl, CPR3_REG_RO_MASK(0), 0); + + /* + * Mask all sensors except for the one to measure and bypass all + * sensors in collapsible domains. + */ + for (i = 0; i <= ctrl->sensor_count / 32; i++) { + mask = GENMASK(min(31, ctrl->sensor_count - i * 32), 0); + if (aging_sensor->sensor_id / 32 >= i + && aging_sensor->sensor_id / 32 < (i + 1)) + mask &= ~BIT(aging_sensor->sensor_id % 32); + cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), mask); + cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), + aging_sensor->bypass_mask[i]); + } + + /* Set CPR loop delays to 0 us */ + if (ctrl->supports_hw_closed_loop + && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cont_dly_restore = cpr3_read(ctrl, CPR3_REG_CPR_TIMER_MID_CONT); + up_down_dly_restore = cpr3_read(ctrl, + CPR3_REG_CPR_TIMER_UP_DN_CONT); + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, 0); + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, 0); + } else { + cont_dly_restore = cpr3_read(ctrl, + CPR3_REG_CPR_TIMER_AUTO_CONT); + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, 0); + } + + /* Set count mode to all-at-once min with no repeat */ + cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, + CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN + << CPR3_CPR_CTL_COUNT_MODE_SHIFT); + + cpr3_ctrl_loop_enable(ctrl); + + rc = cpr3_regulator_wait_for_idle(ctrl, + CPR3_AGING_MEASUREMENT_TIMEOUT_NS); + if (rc) + goto cleanup; + + /* Set count mode to all-at-once aging */ + cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, CPR3_CPR_CTL_COUNT_MODE_MASK, + CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE + << CPR3_CPR_CTL_COUNT_MODE_SHIFT); + + aging_measurement_count = 0; + for (i = 0; i < CPR3_AGING_MEASUREMENT_ITERATIONS; i++) { + /* Send CONT_NACK */ + cpr3_write(ctrl, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_NACK); + + rc = cpr3_regulator_wait_for_idle(ctrl, + CPR3_AGING_MEASUREMENT_TIMEOUT_NS); + if (rc) + goto cleanup; + + /* Check for PAGE_IS_AGE flag in status register */ + reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); + is_aging_measurement + = reg & CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK; + + /* Read CPR measurement results */ + result = cpr3_read(ctrl, CPR3_REG_RESULT1(0)); + quot_min = (result & CPR3_RESULT1_QUOT_MIN_MASK) + >> CPR3_RESULT1_QUOT_MIN_SHIFT; + quot_max = (result & CPR3_RESULT1_QUOT_MAX_MASK) + >> CPR3_RESULT1_QUOT_MAX_SHIFT; + sel_min = (result & CPR3_RESULT1_RO_MIN_MASK) + >> CPR3_RESULT1_RO_MIN_SHIFT; + sel_max = (result & CPR3_RESULT1_RO_MAX_MASK) + >> CPR3_RESULT1_RO_MAX_SHIFT; + + /* + * Scale the quotients so that they are equivalent to the fused + * values. This accounts for the difference in measurement + * interval times. + */ + quot_min_scaled = quot_min * (gcnt_ref + 1) / (gcnt + 1); + quot_max_scaled = quot_max * (gcnt_ref + 1) / (gcnt + 1); + + if (sel_max == 1) { + quot_delta = quot_max - quot_min; + quot_delta_scaled = quot_max_scaled - quot_min_scaled; + } else { + quot_delta = quot_min - quot_max; + quot_delta_scaled = quot_min_scaled - quot_max_scaled; + } + + if (is_aging_measurement) + quot_delta_results[aging_measurement_count++] + = quot_delta_scaled; + + cpr3_debug(ctrl, "aging results: page_is_age=%u, sel_min=%u, sel_max=%u, quot_min=%u, quot_max=%u, quot_delta=%d, quot_min_scaled=%u, quot_max_scaled=%u, quot_delta_scaled=%d\n", + is_aging_measurement, sel_min, sel_max, quot_min, + quot_max, quot_delta, quot_min_scaled, quot_max_scaled, + quot_delta_scaled); + } + + filtered_count + = aging_measurement_count - CPR3_AGING_MEASUREMENT_FILTER * 2; + if (filtered_count > 0) { + sort(quot_delta_results, aging_measurement_count, + sizeof(*quot_delta_results), cmp_int, NULL); + + quot_delta_scaled_sum = 0; + for (i = 0; i < filtered_count; i++) + quot_delta_scaled_sum + += quot_delta_results[i + + CPR3_AGING_MEASUREMENT_FILTER]; + + aging_sensor->measured_quot_diff + = quot_delta_scaled_sum / filtered_count; + cpr3_info(ctrl, "average quotient delta=%d (count=%d)\n", + aging_sensor->measured_quot_diff, + filtered_count); + } else { + cpr3_err(ctrl, "%d aging measurements completed after %d iterations\n", + aging_measurement_count, + CPR3_AGING_MEASUREMENT_ITERATIONS); + rc = -EBUSY; + } + +cleanup: + kfree(quot_delta_results); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc2 = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc2) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc2); + rc = rc2; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_restore); + + cpr3_write(ctrl, CPR3_REG_RO_MASK(0), ro_mask_restore); + + cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt0_restore); + cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt1_restore); + + if (ctrl->supports_hw_closed_loop + && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly_restore); + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, + up_down_dly_restore); + } else { + cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, + cont_dly_restore); + } + + for (i = 0; i <= ctrl->sensor_count / 32; i++) { + cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), 0); + cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), 0); + } + + cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, + (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) + | (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT)); + + cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), + ctrl->sensor_owner[aging_sensor->sensor_id]); + + cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, + CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); + + if (ctrl->supports_hw_closed_loop) { + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, + ctrl->use_hw_closed_loop + ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE + : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); + } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, + ctrl->use_hw_closed_loop + ? CPR3_HW_CLOSED_LOOP_ENABLE + : CPR3_HW_CLOSED_LOOP_DISABLE); + } + } + + return rc; +} + +/** + * cpr3_regulator_readjust_volt_and_quot() - readjust the target quotients as + * well as the floor, ceiling, and open-loop voltages for the + * regulator by removing the old adjustment and adding the new one + * @vreg: Pointer to the CPR3 regulator + * @old_adjust_volt: Old aging adjustment voltage in microvolts + * @new_adjust_volt: New aging adjustment voltage in microvolts + * + * Also reset the cached closed loop voltage (last_volt) to equal the open-loop + * voltage for each corner. + * + * Return: None + */ +static void cpr3_regulator_readjust_volt_and_quot(struct cpr3_regulator *vreg, + int old_adjust_volt, int new_adjust_volt) +{ + unsigned long long temp; + int i, j, old_volt, new_volt, rounded_volt; + + if (!vreg->aging_allowed) + return; + + for (i = 0; i < vreg->corner_count; i++) { + temp = (unsigned long long)old_adjust_volt + * (unsigned long long)vreg->corner[i].aging_derate; + do_div(temp, 1000); + old_volt = temp; + + temp = (unsigned long long)new_adjust_volt + * (unsigned long long)vreg->corner[i].aging_derate; + do_div(temp, 1000); + new_volt = temp; + + old_volt = min(vreg->aging_max_adjust_volt, old_volt); + new_volt = min(vreg->aging_max_adjust_volt, new_volt); + + for (j = 0; j < CPR3_RO_COUNT; j++) { + if (vreg->corner[i].target_quot[j] != 0) { + vreg->corner[i].target_quot[j] + += cpr3_quot_adjustment( + vreg->corner[i].ro_scale[j], + new_volt) + - cpr3_quot_adjustment( + vreg->corner[i].ro_scale[j], + old_volt); + } + } + + rounded_volt = CPR3_ROUND(new_volt, + vreg->thread->ctrl->step_volt); + + if (!vreg->aging_allow_open_loop_adj) + rounded_volt = 0; + + vreg->corner[i].ceiling_volt + = vreg->corner[i].unaged_ceiling_volt + rounded_volt; + vreg->corner[i].ceiling_volt = min(vreg->corner[i].ceiling_volt, + vreg->corner[i].abs_ceiling_volt); + vreg->corner[i].floor_volt + = vreg->corner[i].unaged_floor_volt + rounded_volt; + vreg->corner[i].floor_volt = min(vreg->corner[i].floor_volt, + vreg->corner[i].ceiling_volt); + vreg->corner[i].open_loop_volt + = vreg->corner[i].unaged_open_loop_volt + rounded_volt; + vreg->corner[i].open_loop_volt + = min(vreg->corner[i].open_loop_volt, + vreg->corner[i].ceiling_volt); + + vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; + + cpr3_debug(vreg, "corner %d: applying %d uV closed-loop and %d uV open-loop voltage margin adjustment\n", + i, new_volt, rounded_volt); + } +} + +/** + * cpr3_regulator_set_aging_ref_adjustment() - adjust target quotients for the + * regulators managed by this CPR controller to account for aging + * @ctrl: Pointer to the CPR3 controller + * @ref_adjust_volt: New aging reference adjustment voltage in microvolts to + * apply to all regulators managed by this CPR controller + * + * The existing aging adjustment as defined by ctrl->aging_ref_adjust_volt is + * first removed and then the adjustment is applied. Lastly, the value of + * ctrl->aging_ref_adjust_volt is updated to ref_adjust_volt. + */ +static void cpr3_regulator_set_aging_ref_adjustment( + struct cpr3_controller *ctrl, int ref_adjust_volt) +{ + struct cpr3_regulator *vreg; + int i, j; + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + cpr3_regulator_readjust_volt_and_quot(vreg, + ctrl->aging_ref_adjust_volt, ref_adjust_volt); + } + } + + ctrl->aging_ref_adjust_volt = ref_adjust_volt; +} + +/** + * cpr3_regulator_aging_adjust() - adjust the target quotients for regulators + * based on the output of CPR aging sensors + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_aging_adjust(struct cpr3_controller *ctrl) +{ + struct cpr3_regulator *vreg; + struct cpr3_corner restore_aging_corner; + struct cpr3_corner *corner; + int *restore_current_corner; + bool *restore_vreg_enabled; + int i, j, id, rc, rc2, vreg_count, aging_volt, max_aging_volt = 0; + u32 reg; + + if (!ctrl->aging_required || !ctrl->cpr_enabled + || ctrl->aggr_corner.ceiling_volt == 0 + || ctrl->aggr_corner.ceiling_volt > ctrl->aging_ref_volt) + return 0; + + for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + vreg_count++; + + if (vreg->aging_allowed && vreg->vreg_enabled + && vreg->current_corner > vreg->aging_corner) + return 0; + } + } + + /* Verify that none of the aging sensors are currently masked. */ + for (i = 0; i < ctrl->aging_sensor_count; i++) { + id = ctrl->aging_sensor[i].sensor_id; + reg = cpr3_read(ctrl, CPR3_REG_SENSOR_MASK_READ(id)); + if (reg & BIT(id % 32)) + return 0; + } + + /* + * Verify that the aging possible register (if specified) has an + * acceptable value. + */ + if (ctrl->aging_possible_reg) { + reg = readl_relaxed(ctrl->aging_possible_reg); + reg &= ctrl->aging_possible_mask; + if (reg != ctrl->aging_possible_val) + return 0; + } + + restore_current_corner = kcalloc(vreg_count, + sizeof(*restore_current_corner), GFP_KERNEL); + restore_vreg_enabled = kcalloc(vreg_count, + sizeof(*restore_vreg_enabled), GFP_KERNEL); + if (!restore_current_corner || !restore_vreg_enabled) { + kfree(restore_current_corner); + kfree(restore_vreg_enabled); + return -ENOMEM; + } + + /* Force all regulators to the aging corner */ + for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { + vreg = &ctrl->thread[i].vreg[j]; + + restore_current_corner[vreg_count] + = vreg->current_corner; + restore_vreg_enabled[vreg_count] + = vreg->vreg_enabled; + + vreg->current_corner = vreg->aging_corner; + vreg->vreg_enabled = true; + } + } + + /* Force one of the regulators to require the aging reference voltage */ + vreg = &ctrl->thread[0].vreg[0]; + corner = &vreg->corner[vreg->current_corner]; + restore_aging_corner = *corner; + corner->ceiling_volt = ctrl->aging_ref_volt; + corner->floor_volt = ctrl->aging_ref_volt; + corner->open_loop_volt = ctrl->aging_ref_volt; + corner->last_volt = ctrl->aging_ref_volt; + + /* Skip last_volt caching */ + ctrl->last_corner_was_closed_loop = false; + + /* Set the vdd supply voltage to the aging reference voltage */ + rc = _cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(ctrl, "unable to force vdd-supply to the aging reference voltage=%d uV, rc=%d\n", + ctrl->aging_ref_volt, rc); + goto cleanup; + } + + if (ctrl->aging_vdd_mode) { + rc = regulator_set_mode(ctrl->vdd_regulator, + ctrl->aging_vdd_mode); + if (rc) { + cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", + ctrl->aging_vdd_mode, rc); + goto cleanup; + } + } + + /* Perform aging measurement on all aging sensors */ + for (i = 0; i < ctrl->aging_sensor_count; i++) { + for (j = 0; j < CPR3_AGING_RETRY_COUNT; j++) { + rc = cpr3_regulator_measure_aging(ctrl, + &ctrl->aging_sensor[i]); + if (!rc) + break; + } + + if (!rc) { + aging_volt = + cpr3_voltage_adjustment( + ctrl->aging_sensor[i].ro_scale, + ctrl->aging_sensor[i].measured_quot_diff + - ctrl->aging_sensor[i].init_quot_diff); + max_aging_volt = max(max_aging_volt, aging_volt); + } else { + cpr3_err(ctrl, "CPR aging measurement failed after %d tries, rc=%d\n", + j, rc); + ctrl->aging_failed = true; + ctrl->aging_required = false; + goto cleanup; + } + } + +cleanup: + vreg = &ctrl->thread[0].vreg[0]; + vreg->corner[vreg->current_corner] = restore_aging_corner; + + for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { + vreg = &ctrl->thread[i].vreg[j]; + vreg->current_corner + = restore_current_corner[vreg_count]; + vreg->vreg_enabled = restore_vreg_enabled[vreg_count]; + } + } + + kfree(restore_current_corner); + kfree(restore_vreg_enabled); + + /* Adjust the CPR target quotients according to the aging measurement */ + if (!rc) { + cpr3_regulator_set_aging_ref_adjustment(ctrl, max_aging_volt); + + cpr3_info(ctrl, "aging measurement successful; aging reference adjustment voltage=%d uV\n", + ctrl->aging_ref_adjust_volt); + ctrl->aging_succeeded = true; + ctrl->aging_required = false; + } + + if (ctrl->aging_complete_vdd_mode) { + rc = regulator_set_mode(ctrl->vdd_regulator, + ctrl->aging_complete_vdd_mode); + if (rc) + cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", + ctrl->aging_complete_vdd_mode, rc); + } + + /* Skip last_volt caching */ + ctrl->last_corner_was_closed_loop = false; + + /* + * Restore vdd-supply to the voltage before the aging measurement and + * restore the CPR3 controller hardware state. + */ + rc2 = _cpr3_regulator_update_ctrl_state(ctrl); + + /* Stop last_volt caching on for the next request */ + ctrl->last_corner_was_closed_loop = false; + + return rc ? rc : rc2; +} + +/** + * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller + * to reflect the corners used by all CPR3 regulators as well as + * the CPR operating mode and perform aging adjustments if needed + * @ctrl: Pointer to the CPR3 controller + * + * Note, CPR3 controller lock must be held by the caller. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) +{ + int rc; + + rc = _cpr3_regulator_update_ctrl_state(ctrl); + if (rc) + return rc; + + return cpr3_regulator_aging_adjust(ctrl); +} + +/** + * cpr3_regulator_set_voltage() - set the voltage corner for the CPR3 regulator + * associated with the regulator device + * @rdev: Regulator device pointer for the cpr3-regulator + * @corner: New voltage corner to set (offset by CPR3_CORNER_OFFSET) + * @corner_max: Maximum voltage corner allowed (offset by + * CPR3_CORNER_OFFSET) + * @selector: Pointer which is filled with the selector value for the + * corner + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. The VDD voltage will not be + * physically configured until both this function and cpr3_regulator_enable() + * are called. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_set_voltage(struct regulator_dev *rdev, + int corner, int corner_max, unsigned *selector) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + struct cpr3_controller *ctrl = vreg->thread->ctrl; + int rc = 0; + int last_corner; + + corner -= CPR3_CORNER_OFFSET; + corner_max -= CPR3_CORNER_OFFSET; + *selector = corner; + + mutex_lock(&ctrl->lock); + + if (!vreg->vreg_enabled) { + vreg->current_corner = corner; + cpr3_debug(vreg, "stored corner=%d\n", corner); + goto done; + } else if (vreg->current_corner == corner) { + goto done; + } + + last_corner = vreg->current_corner; + vreg->current_corner = corner; + + if (vreg->cpr4_regulator_data != NULL) + if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL) + vreg->cpr4_regulator_data->mem_acc_funcs->set_mem_acc(rdev); + + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); + vreg->current_corner = last_corner; + } + + if (vreg->cpr4_regulator_data != NULL) + if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL) + vreg->cpr4_regulator_data->mem_acc_funcs->clear_mem_acc(rdev); + + cpr3_debug(vreg, "set corner=%d\n", corner); +done: + mutex_unlock(&ctrl->lock); + + return rc; +} + +/** + * cpr3_handle_temp_open_loop_adjustment() - voltage based cold temperature + * + * @rdev: Regulator device pointer for the cpr3-regulator + * @is_cold: Flag to denote enter/exit cold condition + * + * This function is adjusts voltage margin based on cold condition + * + * Return: 0 = success + */ + +int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, + bool is_cold) +{ + int i ,j, k, rc; + struct cpr3_regulator *vreg; + + mutex_lock(&ctrl->lock); + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + for (k = 0; k < vreg->corner_count; k++) { + vreg->corner[k].open_loop_volt = is_cold ? + vreg->corner[k].cold_temp_open_loop_volt : + vreg->corner[k].normal_temp_open_loop_volt; + } + } + } + rc = cpr3_regulator_update_ctrl_state(ctrl); + mutex_unlock(&ctrl->lock); + + return rc; +} + +/** + * cpr3_regulator_get_voltage() - get the voltage corner for the CPR3 regulator + * associated with the regulator device + * @rdev: Regulator device pointer for the cpr3-regulator + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. + * + * Return: voltage corner value offset by CPR3_CORNER_OFFSET + */ +static int cpr3_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + + if (vreg->current_corner == CPR3_REGULATOR_CORNER_INVALID) + return CPR3_CORNER_OFFSET; + else + return vreg->current_corner + CPR3_CORNER_OFFSET; +} + +/** + * cpr3_regulator_list_voltage() - return the voltage corner mapped to the + * specified selector + * @rdev: Regulator device pointer for the cpr3-regulator + * @selector: Regulator selector + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. + * + * Return: voltage corner value offset by CPR3_CORNER_OFFSET + */ +static int cpr3_regulator_list_voltage(struct regulator_dev *rdev, + unsigned selector) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + + if (selector < vreg->corner_count) + return selector + CPR3_CORNER_OFFSET; + else + return 0; +} + +/** + * cpr3_regulator_is_enabled() - return the enable state of the CPR3 regulator + * @rdev: Regulator device pointer for the cpr3-regulator + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. + * + * Return: true if regulator is enabled, false if regulator is disabled + */ +static int cpr3_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + + return vreg->vreg_enabled; +} + +/** + * cpr3_regulator_enable() - enable the CPR3 regulator + * @rdev: Regulator device pointer for the cpr3-regulator + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_enable(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + struct cpr3_controller *ctrl = vreg->thread->ctrl; + int rc = 0; + + if (vreg->vreg_enabled == true) + return 0; + + mutex_lock(&ctrl->lock); + + if (ctrl->system_regulator) { + rc = regulator_enable(ctrl->system_regulator); + if (rc) { + cpr3_err(ctrl, "regulator_enable(system) failed, rc=%d\n", + rc); + goto done; + } + } + + rc = regulator_enable(ctrl->vdd_regulator); + if (rc) { + cpr3_err(vreg, "regulator_enable(vdd) failed, rc=%d\n", rc); + goto done; + } + + vreg->vreg_enabled = true; + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); + regulator_disable(ctrl->vdd_regulator); + vreg->vreg_enabled = false; + goto done; + } + + cpr3_debug(vreg, "Enabled\n"); +done: + mutex_unlock(&ctrl->lock); + + return rc; +} + +/** + * cpr3_regulator_disable() - disable the CPR3 regulator + * @rdev: Regulator device pointer for the cpr3-regulator + * + * This function is passed as a callback function into the regulator ops that + * are registered for each cpr3-regulator device. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_disable(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + struct cpr3_controller *ctrl = vreg->thread->ctrl; + int rc, rc2; + + if (vreg->vreg_enabled == false) + return 0; + + mutex_lock(&ctrl->lock); + rc = regulator_disable(ctrl->vdd_regulator); + if (rc) { + cpr3_err(vreg, "regulator_disable(vdd) failed, rc=%d\n", rc); + goto done; + } + + vreg->vreg_enabled = false; + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); + rc2 = regulator_enable(ctrl->vdd_regulator); + vreg->vreg_enabled = true; + goto done; + } + + if (ctrl->system_regulator) { + rc = regulator_disable(ctrl->system_regulator); + if (rc) { + cpr3_err(ctrl, "regulator_disable(system) failed, rc=%d\n", + rc); + goto done; + } + } + + cpr3_debug(vreg, "Disabled\n"); +done: + mutex_unlock(&ctrl->lock); + + return rc; +} + +static struct regulator_ops cpr3_regulator_ops = { + .enable = cpr3_regulator_enable, + .disable = cpr3_regulator_disable, + .is_enabled = cpr3_regulator_is_enabled, + .set_voltage = cpr3_regulator_set_voltage, + .get_voltage = cpr3_regulator_get_voltage, + .list_voltage = cpr3_regulator_list_voltage, +}; + +/** + * cpr3_print_result() - print CPR measurement results to the kernel log for + * debugging purposes + * @thread: Pointer to the CPR3 thread + * + * Return: None + */ +static void cpr3_print_result(struct cpr3_thread *thread) +{ + struct cpr3_controller *ctrl = thread->ctrl; + u32 result[3], busy, step_dn, step_up, error_steps, error, negative; + u32 quot_min, quot_max, ro_min, ro_max, step_quot_min, step_quot_max; + u32 sensor_min, sensor_max; + char *sign; + + result[0] = cpr3_read(ctrl, CPR3_REG_RESULT0(thread->thread_id)); + result[1] = cpr3_read(ctrl, CPR3_REG_RESULT1(thread->thread_id)); + result[2] = cpr3_read(ctrl, CPR3_REG_RESULT2(thread->thread_id)); + + busy = !!(result[0] & CPR3_RESULT0_BUSY_MASK); + step_dn = !!(result[0] & CPR3_RESULT0_STEP_DN_MASK); + step_up = !!(result[0] & CPR3_RESULT0_STEP_UP_MASK); + error_steps = (result[0] & CPR3_RESULT0_ERROR_STEPS_MASK) + >> CPR3_RESULT0_ERROR_STEPS_SHIFT; + error = (result[0] & CPR3_RESULT0_ERROR_MASK) + >> CPR3_RESULT0_ERROR_SHIFT; + negative = !!(result[0] & CPR3_RESULT0_NEGATIVE_MASK); + + quot_min = (result[1] & CPR3_RESULT1_QUOT_MIN_MASK) + >> CPR3_RESULT1_QUOT_MIN_SHIFT; + quot_max = (result[1] & CPR3_RESULT1_QUOT_MAX_MASK) + >> CPR3_RESULT1_QUOT_MAX_SHIFT; + ro_min = (result[1] & CPR3_RESULT1_RO_MIN_MASK) + >> CPR3_RESULT1_RO_MIN_SHIFT; + ro_max = (result[1] & CPR3_RESULT1_RO_MAX_MASK) + >> CPR3_RESULT1_RO_MAX_SHIFT; + + step_quot_min = (result[2] & CPR3_RESULT2_STEP_QUOT_MIN_MASK) + >> CPR3_RESULT2_STEP_QUOT_MIN_SHIFT; + step_quot_max = (result[2] & CPR3_RESULT2_STEP_QUOT_MAX_MASK) + >> CPR3_RESULT2_STEP_QUOT_MAX_SHIFT; + sensor_min = (result[2] & CPR3_RESULT2_SENSOR_MIN_MASK) + >> CPR3_RESULT2_SENSOR_MIN_SHIFT; + sensor_max = (result[2] & CPR3_RESULT2_SENSOR_MAX_MASK) + >> CPR3_RESULT2_SENSOR_MAX_SHIFT; + + sign = negative ? "-" : ""; + cpr3_debug(ctrl, "thread %u: busy=%u, step_dn=%u, step_up=%u, error_steps=%s%u, error=%s%u\n", + thread->thread_id, busy, step_dn, step_up, sign, error_steps, + sign, error); + cpr3_debug(ctrl, "thread %u: quot_min=%u, quot_max=%u, ro_min=%u, ro_max=%u\n", + thread->thread_id, quot_min, quot_max, ro_min, ro_max); + cpr3_debug(ctrl, "thread %u: step_quot_min=%u, step_quot_max=%u, sensor_min=%u, sensor_max=%u\n", + thread->thread_id, step_quot_min, step_quot_max, sensor_min, + sensor_max); +} + +/** + * cpr3_thread_busy() - returns if the specified CPR3 thread is busy taking + * a measurement + * @thread: Pointer to the CPR3 thread + * + * Return: CPR3 busy status + */ +static bool cpr3_thread_busy(struct cpr3_thread *thread) +{ + u32 result; + + result = cpr3_read(thread->ctrl, CPR3_REG_RESULT0(thread->thread_id)); + + return !!(result & CPR3_RESULT0_BUSY_MASK); +} + +/** + * cpr3_irq_handler() - CPR interrupt handler callback function used for + * software closed-loop operation + * @irq: CPR interrupt number + * @data: Private data corresponding to the CPR3 controller + * pointer + * + * This function increases or decreases the vdd supply voltage based upon the + * CPR controller recommendation. + * + * Return: IRQ_HANDLED + */ +static irqreturn_t cpr3_irq_handler(int irq, void *data) +{ + struct cpr3_controller *ctrl = data; + struct cpr3_corner *aggr = &ctrl->aggr_corner; + u32 cont = CPR3_CONT_CMD_NACK; + u32 reg_last_measurement = 0; + struct cpr3_regulator *vreg; + struct cpr3_corner *corner; + unsigned long flags; + int i, j, new_volt, last_volt, dynamic_floor_volt, rc; + u32 irq_en, status, cpr_status, ctl; + bool up, down; + + mutex_lock(&ctrl->lock); + + if (!ctrl->cpr_enabled) { + cpr3_debug(ctrl, "CPR interrupt received but CPR is disabled\n"); + mutex_unlock(&ctrl->lock); + return IRQ_HANDLED; + } else if (ctrl->use_hw_closed_loop) { + cpr3_debug(ctrl, "CPR interrupt received but CPR is using HW closed-loop\n"); + goto done; + } + + /* + * CPR IRQ status checking and CPR controller disabling must happen + * atomically and without invening delay in order to avoid an interrupt + * storm caused by the handler racing with the CPR controller. + */ + local_irq_save(flags); + preempt_disable(); + + status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); + up = status & CPR3_IRQ_UP; + down = status & CPR3_IRQ_DOWN; + + if (!up && !down) { + /* + * Toggle the CPR controller off and then back on since the + * hardware and software states are out of sync. This condition + * occurs after an aging measurement completes as the CPR IRQ + * physically triggers during the aging measurement but the + * handler is stuck waiting on the mutex lock. + */ + cpr3_ctrl_loop_disable(ctrl); + + local_irq_restore(flags); + preempt_enable(); + + /* Wait for the loop disable write to complete */ + mb(); + + /* Wait for BUSY=1 and LOOP_EN=0 in CPR controller registers. */ + for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { + cpr_status = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); + ctl = cpr3_read(ctrl, CPR3_REG_CPR_CTL); + if (cpr_status & CPR3_CPR_STATUS_BUSY_MASK + && (ctl & CPR3_CPR_CTL_LOOP_EN_MASK) + == CPR3_CPR_CTL_LOOP_DISABLE) + break; + udelay(10); + } + if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) + cpr3_debug(ctrl, "CPR controller not disabled after %d us\n", + CPR3_REGISTER_WRITE_DELAY_US); + + /* Clear interrupt status */ + cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, + CPR3_IRQ_UP | CPR3_IRQ_DOWN); + + /* Wait for the interrupt clearing write to complete */ + mb(); + + /* Wait for IRQ_STATUS register to be cleared. */ + for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { + status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); + if (!(status & (CPR3_IRQ_UP | CPR3_IRQ_DOWN))) + break; + udelay(10); + } + if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) + cpr3_debug(ctrl, "CPR interrupts not cleared after %d us\n", + CPR3_REGISTER_WRITE_DELAY_US); + + cpr3_ctrl_loop_enable(ctrl); + + cpr3_debug(ctrl, "CPR interrupt received but no up or down status bit is set\n"); + + mutex_unlock(&ctrl->lock); + return IRQ_HANDLED; + } else if (up && down) { + cpr3_debug(ctrl, "both up and down status bits set\n"); + /* The up flag takes precedence over the down flag. */ + down = false; + } + + if (ctrl->supports_hw_closed_loop) + reg_last_measurement + = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); + dynamic_floor_volt = cpr3_regulator_get_dynamic_floor_volt(ctrl, + reg_last_measurement); + + local_irq_restore(flags); + preempt_enable(); + + irq_en = aggr->irq_en; + last_volt = aggr->last_volt; + + for (i = 0; i < ctrl->thread_count; i++) { + if (cpr3_thread_busy(&ctrl->thread[i])) { + cpr3_debug(ctrl, "CPR thread %u busy when it should be waiting for SW cont\n", + ctrl->thread[i].thread_id); + goto done; + } + } + + new_volt = up ? last_volt + ctrl->step_volt + : last_volt - ctrl->step_volt; + + /* Re-enable UP/DOWN interrupt when its opposite is received. */ + irq_en |= up ? CPR3_IRQ_DOWN : CPR3_IRQ_UP; + + if (new_volt > aggr->ceiling_volt) { + new_volt = aggr->ceiling_volt; + irq_en &= ~CPR3_IRQ_UP; + cpr3_debug(ctrl, "limiting to ceiling=%d uV\n", + aggr->ceiling_volt); + } else if (new_volt < aggr->floor_volt) { + new_volt = aggr->floor_volt; + irq_en &= ~CPR3_IRQ_DOWN; + cpr3_debug(ctrl, "limiting to floor=%d uV\n", aggr->floor_volt); + } + + if (down && new_volt < dynamic_floor_volt) { + /* + * The vdd-supply voltage should not be decreased below the + * dynamic floor voltage. However, it is not necessary (and + * counter productive) to force the voltage up to this level + * if it happened to be below it since the closed-loop voltage + * must have gotten there in a safe manner while the power + * domains for the CPR3 regulator imposing the dynamic floor + * were not bypassed. + */ + new_volt = last_volt; + irq_en &= ~CPR3_IRQ_DOWN; + cpr3_debug(ctrl, "limiting to dynamic floor=%d uV\n", + dynamic_floor_volt); + } + + for (i = 0; i < ctrl->thread_count; i++) + cpr3_print_result(&ctrl->thread[i]); + + cpr3_debug(ctrl, "%s: new_volt=%d uV, last_volt=%d uV\n", + up ? "UP" : "DN", new_volt, last_volt); + + if (ctrl->proc_clock_throttle && last_volt == aggr->ceiling_volt + && new_volt < last_volt) + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + ctrl->proc_clock_throttle); + + if (new_volt != last_volt) { + rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, + last_volt, + aggr); + if (rc) { + cpr3_err(ctrl, "scale_vdd() failed to set vdd=%d uV, rc=%d\n", + new_volt, rc); + goto done; + } + cont = CPR3_CONT_CMD_ACK; + + /* + * Update the closed-loop voltage for all regulators managed + * by this CPR controller. + */ + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + cpr3_update_vreg_closed_loop_volt(vreg, + new_volt, reg_last_measurement); + } + } + } + + if (ctrl->proc_clock_throttle && new_volt == aggr->ceiling_volt) + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + CPR3_PD_THROTTLE_DISABLE); + + corner = &ctrl->thread[0].vreg[0].corner[ + ctrl->thread[0].vreg[0].current_corner]; + + if (irq_en != aggr->irq_en) { + aggr->irq_en = irq_en; + cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_en); + } + + aggr->last_volt = new_volt; + +done: + /* Clear interrupt status */ + cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, CPR3_IRQ_UP | CPR3_IRQ_DOWN); + + /* ACK or NACK the CPR controller */ + cpr3_write(ctrl, CPR3_REG_CONT_CMD, cont); + + mutex_unlock(&ctrl->lock); + return IRQ_HANDLED; +} + +/** + * cpr3_ceiling_irq_handler() - CPR ceiling reached interrupt handler callback + * function used for hardware closed-loop operation + * @irq: CPR ceiling interrupt number + * @data: Private data corresponding to the CPR3 controller + * pointer + * + * This function disables processor clock throttling and closed-loop operation + * when the ceiling voltage is reached. + * + * Return: IRQ_HANDLED + */ +static irqreturn_t cpr3_ceiling_irq_handler(int irq, void *data) +{ + struct cpr3_controller *ctrl = data; + int volt; + + mutex_lock(&ctrl->lock); + + if (!ctrl->cpr_enabled) { + cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is disabled\n"); + goto done; + } else if (!ctrl->use_hw_closed_loop) { + cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is using SW closed-loop\n"); + goto done; + } + + volt = regulator_get_voltage(ctrl->vdd_regulator); + if (volt < 0) { + cpr3_err(ctrl, "could not get vdd voltage, rc=%d\n", volt); + goto done; + } else if (volt != ctrl->aggr_corner.ceiling_volt) { + cpr3_debug(ctrl, "CPR ceiling interrupt received but vdd voltage: %d uV != ceiling voltage: %d uV\n", + volt, ctrl->aggr_corner.ceiling_volt); + goto done; + } + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + /* + * Since the ceiling voltage has been reached, disable processor + * clock throttling as well as CPR closed-loop operation. + */ + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + CPR3_PD_THROTTLE_DISABLE); + cpr3_ctrl_loop_disable(ctrl); + cpr3_debug(ctrl, "CPR closed-loop and throttling disabled\n"); + } + +done: + mutex_unlock(&ctrl->lock); + return IRQ_HANDLED; +} + +/** + * cpr3_regulator_vreg_register() - register a regulator device for a CPR3 + * regulator + * @vreg: Pointer to the CPR3 regulator + * + * This function initializes all regulator framework related structures and then + * calls regulator_register() for the CPR3 regulator. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_vreg_register(struct cpr3_regulator *vreg) +{ + struct regulator_config config = {}; + struct regulator_desc *rdesc; + struct regulator_init_data *init_data; + int rc; + + init_data = of_get_regulator_init_data(vreg->thread->ctrl->dev, + vreg->of_node, &vreg->rdesc); + if (!init_data) { + cpr3_err(vreg, "regulator init data is missing\n"); + return -EINVAL; + } + + init_data->constraints.input_uV = init_data->constraints.max_uV; + rdesc = &vreg->rdesc; + init_data->constraints.valid_ops_mask |= + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS; + rdesc->ops = &cpr3_regulator_ops; + + rdesc->n_voltages = vreg->corner_count; + rdesc->name = init_data->constraints.name; + rdesc->owner = THIS_MODULE; + rdesc->type = REGULATOR_VOLTAGE; + + config.dev = vreg->thread->ctrl->dev; + config.driver_data = vreg; + config.init_data = init_data; + config.of_node = vreg->of_node; + + vreg->rdev = regulator_register(rdesc, &config); + if (IS_ERR(vreg->rdev)) { + rc = PTR_ERR(vreg->rdev); + cpr3_err(vreg, "regulator_register failed, rc=%d\n", rc); + return rc; + } + + return 0; +} + +static int debugfs_int_set(void *data, u64 val) +{ + *(int *)data = val; + return 0; +} + +static int debugfs_int_get(void *data, u64 *val) +{ + *val = *(int *)data; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(fops_int, debugfs_int_get, debugfs_int_set, "%lld\n"); +DEFINE_SIMPLE_ATTRIBUTE(fops_int_ro, debugfs_int_get, NULL, "%lld\n"); +DEFINE_SIMPLE_ATTRIBUTE(fops_int_wo, NULL, debugfs_int_set, "%lld\n"); + +/** + * debugfs_create_int - create a debugfs file that is used to read and write a + * signed int value + * @name: Pointer to a string containing the name of the file to + * create + * @mode: The permissions that the file should have + * @parent: Pointer to the parent dentry for this file. This should + * be a directory dentry if set. If this parameter is + * %NULL, then the file will be created in the root of the + * debugfs filesystem. + * @value: Pointer to the variable that the file should read to and + * write from + * + * This function creates a file in debugfs with the given name that + * contains the value of the variable @value. If the @mode variable is so + * set, it can be read from, and written to. + * + * This function will return a pointer to a dentry if it succeeds. This + * pointer must be passed to the debugfs_remove() function when the file is + * to be removed. If an error occurs, %NULL will be returned. + */ +static struct dentry *debugfs_create_int(const char *name, umode_t mode, + struct dentry *parent, int *value) +{ + /* if there are no write bits set, make read only */ + if (!(mode & S_IWUGO)) + return debugfs_create_file(name, mode, parent, value, + &fops_int_ro); + /* if there are no read bits set, make write only */ + if (!(mode & S_IRUGO)) + return debugfs_create_file(name, mode, parent, value, + &fops_int_wo); + + return debugfs_create_file(name, mode, parent, value, &fops_int); +} + +static int debugfs_bool_get(void *data, u64 *val) +{ + *val = *(bool *)data; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(fops_bool_ro, debugfs_bool_get, NULL, "%lld\n"); + +/** + * struct cpr3_debug_corner_info - data structure used by the + * cpr3_debugfs_create_corner_int function + * @vreg: Pointer to the CPR3 regulator + * @index: Pointer to the corner array index + * @member_offset: Offset in bytes from the beginning of struct cpr3_corner + * to the beginning of the value to be read from + * @corner: Pointer to the CPR3 corner array + */ +struct cpr3_debug_corner_info { + struct cpr3_regulator *vreg; + int *index; + size_t member_offset; + struct cpr3_corner *corner; +}; + +static int cpr3_debug_corner_int_get(void *data, u64 *val) +{ + struct cpr3_debug_corner_info *info = data; + struct cpr3_controller *ctrl = info->vreg->thread->ctrl; + int i; + + mutex_lock(&ctrl->lock); + + i = *info->index; + if (i < 0) + i = 0; + + *val = *(int *)((char *)&info->vreg->corner[i] + info->member_offset); + + mutex_unlock(&ctrl->lock); + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_int_fops, cpr3_debug_corner_int_get, + NULL, "%lld\n"); + +/** + * cpr3_debugfs_create_corner_int - create a debugfs file that is used to read + * a signed int value out of a CPR3 regulator's corner array + * @vreg: Pointer to the CPR3 regulator + * @name: Pointer to a string containing the name of the file to + * create + * @mode: The permissions that the file should have + * @parent: Pointer to the parent dentry for this file. This should + * be a directory dentry if set. If this parameter is + * %NULL, then the file will be created in the root of the + * debugfs filesystem. + * @index: Pointer to the corner array index + * @member_offset: Offset in bytes from the beginning of struct cpr3_corner + * to the beginning of the value to be read from + * + * This function creates a file in debugfs with the given name that + * contains the value of the int type variable vreg->corner[index].member + * where member_offset == offsetof(struct cpr3_corner, member). + */ +static struct dentry *cpr3_debugfs_create_corner_int( + struct cpr3_regulator *vreg, const char *name, umode_t mode, + struct dentry *parent, int *index, size_t member_offset) +{ + struct cpr3_debug_corner_info *info; + + info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return NULL; + + info->vreg = vreg; + info->index = index; + info->member_offset = member_offset; + + return debugfs_create_file(name, mode, parent, info, + &cpr3_debug_corner_int_fops); +} + +static int cpr3_debug_quot_open(struct inode *inode, struct file *file) +{ + struct cpr3_debug_corner_info *info = inode->i_private; + struct cpr3_thread *thread = info->vreg->thread; + int size, i, pos; + u32 *quot; + char *buf; + + /* + * Max size: + * - 10 digits + ' ' or '\n' = 11 bytes per number + * - terminating '\0' + */ + size = CPR3_RO_COUNT * 11; + buf = kzalloc(size + 1, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + file->private_data = buf; + + mutex_lock(&thread->ctrl->lock); + + quot = info->corner[*info->index].target_quot; + + for (i = 0, pos = 0; i < CPR3_RO_COUNT; i++) + pos += scnprintf(buf + pos, size - pos, "%u%c", + quot[i], i < CPR3_RO_COUNT - 1 ? ' ' : '\n'); + + mutex_unlock(&thread->ctrl->lock); + + return nonseekable_open(inode, file); +} + +static ssize_t cpr3_debug_quot_read(struct file *file, char __user *buf, + size_t len, loff_t *ppos) +{ + return simple_read_from_buffer(buf, len, ppos, file->private_data, + strlen(file->private_data)); +} + +static int cpr3_debug_quot_release(struct inode *inode, struct file *file) +{ + kfree(file->private_data); + + return 0; +} + +static const struct file_operations cpr3_debug_quot_fops = { + .owner = THIS_MODULE, + .open = cpr3_debug_quot_open, + .release = cpr3_debug_quot_release, + .read = cpr3_debug_quot_read, + .llseek = no_llseek, +}; + +/** + * cpr3_regulator_debugfs_corner_add() - add debugfs files to expose + * configuration data for the CPR corner + * @vreg: Pointer to the CPR3 regulator + * @corner_dir: Pointer to the parent corner dentry for the new files + * @index: Pointer to the corner array index + * + * Return: none + */ +static void cpr3_regulator_debugfs_corner_add(struct cpr3_regulator *vreg, + struct dentry *corner_dir, int *index) +{ + struct cpr3_debug_corner_info *info; + struct dentry *temp; + + temp = cpr3_debugfs_create_corner_int(vreg, "floor_volt", S_IRUGO, + corner_dir, index, offsetof(struct cpr3_corner, floor_volt)); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "floor_volt debugfs file creation failed\n"); + return; + } + + temp = cpr3_debugfs_create_corner_int(vreg, "ceiling_volt", S_IRUGO, + corner_dir, index, offsetof(struct cpr3_corner, ceiling_volt)); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "ceiling_volt debugfs file creation failed\n"); + return; + } + + temp = cpr3_debugfs_create_corner_int(vreg, "open_loop_volt", S_IRUGO, + corner_dir, index, + offsetof(struct cpr3_corner, open_loop_volt)); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "open_loop_volt debugfs file creation failed\n"); + return; + } + + temp = cpr3_debugfs_create_corner_int(vreg, "last_volt", S_IRUGO, + corner_dir, index, offsetof(struct cpr3_corner, last_volt)); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "last_volt debugfs file creation failed\n"); + return; + } + + info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return; + + info->vreg = vreg; + info->index = index; + info->corner = vreg->corner; + + temp = debugfs_create_file("target_quots", S_IRUGO, corner_dir, + info, &cpr3_debug_quot_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "target_quots debugfs file creation failed\n"); + return; + } +} + +/** + * cpr3_debug_corner_index_set() - debugfs callback used to change the + * value of the CPR3 regulator debug_corner index + * @data: Pointer to private data which is equal to the CPR3 + * regulator pointer + * @val: New value for debug_corner + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_corner_index_set(void *data, u64 val) +{ + struct cpr3_regulator *vreg = data; + + if (val < CPR3_CORNER_OFFSET || val > vreg->corner_count) { + cpr3_err(vreg, "invalid corner index %llu; allowed values: %d-%d\n", + val, CPR3_CORNER_OFFSET, vreg->corner_count); + return -EINVAL; + } + + mutex_lock(&vreg->thread->ctrl->lock); + vreg->debug_corner = val - CPR3_CORNER_OFFSET; + mutex_unlock(&vreg->thread->ctrl->lock); + + return 0; +} + +/** + * cpr3_debug_corner_index_get() - debugfs callback used to retrieve + * the value of the CPR3 regulator debug_corner index + * @data: Pointer to private data which is equal to the CPR3 + * regulator pointer + * @val: Output parameter written with the value of + * debug_corner + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_corner_index_get(void *data, u64 *val) +{ + struct cpr3_regulator *vreg = data; + + *val = vreg->debug_corner + CPR3_CORNER_OFFSET; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_index_fops, + cpr3_debug_corner_index_get, + cpr3_debug_corner_index_set, + "%llu\n"); + +/** + * cpr3_debug_current_corner_index_get() - debugfs callback used to retrieve + * the value of the CPR3 regulator current_corner index + * @data: Pointer to private data which is equal to the CPR3 + * regulator pointer + * @val: Output parameter written with the value of + * current_corner + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_current_corner_index_get(void *data, u64 *val) +{ + struct cpr3_regulator *vreg = data; + + *val = vreg->current_corner + CPR3_CORNER_OFFSET; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_current_corner_index_fops, + cpr3_debug_current_corner_index_get, + NULL, "%llu\n"); + +/** + * cpr3_regulator_debugfs_vreg_add() - add debugfs files to expose configuration + * data for the CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * @thread_dir CPR3 thread debugfs directory handle + * + * Return: none + */ +static void cpr3_regulator_debugfs_vreg_add(struct cpr3_regulator *vreg, + struct dentry *thread_dir) +{ + struct dentry *temp, *corner_dir, *vreg_dir; + + vreg_dir = debugfs_create_dir(vreg->name, thread_dir); + if (IS_ERR_OR_NULL(vreg_dir)) { + cpr3_err(vreg, "%s debugfs directory creation failed\n", + vreg->name); + return; + } + + temp = debugfs_create_int("speed_bin_fuse", S_IRUGO, vreg_dir, + &vreg->speed_bin_fuse); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "speed_bin_fuse debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("cpr_rev_fuse", S_IRUGO, vreg_dir, + &vreg->cpr_rev_fuse); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "cpr_rev_fuse debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("fuse_combo", S_IRUGO, vreg_dir, + &vreg->fuse_combo); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "fuse_combo debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("corner_count", S_IRUGO, vreg_dir, + &vreg->corner_count); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "corner_count debugfs file creation failed\n"); + return; + } + + corner_dir = debugfs_create_dir("corner", vreg_dir); + if (IS_ERR_OR_NULL(corner_dir)) { + cpr3_err(vreg, "corner debugfs directory creation failed\n"); + return; + } + + temp = debugfs_create_file("index", S_IRUGO | S_IWUSR, corner_dir, + vreg, &cpr3_debug_corner_index_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "index debugfs file creation failed\n"); + return; + } + + cpr3_regulator_debugfs_corner_add(vreg, corner_dir, + &vreg->debug_corner); + + corner_dir = debugfs_create_dir("current_corner", vreg_dir); + if (IS_ERR_OR_NULL(corner_dir)) { + cpr3_err(vreg, "current_corner debugfs directory creation failed\n"); + return; + } + + temp = debugfs_create_file("index", S_IRUGO, corner_dir, + vreg, &cpr3_debug_current_corner_index_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(vreg, "index debugfs file creation failed\n"); + return; + } + + cpr3_regulator_debugfs_corner_add(vreg, corner_dir, + &vreg->current_corner); +} + +/** + * cpr3_regulator_debugfs_thread_add() - add debugfs files to expose + * configuration data for the CPR thread + * @thread: Pointer to the CPR3 thread + * + * Return: none + */ +static void cpr3_regulator_debugfs_thread_add(struct cpr3_thread *thread) +{ + struct cpr3_controller *ctrl = thread->ctrl; + struct dentry *aggr_dir, *temp, *thread_dir; + struct cpr3_debug_corner_info *info; + char buf[20]; + int *index; + int i; + + scnprintf(buf, sizeof(buf), "thread%u", thread->thread_id); + thread_dir = debugfs_create_dir(buf, thread->ctrl->debugfs); + if (IS_ERR_OR_NULL(thread_dir)) { + cpr3_err(ctrl, "thread %u %s debugfs directory creation failed\n", + thread->thread_id, buf); + return; + } + + aggr_dir = debugfs_create_dir("max_aggregated_params", thread_dir); + if (IS_ERR_OR_NULL(aggr_dir)) { + cpr3_err(ctrl, "thread %u max_aggregated_params debugfs directory creation failed\n", + thread->thread_id); + return; + } + + temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir, + &thread->aggr_corner.floor_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread %u aggr floor_volt debugfs file creation failed\n", + thread->thread_id); + return; + } + + temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir, + &thread->aggr_corner.ceiling_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread %u aggr ceiling_volt debugfs file creation failed\n", + thread->thread_id); + return; + } + + temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir, + &thread->aggr_corner.open_loop_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread %u aggr open_loop_volt debugfs file creation failed\n", + thread->thread_id); + return; + } + + temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir, + &thread->aggr_corner.last_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread %u aggr last_volt debugfs file creation failed\n", + thread->thread_id); + return; + } + + info = devm_kzalloc(thread->ctrl->dev, sizeof(*info), GFP_KERNEL); + index = devm_kzalloc(thread->ctrl->dev, sizeof(*index), GFP_KERNEL); + if (!info || !index) + return; + *index = 0; + info->vreg = &thread->vreg[0]; + info->index = index; + info->corner = &thread->aggr_corner; + + temp = debugfs_create_file("target_quots", S_IRUGO, aggr_dir, + info, &cpr3_debug_quot_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread %u target_quots debugfs file creation failed\n", + thread->thread_id); + return; + } + + for (i = 0; i < thread->vreg_count; i++) + cpr3_regulator_debugfs_vreg_add(&thread->vreg[i], thread_dir); +} + +/** + * cpr3_debug_closed_loop_enable_set() - debugfs callback used to change the + * value of the CPR controller cpr_allowed_sw flag which enables or + * disables closed-loop operation + * @data: Pointer to private data which is equal to the CPR + * controller pointer + * @val: New value for cpr_allowed_sw + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_closed_loop_enable_set(void *data, u64 val) +{ + struct cpr3_controller *ctrl = data; + bool enable = !!val; + int rc; + + mutex_lock(&ctrl->lock); + + if (ctrl->cpr_allowed_sw == enable) + goto done; + + if (enable && !ctrl->cpr_allowed_hw) { + cpr3_err(ctrl, "CPR closed-loop operation is not allowed\n"); + goto done; + } + + ctrl->cpr_allowed_sw = enable; + + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(ctrl, "could not change CPR enable state=%u, rc=%d\n", + enable, rc); + goto done; + } + + if (ctrl->proc_clock_throttle && !ctrl->cpr_enabled) { + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "clock enable failed, rc=%d\n", + rc); + goto done; + } + ctrl->cpr_enabled = true; + + cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, + CPR3_PD_THROTTLE_DISABLE); + + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + } + + cpr3_debug(ctrl, "closed-loop=%s\n", enable ? "enabled" : "disabled"); +done: + mutex_unlock(&ctrl->lock); + return 0; +} + +/** + * cpr3_debug_closed_loop_enable_get() - debugfs callback used to retrieve + * the value of the CPR controller cpr_allowed_sw flag which + * indicates if closed-loop operation is enabled + * @data: Pointer to private data which is equal to the CPR + * controller pointer + * @val: Output parameter written with the value of + * cpr_allowed_sw + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_closed_loop_enable_get(void *data, u64 *val) +{ + struct cpr3_controller *ctrl = data; + + *val = ctrl->cpr_allowed_sw; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_closed_loop_enable_fops, + cpr3_debug_closed_loop_enable_get, + cpr3_debug_closed_loop_enable_set, + "%llu\n"); + +/** + * cpr3_debug_hw_closed_loop_enable_set() - debugfs callback used to change the + * value of the CPR controller use_hw_closed_loop flag which + * switches between software closed-loop and hardware closed-loop + * operation for CPR3 and CPR4 controllers and between open-loop + * and full hardware closed-loop operation for CPRh controllers. + * @data: Pointer to private data which is equal to the CPR + * controller pointer + * @val: New value for use_hw_closed_loop + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_hw_closed_loop_enable_set(void *data, u64 val) +{ + struct cpr3_controller *ctrl = data; + bool use_hw_closed_loop = !!val; + struct cpr3_regulator *vreg; + bool cpr_enabled; + int i, j, k, rc; + + mutex_lock(&ctrl->lock); + + if (ctrl->use_hw_closed_loop == use_hw_closed_loop) + goto done; + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + goto done; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + ctrl->use_hw_closed_loop = use_hw_closed_loop; + + cpr_enabled = ctrl->cpr_enabled; + + /* Ensure that CPR clocks are enabled before writing to registers. */ + if (!cpr_enabled) { + rc = cpr3_clock_enable(ctrl); + if (rc) { + cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); + goto done; + } + ctrl->cpr_enabled = true; + } + + if (ctrl->use_hw_closed_loop) + cpr3_write(ctrl, CPR3_REG_IRQ_EN, 0); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, + ctrl->use_hw_closed_loop + ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE + : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); + } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, + ctrl->use_hw_closed_loop + ? CPR3_HW_CLOSED_LOOP_ENABLE + : CPR3_HW_CLOSED_LOOP_DISABLE); + } + + /* Turn off CPR clocks if they were off before this function call. */ + if (!cpr_enabled) { + cpr3_clock_disable(ctrl); + ctrl->cpr_enabled = false; + } + + if (ctrl->use_hw_closed_loop && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + rc = regulator_enable(ctrl->vdd_limit_regulator); + if (rc) { + cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", + rc); + goto done; + } + } else if (!ctrl->use_hw_closed_loop + && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + rc = regulator_disable(ctrl->vdd_limit_regulator); + if (rc) { + cpr3_err(ctrl, "CPR limit regulator disable failed, rc=%d\n", + rc); + goto done; + } + } + + /* + * Due to APM and mem-acc floor restriction constraints, + * the closed-loop voltage may be different when using + * software closed-loop vs hardware closed-loop. Therefore, + * reset the cached closed-loop voltage for all corners to the + * corresponding open-loop voltage when switching between + * SW and HW closed-loop mode. + */ + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + for (k = 0; k < vreg->corner_count; k++) + vreg->corner[k].last_volt + = vreg->corner[k].open_loop_volt; + } + } + + /* Skip last_volt caching */ + ctrl->last_corner_was_closed_loop = false; + + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(ctrl, "could not change CPR HW closed-loop enable state=%u, rc=%d\n", + use_hw_closed_loop, rc); + goto done; + } + + cpr3_debug(ctrl, "CPR mode=%s\n", + use_hw_closed_loop ? + "HW closed-loop" : "SW closed-loop"); +done: + mutex_unlock(&ctrl->lock); + return 0; +} + +/** + * cpr3_debug_hw_closed_loop_enable_get() - debugfs callback used to retrieve + * the value of the CPR controller use_hw_closed_loop flag which + * indicates if hardware closed-loop operation is being used in + * place of software closed-loop operation + * @data: Pointer to private data which is equal to the CPR + * controller pointer + * @val: Output parameter written with the value of + * use_hw_closed_loop + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_hw_closed_loop_enable_get(void *data, u64 *val) +{ + struct cpr3_controller *ctrl = data; + + *val = ctrl->use_hw_closed_loop; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_hw_closed_loop_enable_fops, + cpr3_debug_hw_closed_loop_enable_get, + cpr3_debug_hw_closed_loop_enable_set, + "%llu\n"); + +/** + * cpr3_debug_trigger_aging_measurement_set() - debugfs callback used to trigger + * another CPR measurement + * @data: Pointer to private data which is equal to the CPR + * controller pointer + * @val: Unused + * + * Return: 0 on success, errno on failure + */ +static int cpr3_debug_trigger_aging_measurement_set(void *data, u64 val) +{ + struct cpr3_controller *ctrl = data; + int rc; + + mutex_lock(&ctrl->lock); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + goto done; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); + ctrl->aging_required = true; + ctrl->aging_succeeded = false; + ctrl->aging_failed = false; + + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) { + cpr3_err(ctrl, "could not update the CPR controller state, rc=%d\n", + rc); + goto done; + } + +done: + mutex_unlock(&ctrl->lock); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_trigger_aging_measurement_fops, + NULL, + cpr3_debug_trigger_aging_measurement_set, + "%llu\n"); + +/** + * cpr3_regulator_debugfs_ctrl_add() - add debugfs files to expose configuration + * data for the CPR controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: none + */ +static void cpr3_regulator_debugfs_ctrl_add(struct cpr3_controller *ctrl) +{ + struct dentry *temp, *aggr_dir; + int i; + + /* Add cpr3-regulator base directory if it isn't present already. */ + if (cpr3_debugfs_base == NULL) { + cpr3_debugfs_base = debugfs_create_dir("cpr3-regulator", NULL); + if (IS_ERR_OR_NULL(cpr3_debugfs_base)) { + cpr3_err(ctrl, "cpr3-regulator debugfs base directory creation failed\n"); + cpr3_debugfs_base = NULL; + return; + } + } + + ctrl->debugfs = debugfs_create_dir(ctrl->name, cpr3_debugfs_base); + if (IS_ERR_OR_NULL(ctrl->debugfs)) { + cpr3_err(ctrl, "cpr3-regulator controller debugfs directory creation failed\n"); + return; + } + + temp = debugfs_create_file("cpr_closed_loop_enable", S_IRUGO | S_IWUSR, + ctrl->debugfs, ctrl, + &cpr3_debug_closed_loop_enable_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "cpr_closed_loop_enable debugfs file creation failed\n"); + return; + } + + if (ctrl->supports_hw_closed_loop) { + temp = debugfs_create_file("use_hw_closed_loop", + S_IRUGO | S_IWUSR, ctrl->debugfs, ctrl, + &cpr3_debug_hw_closed_loop_enable_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "use_hw_closed_loop debugfs file creation failed\n"); + return; + } + } + + temp = debugfs_create_int("thread_count", S_IRUGO, ctrl->debugfs, + &ctrl->thread_count); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "thread_count debugfs file creation failed\n"); + return; + } + + if (ctrl->apm) { + temp = debugfs_create_int("apm_threshold_volt", S_IRUGO, + ctrl->debugfs, &ctrl->apm_threshold_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "apm_threshold_volt debugfs file creation failed\n"); + return; + } + } + + if (ctrl->aging_required || ctrl->aging_succeeded + || ctrl->aging_failed) { + temp = debugfs_create_int("aging_adj_volt", S_IRUGO, + ctrl->debugfs, &ctrl->aging_ref_adjust_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aging_adj_volt debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_file("aging_succeeded", S_IRUGO, + ctrl->debugfs, &ctrl->aging_succeeded, &fops_bool_ro); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aging_succeeded debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_file("aging_failed", S_IRUGO, + ctrl->debugfs, &ctrl->aging_failed, &fops_bool_ro); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aging_failed debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_file("aging_trigger", S_IWUSR, + ctrl->debugfs, ctrl, + &cpr3_debug_trigger_aging_measurement_fops); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aging_trigger debugfs file creation failed\n"); + return; + } + } + + aggr_dir = debugfs_create_dir("max_aggregated_voltages", ctrl->debugfs); + if (IS_ERR_OR_NULL(aggr_dir)) { + cpr3_err(ctrl, "max_aggregated_voltages debugfs directory creation failed\n"); + return; + } + + temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir, + &ctrl->aggr_corner.floor_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aggr floor_volt debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir, + &ctrl->aggr_corner.ceiling_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aggr ceiling_volt debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir, + &ctrl->aggr_corner.open_loop_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aggr open_loop_volt debugfs file creation failed\n"); + return; + } + + temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir, + &ctrl->aggr_corner.last_volt); + if (IS_ERR_OR_NULL(temp)) { + cpr3_err(ctrl, "aggr last_volt debugfs file creation failed\n"); + return; + } + + for (i = 0; i < ctrl->thread_count; i++) + cpr3_regulator_debugfs_thread_add(&ctrl->thread[i]); +} + +/** + * cpr3_regulator_debugfs_ctrl_remove() - remove debugfs files for the CPR + * controller + * @ctrl: Pointer to the CPR3 controller + * + * Note, this function must be called after the controller has been removed from + * cpr3_controller_list and while the cpr3_controller_list_mutex lock is held. + * + * Return: none + */ +static void cpr3_regulator_debugfs_ctrl_remove(struct cpr3_controller *ctrl) +{ + if (list_empty(&cpr3_controller_list)) { + debugfs_remove_recursive(cpr3_debugfs_base); + cpr3_debugfs_base = NULL; + } else { + debugfs_remove_recursive(ctrl->debugfs); + } +} + +/** + * cpr3_regulator_init_ctrl_data() - performs initialization of CPR controller + * elements + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_init_ctrl_data(struct cpr3_controller *ctrl) +{ + /* Read the initial vdd voltage from hardware. */ + ctrl->aggr_corner.last_volt + = regulator_get_voltage(ctrl->vdd_regulator); + if (ctrl->aggr_corner.last_volt < 0) { + cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", + ctrl->aggr_corner.last_volt); + return ctrl->aggr_corner.last_volt; + } + ctrl->aggr_corner.open_loop_volt = ctrl->aggr_corner.last_volt; + + return 0; +} + +/** + * cpr3_regulator_init_vreg_data() - performs initialization of common CPR3 + * regulator elements and validate aging configurations + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_init_vreg_data(struct cpr3_regulator *vreg) +{ + int i, j; + bool init_aging; + + vreg->current_corner = CPR3_REGULATOR_CORNER_INVALID; + vreg->last_closed_loop_corner = CPR3_REGULATOR_CORNER_INVALID; + + init_aging = vreg->aging_allowed && vreg->thread->ctrl->aging_required; + + for (i = 0; i < vreg->corner_count; i++) { + vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; + vreg->corner[i].irq_en = CPR3_IRQ_UP | CPR3_IRQ_DOWN; + + vreg->corner[i].ro_mask = 0; + for (j = 0; j < CPR3_RO_COUNT; j++) { + if (vreg->corner[i].target_quot[j] == 0) + vreg->corner[i].ro_mask |= BIT(j); + } + + if (init_aging) { + vreg->corner[i].unaged_floor_volt + = vreg->corner[i].floor_volt; + vreg->corner[i].unaged_ceiling_volt + = vreg->corner[i].ceiling_volt; + vreg->corner[i].unaged_open_loop_volt + = vreg->corner[i].open_loop_volt; + } + + if (vreg->aging_allowed) { + if (vreg->corner[i].unaged_floor_volt <= 0) { + cpr3_err(vreg, "invalid unaged_floor_volt[%d] = %d\n", + i, vreg->corner[i].unaged_floor_volt); + return -EINVAL; + } + if (vreg->corner[i].unaged_ceiling_volt <= 0) { + cpr3_err(vreg, "invalid unaged_ceiling_volt[%d] = %d\n", + i, vreg->corner[i].unaged_ceiling_volt); + return -EINVAL; + } + if (vreg->corner[i].unaged_open_loop_volt <= 0) { + cpr3_err(vreg, "invalid unaged_open_loop_volt[%d] = %d\n", + i, vreg->corner[i].unaged_open_loop_volt); + return -EINVAL; + } + } + } + + if (vreg->aging_allowed && vreg->corner[vreg->aging_corner].ceiling_volt + > vreg->thread->ctrl->aging_ref_volt) { + cpr3_err(vreg, "aging corner %d ceiling voltage = %d > aging ref voltage = %d uV\n", + vreg->aging_corner, + vreg->corner[vreg->aging_corner].ceiling_volt, + vreg->thread->ctrl->aging_ref_volt); + return -EINVAL; + } + + return 0; +} + +/** + * cpr3_regulator_suspend() - perform common required CPR3 power down steps + * before the system enters suspend + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_regulator_suspend(struct cpr3_controller *ctrl) +{ + int rc; + + mutex_lock(&ctrl->lock); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) { + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + mutex_unlock(&ctrl->lock); + return rc; + } + } + + cpr3_ctrl_loop_disable(ctrl); + + rc = cpr3_closed_loop_disable(ctrl); + if (rc) + cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); + + ctrl->cpr_suspended = true; + + mutex_unlock(&ctrl->lock); + return 0; +} + +/** + * cpr3_regulator_resume() - perform common required CPR3 power up steps after + * the system resumes from suspend + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_regulator_resume(struct cpr3_controller *ctrl) +{ + int rc; + + mutex_lock(&ctrl->lock); + + ctrl->cpr_suspended = false; + rc = cpr3_regulator_update_ctrl_state(ctrl); + if (rc) + cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); + + mutex_unlock(&ctrl->lock); + return 0; +} + +/** + * cpr3_regulator_validate_controller() - verify the data passed in via the + * cpr3_controller data structure + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_regulator_validate_controller(struct cpr3_controller *ctrl) +{ + struct cpr3_thread *thread; + struct cpr3_regulator *vreg; + int i, j, allow_boost_vreg_count = 0; + + if (!ctrl->vdd_regulator) { + cpr3_err(ctrl, "vdd regulator missing\n"); + return -EINVAL; + } else if (ctrl->sensor_count <= 0 + || ctrl->sensor_count > CPR3_MAX_SENSOR_COUNT) { + cpr3_err(ctrl, "invalid CPR sensor count=%d\n", + ctrl->sensor_count); + return -EINVAL; + } else if (!ctrl->sensor_owner) { + cpr3_err(ctrl, "CPR sensor ownership table missing\n"); + return -EINVAL; + } + + if (ctrl->aging_required) { + for (i = 0; i < ctrl->aging_sensor_count; i++) { + if (ctrl->aging_sensor[i].sensor_id + >= ctrl->sensor_count) { + cpr3_err(ctrl, "aging_sensor[%d] id=%u is not in the value range 0-%d", + i, ctrl->aging_sensor[i].sensor_id, + ctrl->sensor_count - 1); + return -EINVAL; + } + } + } + + for (i = 0; i < ctrl->thread_count; i++) { + thread = &ctrl->thread[i]; + for (j = 0; j < thread->vreg_count; j++) { + vreg = &thread->vreg[j]; + if (vreg->allow_boost) + allow_boost_vreg_count++; + } + } + + if (allow_boost_vreg_count > 1) { + /* + * Boost feature is not allowed to be used for more + * than one CPR3 regulator of a CPR3 controller. + */ + cpr3_err(ctrl, "Boost feature is enabled for more than one regulator\n"); + return -EINVAL; + } + + return 0; +} + +/** + * cpr3_panic_callback() - panic notification callback function. This function + * is invoked when a kernel panic occurs. + * @nfb: Notifier block pointer of CPR3 controller + * @event: Value passed unmodified to notifier function + * @data: Pointer passed unmodified to notifier function + * + * Return: NOTIFY_OK + */ +static int cpr3_panic_callback(struct notifier_block *nfb, + unsigned long event, void *data) +{ + struct cpr3_controller *ctrl = container_of(nfb, + struct cpr3_controller, panic_notifier); + struct cpr3_panic_regs_info *regs_info = ctrl->panic_regs_info; + struct cpr3_reg_info *reg; + int i = 0; + + for (i = 0; i < regs_info->reg_count; i++) { + reg = &(regs_info->regs[i]); + reg->value = readl_relaxed(reg->virt_addr); + pr_err("%s[0x%08x] = 0x%08x\n", reg->name, reg->addr, + reg->value); + } + /* + * Barrier to ensure that the information has been updated in the + * structure. + */ + mb(); + + return NOTIFY_OK; +} + +/** + * cpr3_regulator_register() - register the regulators for a CPR3 controller and + * perform CPR hardware initialization + * @pdev: Platform device pointer for the CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl) +{ + struct device *dev = &pdev->dev; + struct resource *res; + int i, j, rc; + + if (!dev->of_node) { + dev_err(dev, "%s: Device tree node is missing\n", __func__); + return -EINVAL; + } + + if (!ctrl || !ctrl->name) { + dev_err(dev, "%s: CPR controller data is missing\n", __func__); + return -EINVAL; + } + + rc = cpr3_regulator_validate_controller(ctrl); + if (rc) { + cpr3_err(ctrl, "controller validation failed, rc=%d\n", rc); + return rc; + } + + mutex_init(&ctrl->lock); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpr_ctrl"); + if (!res || !res->start) { + cpr3_err(ctrl, "CPR controller address is missing\n"); + return -ENXIO; + } + ctrl->cpr_ctrl_base = devm_ioremap(dev, res->start, resource_size(res)); + + if (ctrl->aging_possible_mask) { + /* + * Aging possible register address is required if an aging + * possible mask has been specified. + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "aging_allowed"); + if (!res || !res->start) { + cpr3_err(ctrl, "CPR aging allowed address is missing\n"); + return -ENXIO; + } + ctrl->aging_possible_reg = devm_ioremap(dev, res->start, + resource_size(res)); + } + + ctrl->irq = platform_get_irq_byname(pdev, "cpr"); + if (ctrl->irq < 0) { + cpr3_err(ctrl, "missing CPR interrupt\n"); + return ctrl->irq; + } + + if (ctrl->supports_hw_closed_loop) { + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + ctrl->ceiling_irq = platform_get_irq_byname(pdev, + "ceiling"); + if (ctrl->ceiling_irq < 0) { + cpr3_err(ctrl, "missing ceiling interrupt\n"); + return ctrl->ceiling_irq; + } + } + } + + rc = cpr3_regulator_init_ctrl_data(ctrl); + if (rc) { + cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n", + rc); + return rc; + } + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + rc = cpr3_regulator_init_vreg_data( + &ctrl->thread[i].vreg[j]); + if (rc) + return rc; + cpr3_print_quots(&ctrl->thread[i].vreg[j]); + } + } + + /* + * Add the maximum possible aging voltage margin until it is possible + * to perform an aging measurement. + */ + if (ctrl->aging_required) + cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); + + rc = cpr3_regulator_init_ctrl(ctrl); + if (rc) { + cpr3_err(ctrl, "CPR controller initialization failed, rc=%d\n", + rc); + return rc; + } + + /* Register regulator devices for all threads. */ + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + rc = cpr3_regulator_vreg_register( + &ctrl->thread[i].vreg[j]); + if (rc) { + cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n", + rc); + goto free_regulators; + } + } + } + + rc = devm_request_threaded_irq(dev, ctrl->irq, NULL, + cpr3_irq_handler, + IRQF_ONESHOT | + IRQF_TRIGGER_RISING, + "cpr3", ctrl); + if (rc) { + cpr3_err(ctrl, "could not request IRQ %d, rc=%d\n", + ctrl->irq, rc); + goto free_regulators; + } + + if (ctrl->supports_hw_closed_loop && + ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { + rc = devm_request_threaded_irq(dev, ctrl->ceiling_irq, NULL, + cpr3_ceiling_irq_handler, + IRQF_ONESHOT | IRQF_TRIGGER_RISING, + "cpr3_ceiling", ctrl); + if (rc) { + cpr3_err(ctrl, "could not request ceiling IRQ %d, rc=%d\n", + ctrl->ceiling_irq, rc); + goto free_regulators; + } + } + + mutex_lock(&cpr3_controller_list_mutex); + cpr3_regulator_debugfs_ctrl_add(ctrl); + list_add(&ctrl->list, &cpr3_controller_list); + mutex_unlock(&cpr3_controller_list_mutex); + + if (ctrl->panic_regs_info) { + /* Register panic notification call back */ + ctrl->panic_notifier.notifier_call = cpr3_panic_callback; + atomic_notifier_chain_register(&panic_notifier_list, + &ctrl->panic_notifier); + } + + return 0; + +free_regulators: + for (i = 0; i < ctrl->thread_count; i++) + for (j = 0; j < ctrl->thread[i].vreg_count; j++) + if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev)) + regulator_unregister( + ctrl->thread[i].vreg[j].rdev); + return rc; +} + +/** + * cpr3_open_loop_regulator_register() - register the regulators for a CPR3 + * controller which will always work in Open loop and + * won't support close loop. + * @pdev: Platform device pointer for the CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_open_loop_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl) +{ + struct device *dev = &pdev->dev; + struct cpr3_regulator *vreg; + int i, j, rc; + + if (!dev->of_node) { + dev_err(dev, "%s: Device tree node is missing\n", __func__); + return -EINVAL; + } + + if (!ctrl || !ctrl->name) { + dev_err(dev, "%s: CPR controller data is missing\n", __func__); + return -EINVAL; + } + + if (!ctrl->vdd_regulator) { + cpr3_err(ctrl, "vdd regulator missing\n"); + return -EINVAL; + } + + mutex_init(&ctrl->lock); + + rc = cpr3_regulator_init_ctrl_data(ctrl); + if (rc) { + cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n", + rc); + return rc; + } + + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + vreg = &ctrl->thread[i].vreg[j]; + vreg->corner[i].last_volt = + vreg->corner[i].open_loop_volt; + } + } + + /* Register regulator devices for all threads. */ + for (i = 0; i < ctrl->thread_count; i++) { + for (j = 0; j < ctrl->thread[i].vreg_count; j++) { + rc = cpr3_regulator_vreg_register( + &ctrl->thread[i].vreg[j]); + if (rc) { + cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n", + rc); + goto free_regulators; + } + } + } + + mutex_lock(&cpr3_controller_list_mutex); + list_add(&ctrl->list, &cpr3_controller_list); + mutex_unlock(&cpr3_controller_list_mutex); + + return 0; + +free_regulators: + for (i = 0; i < ctrl->thread_count; i++) + for (j = 0; j < ctrl->thread[i].vreg_count; j++) + if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev)) + regulator_unregister( + ctrl->thread[i].vreg[j].rdev); + return rc; +} + +/** + * cpr3_regulator_unregister() - unregister the regulators for a CPR3 controller + * and perform CPR hardware shutdown + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_regulator_unregister(struct cpr3_controller *ctrl) +{ + int i, j, rc = 0; + + mutex_lock(&cpr3_controller_list_mutex); + list_del(&ctrl->list); + cpr3_regulator_debugfs_ctrl_remove(ctrl); + mutex_unlock(&cpr3_controller_list_mutex); + + if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { + rc = cpr3_ctrl_clear_cpr4_config(ctrl); + if (rc) + cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", + rc); + } + + cpr3_ctrl_loop_disable(ctrl); + + cpr3_closed_loop_disable(ctrl); + + if (ctrl->vdd_limit_regulator) { + regulator_disable(ctrl->vdd_limit_regulator); + } + + for (i = 0; i < ctrl->thread_count; i++) + for (j = 0; j < ctrl->thread[i].vreg_count; j++) + regulator_unregister(ctrl->thread[i].vreg[j].rdev); + + if (ctrl->panic_notifier.notifier_call) + atomic_notifier_chain_unregister(&panic_notifier_list, + &ctrl->panic_notifier); + + return 0; +} + +/** + * cpr3_open_loop_regulator_unregister() - unregister the regulators for a CPR3 + * open loop controller and perform CPR hardware shutdown + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl) +{ + int i, j; + + mutex_lock(&cpr3_controller_list_mutex); + list_del(&ctrl->list); + mutex_unlock(&cpr3_controller_list_mutex); + + if (ctrl->vdd_limit_regulator) { + regulator_disable(ctrl->vdd_limit_regulator); + } + + for (i = 0; i < ctrl->thread_count; i++) + for (j = 0; j < ctrl->thread[i].vreg_count; j++) + regulator_unregister(ctrl->thread[i].vreg[j].rdev); + + if (ctrl->panic_notifier.notifier_call) + atomic_notifier_chain_unregister(&panic_notifier_list, + &ctrl->panic_notifier); + + return 0; +} diff --git a/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.h b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.h new file mode 100644 index 000000000..7c69c4630 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.h @@ -0,0 +1,1211 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __REGULATOR_CPR3_REGULATOR_H__ +#define __REGULATOR_CPR3_REGULATOR_H__ + +#include +#include +#include +#include +#include +#include +#include + +struct cpr3_controller; +struct cpr3_thread; + +/** + * struct cpr3_fuse_param - defines one contiguous segment of a fuse parameter + * that is contained within a given row. + * @row: Fuse row number + * @bit_start: The first bit within the row of the fuse parameter segment + * @bit_end: The last bit within the row of the fuse parameter segment + * + * Each fuse row is 64 bits in length. bit_start and bit_end may take values + * from 0 to 63. bit_start must be less than or equal to bit_end. + */ +struct cpr3_fuse_param { + unsigned row; + unsigned bit_start; + unsigned bit_end; +}; + +/* Each CPR3 sensor has 16 ring oscillators */ +#define CPR3_RO_COUNT 16 + +/* The maximum number of sensors that can be present on a single CPR loop. */ +#define CPR3_MAX_SENSOR_COUNT 256 + +/* This constant is used when allocating array printing buffers. */ +#define MAX_CHARS_PER_INT 10 + +/** + * struct cpr4_sdelta - CPR4 controller specific data structure for the sdelta + * adjustment table which is used to adjust the VDD supply + * voltage automatically based upon the temperature and/or + * the number of online CPU cores. + * @allow_core_count_adj: Core count adjustments are allowed. + * @allow_temp_adj: Temperature based adjustments are allowed. + * @max_core_count: Maximum number of cores considered for core count + * adjustment logic. + * @temp_band_count: Number of temperature bands considered for temperature + * based adjustment logic. + * @cap_volt: CAP in uV to apply to SDELTA margins with multiple + * cpr3-regulators defined for single controller. + * @table: SDELTA table with per-online-core and temperature based + * adjustments of size (max_core_count * temp_band_count) + * Outer: core count + * Inner: temperature band + * Each element has units of VDD supply steps. Positive + * values correspond to a reduction in voltage and negative + * value correspond to an increase (this follows the SDELTA + * register semantics). + * @allow_boost: Voltage boost allowed. + * @boost_num_cores: The number of online cores at which the boost voltage + * adjustments will be applied + * @boost_table: SDELTA table with boost voltage adjustments of size + * temp_band_count. Each element has units of VDD supply + * steps. Positive values correspond to a reduction in + * voltage and negative value correspond to an increase + * (this follows the SDELTA register semantics). + */ +struct cpr4_sdelta { + bool allow_core_count_adj; + bool allow_temp_adj; + int max_core_count; + int temp_band_count; + int cap_volt; + int *table; + bool allow_boost; + int boost_num_cores; + int *boost_table; +}; + +/** + * struct cpr3_corner - CPR3 virtual voltage corner data structure + * @floor_volt: CPR closed-loop floor voltage in microvolts + * @ceiling_volt: CPR closed-loop ceiling voltage in microvolts + * @open_loop_volt: CPR open-loop voltage (i.e. initial voltage) in + * microvolts + * @last_volt: Last known settled CPR closed-loop voltage which is used + * when switching to a new corner + * @abs_ceiling_volt: The absolute CPR closed-loop ceiling voltage in + * microvolts. This is used to limit the ceiling_volt + * value when it is increased as a result of aging + * adjustment. + * @unaged_floor_volt: The CPR closed-loop floor voltage in microvolts before + * any aging adjustment is performed + * @unaged_ceiling_volt: The CPR closed-loop ceiling voltage in microvolts + * before any aging adjustment is performed + * @unaged_open_loop_volt: The CPR open-loop voltage (i.e. initial voltage) in + * microvolts before any aging adjusment is performed + * @system_volt: The system-supply voltage in microvolts or corners or + * levels + * @mem_acc_volt: The mem-acc-supply voltage in corners + * @proc_freq: Processor frequency in Hertz. For CPR rev. 3 and 4 + * conrollers, this field is only used by platform specific + * CPR3 driver for interpolation. For CPRh-compliant + * controllers, this frequency is also utilized by the + * clock driver to determine the corner to CPU clock + * frequency mappings. + * @cpr_fuse_corner: Fused corner index associated with this virtual corner + * (only used by platform specific CPR3 driver for + * mapping purposes) + * @target_quot: Array of target quotient values to use for each ring + * oscillator (RO) for this corner. A value of 0 should be + * specified as the target quotient for each RO that is + * unused by this corner. + * @ro_scale: Array of CPR ring oscillator (RO) scaling factors. The + * scaling factor for each RO is defined from RO0 to RO15 + * with units of QUOT/V. A value of 0 may be specified for + * an RO that is unused. + * @ro_mask: Bitmap where each of the 16 LSBs indicate if the + * corresponding ROs should be masked for this corner + * @irq_en: Bitmap of the CPR interrupts to enable for this corner + * @aging_derate: The amount to derate the aging voltage adjustment + * determined for the reference corner in units of uV/mV. + * E.g. a value of 900 would imply that the adjustment for + * this corner should be 90% (900/1000) of that for the + * reference corner. + * @use_open_loop: Boolean indicating that open-loop (i.e CPR disabled) as + * opposed to closed-loop operation must be used for this + * corner on CPRh controllers. + * @sdelta: The CPR4 controller specific data for this corner. This + * field is applicable for CPR4 controllers. + * + * The value of last_volt is initialized inside of the cpr3_regulator_register() + * call with the open_loop_volt value. It can later be updated to the settled + * VDD supply voltage. The values for unaged_floor_volt, unaged_ceiling_volt, + * and unaged_open_loop_volt are initialized inside of cpr3_regulator_register() + * if ctrl->aging_required == true. These three values must be pre-initialized + * if cpr3_regulator_register() is called with ctrl->aging_required == false and + * ctrl->aging_succeeded == true. + * + * The values of ro_mask and irq_en are initialized inside of the + * cpr3_regulator_register() call. + */ +struct cpr3_corner { + int floor_volt; + int ceiling_volt; + int cold_temp_open_loop_volt; + int normal_temp_open_loop_volt; + int open_loop_volt; + int last_volt; + int abs_ceiling_volt; + int unaged_floor_volt; + int unaged_ceiling_volt; + int unaged_open_loop_volt; + int system_volt; + int mem_acc_volt; + u32 proc_freq; + int cpr_fuse_corner; + u32 target_quot[CPR3_RO_COUNT]; + u32 ro_scale[CPR3_RO_COUNT]; + u32 ro_mask; + u32 irq_en; + int aging_derate; + bool use_open_loop; + struct cpr4_sdelta *sdelta; +}; + +/** + * struct cprh_corner_band - CPRh controller specific data structure which + * encapsulates the range of corners and the SDELTA + * adjustment table to be applied to the corners within + * the min and max bounds of the corner band. + * @corner: Corner number which defines the corner band boundary + * @sdelta: The SDELTA adjustment table which contains core-count + * and temp based margin adjustments that are applicable + * to the corner band. + */ +struct cprh_corner_band { + int corner; + struct cpr4_sdelta *sdelta; +}; + +/** + * struct cpr3_fuse_parameters - CPR4 fuse specific data structure which has + * the required fuse parameters need for Close Loop CPR + * @(*apss_ro_sel_param)[2]: Pointer to RO select fuse details + * @(*apss_init_voltage_param)[2]: Pointer to Target voltage fuse details + * @(*apss_target_quot_param)[2]: Pointer to Target quot fuse details + * @(*apss_quot_offset_param)[2]: Pointer to quot offset fuse details + * @cpr_fusing_rev_param: Pointer to CPR revision fuse details + * @apss_speed_bin_param: Pointer to Speed bin fuse details + * @cpr_boost_fuse_cfg_param: Pointer to Boost fuse cfg details + * @apss_boost_fuse_volt_param: Pointer to Boost fuse volt details + * @misc_fuse_volt_adj_param: Pointer to Misc fuse volt fuse details + */ +struct cpr3_fuse_parameters { + struct cpr3_fuse_param (*apss_ro_sel_param)[2]; + struct cpr3_fuse_param (*apss_init_voltage_param)[2]; + struct cpr3_fuse_param (*apss_target_quot_param)[2]; + struct cpr3_fuse_param (*apss_quot_offset_param)[2]; + struct cpr3_fuse_param *cpr_fusing_rev_param; + struct cpr3_fuse_param *apss_speed_bin_param; + struct cpr3_fuse_param *cpr_boost_fuse_cfg_param; + struct cpr3_fuse_param *apss_boost_fuse_volt_param; + struct cpr3_fuse_param *misc_fuse_volt_adj_param; +}; + +struct cpr4_mem_acc_func { + void (*set_mem_acc)(struct regulator_dev *); + void (*clear_mem_acc)(struct regulator_dev *); +}; + +/** + * struct cpr4_reg_data - CPR4 regulator specific data structure which is + * target specific + * @cpr_valid_fuse_count: Number of valid fuse corners + * @fuse_ref_volt: Pointer to fuse reference voltage + * @fuse_step_volt: CPR step voltage available in fuse + * @cpr_clk_rate: CPR clock rate + * @boost_fuse_ref_volt: Boost fuse reference voltage + * @boost_ceiling_volt: Boost ceiling voltage + * @boost_floor_volt: Boost floor voltage + * @cpr3_fuse_params: Pointer to CPR fuse parameters + * @mem_acc_funcs: Pointer to MEM ACC set/clear functions + **/ +struct cpr4_reg_data { + u32 cpr_valid_fuse_count; + int *fuse_ref_volt; + u32 fuse_step_volt; + u32 cpr_clk_rate; + int boost_fuse_ref_volt; + int boost_ceiling_volt; + int boost_floor_volt; + struct cpr3_fuse_parameters *cpr3_fuse_params; + struct cpr4_mem_acc_func *mem_acc_funcs; +}; +/** + * struct cpr3_reg_data - CPR3 regulator specific data structure which is + * target specific + * @cpr_valid_fuse_count: Number of valid fuse corners + * @(*init_voltage_param)[2]: Pointer to Target voltage fuse details + * @fuse_ref_volt: Pointer to fuse reference voltage + * @fuse_step_volt: CPR step voltage available in fuse + * @cpr_clk_rate: CPR clock rate + * @cpr3_fuse_params: Pointer to CPR fuse parameters + **/ +struct cpr3_reg_data { + u32 cpr_valid_fuse_count; + struct cpr3_fuse_param (*init_voltage_param)[2]; + int *fuse_ref_volt; + u32 fuse_step_volt; + u32 cpr_clk_rate; +}; + +/** + * struct cpr3_regulator - CPR3 logical regulator instance associated with a + * given CPR3 hardware thread + * @of_node: Device node associated with the device tree child node + * of this CPR3 regulator + * @thread: Pointer to the CPR3 thread which manages this CPR3 + * regulator + * @name: Unique name for this CPR3 regulator which is filled + * using the device tree regulator-name property + * @rdesc: Regulator description for this CPR3 regulator + * @rdev: Regulator device pointer for the regulator registered + * for this CPR3 regulator + * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used + * to manage memory circuitry settings based upon CPR3 + * regulator output voltage. + * @corner: Array of all corners supported by this CPR3 regulator + * @corner_count: The number of elements in the corner array + * @corner_band: Array of all corner bands supported by CPRh compatible + * controllers + * @cpr4_regulator_data Target specific cpr4 regulator data + * @cpr3_regulator_data Target specific cpr3 regulator data + * @corner_band_count: The number of elements in the corner band array + * @platform_fuses: Pointer to platform specific CPR fuse data (only used by + * platform specific CPR3 driver) + * @speed_bin_fuse: Value read from the speed bin fuse parameter + * @speed_bins_supported: The number of speed bins supported by the device tree + * configuration for this CPR3 regulator + * @cpr_rev_fuse: Value read from the CPR fusing revision fuse parameter + * @fuse_combo: Platform specific enum value identifying the specific + * combination of fuse values found on a given chip + * @fuse_combos_supported: The number of fuse combinations supported by the + * device tree configuration for this CPR3 regulator + * @fuse_corner_count: Number of corners defined by fuse parameters + * @fuse_corner_map: Array of length fuse_corner_count which specifies the + * highest corner associated with each fuse corner. Note + * that each element must correspond to a valid corner + * and that element values must be strictly increasing. + * Also, it is acceptable for the lowest fuse corner to map + * to a corner other than the lowest. Likewise, it is + * acceptable for the highest fuse corner to map to a + * corner other than the highest. + * @fuse_combo_corner_sum: The sum of the corner counts across all fuse combos + * @fuse_combo_offset: The device tree property array offset for the selected + * fuse combo + * @speed_bin_corner_sum: The sum of the corner counts across all speed bins + * This may be specified as 0 if per speed bin parsing + * support is not required. + * @speed_bin_offset: The device tree property array offset for the selected + * speed bin + * @fuse_combo_corner_band_sum: The sum of the corner band counts across all + * fuse combos + * @fuse_combo_corner_band_offset: The device tree property array offset for + * the corner band count corresponding to the selected + * fuse combo + * @speed_bin_corner_band_sum: The sum of the corner band counts across all + * speed bins. This may be specified as 0 if per speed bin + * parsing support is not required + * @speed_bin_corner_band_offset: The device tree property array offset for the + * corner band count corresponding to the selected speed + * bin + * @pd_bypass_mask: Bit mask of power domains associated with this CPR3 + * regulator + * @dynamic_floor_corner: Index identifying the voltage corner for the CPR3 + * regulator whose last_volt value should be used as the + * global CPR floor voltage if all of the power domains + * associated with this CPR3 regulator are bypassed + * @uses_dynamic_floor: Boolean flag indicating that dynamic_floor_corner should + * be utilized for the CPR3 regulator + * @current_corner: Index identifying the currently selected voltage corner + * for the CPR3 regulator or less than 0 if no corner has + * been requested + * @last_closed_loop_corner: Index identifying the last voltage corner for the + * CPR3 regulator which was configured when operating in + * CPR closed-loop mode or less than 0 if no corner has + * been requested. CPR registers are only written to when + * using closed-loop mode. + * @aggregated: Boolean flag indicating that this CPR3 regulator + * participated in the last aggregation event + * @debug_corner: Index identifying voltage corner used for displaying + * corner configuration values in debugfs + * @vreg_enabled: Boolean defining the enable state of the CPR3 + * regulator's regulator within the regulator framework. + * @aging_allowed: Boolean defining if CPR aging adjustments are allowed + * for this CPR3 regulator given the fuse combo of the + * device + * @aging_allow_open_loop_adj: Boolean defining if the open-loop voltage of each + * corner of this regulator should be adjusted as a result + * of an aging measurement. This flag can be set to false + * when the open-loop voltage adjustments have been + * specified such that they include the maximum possible + * aging adjustment. This flag is only used if + * aging_allowed == true. + * @aging_corner: The corner that should be configured for this regulator + * when an aging measurement is performed. + * @aging_max_adjust_volt: The maximum aging voltage margin in microvolts that + * may be added to the target quotients of this regulator. + * A value of 0 may be specified if this regulator does not + * require any aging adjustment. + * @allow_core_count_adj: Core count adjustments are allowed for this regulator. + * @allow_temp_adj: Temperature based adjustments are allowed for this + * regulator. + * @max_core_count: Maximum number of cores considered for core count + * adjustment logic. + * @allow_boost: Voltage boost allowed for this regulator. + * + * This structure contains both configuration and runtime state data. The + * elements current_corner, last_closed_loop_corner, aggregated, debug_corner, + * and vreg_enabled are state variables. + */ +struct cpr3_regulator { + struct device_node *of_node; + struct cpr3_thread *thread; + const char *name; + struct regulator_desc rdesc; + struct regulator_dev *rdev; + struct regulator *mem_acc_regulator; + struct cpr3_corner *corner; + int corner_count; + struct cprh_corner_band *corner_band; + struct cpr4_reg_data *cpr4_regulator_data; + struct cpr3_reg_data *cpr3_regulator_data; + u32 corner_band_count; + + void *platform_fuses; + int speed_bin_fuse; + int speed_bins_supported; + int cpr_rev_fuse; + int part_type; + int part_type_supported; + int fuse_combo; + int fuse_combos_supported; + int fuse_corner_count; + int *fuse_corner_map; + int fuse_combo_corner_sum; + int fuse_combo_offset; + int speed_bin_corner_sum; + int speed_bin_offset; + int fuse_combo_corner_band_sum; + int fuse_combo_corner_band_offset; + int speed_bin_corner_band_sum; + int speed_bin_corner_band_offset; + u32 pd_bypass_mask; + int dynamic_floor_corner; + bool uses_dynamic_floor; + + int current_corner; + int last_closed_loop_corner; + bool aggregated; + int debug_corner; + bool vreg_enabled; + + bool aging_allowed; + bool aging_allow_open_loop_adj; + int aging_corner; + int aging_max_adjust_volt; + + bool allow_core_count_adj; + bool allow_temp_adj; + int max_core_count; + bool allow_boost; +}; + +/** + * struct cpr3_thread - CPR3 hardware thread data structure + * @thread_id: Hardware thread ID + * @of_node: Device node associated with the device tree child node + * of this CPR3 thread + * @ctrl: Pointer to the CPR3 controller which manages this thread + * @vreg: Array of CPR3 regulators handled by the CPR3 thread + * @vreg_count: Number of elements in the vreg array + * @aggr_corner: CPR corner containing the in process aggregated voltage + * and target quotient configurations which will be applied + * @last_closed_loop_aggr_corner: CPR corner containing the most recent + * configurations which were written into hardware + * registers when operating in closed loop mode (i.e. with + * CPR enabled) + * @consecutive_up: The number of consecutive CPR step up events needed to + * to trigger an up interrupt + * @consecutive_down: The number of consecutive CPR step down events needed to + * to trigger a down interrupt + * @up_threshold: The number CPR error steps required to generate an up + * event + * @down_threshold: The number CPR error steps required to generate a down + * event + * + * This structure contains both configuration and runtime state data. The + * elements aggr_corner and last_closed_loop_aggr_corner are state variables. + */ +struct cpr3_thread { + u32 thread_id; + struct device_node *of_node; + struct cpr3_controller *ctrl; + struct cpr3_regulator *vreg; + int vreg_count; + struct cpr3_corner aggr_corner; + struct cpr3_corner last_closed_loop_aggr_corner; + + u32 consecutive_up; + u32 consecutive_down; + u32 up_threshold; + u32 down_threshold; +}; + +/* Per CPR controller data */ +/** + * enum cpr3_mem_acc_corners - Constants which define the number of mem-acc + * regulator corners available in the mem-acc corner map array. + * %CPR3_MEM_ACC_LOW_CORNER: Index in mem-acc corner map array mapping to the + * mem-acc regulator corner + * to be used for low voltage vdd supply + * %CPR3_MEM_ACC_HIGH_CORNER: Index in mem-acc corner map array mapping to the + * mem-acc regulator corner to be used for high + * voltage vdd supply + * %CPR3_MEM_ACC_CORNERS: Number of elements in the mem-acc corner map + * array + */ +enum cpr3_mem_acc_corners { + CPR3_MEM_ACC_LOW_CORNER = 0, + CPR3_MEM_ACC_HIGH_CORNER = 1, + CPR3_MEM_ACC_CORNERS = 2, +}; + +/** + * enum cpr3_count_mode - CPR3 controller count mode which defines the + * method that CPR sensor data is acquired + * %CPR3_COUNT_MODE_ALL_AT_ONCE_MIN: Capture all CPR sensor readings + * simultaneously and report the minimum + * value seen in successive measurements + * %CPR3_COUNT_MODE_ALL_AT_ONCE_MAX: Capture all CPR sensor readings + * simultaneously and report the maximum + * value seen in successive measurements + * %CPR3_COUNT_MODE_STAGGERED: Read one sensor at a time in a + * sequential fashion + * %CPR3_COUNT_MODE_ALL_AT_ONCE_AGE: Capture all CPR aging sensor readings + * simultaneously. + */ +enum cpr3_count_mode { + CPR3_COUNT_MODE_ALL_AT_ONCE_MIN = 0, + CPR3_COUNT_MODE_ALL_AT_ONCE_MAX = 1, + CPR3_COUNT_MODE_STAGGERED = 2, + CPR3_COUNT_MODE_ALL_AT_ONCE_AGE = 3, +}; + +/** + * enum cpr_controller_type - supported CPR controller hardware types + * %CPR_CTRL_TYPE_CPR3: HW has CPR3 controller + * %CPR_CTRL_TYPE_CPR4: HW has CPR4 controller + */ +enum cpr_controller_type { + CPR_CTRL_TYPE_CPR3, + CPR_CTRL_TYPE_CPR4, +}; + +/** + * cpr_setting - supported CPR global settings + * %CPR_DEFAULT: default mode from dts will be used + * %CPR_DISABLED: ceiling voltage will be used for all the corners + * %CPR_OPEN_LOOP_EN: CPR will work in OL + * %CPR_CLOSED_LOOP_EN: CPR will work in CL, if supported + */ +enum cpr_setting { + CPR_DEFAULT = 0, + CPR_DISABLED = 1, + CPR_OPEN_LOOP_EN = 2, + CPR_CLOSED_LOOP_EN = 3, +}; + +/** + * struct cpr3_aging_sensor_info - CPR3 aging sensor information + * @sensor_id The index of the CPR3 sensor to be used in the aging + * measurement. + * @ro_scale The CPR ring oscillator (RO) scaling factor for the + * aging sensor with units of QUOT/V. + * @init_quot_diff: The fused quotient difference between aged and un-aged + * paths that was measured at manufacturing time. + * @measured_quot_diff: The quotient difference measured at runtime. + * @bypass_mask: Bit mask of the CPR sensors that must be bypassed during + * the aging measurement for this sensor + * + * This structure contains both configuration and runtime state data. The + * element measured_quot_diff is a state variable. + */ +struct cpr3_aging_sensor_info { + u32 sensor_id; + u32 ro_scale; + int init_quot_diff; + int measured_quot_diff; + u32 bypass_mask[CPR3_MAX_SENSOR_COUNT / 32]; +}; + +/** + * struct cpr3_reg_info - Register information data structure + * @name: Register name + * @addr: Register physical address + * @value: Register content + * @virt_addr: Register virtual address + * + * This data structure is used to dump some critical register contents + * when the device crashes due to a kernel panic. + */ +struct cpr3_reg_info { + const char *name; + u32 addr; + u32 value; + void __iomem *virt_addr; +}; + +/** + * struct cpr3_panic_regs_info - Data structure to dump critical register + * contents. + * @reg_count: Number of elements in the regs array + * @regs: Array of critical registers information + * + * This data structure is used to dump critical register contents when + * the device crashes due to a kernel panic. + */ +struct cpr3_panic_regs_info { + int reg_count; + struct cpr3_reg_info *regs; +}; + +/** + * struct cpr3_controller - CPR3 controller data structure + * @dev: Device pointer for the CPR3 controller device + * @name: Unique name for the CPR3 controller + * @ctrl_id: Controller ID corresponding to the VDD supply number + * that this CPR3 controller manages. + * @cpr_ctrl_base: Virtual address of the CPR3 controller base register + * @fuse_base: Virtual address of fuse row 0 + * @aging_possible_reg: Virtual address of an optional platform-specific + * register that must be ready to determine if it is + * possible to perform an aging measurement. + * @list: list head used in a global cpr3-regulator list so that + * cpr3-regulator structs can be found easily in RAM dumps + * @thread: Array of CPR3 threads managed by the CPR3 controller + * @thread_count: Number of elements in the thread array + * @sensor_owner: Array of thread IDs indicating which thread owns a given + * CPR sensor + * @sensor_count: The number of CPR sensors found on the CPR loop managed + * by this CPR controller. Must be equal to the number of + * elements in the sensor_owner array + * @soc_revision: Revision number of the SoC. This may be unused by + * platforms that do not have different behavior for + * different SoC revisions. + * @lock: Mutex lock used to ensure mutual exclusion between + * all of the threads associated with the controller + * @vdd_regulator: Pointer to the VDD supply regulator which this CPR3 + * controller manages + * @system_regulator: Pointer to the optional system-supply regulator upon + * which the VDD supply regulator depends. + * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used + * to manage memory circuitry settings based upon the + * VDD supply output voltage. + * @vdd_limit_regulator: Pointer to the VDD supply limit regulator which is used + * for hardware closed-loop in order specify ceiling and + * floor voltage limits (platform specific) + * @system_supply_max_volt: Voltage in microvolts which corresponds to the + * absolute ceiling voltage of the system-supply + * @mem_acc_threshold_volt: mem-acc threshold voltage in microvolts + * @mem_acc_corner_map: mem-acc regulator corners mapping to low and high + * voltage mem-acc settings for the memories powered by + * this CPR3 controller and its associated CPR3 regulators + * @mem_acc_crossover_volt: Voltage in microvolts corresponding to the voltage + * that the VDD supply must be set to while a MEM ACC + * switch is in progress. This element must be initialized + * for CPRh controllers when a MEM ACC threshold voltage is + * defined. + * @core_clk: Pointer to the CPR3 controller core clock + * @iface_clk: Pointer to the CPR3 interface clock (platform specific) + * @bus_clk: Pointer to the CPR3 bus clock (platform specific) + * @irq: CPR interrupt number + * @irq_affinity_mask: The cpumask for the CPUs which the CPR interrupt should + * have affinity for + * @cpu_hotplug_notifier: CPU hotplug notifier used to reset IRQ affinity when a + * CPU is brought back online + * @ceiling_irq: Interrupt number for the interrupt that is triggered + * when hardware closed-loop attempts to exceed the ceiling + * voltage + * @apm: Handle to the array power mux (APM) + * @apm_threshold_volt: Voltage in microvolts which defines the threshold + * voltage to determine the APM supply selection for + * each corner + * @apm_crossover_volt: Voltage in microvolts corresponding to the voltage that + * the VDD supply must be set to while an APM switch is in + * progress. This element must be initialized for CPRh + * controllers when an APM threshold voltage is defined + * @apm_adj_volt: Minimum difference between APM threshold voltage and + * open-loop voltage which allows the APM threshold voltage + * to be used as a ceiling + * @apm_high_supply: APM supply to configure if VDD voltage is greater than + * or equal to the APM threshold voltage + * @apm_low_supply: APM supply to configure if the VDD voltage is less than + * the APM threshold voltage + * @base_volt: Minimum voltage in microvolts supported by the VDD + * supply managed by this CPR controller + * @corner_switch_delay_time: The delay time in nanoseconds used by the CPR + * controller to wait for voltage settling before + * acknowledging the OSM block after corner changes + * @cpr_clock_rate: CPR reference clock frequency in Hz. + * @sensor_time: The time in nanoseconds that each sensor takes to + * perform a measurement. + * @loop_time: The time in nanoseconds between consecutive CPR + * measurements. + * @up_down_delay_time: The time to delay in nanoseconds between consecutive CPR + * measurements when the last measurement recommended + * increasing or decreasing the vdd-supply voltage. + * (platform specific) + * @idle_clocks: Number of CPR reference clock ticks that the CPR + * controller waits in transitional states. + * @step_quot_init_min: The default minimum CPR step quotient value. The step + * quotient is the number of additional ring oscillator + * ticks observed when increasing one step in vdd-supply + * output voltage. + * @step_quot_init_max: The default maximum CPR step quotient value. + * @step_volt: Step size in microvolts between available set points + * of the VDD supply + * @down_error_step_limit: CPR4 hardware closed-loop down error step limit which + * defines the maximum number of VDD supply regulator steps + * that the voltage may be reduced as the result of a + * single CPR measurement. + * @up_error_step_limit: CPR4 hardware closed-loop up error step limit which + * defines the maximum number of VDD supply regulator steps + * that the voltage may be increased as the result of a + * single CPR measurement. + * @count_mode: CPR controller count mode + * @count_repeat: Number of times to perform consecutive sensor + * measurements when using all-at-once count modes. + * @proc_clock_throttle: Defines the processor clock frequency throttling + * register value to use. This can be used to reduce the + * clock frequency when a power domain exits a low power + * mode until CPR settles at a new voltage. + * (platform specific) + * @cpr_allowed_hw: Boolean which indicates if closed-loop CPR operation is + * permitted for a given chip based upon hardware fuse + * values + * @cpr_allowed_sw: Boolean which indicates if closed-loop CPR operation is + * permitted based upon software policies + * @supports_hw_closed_loop: Boolean which indicates if this CPR3/4 controller + * physically supports hardware closed-loop CPR operation + * @use_hw_closed_loop: Boolean which indicates that this controller will be + * using hardware closed-loop operation in place of + * software closed-loop operation. + * @ctrl_type: CPR controller type + * @saw_use_unit_mV: Boolean which indicates the unit used in SAW PVC + * interface is mV. + * @aggr_corner: CPR corner containing the most recently aggregated + * voltage configurations which are being used currently + * @cpr_enabled: Boolean which indicates that the CPR controller is + * enabled and operating in closed-loop mode. CPR clocks + * have been prepared and enabled whenever this flag is + * true. + * @last_corner_was_closed_loop: Boolean indicating if the last known corners + * were updated during closed loop operation. + * @cpr_suspended: Boolean which indicates that CPR has been temporarily + * disabled while enterring system suspend. + * @debugfs: Pointer to the debugfs directory of this CPR3 controller + * @aging_ref_volt: Reference voltage in microvolts to configure when + * performing CPR aging measurements. + * @aging_vdd_mode: vdd-supply regulator mode to configure before performing + * a CPR aging measurement. It should be one of + * REGULATOR_MODE_*. + * @aging_complete_vdd_mode: vdd-supply regulator mode to configure after + * performing a CPR aging measurement. It should be one of + * REGULATOR_MODE_*. + * @aging_ref_adjust_volt: The reference aging voltage margin in microvolts that + * should be added to the target quotients of the + * regulators managed by this controller after derating. + * @aging_required: Flag which indicates that a CPR aging measurement still + * needs to be performed for this CPR3 controller. + * @aging_succeeded: Flag which indicates that a CPR aging measurement has + * completed successfully. + * @aging_failed: Flag which indicates that a CPR aging measurement has + * failed to complete successfully. + * @aging_sensor: Array of CPR3 aging sensors which are used to perform + * aging measurements at a runtime. + * @aging_sensor_count: Number of elements in the aging_sensor array + * @aging_possible_mask: Optional bitmask used to mask off the + * aging_possible_reg register. + * @aging_possible_val: Optional value that the masked aging_possible_reg + * register must have in order for a CPR aging measurement + * to be possible. + * @step_quot_fixed: Fixed step quotient value used for target quotient + * adjustment if use_dynamic_step_quot is not set. + * This parameter is only relevant for CPR4 controllers + * when using the per-online-core or per-temperature + * adjustments. + * @initial_temp_band: Temperature band used for calculation of base-line + * target quotients (fused). + * @use_dynamic_step_quot: Boolean value which indicates that margin adjustment + * of target quotient will be based on the step quotient + * calculated dynamically in hardware for each RO. + * @allow_core_count_adj: Core count adjustments are allowed for this controller + * @allow_temp_adj: Temperature based adjustments are allowed for + * this controller + * @allow_boost: Voltage boost allowed for this controller. + * @temp_band_count: Number of temperature bands used for temperature based + * adjustment logic + * @temp_points: Array of temperature points in decidegrees Celsius used + * to specify the ranges for selected temperature bands. + * The array must have (temp_band_count - 1) elements + * allocated. + * @temp_sensor_id_start: Start ID of temperature sensors used for temperature + * based adjustments. + * @temp_sensor_id_end: End ID of temperature sensors used for temperature + * based adjustments. + * @voltage_settling_time: The time in nanoseconds that it takes for the + * VDD supply voltage to settle after being increased or + * decreased by step_volt microvolts which is used when + * SDELTA voltage margin adjustments are applied. + * @cpr_global_setting: Global setting for this CPR controller + * @panic_regs_info: Array of panic registers information which provides the + * list of registers to dump when the device crashes. + * @panic_notifier: Notifier block registered to global panic notifier list. + * + * This structure contains both configuration and runtime state data. The + * elements cpr_allowed_sw, use_hw_closed_loop, aggr_corner, cpr_enabled, + * last_corner_was_closed_loop, cpr_suspended, aging_ref_adjust_volt, + * aging_required, aging_succeeded, and aging_failed are state variables. + * + * The apm* elements do not need to be initialized if the VDD supply managed by + * the CPR3 controller does not utilize an APM. + * + * The elements step_quot_fixed, initial_temp_band, allow_core_count_adj, + * allow_temp_adj and temp* need to be initialized for CPR4 controllers which + * are using per-online-core or per-temperature adjustments. + */ +struct cpr3_controller { + struct device *dev; + const char *name; + int ctrl_id; + void __iomem *cpr_ctrl_base; + void __iomem *fuse_base; + void __iomem *aging_possible_reg; + struct list_head list; + struct cpr3_thread *thread; + int thread_count; + u8 *sensor_owner; + int sensor_count; + int soc_revision; + struct mutex lock; + struct regulator *vdd_regulator; + struct regulator *system_regulator; + struct regulator *mem_acc_regulator; + struct regulator *vdd_limit_regulator; + int system_supply_max_volt; + int mem_acc_threshold_volt; + int mem_acc_corner_map[CPR3_MEM_ACC_CORNERS]; + int mem_acc_crossover_volt; + struct clk *core_clk; + struct clk *iface_clk; + struct clk *bus_clk; + int irq; + struct cpumask irq_affinity_mask; + struct notifier_block cpu_hotplug_notifier; + int ceiling_irq; + struct msm_apm_ctrl_dev *apm; + int apm_threshold_volt; + int apm_crossover_volt; + int apm_adj_volt; + enum msm_apm_supply apm_high_supply; + enum msm_apm_supply apm_low_supply; + int base_volt; + u32 corner_switch_delay_time; + u32 cpr_clock_rate; + u32 sensor_time; + u32 loop_time; + u32 up_down_delay_time; + u32 idle_clocks; + u32 step_quot_init_min; + u32 step_quot_init_max; + int step_volt; + u32 down_error_step_limit; + u32 up_error_step_limit; + enum cpr3_count_mode count_mode; + u32 count_repeat; + u32 proc_clock_throttle; + bool cpr_allowed_hw; + bool cpr_allowed_sw; + bool supports_hw_closed_loop; + bool use_hw_closed_loop; + enum cpr_controller_type ctrl_type; + bool saw_use_unit_mV; + struct cpr3_corner aggr_corner; + bool cpr_enabled; + bool last_corner_was_closed_loop; + bool cpr_suspended; + struct dentry *debugfs; + + int aging_ref_volt; + unsigned int aging_vdd_mode; + unsigned int aging_complete_vdd_mode; + int aging_ref_adjust_volt; + bool aging_required; + bool aging_succeeded; + bool aging_failed; + struct cpr3_aging_sensor_info *aging_sensor; + int aging_sensor_count; + u32 cur_sensor_state; + u32 aging_possible_mask; + u32 aging_possible_val; + + u32 step_quot_fixed; + u32 initial_temp_band; + bool use_dynamic_step_quot; + bool allow_core_count_adj; + bool allow_temp_adj; + bool allow_boost; + int temp_band_count; + int *temp_points; + u32 temp_sensor_id_start; + u32 temp_sensor_id_end; + u32 voltage_settling_time; + enum cpr_setting cpr_global_setting; + struct cpr3_panic_regs_info *panic_regs_info; + struct notifier_block panic_notifier; +}; + +/* Used for rounding voltages to the closest physically available set point. */ +#define CPR3_ROUND(n, d) (DIV_ROUND_UP(n, d) * (d)) + +#define cpr3_err(cpr3_thread, message, ...) \ + pr_err("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) +#define cpr3_info(cpr3_thread, message, ...) \ + pr_info("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) +#define cpr3_debug(cpr3_thread, message, ...) \ + pr_debug("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) + +/* + * Offset subtracted from voltage corner values passed in from the regulator + * framework in order to get internal voltage corner values. This is needed + * since the regulator framework treats 0 as an error value at regulator + * registration time. + */ +#define CPR3_CORNER_OFFSET 1 + +#ifdef CONFIG_REGULATOR_CPR3 + +int cpr3_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl); +int cpr3_open_loop_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl); +int cpr3_regulator_unregister(struct cpr3_controller *ctrl); +int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl); +int cpr3_regulator_suspend(struct cpr3_controller *ctrl); +int cpr3_regulator_resume(struct cpr3_controller *ctrl); + +int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id, + u32 max_thread_id); +int cpr3_map_fuse_base(struct cpr3_controller *ctrl, + struct platform_device *pdev); +int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, + struct platform_device *pdev, u8 start, u8 end); +int cpr3_read_fuse_param(void __iomem *fuse_base_addr, + const struct cpr3_fuse_param *param, u64 *param_value); +int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse, + int fuse_len); +u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x); +int cpr3_parse_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out); +int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out); +int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out); +int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg); +int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname, + u32 *out_value, u32 value_min, u32 value_max); +int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname, + u32 *out_value, u32 value_min, u32 value_max); +int cpr3_parse_common_thread_data(struct cpr3_thread *thread); +int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl); +int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl); +int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg); +void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg); +int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg); +void cpr3_print_quots(struct cpr3_regulator *vreg); +int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt); +int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, + int *fuse_volt); +int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg, + int *fuse_volt); +int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg); +int cpr3_quot_adjustment(int ro_scale, int volt_adjust); +int cpr3_voltage_adjustment(int ro_scale, int quot_adjust); +int cpr3_parse_closed_loop_voltage_adjustments(struct cpr3_regulator *vreg, + u64 *ro_sel, int *volt_adjust, + int *volt_adjust_fuse, int *ro_scale); +int cpr4_parse_core_count_temp_voltage_adj(struct cpr3_regulator *vreg, + bool use_corner_band); +int cpr3_apm_init(struct cpr3_controller *ctrl); +int cpr3_mem_acc_init(struct cpr3_regulator *vreg); +void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg); +void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg); +int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, + int *fuse_volt_adjust); +int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, + bool is_cold); +int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp); +bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg); + +#else + +static inline int cpr3_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl) +{ + return -ENXIO; +} + +static inline int +cpr3_open_loop_regulator_register(struct platform_device *pdev, + struct cpr3_controller *ctrl); +{ + return -ENXIO; +} + +static inline int cpr3_regulator_unregister(struct cpr3_controller *ctrl) +{ + return -ENXIO; +} + +static inline int +cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl) +{ + return -ENXIO; +} + +static inline int cpr3_regulator_suspend(struct cpr3_controller *ctrl) +{ + return -ENXIO; +} + +static inline int cpr3_regulator_resume(struct cpr3_controller *ctrl) +{ + return -ENXIO; +} + +static inline int cpr3_get_thread_name(struct cpr3_thread *thread, + struct device_node *thread_node) +{ + return -EPERM; +} + +static inline int cpr3_allocate_threads(struct cpr3_controller *ctrl, + u32 min_thread_id, u32 max_thread_id) +{ + return -EPERM; +} + +static inline int cpr3_map_fuse_base(struct cpr3_controller *ctrl, + struct platform_device *pdev) +{ + return -ENXIO; +} + +static inline int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, + struct platform_device *pdev, u8 start, u8 end) +{ + return 0; +} + +static inline int cpr3_read_fuse_param(void __iomem *fuse_base_addr, + const struct cpr3_fuse_param *param, u64 *param_value) +{ + return -EPERM; +} + +static inline int cpr3_convert_open_loop_voltage_fuse(int ref_volt, + int step_volt, u32 fuse, int fuse_len) +{ + return -EPERM; +} + +static inline u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x) +{ + return 0; +} + +static inline int cpr3_parse_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out) +{ + return -EPERM; +} + +static inline int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out) +{ + return -EPERM; +} + +static inline int cpr3_parse_corner_band_array_property( + struct cpr3_regulator *vreg, const char *prop_name, + int tuple_size, u32 *out) +{ + return -EPERM; +} + +static inline int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg) +{ + return -EPERM; +} + +static inline int cpr3_parse_thread_u32(struct cpr3_thread *thread, + const char *propname, u32 *out_value, u32 value_min, + u32 value_max) +{ + return -EPERM; +} + +static inline int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, + const char *propname, u32 *out_value, u32 value_min, + u32 value_max) +{ + return -EPERM; +} + +static inline int cpr3_parse_common_thread_data(struct cpr3_thread *thread) +{ + return -EPERM; +} + +static inline int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl) +{ + return -EPERM; +} + +static inline int +cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl) +{ + return -EPERM; +} + +static inline int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg) +{ + return -EPERM; +} + +static inline void cpr3_open_loop_voltage_as_ceiling( + struct cpr3_regulator *vreg) +{ + return; +} + +static inline int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg) +{ + return -EPERM; +} + +static inline void cpr3_print_quots(struct cpr3_regulator *vreg) +{ + return; +} + +static inline int +cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt) +{ + return -EPERM; +} + +static inline int +cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, + int *fuse_volt) +{ + return -EPERM; +} + +static inline int cpr3_adjust_fused_open_loop_voltages( + struct cpr3_regulator *vreg, int *fuse_volt) +{ + return -EPERM; +} + +static inline int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg) +{ + return -EPERM; +} + +static inline int cpr3_quot_adjustment(int ro_scale, int volt_adjust) +{ + return 0; +} + +static inline int cpr3_voltage_adjustment(int ro_scale, int quot_adjust) +{ + return 0; +} + +static inline int cpr3_parse_closed_loop_voltage_adjustments( + struct cpr3_regulator *vreg, u64 *ro_sel, + int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) +{ + return 0; +} + +static inline int cpr4_parse_core_count_temp_voltage_adj( + struct cpr3_regulator *vreg, bool use_corner_band) +{ + return 0; +} + +static inline int cpr3_apm_init(struct cpr3_controller *ctrl) +{ + return 0; +} + +static inline int cpr3_mem_acc_init(struct cpr3_regulator *vreg) +{ + return 0; +} + +static inline void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg) +{ +} + +static inline void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg) +{ +} + +static inline int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, + int *fuse_volt_adjust) +{ + return 0; +} + +static inline int +cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, + bool is_cold) +{ + return 0; +} + +static inline bool +cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg) +{ + return false; +} + +static inline int +cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp) +{ + return 0; +} +#endif /* CONFIG_REGULATOR_CPR3 */ + +#endif /* __REGULATOR_CPR_REGULATOR_H__ */ diff --git a/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-util.c b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-util.c new file mode 100644 index 000000000..45493af71 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-util.c @@ -0,0 +1,2750 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file contains utility functions to be used by platform specific CPR3 + * regulator drivers. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "cpr3-regulator.h" + +#define BYTES_PER_FUSE_ROW 8 +#define MAX_FUSE_ROW_BIT 63 + +#define CPR3_CONSECUTIVE_UP_DOWN_MIN 0 +#define CPR3_CONSECUTIVE_UP_DOWN_MAX 15 +#define CPR3_UP_DOWN_THRESHOLD_MIN 0 +#define CPR3_UP_DOWN_THRESHOLD_MAX 31 +#define CPR3_STEP_QUOT_MIN 0 +#define CPR3_STEP_QUOT_MAX 63 +#define CPR3_IDLE_CLOCKS_MIN 0 +#define CPR3_IDLE_CLOCKS_MAX 31 + +/* This constant has units of uV/mV so 1000 corresponds to 100%. */ +#define CPR3_AGING_DERATE_UNITY 1000 + +/** + * cpr3_allocate_regulators() - allocate and initialize CPR3 regulators for a + * given thread based upon device tree data + * @thread: Pointer to the CPR3 thread + * + * This function allocates the thread->vreg array based upon the number of + * device tree regulator subnodes. It also initializes generic elements of each + * regulator struct such as name, of_node, and thread. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_allocate_regulators(struct cpr3_thread *thread) +{ + struct device_node *node; + int i, rc; + + thread->vreg_count = 0; + + for_each_available_child_of_node(thread->of_node, node) { + thread->vreg_count++; + } + + thread->vreg = devm_kcalloc(thread->ctrl->dev, thread->vreg_count, + sizeof(*thread->vreg), GFP_KERNEL); + if (!thread->vreg) + return -ENOMEM; + + i = 0; + for_each_available_child_of_node(thread->of_node, node) { + thread->vreg[i].of_node = node; + thread->vreg[i].thread = thread; + + rc = of_property_read_string(node, "regulator-name", + &thread->vreg[i].name); + if (rc) { + dev_err(thread->ctrl->dev, "could not find regulator name, rc=%d\n", + rc); + return rc; + } + + i++; + } + + return 0; +} + +/** + * cpr3_allocate_threads() - allocate and initialize CPR3 threads for a given + * controller based upon device tree data + * @ctrl: Pointer to the CPR3 controller + * @min_thread_id: Minimum allowed hardware thread ID for this controller + * @max_thread_id: Maximum allowed hardware thread ID for this controller + * + * This function allocates the ctrl->thread array based upon the number of + * device tree thread subnodes. It also initializes generic elements of each + * thread struct such as thread_id, of_node, ctrl, and vreg array. + * + * Return: 0 on success, errno on failure + */ +int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id, + u32 max_thread_id) +{ + struct device *dev = ctrl->dev; + struct device_node *thread_node; + int i, j, rc; + + ctrl->thread_count = 0; + + for_each_available_child_of_node(dev->of_node, thread_node) { + ctrl->thread_count++; + } + + ctrl->thread = devm_kcalloc(dev, ctrl->thread_count, + sizeof(*ctrl->thread), GFP_KERNEL); + if (!ctrl->thread) + return -ENOMEM; + + i = 0; + for_each_available_child_of_node(dev->of_node, thread_node) { + ctrl->thread[i].of_node = thread_node; + ctrl->thread[i].ctrl = ctrl; + + rc = of_property_read_u32(thread_node, "qcom,cpr-thread-id", + &ctrl->thread[i].thread_id); + if (rc) { + dev_err(dev, "could not read DT property qcom,cpr-thread-id, rc=%d\n", + rc); + return rc; + } + + if (ctrl->thread[i].thread_id < min_thread_id || + ctrl->thread[i].thread_id > max_thread_id) { + dev_err(dev, "invalid thread id = %u; not within [%u, %u]\n", + ctrl->thread[i].thread_id, min_thread_id, + max_thread_id); + return -EINVAL; + } + + /* Verify that the thread ID is unique for all child nodes. */ + for (j = 0; j < i; j++) { + if (ctrl->thread[j].thread_id + == ctrl->thread[i].thread_id) { + dev_err(dev, "duplicate thread id = %u found\n", + ctrl->thread[i].thread_id); + return -EINVAL; + } + } + + rc = cpr3_allocate_regulators(&ctrl->thread[i]); + if (rc) + return rc; + + i++; + } + + return 0; +} + +/** + * cpr3_map_fuse_base() - ioremap the base address of the fuse region + * @ctrl: Pointer to the CPR3 controller + * @pdev: Platform device pointer for the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_map_fuse_base(struct cpr3_controller *ctrl, + struct platform_device *pdev) +{ + struct resource *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fuse_base"); + if (!res || !res->start) { + dev_err(&pdev->dev, "fuse base address is missing\n"); + return -ENXIO; + } + + ctrl->fuse_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + + return 0; +} + +/** + * cpr3_read_tcsr_setting - reads the CPR setting bits from TCSR register + * @ctrl: Pointer to the CPR3 controller + * @pdev: Platform device pointer for the CPR3 controller + * @start: start bit in TCSR register + * @end: end bit in TCSR register + * + * Return: 0 on success, errno on failure + */ +int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, + struct platform_device *pdev, u8 start, u8 end) +{ + struct resource *res; + void __iomem *tcsr_reg; + u32 val; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "cpr_tcsr_reg"); + if (!res || !res->start) + return 0; + + tcsr_reg = ioremap(res->start, resource_size(res)); + if (!tcsr_reg) { + dev_err(&pdev->dev, "tcsr ioremap failed\n"); + return 0; + } + + val = readl_relaxed(tcsr_reg); + val &= GENMASK(end, start); + val >>= start; + + switch (val) { + case 1: + ctrl->cpr_global_setting = CPR_DISABLED; + break; + case 2: + ctrl->cpr_global_setting = CPR_OPEN_LOOP_EN; + break; + case 3: + ctrl->cpr_global_setting = CPR_CLOSED_LOOP_EN; + break; + default: + ctrl->cpr_global_setting = CPR_DEFAULT; + } + + iounmap(tcsr_reg); + + return 0; +} + +/** + * cpr3_read_fuse_param() - reads a CPR3 fuse parameter out of eFuses + * @fuse_base_addr: Virtual memory address of the eFuse base address + * @param: Null terminated array of fuse param segments to read + * from + * @param_value: Output with value read from the eFuses + * + * This function reads from each of the parameter segments listed in the param + * array and concatenates their values together. Reading stops when an element + * is reached which has all 0 struct values. The total number of bits specified + * for the fuse parameter across all segments must be less than or equal to 64. + * + * Return: 0 on success, errno on failure + */ +int cpr3_read_fuse_param(void __iomem *fuse_base_addr, + const struct cpr3_fuse_param *param, u64 *param_value) +{ + u64 fuse_val, val; + int bits; + int bits_total = 0; + + *param_value = 0; + + while (param->row || param->bit_start || param->bit_end) { + if (param->bit_start > param->bit_end + || param->bit_end > MAX_FUSE_ROW_BIT) { + pr_err("Invalid fuse parameter segment: row=%u, start=%u, end=%u\n", + param->row, param->bit_start, param->bit_end); + return -EINVAL; + } + + bits = param->bit_end - param->bit_start + 1; + if (bits_total + bits > 64) { + pr_err("Invalid fuse parameter segments; total bits = %d\n", + bits_total + bits); + return -EINVAL; + } + + fuse_val = readq_relaxed(fuse_base_addr + + param->row * BYTES_PER_FUSE_ROW); + val = (fuse_val >> param->bit_start) & ((1ULL << bits) - 1); + *param_value |= val << bits_total; + bits_total += bits; + + param++; + } + + return 0; +} + +/** + * cpr3_convert_open_loop_voltage_fuse() - converts an open loop voltage fuse + * value into an absolute voltage with units of microvolts + * @ref_volt: Reference voltage in microvolts + * @step_volt: The step size in microvolts of the fuse LSB + * @fuse: Open loop voltage fuse value + * @fuse_len: The bit length of the fuse value + * + * The MSB of the fuse parameter corresponds to a sign bit. If it is set, then + * the lower bits correspond to the number of steps to go down from the + * reference voltage. If it is not set, then the lower bits correspond to the + * number of steps to go up from the reference voltage. + */ +int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse, + int fuse_len) +{ + int sign, steps; + + sign = (fuse & (1 << (fuse_len - 1))) ? -1 : 1; + steps = fuse & ((1 << (fuse_len - 1)) - 1); + + return ref_volt + sign * steps * step_volt; +} + +/** + * cpr3_interpolate() - performs linear interpolation + * @x1 Lower known x value + * @y1 Lower known y value + * @x2 Upper known x value + * @y2 Upper known y value + * @x Intermediate x value + * + * Returns y where (x, y) falls on the line between (x1, y1) and (x2, y2). + * It is required that x1 < x2, y1 <= y2, and x1 <= x <= x2. If these + * conditions are not met, then y2 will be returned. + */ +u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x) +{ + u64 temp; + + if (x1 >= x2 || y1 > y2 || x1 > x || x > x2) + return y2; + + temp = (x2 - x) * (y2 - y1); + do_div(temp, (u32)(x2 - x1)); + + return y2 - temp; +} + +/** + * cpr3_parse_array_property() - fill an array from a portion of the values + * specified for a device tree property + * @vreg: Pointer to the CPR3 regulator + * @prop_name: The name of the device tree property to read from + * @tuple_size: The number of elements in each tuple + * @out: Output data array which must be of size tuple_size + * + * cpr3_parse_common_corner_data() must be called for vreg before this function + * is called so that fuse combo and speed bin size elements are initialized. + * + * Three formats are supported for the device tree property: + * 1. Length == tuple_size + * (reading begins at index 0) + * 2. Length == tuple_size * vreg->fuse_combos_supported + * (reading begins at index tuple_size * vreg->fuse_combo) + * 3. Length == tuple_size * vreg->speed_bins_supported + * (reading begins at index tuple_size * vreg->speed_bin_fuse) + * + * All other property lengths are treated as errors. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out) +{ + struct device_node *node = vreg->of_node; + int len = 0; + int i, offset, rc; + + if (!of_find_property(node, prop_name, &len)) { + cpr3_err(vreg, "property %s is missing\n", prop_name); + return -EINVAL; + } + + if (len == tuple_size * sizeof(u32)) { + offset = 0; + } else if (len == tuple_size * vreg->fuse_combos_supported + * sizeof(u32)) { + offset = tuple_size * vreg->fuse_combo; + } else if (vreg->speed_bins_supported > 0 && + len == tuple_size * vreg->speed_bins_supported * sizeof(u32)) { + offset = tuple_size * vreg->speed_bin_fuse; + } else { + if (vreg->speed_bins_supported > 0) + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", + prop_name, len, + tuple_size * sizeof(u32), + tuple_size * vreg->speed_bins_supported + * sizeof(u32), + tuple_size * vreg->fuse_combos_supported + * sizeof(u32)); + else + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", + prop_name, len, + tuple_size * sizeof(u32), + tuple_size * vreg->fuse_combos_supported + * sizeof(u32)); + return -EINVAL; + } + + for (i = 0; i < tuple_size; i++) { + rc = of_property_read_u32_index(node, prop_name, offset + i, + &out[i]); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_name, rc); + return rc; + } + } + + return 0; +} + +/** + * cpr3_parse_corner_array_property() - fill a per-corner array from a portion + * of the values specified for a device tree property + * @vreg: Pointer to the CPR3 regulator + * @prop_name: The name of the device tree property to read from + * @tuple_size: The number of elements in each per-corner tuple + * @out: Output data array which must be of size: + * tuple_size * vreg->corner_count + * + * cpr3_parse_common_corner_data() must be called for vreg before this function + * is called so that fuse combo and speed bin size elements are initialized. + * + * Three formats are supported for the device tree property: + * 1. Length == tuple_size * vreg->corner_count + * (reading begins at index 0) + * 2. Length == tuple_size * vreg->fuse_combo_corner_sum + * (reading begins at index tuple_size * vreg->fuse_combo_offset) + * 3. Length == tuple_size * vreg->speed_bin_corner_sum + * (reading begins at index tuple_size * vreg->speed_bin_offset) + * + * All other property lengths are treated as errors. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out) +{ + struct device_node *node = vreg->of_node; + int len = 0; + int i, offset, rc; + + if (!of_find_property(node, prop_name, &len)) { + cpr3_err(vreg, "property %s is missing\n", prop_name); + return -EINVAL; + } + + if (len == tuple_size * vreg->corner_count * sizeof(u32)) { + offset = 0; + } else if (len == tuple_size * vreg->fuse_combo_corner_sum + * sizeof(u32)) { + offset = tuple_size * vreg->fuse_combo_offset; + } else if (vreg->speed_bin_corner_sum > 0 && + len == tuple_size * vreg->speed_bin_corner_sum * sizeof(u32)) { + offset = tuple_size * vreg->speed_bin_offset; + } else { + if (vreg->speed_bin_corner_sum > 0) + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", + prop_name, len, + tuple_size * vreg->corner_count * sizeof(u32), + tuple_size * vreg->speed_bin_corner_sum + * sizeof(u32), + tuple_size * vreg->fuse_combo_corner_sum + * sizeof(u32)); + else + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", + prop_name, len, + tuple_size * vreg->corner_count * sizeof(u32), + tuple_size * vreg->fuse_combo_corner_sum + * sizeof(u32)); + return -EINVAL; + } + + for (i = 0; i < tuple_size * vreg->corner_count; i++) { + rc = of_property_read_u32_index(node, prop_name, offset + i, + &out[i]); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_name, rc); + return rc; + } + } + + return 0; +} + +/** + * cpr3_parse_corner_band_array_property() - fill a per-corner band array + * from a portion of the values specified for a device tree + * property + * @vreg: Pointer to the CPR3 regulator + * @prop_name: The name of the device tree property to read from + * @tuple_size: The number of elements in each per-corner band tuple + * @out: Output data array which must be of size: + * tuple_size * vreg->corner_band_count + * + * cpr3_parse_common_corner_data() must be called for vreg before this function + * is called so that fuse combo and speed bin size elements are initialized. + * In addition, corner band fuse combo and speed bin sum and offset elements + * must be initialized prior to executing this function. + * + * Three formats are supported for the device tree property: + * 1. Length == tuple_size * vreg->corner_band_count + * (reading begins at index 0) + * 2. Length == tuple_size * vreg->fuse_combo_corner_band_sum + * (reading begins at index tuple_size * + * vreg->fuse_combo_corner_band_offset) + * 3. Length == tuple_size * vreg->speed_bin_corner_band_sum + * (reading begins at index tuple_size * + * vreg->speed_bin_corner_band_offset) + * + * All other property lengths are treated as errors. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg, + const char *prop_name, int tuple_size, u32 *out) +{ + struct device_node *node = vreg->of_node; + int len = 0; + int i, offset, rc; + + if (!of_find_property(node, prop_name, &len)) { + cpr3_err(vreg, "property %s is missing\n", prop_name); + return -EINVAL; + } + + if (len == tuple_size * vreg->corner_band_count * sizeof(u32)) { + offset = 0; + } else if (len == tuple_size * vreg->fuse_combo_corner_band_sum + * sizeof(u32)) { + offset = tuple_size * vreg->fuse_combo_corner_band_offset; + } else if (vreg->speed_bin_corner_band_sum > 0 && + len == tuple_size * vreg->speed_bin_corner_band_sum * + sizeof(u32)) { + offset = tuple_size * vreg->speed_bin_corner_band_offset; + } else { + if (vreg->speed_bin_corner_band_sum > 0) + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", + prop_name, len, + tuple_size * vreg->corner_band_count * + sizeof(u32), + tuple_size * vreg->speed_bin_corner_band_sum + * sizeof(u32), + tuple_size * vreg->fuse_combo_corner_band_sum + * sizeof(u32)); + else + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", + prop_name, len, + tuple_size * vreg->corner_band_count * + sizeof(u32), + tuple_size * vreg->fuse_combo_corner_band_sum + * sizeof(u32)); + return -EINVAL; + } + + for (i = 0; i < tuple_size * vreg->corner_band_count; i++) { + rc = of_property_read_u32_index(node, prop_name, offset + i, + &out[i]); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_name, rc); + return rc; + } + } + + return 0; +} + +/** + * cpr3_parse_common_corner_data() - parse common CPR3 properties relating to + * the corners supported by a CPR3 regulator from device tree + * @vreg: Pointer to the CPR3 regulator + * + * This function reads, validates, and utilizes the following device tree + * properties: qcom,cpr-fuse-corners, qcom,cpr-fuse-combos, qcom,cpr-speed-bins, + * qcom,cpr-speed-bin-corners, qcom,cpr-corners, qcom,cpr-voltage-ceiling, + * qcom,cpr-voltage-floor, qcom,corner-frequencies, + * and qcom,cpr-corner-fmax-map. + * + * It initializes these CPR3 regulator elements: corner, corner_count, + * fuse_combos_supported, fuse_corner_map, and speed_bins_supported. It + * initializes these elements for each corner: ceiling_volt, floor_volt, + * proc_freq, and cpr_fuse_corner. + * + * It requires that the following CPR3 regulator elements be initialized before + * being called: fuse_corner_count, fuse_combo, and speed_bin_fuse. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg) +{ + struct device_node *node = vreg->of_node; + struct cpr3_controller *ctrl = vreg->thread->ctrl; + u32 max_fuse_combos, fuse_corners, aging_allowed = 0; + u32 max_speed_bins = 0; + u32 *combo_corners; + u32 *speed_bin_corners; + u32 *temp; + int i, j, rc; + + rc = of_property_read_u32(node, "qcom,cpr-fuse-corners", &fuse_corners); + if (rc) { + cpr3_err(vreg, "error reading property qcom,cpr-fuse-corners, rc=%d\n", + rc); + return rc; + } + + if (vreg->fuse_corner_count != fuse_corners) { + cpr3_err(vreg, "device tree config supports %d fuse corners but the hardware has %d fuse corners\n", + fuse_corners, vreg->fuse_corner_count); + return -EINVAL; + } + + rc = of_property_read_u32(node, "qcom,cpr-fuse-combos", + &max_fuse_combos); + if (rc) { + cpr3_err(vreg, "error reading property qcom,cpr-fuse-combos, rc=%d\n", + rc); + return rc; + } + + /* + * Sanity check against arbitrarily large value to avoid excessive + * memory allocation. + */ + if (max_fuse_combos > 100 || max_fuse_combos == 0) { + cpr3_err(vreg, "qcom,cpr-fuse-combos is invalid: %u\n", + max_fuse_combos); + return -EINVAL; + } + + if (vreg->fuse_combo >= max_fuse_combos) { + cpr3_err(vreg, "device tree config supports fuse combos 0-%u but the hardware has combo %d\n", + max_fuse_combos - 1, vreg->fuse_combo); + BUG_ON(1); + return -EINVAL; + } + + vreg->fuse_combos_supported = max_fuse_combos; + + of_property_read_u32(node, "qcom,cpr-speed-bins", &max_speed_bins); + + /* + * Sanity check against arbitrarily large value to avoid excessive + * memory allocation. + */ + if (max_speed_bins > 100) { + cpr3_err(vreg, "qcom,cpr-speed-bins is invalid: %u\n", + max_speed_bins); + return -EINVAL; + } + + if (max_speed_bins && vreg->speed_bin_fuse >= max_speed_bins) { + cpr3_err(vreg, "device tree config supports speed bins 0-%u but the hardware has speed bin %d\n", + max_speed_bins - 1, vreg->speed_bin_fuse); + BUG(); + return -EINVAL; + } + + vreg->speed_bins_supported = max_speed_bins; + + combo_corners = kcalloc(vreg->fuse_combos_supported, + sizeof(*combo_corners), GFP_KERNEL); + if (!combo_corners) + return -ENOMEM; + + rc = of_property_read_u32_array(node, "qcom,cpr-corners", combo_corners, + vreg->fuse_combos_supported); + if (rc == -EOVERFLOW) { + /* Single value case */ + rc = of_property_read_u32(node, "qcom,cpr-corners", + combo_corners); + for (i = 1; i < vreg->fuse_combos_supported; i++) + combo_corners[i] = combo_corners[0]; + } + if (rc) { + cpr3_err(vreg, "error reading property qcom,cpr-corners, rc=%d\n", + rc); + kfree(combo_corners); + return rc; + } + + vreg->fuse_combo_offset = 0; + vreg->fuse_combo_corner_sum = 0; + for (i = 0; i < vreg->fuse_combos_supported; i++) { + vreg->fuse_combo_corner_sum += combo_corners[i]; + if (i < vreg->fuse_combo) + vreg->fuse_combo_offset += combo_corners[i]; + } + + vreg->corner_count = combo_corners[vreg->fuse_combo]; + + kfree(combo_corners); + + vreg->speed_bin_offset = 0; + vreg->speed_bin_corner_sum = 0; + if (vreg->speed_bins_supported > 0) { + speed_bin_corners = kcalloc(vreg->speed_bins_supported, + sizeof(*speed_bin_corners), GFP_KERNEL); + if (!speed_bin_corners) + return -ENOMEM; + + rc = of_property_read_u32_array(node, + "qcom,cpr-speed-bin-corners", speed_bin_corners, + vreg->speed_bins_supported); + if (rc) { + cpr3_err(vreg, "error reading property qcom,cpr-speed-bin-corners, rc=%d\n", + rc); + kfree(speed_bin_corners); + return rc; + } + + for (i = 0; i < vreg->speed_bins_supported; i++) { + vreg->speed_bin_corner_sum += speed_bin_corners[i]; + if (i < vreg->speed_bin_fuse) + vreg->speed_bin_offset += speed_bin_corners[i]; + } + + if (speed_bin_corners[vreg->speed_bin_fuse] + != vreg->corner_count) { + cpr3_err(vreg, "qcom,cpr-corners and qcom,cpr-speed-bin-corners conflict on number of corners: %d vs %u\n", + vreg->corner_count, + speed_bin_corners[vreg->speed_bin_fuse]); + kfree(speed_bin_corners); + return -EINVAL; + } + + kfree(speed_bin_corners); + } + + vreg->corner = devm_kcalloc(ctrl->dev, vreg->corner_count, + sizeof(*vreg->corner), GFP_KERNEL); + temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL); + if (!vreg->corner || !temp) + return -ENOMEM; + + rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-ceiling", + 1, temp); + if (rc) + goto free_temp; + for (i = 0; i < vreg->corner_count; i++) { + vreg->corner[i].ceiling_volt + = CPR3_ROUND(temp[i], ctrl->step_volt); + vreg->corner[i].abs_ceiling_volt = vreg->corner[i].ceiling_volt; + } + + rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-floor", + 1, temp); + if (rc) + goto free_temp; + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].floor_volt + = CPR3_ROUND(temp[i], ctrl->step_volt); + + /* Validate ceiling and floor values */ + for (i = 0; i < vreg->corner_count; i++) { + if (vreg->corner[i].floor_volt + > vreg->corner[i].ceiling_volt) { + cpr3_err(vreg, "CPR floor[%d]=%d > ceiling[%d]=%d uV\n", + i, vreg->corner[i].floor_volt, + i, vreg->corner[i].ceiling_volt); + rc = -EINVAL; + goto free_temp; + } + } + + /* Load optional system-supply voltages */ + if (of_find_property(vreg->of_node, "qcom,system-voltage", NULL)) { + rc = cpr3_parse_corner_array_property(vreg, + "qcom,system-voltage", 1, temp); + if (rc) + goto free_temp; + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].system_volt = temp[i]; + } + + rc = cpr3_parse_corner_array_property(vreg, "qcom,corner-frequencies", + 1, temp); + if (rc) + goto free_temp; + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].proc_freq = temp[i]; + + /* Validate frequencies */ + for (i = 1; i < vreg->corner_count; i++) { + if (vreg->corner[i].proc_freq + < vreg->corner[i - 1].proc_freq) { + cpr3_err(vreg, "invalid frequency: freq[%d]=%u < freq[%d]=%u\n", + i, vreg->corner[i].proc_freq, i - 1, + vreg->corner[i - 1].proc_freq); + rc = -EINVAL; + goto free_temp; + } + } + + vreg->fuse_corner_map = devm_kcalloc(ctrl->dev, vreg->fuse_corner_count, + sizeof(*vreg->fuse_corner_map), GFP_KERNEL); + if (!vreg->fuse_corner_map) { + rc = -ENOMEM; + goto free_temp; + } + + rc = cpr3_parse_array_property(vreg, "qcom,cpr-corner-fmax-map", + vreg->fuse_corner_count, temp); + if (rc) + goto free_temp; + for (i = 0; i < vreg->fuse_corner_count; i++) { + vreg->fuse_corner_map[i] = temp[i] - CPR3_CORNER_OFFSET; + if (temp[i] < CPR3_CORNER_OFFSET + || temp[i] > vreg->corner_count + CPR3_CORNER_OFFSET) { + cpr3_err(vreg, "invalid corner value specified in qcom,cpr-corner-fmax-map: %u\n", + temp[i]); + rc = -EINVAL; + goto free_temp; + } else if (i > 0 && temp[i - 1] >= temp[i]) { + cpr3_err(vreg, "invalid corner %u less than or equal to previous corner %u\n", + temp[i], temp[i - 1]); + rc = -EINVAL; + goto free_temp; + } + } + if (temp[vreg->fuse_corner_count - 1] != vreg->corner_count) + cpr3_debug(vreg, "Note: highest Fmax corner %u in qcom,cpr-corner-fmax-map does not match highest supported corner %d\n", + temp[vreg->fuse_corner_count - 1], + vreg->corner_count); + + for (i = 0; i < vreg->corner_count; i++) { + for (j = 0; j < vreg->fuse_corner_count; j++) { + if (i + CPR3_CORNER_OFFSET <= temp[j]) { + vreg->corner[i].cpr_fuse_corner = j; + break; + } + } + if (j == vreg->fuse_corner_count) { + /* + * Handle the case where the highest fuse corner maps + * to a corner below the highest corner. + */ + vreg->corner[i].cpr_fuse_corner + = vreg->fuse_corner_count - 1; + } + } + + if (of_find_property(vreg->of_node, + "qcom,allow-aging-voltage-adjustment", NULL)) { + rc = cpr3_parse_array_property(vreg, + "qcom,allow-aging-voltage-adjustment", + 1, &aging_allowed); + if (rc) + goto free_temp; + + vreg->aging_allowed = aging_allowed; + } + + if (of_find_property(vreg->of_node, + "qcom,allow-aging-open-loop-voltage-adjustment", NULL)) { + rc = cpr3_parse_array_property(vreg, + "qcom,allow-aging-open-loop-voltage-adjustment", + 1, &aging_allowed); + if (rc) + goto free_temp; + + vreg->aging_allow_open_loop_adj = aging_allowed; + } + + if (vreg->aging_allowed) { + if (ctrl->aging_ref_volt <= 0) { + cpr3_err(ctrl, "qcom,cpr-aging-ref-voltage must be specified\n"); + rc = -EINVAL; + goto free_temp; + } + + rc = cpr3_parse_array_property(vreg, + "qcom,cpr-aging-max-voltage-adjustment", + 1, &vreg->aging_max_adjust_volt); + if (rc) + goto free_temp; + + rc = cpr3_parse_array_property(vreg, + "qcom,cpr-aging-ref-corner", 1, &vreg->aging_corner); + if (rc) { + goto free_temp; + } else if (vreg->aging_corner < CPR3_CORNER_OFFSET + || vreg->aging_corner > vreg->corner_count - 1 + + CPR3_CORNER_OFFSET) { + cpr3_err(vreg, "aging reference corner=%d not in range [%d, %d]\n", + vreg->aging_corner, CPR3_CORNER_OFFSET, + vreg->corner_count - 1 + CPR3_CORNER_OFFSET); + rc = -EINVAL; + goto free_temp; + } + vreg->aging_corner -= CPR3_CORNER_OFFSET; + + if (of_find_property(vreg->of_node, "qcom,cpr-aging-derate", + NULL)) { + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-aging-derate", 1, temp); + if (rc) + goto free_temp; + + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].aging_derate = temp[i]; + } else { + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].aging_derate + = CPR3_AGING_DERATE_UNITY; + } + } + +free_temp: + kfree(temp); + return rc; +} + +/** + * cpr3_parse_thread_u32() - parse the specified property from the CPR3 thread's + * device tree node and verify that it is within the allowed limits + * @thread: Pointer to the CPR3 thread + * @propname: The name of the device tree property to read + * @out_value: The output pointer to fill with the value read + * @value_min: The minimum allowed property value + * @value_max: The maximum allowed property value + * + * This function prints a verbose error message if the property is missing or + * has a value which is not within the specified range. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname, + u32 *out_value, u32 value_min, u32 value_max) +{ + int rc; + + rc = of_property_read_u32(thread->of_node, propname, out_value); + if (rc) { + cpr3_err(thread->ctrl, "thread %u error reading property %s, rc=%d\n", + thread->thread_id, propname, rc); + return rc; + } + + if (*out_value < value_min || *out_value > value_max) { + cpr3_err(thread->ctrl, "thread %u %s=%u is invalid; allowed range: [%u, %u]\n", + thread->thread_id, propname, *out_value, value_min, + value_max); + return -EINVAL; + } + + return 0; +} + +/** + * cpr3_parse_ctrl_u32() - parse the specified property from the CPR3 + * controller's device tree node and verify that it is within the + * allowed limits + * @ctrl: Pointer to the CPR3 controller + * @propname: The name of the device tree property to read + * @out_value: The output pointer to fill with the value read + * @value_min: The minimum allowed property value + * @value_max: The maximum allowed property value + * + * This function prints a verbose error message if the property is missing or + * has a value which is not within the specified range. + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname, + u32 *out_value, u32 value_min, u32 value_max) +{ + int rc; + + rc = of_property_read_u32(ctrl->dev->of_node, propname, out_value); + if (rc) { + cpr3_err(ctrl, "error reading property %s, rc=%d\n", + propname, rc); + return rc; + } + + if (*out_value < value_min || *out_value > value_max) { + cpr3_err(ctrl, "%s=%u is invalid; allowed range: [%u, %u]\n", + propname, *out_value, value_min, value_max); + return -EINVAL; + } + + return 0; +} + +/** + * cpr3_parse_common_thread_data() - parse common CPR3 thread properties from + * device tree + * @thread: Pointer to the CPR3 thread + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_common_thread_data(struct cpr3_thread *thread) +{ + int rc; + + rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-up", + &thread->consecutive_up, CPR3_CONSECUTIVE_UP_DOWN_MIN, + CPR3_CONSECUTIVE_UP_DOWN_MAX); + if (rc) + return rc; + + rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-down", + &thread->consecutive_down, CPR3_CONSECUTIVE_UP_DOWN_MIN, + CPR3_CONSECUTIVE_UP_DOWN_MAX); + if (rc) + return rc; + + rc = cpr3_parse_thread_u32(thread, "qcom,cpr-up-threshold", + &thread->up_threshold, CPR3_UP_DOWN_THRESHOLD_MIN, + CPR3_UP_DOWN_THRESHOLD_MAX); + if (rc) + return rc; + + rc = cpr3_parse_thread_u32(thread, "qcom,cpr-down-threshold", + &thread->down_threshold, CPR3_UP_DOWN_THRESHOLD_MIN, + CPR3_UP_DOWN_THRESHOLD_MAX); + if (rc) + return rc; + + return rc; +} + +/** + * cpr3_parse_irq_affinity() - parse CPR IRQ affinity information + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr3_parse_irq_affinity(struct cpr3_controller *ctrl) +{ + struct device_node *cpu_node; + int i, cpu; + int len = 0; + + if (!of_find_property(ctrl->dev->of_node, "qcom,cpr-interrupt-affinity", + &len)) { + /* No IRQ affinity required */ + return 0; + } + + len /= sizeof(u32); + + for (i = 0; i < len; i++) { + cpu_node = of_parse_phandle(ctrl->dev->of_node, + "qcom,cpr-interrupt-affinity", i); + if (!cpu_node) { + cpr3_err(ctrl, "could not find CPU node %d\n", i); + return -EINVAL; + } + + for_each_possible_cpu(cpu) { + if (of_get_cpu_node(cpu, NULL) == cpu_node) { + cpumask_set_cpu(cpu, &ctrl->irq_affinity_mask); + break; + } + } + of_node_put(cpu_node); + } + + return 0; +} + +static int cpr3_panic_notifier_init(struct cpr3_controller *ctrl) +{ + struct device_node *node = ctrl->dev->of_node; + struct cpr3_panic_regs_info *panic_regs_info; + struct cpr3_reg_info *regs; + int i, reg_count, len, rc = 0; + + if (!of_find_property(node, "qcom,cpr-panic-reg-addr-list", &len)) { + /* panic register address list not specified */ + return rc; + } + + reg_count = len / sizeof(u32); + if (!reg_count) { + cpr3_err(ctrl, "qcom,cpr-panic-reg-addr-list has invalid len = %d\n", + len); + return -EINVAL; + } + + if (!of_find_property(node, "qcom,cpr-panic-reg-name-list", NULL)) { + cpr3_err(ctrl, "property qcom,cpr-panic-reg-name-list not specified\n"); + return -EINVAL; + } + + len = of_property_count_strings(node, "qcom,cpr-panic-reg-name-list"); + if (reg_count != len) { + cpr3_err(ctrl, "qcom,cpr-panic-reg-name-list should have %d strings\n", + reg_count); + return -EINVAL; + } + + panic_regs_info = devm_kzalloc(ctrl->dev, sizeof(*panic_regs_info), + GFP_KERNEL); + if (!panic_regs_info) + return -ENOMEM; + + regs = devm_kcalloc(ctrl->dev, reg_count, sizeof(*regs), GFP_KERNEL); + if (!regs) + return -ENOMEM; + + for (i = 0; i < reg_count; i++) { + rc = of_property_read_string_index(node, + "qcom,cpr-panic-reg-name-list", i, + &(regs[i].name)); + if (rc) { + cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-name-list, rc=%d\n", + rc); + return rc; + } + + rc = of_property_read_u32_index(node, + "qcom,cpr-panic-reg-addr-list", i, + &(regs[i].addr)); + if (rc) { + cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-addr-list, rc=%d\n", + rc); + return rc; + } + regs[i].virt_addr = devm_ioremap(ctrl->dev, regs[i].addr, 0x4); + if (!regs[i].virt_addr) { + pr_err("Unable to map panic register addr 0x%08x\n", + regs[i].addr); + return -EINVAL; + } + regs[i].value = 0xFFFFFFFF; + } + + panic_regs_info->reg_count = reg_count; + panic_regs_info->regs = regs; + ctrl->panic_regs_info = panic_regs_info; + + return rc; +} + +/** + * cpr3_parse_common_ctrl_data() - parse common CPR3 controller properties from + * device tree + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl) +{ + int rc; + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-sensor-time", + &ctrl->sensor_time, 0, UINT_MAX); + if (rc) + return rc; + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-loop-time", + &ctrl->loop_time, 0, UINT_MAX); + if (rc) + return rc; + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-idle-cycles", + &ctrl->idle_clocks, CPR3_IDLE_CLOCKS_MIN, + CPR3_IDLE_CLOCKS_MAX); + if (rc) + return rc; + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-min", + &ctrl->step_quot_init_min, CPR3_STEP_QUOT_MIN, + CPR3_STEP_QUOT_MAX); + if (rc) + return rc; + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-max", + &ctrl->step_quot_init_max, CPR3_STEP_QUOT_MIN, + CPR3_STEP_QUOT_MAX); + if (rc) + return rc; + + rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step", + &ctrl->step_volt); + if (rc) { + cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n", + rc); + return rc; + } + if (ctrl->step_volt <= 0) { + cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n", + ctrl->step_volt); + return -EINVAL; + } + + rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-count-mode", + &ctrl->count_mode, CPR3_COUNT_MODE_ALL_AT_ONCE_MIN, + CPR3_COUNT_MODE_STAGGERED); + if (rc) + return rc; + + /* Count repeat is optional */ + ctrl->count_repeat = 0; + of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-count-repeat", + &ctrl->count_repeat); + + ctrl->cpr_allowed_sw = + of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-enable") || + ctrl->cpr_global_setting == CPR_CLOSED_LOOP_EN; + + rc = cpr3_parse_irq_affinity(ctrl); + if (rc) + return rc; + + /* Aging reference voltage is optional */ + ctrl->aging_ref_volt = 0; + of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-aging-ref-voltage", + &ctrl->aging_ref_volt); + + /* Aging possible bitmask is optional */ + ctrl->aging_possible_mask = 0; + of_property_read_u32(ctrl->dev->of_node, + "qcom,cpr-aging-allowed-reg-mask", + &ctrl->aging_possible_mask); + + if (ctrl->aging_possible_mask) { + /* + * Aging possible register value required if bitmask is + * specified + */ + rc = cpr3_parse_ctrl_u32(ctrl, + "qcom,cpr-aging-allowed-reg-value", + &ctrl->aging_possible_val, 0, UINT_MAX); + if (rc) + return rc; + } + + if (of_find_property(ctrl->dev->of_node, "clock-names", NULL)) { + ctrl->core_clk = devm_clk_get(ctrl->dev, "core_clk"); + if (IS_ERR(ctrl->core_clk)) { + rc = PTR_ERR(ctrl->core_clk); + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable request core clock, rc=%d\n", + rc); + return rc; + } + } + + rc = cpr3_panic_notifier_init(ctrl); + if (rc) + return rc; + + if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) { + ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd"); + if (IS_ERR(ctrl->vdd_regulator)) { + rc = PTR_ERR(ctrl->vdd_regulator); + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n", + rc); + return rc; + } + } else { + cpr3_err(ctrl, "vdd supply is not defined\n"); + return -ENODEV; + } + + ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev, + "system"); + if (IS_ERR(ctrl->system_regulator)) { + rc = PTR_ERR(ctrl->system_regulator); + if (rc != -EPROBE_DEFER) { + rc = 0; + ctrl->system_regulator = NULL; + } else { + return rc; + } + } + + ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev, + "mem-acc"); + if (IS_ERR(ctrl->mem_acc_regulator)) { + rc = PTR_ERR(ctrl->mem_acc_regulator); + if (rc != -EPROBE_DEFER) { + rc = 0; + ctrl->mem_acc_regulator = NULL; + } else { + return rc; + } + } + + return rc; +} + +/** + * cpr3_parse_open_loop_common_ctrl_data() - parse common open loop CPR3 + * controller properties from device tree + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl) +{ + int rc; + + rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step", + &ctrl->step_volt); + if (rc) { + cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n", + rc); + return rc; + } + + if (ctrl->step_volt <= 0) { + cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n", + ctrl->step_volt); + return -EINVAL; + } + + if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) { + ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd"); + if (IS_ERR(ctrl->vdd_regulator)) { + rc = PTR_ERR(ctrl->vdd_regulator); + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n", + rc); + return rc; + } + } else { + cpr3_err(ctrl, "vdd supply is not defined\n"); + return -ENODEV; + } + + ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev, + "system"); + if (IS_ERR(ctrl->system_regulator)) { + rc = PTR_ERR(ctrl->system_regulator); + if (rc != -EPROBE_DEFER) { + rc = 0; + ctrl->system_regulator = NULL; + } else { + return rc; + } + } else { + rc = regulator_enable(ctrl->system_regulator); + } + + ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev, + "mem-acc"); + if (IS_ERR(ctrl->mem_acc_regulator)) { + rc = PTR_ERR(ctrl->mem_acc_regulator); + if (rc != -EPROBE_DEFER) { + rc = 0; + ctrl->mem_acc_regulator = NULL; + } else { + return rc; + } + } + + return rc; +} + +/** + * cpr3_limit_open_loop_voltages() - modify the open-loop voltage of each corner + * so that it fits within the floor to ceiling + * voltage range of the corner + * @vreg: Pointer to the CPR3 regulator + * + * This function clips the open-loop voltage for each corner so that it is + * limited to the floor to ceiling range. It also rounds each open-loop voltage + * so that it corresponds to a set point available to the underlying regulator. + * + * Return: 0 on success, errno on failure + */ +int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg) +{ + int i, volt; + + cpr3_debug(vreg, "open-loop voltages after trimming and rounding:\n"); + for (i = 0; i < vreg->corner_count; i++) { + volt = CPR3_ROUND(vreg->corner[i].open_loop_volt, + vreg->thread->ctrl->step_volt); + if (volt < vreg->corner[i].floor_volt) + volt = vreg->corner[i].floor_volt; + else if (volt > vreg->corner[i].ceiling_volt) + volt = vreg->corner[i].ceiling_volt; + vreg->corner[i].open_loop_volt = volt; + cpr3_debug(vreg, "corner[%2d]: open-loop=%d uV\n", i, volt); + } + + return 0; +} + +/** + * cpr3_open_loop_voltage_as_ceiling() - configures the ceiling voltage for each + * corner to equal the open-loop voltage if the relevant device + * tree property is found for the CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * + * This function assumes that the the open-loop voltage for each corner has + * already been rounded to the nearest allowed set point and that it falls + * within the floor to ceiling range. + * + * Return: none + */ +void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg) +{ + int i; + + if (!of_property_read_bool(vreg->of_node, + "qcom,cpr-scaled-open-loop-voltage-as-ceiling")) + return; + + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].ceiling_volt + = vreg->corner[i].open_loop_volt; +} + +/** + * cpr3_limit_floor_voltages() - raise the floor voltage of each corner so that + * the optional maximum floor to ceiling voltage range specified in + * device tree is satisfied + * @vreg: Pointer to the CPR3 regulator + * + * This function also ensures that the open-loop voltage for each corner falls + * within the final floor to ceiling voltage range and that floor voltages + * increase monotonically. + * + * Return: 0 on success, errno on failure + */ +int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg) +{ + char *prop = "qcom,cpr-floor-to-ceiling-max-range"; + int i, floor_new; + u32 *floor_range; + int rc = 0; + + if (!of_find_property(vreg->of_node, prop, NULL)) + goto enforce_monotonicity; + + floor_range = kcalloc(vreg->corner_count, sizeof(*floor_range), + GFP_KERNEL); + if (!floor_range) + return -ENOMEM; + + rc = cpr3_parse_corner_array_property(vreg, prop, 1, floor_range); + if (rc) + goto free_floor_adjust; + + for (i = 0; i < vreg->corner_count; i++) { + if ((s32)floor_range[i] >= 0) { + floor_new = CPR3_ROUND(vreg->corner[i].ceiling_volt + - floor_range[i], + vreg->thread->ctrl->step_volt); + + vreg->corner[i].floor_volt = max(floor_new, + vreg->corner[i].floor_volt); + if (vreg->corner[i].open_loop_volt + < vreg->corner[i].floor_volt) + vreg->corner[i].open_loop_volt + = vreg->corner[i].floor_volt; + } + } + +free_floor_adjust: + kfree(floor_range); + +enforce_monotonicity: + /* Ensure that floor voltages increase monotonically. */ + for (i = 1; i < vreg->corner_count; i++) { + if (vreg->corner[i].floor_volt + < vreg->corner[i - 1].floor_volt) { + cpr3_debug(vreg, "corner %d floor voltage=%d uV < corner %d voltage=%d uV; overriding: corner %d voltage=%d\n", + i, vreg->corner[i].floor_volt, + i - 1, vreg->corner[i - 1].floor_volt, + i, vreg->corner[i - 1].floor_volt); + vreg->corner[i].floor_volt + = vreg->corner[i - 1].floor_volt; + + if (vreg->corner[i].open_loop_volt + < vreg->corner[i].floor_volt) + vreg->corner[i].open_loop_volt + = vreg->corner[i].floor_volt; + if (vreg->corner[i].ceiling_volt + < vreg->corner[i].floor_volt) + vreg->corner[i].ceiling_volt + = vreg->corner[i].floor_volt; + } + } + + return rc; +} + +/** + * cpr3_print_quots() - print CPR target quotients into the kernel log for + * debugging purposes + * @vreg: Pointer to the CPR3 regulator + * + * Return: none + */ +void cpr3_print_quots(struct cpr3_regulator *vreg) +{ + int i, j, pos; + size_t buflen; + char *buf; + + buflen = sizeof(*buf) * CPR3_RO_COUNT * (MAX_CHARS_PER_INT + 2); + buf = kzalloc(buflen, GFP_KERNEL); + if (!buf) + return; + + for (i = 0; i < vreg->corner_count; i++) { + for (j = 0, pos = 0; j < CPR3_RO_COUNT; j++) + pos += scnprintf(buf + pos, buflen - pos, " %u", + vreg->corner[i].target_quot[j]); + cpr3_debug(vreg, "target quots[%2d]:%s\n", i, buf); + } + + kfree(buf); +} + +/** + * cpr3_determine_part_type() - determine the part type (SS/TT/FF). + * + * qcom,cpr-part-types prop tells the number of part types for which correction + * voltages are different. Another prop qcom,cpr-parts-voltage will contain the + * open loop fuse voltage which will be compared with this part voltage + * and accordingly part type will de determined. + * + * if qcom,cpr-part-types has value n, then qcom,cpr-parts-voltage will be + * array of n - 1 elements which will contain the voltage in increasing order. + * This function compares the fused volatge with all these voltage and returns + * the first index for which the fused volatge is greater. + * + * @vreg: Pointer to the CPR3 regulator + * @fuse_volt: fused open loop voltage which will be compared with + * qcom,cpr-parts-voltage array + * + * Return: 0 on success, errno on failure + */ +int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt) +{ + int i, rc, len; + u32 volt; + int soc_version_major; + char prop_name[100]; + const char prop_name_def[] = "qcom,cpr-parts-voltage"; + const char prop_name_v2[] = "qcom,cpr-parts-voltage-v2"; + + soc_version_major = read_ipq_soc_version_major(); + BUG_ON(soc_version_major <= 0); + + if (of_property_read_u32(vreg->of_node, "qcom,cpr-part-types", + &vreg->part_type_supported)) + return 0; + + if (soc_version_major > 1) + strlcpy(prop_name, prop_name_v2, sizeof(prop_name_v2)); + else + strlcpy(prop_name, prop_name_def, sizeof(prop_name_def)); + + if (!of_find_property(vreg->of_node, prop_name, &len)) { + cpr3_err(vreg, "property %s is missing\n", prop_name); + return -EINVAL; + } + + if (len != (vreg->part_type_supported - 1) * sizeof(u32)) { + cpr3_err(vreg, "wrong len in qcom,cpr-parts-voltage\n"); + return -EINVAL; + } + + for (i = 0; i < vreg->part_type_supported - 1; i++) { + rc = of_property_read_u32_index(vreg->of_node, + prop_name, i, &volt); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_name, rc); + return rc; + } + + if (fuse_volt < volt) + break; + } + + vreg->part_type = i; + return 0; +} + +int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, + int *fuse_volt) +{ + int i, rc, prev_volt; + int *volt_adjust; + char prop_str[75]; + int soc_version_major = read_ipq_soc_version_major(); + + BUG_ON(soc_version_major <= 0); + + if (vreg->part_type_supported) { + if (soc_version_major > 1) + snprintf(prop_str, sizeof(prop_str), + "qcom,cpr-cold-temp-voltage-adjustment-v2-%d", + vreg->part_type); + else + snprintf(prop_str, sizeof(prop_str), + "qcom,cpr-cold-temp-voltage-adjustment-%d", + vreg->part_type); + } else { + strlcpy(prop_str, "qcom,cpr-cold-temp-voltage-adjustment", + sizeof(prop_str)); + } + + if (!of_find_property(vreg->of_node, prop_str, NULL)) { + /* No adjustment required. */ + cpr3_info(vreg, "No cold temperature adjustment required.\n"); + return 0; + } + + volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust), + GFP_KERNEL); + if (!volt_adjust) + return -ENOMEM; + + rc = cpr3_parse_array_property(vreg, prop_str, + vreg->fuse_corner_count, volt_adjust); + if (rc) { + cpr3_err(vreg, "could not load cold temp voltage adjustments, rc=%d\n", + rc); + goto done; + } + + for (i = 0; i < vreg->fuse_corner_count; i++) { + if (volt_adjust[i]) { + prev_volt = fuse_volt[i]; + fuse_volt[i] += volt_adjust[i]; + cpr3_debug(vreg, + "adjusted fuse corner %d open-loop voltage: %d -> %d uV\n", + i, prev_volt, fuse_volt[i]); + } + } + +done: + kfree(volt_adjust); + return rc; +} + +/** + * cpr3_can_adjust_cold_temp() - Is cold temperature adjustment available + * + * @vreg: Pointer to the CPR3 regulator + * + * This function checks the cold temperature threshold is available + * + * Return: true on cold temperature threshold is available, else false + */ +bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg) +{ + char prop_str[75]; + int soc_version_major = read_ipq_soc_version_major(); + + BUG_ON(soc_version_major <= 0); + + if (soc_version_major > 1) + strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2", + sizeof(prop_str)); + else + strlcpy(prop_str, "qcom,cpr-cold-temp-threshold", + sizeof(prop_str)); + + if (!of_find_property(vreg->of_node, prop_str, NULL)) { + /* No adjustment required. */ + return false; + } else + return true; +} + +/** + * cpr3_get_cold_temp_threshold() - get cold temperature threshold + * + * @vreg: Pointer to the CPR3 regulator + * @cold_temp: cold temperature read. + * + * This function reads the cold temperature threshold below which + * cold temperature adjustment margins will be applied. + * + * Return: 0 on success, errno on failure + */ +int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp) +{ + int rc; + u32 temp; + char req_prop_str[75], prop_str[75]; + int soc_version_major = read_ipq_soc_version_major(); + + BUG_ON(soc_version_major <= 0); + + if (vreg->part_type_supported) { + if (soc_version_major > 1) + snprintf(req_prop_str, sizeof(req_prop_str), + "qcom,cpr-cold-temp-voltage-adjustment-v2-%d", + vreg->part_type); + else + snprintf(req_prop_str, sizeof(req_prop_str), + "qcom,cpr-cold-temp-voltage-adjustment-%d", + vreg->part_type); + } else { + strlcpy(req_prop_str, "qcom,cpr-cold-temp-voltage-adjustment", + sizeof(req_prop_str)); + } + + if (soc_version_major > 1) + strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2", + sizeof(prop_str)); + else + strlcpy(prop_str, "qcom,cpr-cold-temp-threshold", + sizeof(prop_str)); + + if (!of_find_property(vreg->of_node, req_prop_str, NULL)) { + /* No adjustment required. */ + cpr3_info(vreg, "Cold temperature adjustment not required.\n"); + return 0; + } + + if (!of_find_property(vreg->of_node, prop_str, NULL)) { + /* No adjustment required. */ + cpr3_err(vreg, "Missing %s required for %s\n", + prop_str, req_prop_str); + return -EINVAL; + } + + rc = of_property_read_u32(vreg->of_node, prop_str, &temp); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_str, rc); + return rc; + } + + *cold_temp = temp; + return 0; +} + +/** + * cpr3_adjust_fused_open_loop_voltages() - adjust the fused open-loop voltages + * for each fuse corner according to device tree values + * @vreg: Pointer to the CPR3 regulator + * @fuse_volt: Pointer to an array of the fused open-loop voltage + * values + * + * Voltage values in fuse_volt are modified in place. + * + * Return: 0 on success, errno on failure + */ +int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg, + int *fuse_volt) +{ + int i, rc, prev_volt; + int *volt_adjust; + char prop_str[75]; + int soc_version_major = read_ipq_soc_version_major(); + + BUG_ON(soc_version_major <= 0); + + if (vreg->part_type_supported) { + if (soc_version_major > 1) + snprintf(prop_str, sizeof(prop_str), + "qcom,cpr-open-loop-voltage-fuse-adjustment-v2-%d", + vreg->part_type); + else + snprintf(prop_str, sizeof(prop_str), + "qcom,cpr-open-loop-voltage-fuse-adjustment-%d", + vreg->part_type); + } else { + strlcpy(prop_str, "qcom,cpr-open-loop-voltage-fuse-adjustment", + sizeof(prop_str)); + } + + if (!of_find_property(vreg->of_node, prop_str, NULL)) { + /* No adjustment required. */ + return 0; + } + + volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust), + GFP_KERNEL); + if (!volt_adjust) + return -ENOMEM; + + rc = cpr3_parse_array_property(vreg, + prop_str, vreg->fuse_corner_count, volt_adjust); + if (rc) { + cpr3_err(vreg, "could not load open-loop fused voltage adjustments, rc=%d\n", + rc); + goto done; + } + + for (i = 0; i < vreg->fuse_corner_count; i++) { + if (volt_adjust[i]) { + prev_volt = fuse_volt[i]; + fuse_volt[i] += volt_adjust[i]; + cpr3_debug(vreg, "adjusted fuse corner %d open-loop voltage: %d --> %d uV\n", + i, prev_volt, fuse_volt[i]); + } + } + +done: + kfree(volt_adjust); + return rc; +} + +/** + * cpr3_adjust_open_loop_voltages() - adjust the open-loop voltages for each + * corner according to device tree values + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg) +{ + int i, rc, prev_volt, min_volt; + int *volt_adjust, *volt_diff; + + if (!of_find_property(vreg->of_node, + "qcom,cpr-open-loop-voltage-adjustment", NULL)) { + /* No adjustment required. */ + return 0; + } + + volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), + GFP_KERNEL); + volt_diff = kcalloc(vreg->corner_count, sizeof(*volt_diff), GFP_KERNEL); + if (!volt_adjust || !volt_diff) { + rc = -ENOMEM; + goto done; + } + + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-open-loop-voltage-adjustment", 1, volt_adjust); + if (rc) { + cpr3_err(vreg, "could not load open-loop voltage adjustments, rc=%d\n", + rc); + goto done; + } + + for (i = 0; i < vreg->corner_count; i++) { + if (volt_adjust[i]) { + prev_volt = vreg->corner[i].open_loop_volt; + vreg->corner[i].open_loop_volt += volt_adjust[i]; + cpr3_debug(vreg, "adjusted corner %d open-loop voltage: %d --> %d uV\n", + i, prev_volt, vreg->corner[i].open_loop_volt); + } + } + + if (of_find_property(vreg->of_node, + "qcom,cpr-open-loop-voltage-min-diff", NULL)) { + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-open-loop-voltage-min-diff", 1, volt_diff); + if (rc) { + cpr3_err(vreg, "could not load minimum open-loop voltage differences, rc=%d\n", + rc); + goto done; + } + } + + /* + * Ensure that open-loop voltages increase monotonically with respect + * to configurable minimum allowed differences. + */ + for (i = 1; i < vreg->corner_count; i++) { + min_volt = vreg->corner[i - 1].open_loop_volt + volt_diff[i]; + if (vreg->corner[i].open_loop_volt < min_volt) { + cpr3_debug(vreg, "adjusted corner %d open-loop voltage=%d uV < corner %d voltage=%d uV + min diff=%d uV; overriding: corner %d voltage=%d\n", + i, vreg->corner[i].open_loop_volt, + i - 1, vreg->corner[i - 1].open_loop_volt, + volt_diff[i], i, min_volt); + vreg->corner[i].open_loop_volt = min_volt; + } + } + +done: + kfree(volt_diff); + kfree(volt_adjust); + return rc; +} + +/** + * cpr3_quot_adjustment() - returns the quotient adjustment value resulting from + * the specified voltage adjustment and RO scaling factor + * @ro_scale: The CPR ring oscillator (RO) scaling factor with units + * of QUOT/V + * @volt_adjust: The amount to adjust the voltage by in units of + * microvolts. This value may be positive or negative. + */ +int cpr3_quot_adjustment(int ro_scale, int volt_adjust) +{ + unsigned long long temp; + int quot_adjust; + int sign = 1; + + if (ro_scale < 0) { + sign = -sign; + ro_scale = -ro_scale; + } + + if (volt_adjust < 0) { + sign = -sign; + volt_adjust = -volt_adjust; + } + + temp = (unsigned long long)ro_scale * (unsigned long long)volt_adjust; + do_div(temp, 1000000); + + quot_adjust = temp; + quot_adjust *= sign; + + return quot_adjust; +} + +/** + * cpr3_voltage_adjustment() - returns the voltage adjustment value resulting + * from the specified quotient adjustment and RO scaling factor + * @ro_scale: The CPR ring oscillator (RO) scaling factor with units + * of QUOT/V + * @quot_adjust: The amount to adjust the quotient by in units of + * QUOT. This value may be positive or negative. + */ +int cpr3_voltage_adjustment(int ro_scale, int quot_adjust) +{ + unsigned long long temp; + int volt_adjust; + int sign = 1; + + if (ro_scale < 0) { + sign = -sign; + ro_scale = -ro_scale; + } + + if (quot_adjust < 0) { + sign = -sign; + quot_adjust = -quot_adjust; + } + + if (ro_scale == 0) + return 0; + + temp = (unsigned long long)quot_adjust * 1000000; + do_div(temp, ro_scale); + + volt_adjust = temp; + volt_adjust *= sign; + + return volt_adjust; +} + +/** + * cpr3_parse_closed_loop_voltage_adjustments() - load per-fuse-corner and + * per-corner closed-loop adjustment values from device tree + * @vreg: Pointer to the CPR3 regulator + * @ro_sel: Array of ring oscillator values selected for each + * fuse corner + * @volt_adjust: Pointer to array which will be filled with the + * per-corner closed-loop adjustment voltages + * @volt_adjust_fuse: Pointer to array which will be filled with the + * per-fuse-corner closed-loop adjustment voltages + * @ro_scale: Pointer to array which will be filled with the + * per-fuse-corner RO scaling factor values with units of + * QUOT/V + * + * Return: 0 on success, errno on failure + */ +int cpr3_parse_closed_loop_voltage_adjustments( + struct cpr3_regulator *vreg, u64 *ro_sel, + int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) +{ + int i, rc; + u32 *ro_all_scale; + + char volt_adj[] = "qcom,cpr-closed-loop-voltage-adjustment"; + char volt_fuse_adj[] = "qcom,cpr-closed-loop-voltage-fuse-adjustment"; + char ro_scaling[] = "qcom,cpr-ro-scaling-factor"; + + if (!of_find_property(vreg->of_node, volt_adj, NULL) + && !of_find_property(vreg->of_node, volt_fuse_adj, NULL) + && !vreg->aging_allowed) { + /* No adjustment required. */ + return 0; + } else if (!of_find_property(vreg->of_node, ro_scaling, NULL)) { + cpr3_err(vreg, "Missing %s required for closed-loop voltage adjustment.\n", + ro_scaling); + return -EINVAL; + } + + ro_all_scale = kcalloc(vreg->fuse_corner_count * CPR3_RO_COUNT, + sizeof(*ro_all_scale), GFP_KERNEL); + if (!ro_all_scale) + return -ENOMEM; + + rc = cpr3_parse_array_property(vreg, ro_scaling, + vreg->fuse_corner_count * CPR3_RO_COUNT, ro_all_scale); + if (rc) { + cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n", + rc); + goto done; + } + + for (i = 0; i < vreg->fuse_corner_count; i++) + ro_scale[i] = ro_all_scale[i * CPR3_RO_COUNT + ro_sel[i]]; + + for (i = 0; i < vreg->corner_count; i++) + memcpy(vreg->corner[i].ro_scale, + &ro_all_scale[vreg->corner[i].cpr_fuse_corner * CPR3_RO_COUNT], + sizeof(*ro_all_scale) * CPR3_RO_COUNT); + + if (of_find_property(vreg->of_node, volt_fuse_adj, NULL)) { + rc = cpr3_parse_array_property(vreg, volt_fuse_adj, + vreg->fuse_corner_count, volt_adjust_fuse); + if (rc) { + cpr3_err(vreg, "could not load closed-loop fused voltage adjustments, rc=%d\n", + rc); + goto done; + } + } + + if (of_find_property(vreg->of_node, volt_adj, NULL)) { + rc = cpr3_parse_corner_array_property(vreg, volt_adj, + 1, volt_adjust); + if (rc) { + cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", + rc); + goto done; + } + } + +done: + kfree(ro_all_scale); + return rc; +} + +/** + * cpr3_apm_init() - initialize APM data for a CPR3 controller + * @ctrl: Pointer to the CPR3 controller + * + * This function loads memory array power mux (APM) data from device tree + * if it is present and requests a handle to the appropriate APM controller + * device. + * + * Return: 0 on success, errno on failure + */ +int cpr3_apm_init(struct cpr3_controller *ctrl) +{ + struct device_node *node = ctrl->dev->of_node; + int rc; + + if (!of_find_property(node, "qcom,apm-ctrl", NULL)) { + /* No APM used */ + return 0; + } + + ctrl->apm = msm_apm_ctrl_dev_get(ctrl->dev); + if (IS_ERR(ctrl->apm)) { + rc = PTR_ERR(ctrl->apm); + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "APM get failed, rc=%d\n", rc); + return rc; + } + + rc = of_property_read_u32(node, "qcom,apm-threshold-voltage", + &ctrl->apm_threshold_volt); + if (rc) { + cpr3_err(ctrl, "error reading qcom,apm-threshold-voltage, rc=%d\n", + rc); + return rc; + } + ctrl->apm_threshold_volt + = CPR3_ROUND(ctrl->apm_threshold_volt, ctrl->step_volt); + + /* No error check since this is an optional property. */ + of_property_read_u32(node, "qcom,apm-hysteresis-voltage", + &ctrl->apm_adj_volt); + ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt); + + ctrl->apm_high_supply = MSM_APM_SUPPLY_APCC; + ctrl->apm_low_supply = MSM_APM_SUPPLY_MX; + + return 0; +} + +/** + * cpr3_mem_acc_init() - initialize mem-acc regulator data for + * a CPR3 regulator + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +int cpr3_mem_acc_init(struct cpr3_regulator *vreg) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + u32 *temp; + int i, rc; + + if (!ctrl->mem_acc_regulator) { + cpr3_info(ctrl, "not using memory accelerator regulator\n"); + return 0; + } + + temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL); + if (!temp) + return -ENOMEM; + + rc = cpr3_parse_corner_array_property(vreg, "qcom,mem-acc-voltage", + 1, temp); + if (rc) { + cpr3_err(ctrl, "could not load mem-acc corners, rc=%d\n", rc); + } else { + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].mem_acc_volt = temp[i]; + } + + kfree(temp); + return rc; +} + +/** + * cpr4_load_core_and_temp_adj() - parse amount of voltage adjustment for + * per-online-core and per-temperature voltage adjustment for a + * given corner or corner band from device tree. + * @vreg: Pointer to the CPR3 regulator + * @num: Corner number or corner band number + * @use_corner_band: Boolean indicating if the CPR3 regulator supports + * adjustments per corner band + * + * Return: 0 on success, errno on failure + */ +static int cpr4_load_core_and_temp_adj(struct cpr3_regulator *vreg, + int num, bool use_corner_band) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct cpr4_sdelta *sdelta; + int sdelta_size, i, j, pos, rc = 0; + char str[75]; + size_t buflen; + char *buf; + + sdelta = use_corner_band ? vreg->corner_band[num].sdelta : + vreg->corner[num].sdelta; + + if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj) { + /* corner doesn't need sdelta table */ + sdelta->max_core_count = 0; + sdelta->temp_band_count = 0; + return rc; + } + + sdelta_size = sdelta->max_core_count * sdelta->temp_band_count; + if (use_corner_band) + snprintf(str, sizeof(str), + "corner_band=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n", + num, sdelta->max_core_count, + sdelta->temp_band_count, sdelta_size); + else + snprintf(str, sizeof(str), + "corner=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n", + num, sdelta->max_core_count, + sdelta->temp_band_count, sdelta_size); + + cpr3_debug(vreg, "%s", str); + + sdelta->table = devm_kcalloc(ctrl->dev, sdelta_size, + sizeof(*sdelta->table), GFP_KERNEL); + if (!sdelta->table) + return -ENOMEM; + + if (use_corner_band) + snprintf(str, sizeof(str), + "qcom,cpr-corner-band%d-temp-core-voltage-adjustment", + num + CPR3_CORNER_OFFSET); + else + snprintf(str, sizeof(str), + "qcom,cpr-corner%d-temp-core-voltage-adjustment", + num + CPR3_CORNER_OFFSET); + + rc = cpr3_parse_array_property(vreg, str, sdelta_size, + sdelta->table); + if (rc) { + cpr3_err(vreg, "could not load %s, rc=%d\n", str, rc); + return rc; + } + + /* + * Convert sdelta margins from uV to PMIC steps and apply negation to + * follow the SDELTA register semantics. + */ + for (i = 0; i < sdelta_size; i++) + sdelta->table[i] = -(sdelta->table[i] / ctrl->step_volt); + + buflen = sizeof(*buf) * sdelta_size * (MAX_CHARS_PER_INT + 2); + buf = kzalloc(buflen, GFP_KERNEL); + if (!buf) + return rc; + + for (i = 0; i < sdelta->max_core_count; i++) { + for (j = 0, pos = 0; j < sdelta->temp_band_count; j++) + pos += scnprintf(buf + pos, buflen - pos, " %u", + sdelta->table[i * sdelta->temp_band_count + j]); + cpr3_debug(vreg, "sdelta[%d]:%s\n", i, buf); + } + + kfree(buf); + return rc; +} + +/** + * cpr4_parse_core_count_temp_voltage_adj() - parse configuration data for + * per-online-core and per-temperature voltage adjustment for + * a CPR3 regulator from device tree. + * @vreg: Pointer to the CPR3 regulator + * @use_corner_band: Boolean indicating if the CPR3 regulator supports + * adjustments per corner band + * + * This function supports parsing of per-online-core and per-temperature + * adjustments per corner or per corner band. CPR controllers which support + * corner bands apply the same adjustments to all corners within a corner band. + * + * Return: 0 on success, errno on failure + */ +int cpr4_parse_core_count_temp_voltage_adj( + struct cpr3_regulator *vreg, bool use_corner_band) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct device_node *node = vreg->of_node; + struct cpr3_corner *corner; + struct cpr4_sdelta *sdelta; + int i, sdelta_table_count, rc = 0; + int *allow_core_count_adj = NULL, *allow_temp_adj = NULL; + char prop_str[75]; + + if (of_find_property(node, use_corner_band ? + "qcom,corner-band-allow-temp-adjustment" + : "qcom,corner-allow-temp-adjustment", NULL)) { + if (!ctrl->allow_temp_adj) { + cpr3_err(ctrl, "Temperature adjustment configurations missing\n"); + return -EINVAL; + } + + vreg->allow_temp_adj = true; + } + + if (of_find_property(node, use_corner_band ? + "qcom,corner-band-allow-core-count-adjustment" + : "qcom,corner-allow-core-count-adjustment", + NULL)) { + rc = of_property_read_u32(node, "qcom,max-core-count", + &vreg->max_core_count); + if (rc) { + cpr3_err(vreg, "error reading qcom,max-core-count, rc=%d\n", + rc); + return -EINVAL; + } + + vreg->allow_core_count_adj = true; + ctrl->allow_core_count_adj = true; + } + + if (!vreg->allow_temp_adj && !vreg->allow_core_count_adj) { + /* + * Both per-online-core and temperature based adjustments are + * disabled for this regulator. + */ + return 0; + } else if (!vreg->allow_core_count_adj) { + /* + * Only per-temperature voltage adjusments are allowed. + * Keep max core count value as 1 to allocate SDELTA. + */ + vreg->max_core_count = 1; + } + + if (vreg->allow_core_count_adj) { + allow_core_count_adj = kcalloc(vreg->corner_count, + sizeof(*allow_core_count_adj), + GFP_KERNEL); + if (!allow_core_count_adj) + return -ENOMEM; + + snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ? + "qcom,corner-band-allow-core-count-adjustment" : + "qcom,corner-allow-core-count-adjustment"); + + rc = use_corner_band ? + cpr3_parse_corner_band_array_property(vreg, prop_str, + 1, allow_core_count_adj) : + cpr3_parse_corner_array_property(vreg, prop_str, + 1, allow_core_count_adj); + if (rc) { + cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str, + rc); + goto done; + } + } + + if (vreg->allow_temp_adj) { + allow_temp_adj = kcalloc(vreg->corner_count, + sizeof(*allow_temp_adj), GFP_KERNEL); + if (!allow_temp_adj) { + rc = -ENOMEM; + goto done; + } + + snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ? + "qcom,corner-band-allow-temp-adjustment" : + "qcom,corner-allow-temp-adjustment"); + + rc = use_corner_band ? + cpr3_parse_corner_band_array_property(vreg, prop_str, + 1, allow_temp_adj) : + cpr3_parse_corner_array_property(vreg, prop_str, + 1, allow_temp_adj); + if (rc) { + cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str, + rc); + goto done; + } + } + + sdelta_table_count = use_corner_band ? vreg->corner_band_count : + vreg->corner_count; + + for (i = 0; i < sdelta_table_count; i++) { + sdelta = devm_kzalloc(ctrl->dev, sizeof(*corner->sdelta), + GFP_KERNEL); + if (!sdelta) { + rc = -ENOMEM; + goto done; + } + + if (allow_core_count_adj) + sdelta->allow_core_count_adj = allow_core_count_adj[i]; + if (allow_temp_adj) + sdelta->allow_temp_adj = allow_temp_adj[i]; + sdelta->max_core_count = vreg->max_core_count; + sdelta->temp_band_count = ctrl->temp_band_count; + + if (use_corner_band) + vreg->corner_band[i].sdelta = sdelta; + else + vreg->corner[i].sdelta = sdelta; + + rc = cpr4_load_core_and_temp_adj(vreg, i, use_corner_band); + if (rc) { + cpr3_err(vreg, "corner/band %d core and temp adjustment loading failed, rc=%d\n", + i, rc); + goto done; + } + } + +done: + kfree(allow_core_count_adj); + kfree(allow_temp_adj); + + return rc; +} + +/** + * cprh_adjust_voltages_for_apm() - adjust per-corner floor and ceiling voltages + * so that they do not overlap the APM threshold voltage. + * @vreg: Pointer to the CPR3 regulator + * + * The memory array power mux (APM) must be configured for a specific supply + * based upon where the VDD voltage lies with respect to the APM threshold + * voltage. When using CPR hardware closed-loop, the voltage may vary anywhere + * between the floor and ceiling voltage without software notification. + * Therefore, it is required that the floor to ceiling range for every corner + * not intersect the APM threshold voltage. This function adjusts the floor to + * ceiling range for each corner which violates this requirement. + * + * The following algorithm is applied: + * if floor < threshold <= ceiling: + * if open_loop >= threshold, then floor = threshold - adj + * else ceiling = threshold - step + * where: + * adj = APM hysteresis voltage established to minimize the number of + * corners with artificially increased floor voltages + * step = voltage in microvolts of a single step of the VDD supply + * + * The open-loop voltage is also bounded by the new floor or ceiling value as + * needed. + * + * Return: none + */ +void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct cpr3_corner *corner; + int i, adj, threshold, prev_ceiling, prev_floor, prev_open_loop; + + if (!ctrl->apm_threshold_volt) { + /* APM not being used. */ + return; + } + + ctrl->apm_threshold_volt = CPR3_ROUND(ctrl->apm_threshold_volt, + ctrl->step_volt); + ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt); + + threshold = ctrl->apm_threshold_volt; + adj = ctrl->apm_adj_volt; + + for (i = 0; i < vreg->corner_count; i++) { + corner = &vreg->corner[i]; + + if (threshold <= corner->floor_volt + || threshold > corner->ceiling_volt) + continue; + + prev_floor = corner->floor_volt; + prev_ceiling = corner->ceiling_volt; + prev_open_loop = corner->open_loop_volt; + + if (corner->open_loop_volt >= threshold) { + corner->floor_volt = max(corner->floor_volt, + threshold - adj); + if (corner->open_loop_volt < corner->floor_volt) + corner->open_loop_volt = corner->floor_volt; + } else { + corner->ceiling_volt = threshold - ctrl->step_volt; + } + + if (corner->floor_volt != prev_floor + || corner->ceiling_volt != prev_ceiling + || corner->open_loop_volt != prev_open_loop) + cpr3_debug(vreg, "APM threshold=%d, APM adj=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n", + threshold, adj, i, prev_floor, prev_ceiling, + prev_open_loop, corner->floor_volt, + corner->ceiling_volt, corner->open_loop_volt); + } +} + +/** + * cprh_adjust_voltages_for_mem_acc() - adjust per-corner floor and ceiling + * voltages so that they do not intersect the MEM ACC threshold + * voltage + * @vreg: Pointer to the CPR3 regulator + * + * The following algorithm is applied: + * if floor < threshold <= ceiling: + * if open_loop >= threshold, then floor = threshold + * else ceiling = threshold - step + * where: + * step = voltage in microvolts of a single step of the VDD supply + * + * The open-loop voltage is also bounded by the new floor or ceiling value as + * needed. + * + * Return: none + */ +void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct cpr3_corner *corner; + int i, threshold, prev_ceiling, prev_floor, prev_open_loop; + + if (!ctrl->mem_acc_threshold_volt) { + /* MEM ACC not being used. */ + return; + } + + ctrl->mem_acc_threshold_volt = CPR3_ROUND(ctrl->mem_acc_threshold_volt, + ctrl->step_volt); + + threshold = ctrl->mem_acc_threshold_volt; + + for (i = 0; i < vreg->corner_count; i++) { + corner = &vreg->corner[i]; + + if (threshold <= corner->floor_volt + || threshold > corner->ceiling_volt) + continue; + + prev_floor = corner->floor_volt; + prev_ceiling = corner->ceiling_volt; + prev_open_loop = corner->open_loop_volt; + + if (corner->open_loop_volt >= threshold) { + corner->floor_volt = max(corner->floor_volt, threshold); + if (corner->open_loop_volt < corner->floor_volt) + corner->open_loop_volt = corner->floor_volt; + } else { + corner->ceiling_volt = threshold - ctrl->step_volt; + } + + if (corner->floor_volt != prev_floor + || corner->ceiling_volt != prev_ceiling + || corner->open_loop_volt != prev_open_loop) + cpr3_debug(vreg, "MEM ACC threshold=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n", + threshold, i, prev_floor, prev_ceiling, + prev_open_loop, corner->floor_volt, + corner->ceiling_volt, corner->open_loop_volt); + } +} + +/** + * cpr3_apply_closed_loop_offset_voltages() - modify the closed-loop voltage + * adjustments by the amounts that are needed for this + * fuse combo + * @vreg: Pointer to the CPR3 regulator + * @volt_adjust: Array of closed-loop voltage adjustment values of length + * vreg->corner_count which is further adjusted based upon + * offset voltage fuse values. + * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length + * vreg->fuse_corner_count. + * + * Return: 0 on success, errno on failure + */ +static int cpr3_apply_closed_loop_offset_voltages(struct cpr3_regulator *vreg, + int *volt_adjust, int *fuse_volt_adjust) +{ + u32 *corner_map; + int rc = 0, i; + + if (!of_find_property(vreg->of_node, + "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL)) { + /* No closed-loop offset required. */ + return 0; + } + + corner_map = kcalloc(vreg->corner_count, sizeof(*corner_map), + GFP_KERNEL); + if (!corner_map) + return -ENOMEM; + + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-fused-closed-loop-voltage-adjustment-map", + 1, corner_map); + if (rc) + goto done; + + for (i = 0; i < vreg->corner_count; i++) { + if (corner_map[i] == 0) { + continue; + } else if (corner_map[i] > vreg->fuse_corner_count) { + cpr3_err(vreg, "corner %d mapped to invalid fuse corner: %u\n", + i, corner_map[i]); + rc = -EINVAL; + goto done; + } + + volt_adjust[i] += fuse_volt_adjust[corner_map[i] - 1]; + } + +done: + kfree(corner_map); + return rc; +} + +/** + * cpr3_enforce_inc_quotient_monotonicity() - Ensure that target quotients + * increase monotonically from lower to higher corners + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static void cpr3_enforce_inc_quotient_monotonicity(struct cpr3_regulator *vreg) +{ + int i, j; + + for (i = 1; i < vreg->corner_count; i++) { + for (j = 0; j < CPR3_RO_COUNT; j++) { + if (vreg->corner[i].target_quot[j] + && vreg->corner[i].target_quot[j] + < vreg->corner[i - 1].target_quot[j]) { + cpr3_debug(vreg, "corner %d RO%u target quot=%u < corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", + i, j, + vreg->corner[i].target_quot[j], + i - 1, j, + vreg->corner[i - 1].target_quot[j], + i, j, + vreg->corner[i - 1].target_quot[j]); + vreg->corner[i].target_quot[j] + = vreg->corner[i - 1].target_quot[j]; + } + } + } +} + +/** + * cpr3_enforce_dec_quotient_monotonicity() - Ensure that target quotients + * decrease monotonically from higher to lower corners + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static void cpr3_enforce_dec_quotient_monotonicity(struct cpr3_regulator *vreg) +{ + int i, j; + + for (i = vreg->corner_count - 2; i >= 0; i--) { + for (j = 0; j < CPR3_RO_COUNT; j++) { + if (vreg->corner[i + 1].target_quot[j] + && vreg->corner[i].target_quot[j] + > vreg->corner[i + 1].target_quot[j]) { + cpr3_debug(vreg, "corner %d RO%u target quot=%u > corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", + i, j, + vreg->corner[i].target_quot[j], + i + 1, j, + vreg->corner[i + 1].target_quot[j], + i, j, + vreg->corner[i + 1].target_quot[j]); + vreg->corner[i].target_quot[j] + = vreg->corner[i + 1].target_quot[j]; + } + } + } +} + +/** + * _cpr3_adjust_target_quotients() - adjust the target quotients for each + * corner of the regulator according to input adjustment and + * scaling arrays + * @vreg: Pointer to the CPR3 regulator + * @volt_adjust: Pointer to an array of closed-loop voltage adjustments + * with units of microvolts. The array must have + * vreg->corner_count number of elements. + * @ro_scale: Pointer to a flattened 2D array of RO scaling factors. + * The array must have an inner dimension of CPR3_RO_COUNT + * and an outer dimension of vreg->corner_count + * @label: Null terminated string providing a label for the type + * of adjustment. + * + * Return: true if any corners received a positive voltage adjustment (> 0), + * else false + */ +static bool _cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, + const int *volt_adjust, const int *ro_scale, const char *label) +{ + int i, j, quot_adjust; + bool is_increasing = false; + u32 prev_quot; + + for (i = 0; i < vreg->corner_count; i++) { + for (j = 0; j < CPR3_RO_COUNT; j++) { + if (vreg->corner[i].target_quot[j]) { + quot_adjust = cpr3_quot_adjustment( + ro_scale[i * CPR3_RO_COUNT + j], + volt_adjust[i]); + if (quot_adjust) { + prev_quot = vreg->corner[i]. + target_quot[j]; + vreg->corner[i].target_quot[j] + += quot_adjust; + cpr3_debug(vreg, "adjusted corner %d RO%d target quot %s: %u --> %u (%d uV)\n", + i, j, label, prev_quot, + vreg->corner[i].target_quot[j], + volt_adjust[i]); + } + } + } + if (volt_adjust[i] > 0) + is_increasing = true; + } + + return is_increasing; +} + +/** + * cpr3_adjust_target_quotients() - adjust the target quotients for each + * corner according to device tree values and fuse values + * @vreg: Pointer to the CPR3 regulator + * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length + * vreg->fuse_corner_count. This parameter could be null + * pointer when no fused adjustments are needed. + * + * Return: 0 on success, errno on failure + */ +int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, + int *fuse_volt_adjust) +{ + int i, rc; + int *volt_adjust, *ro_scale; + bool explicit_adjustment, fused_adjustment, is_increasing; + + explicit_adjustment = of_find_property(vreg->of_node, + "qcom,cpr-closed-loop-voltage-adjustment", NULL); + fused_adjustment = of_find_property(vreg->of_node, + "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL); + + if (!explicit_adjustment && !fused_adjustment && !vreg->aging_allowed) { + /* No adjustment required. */ + return 0; + } else if (!of_find_property(vreg->of_node, + "qcom,cpr-ro-scaling-factor", NULL)) { + cpr3_err(vreg, "qcom,cpr-ro-scaling-factor is required for closed-loop voltage adjustment, but is missing\n"); + return -EINVAL; + } + + volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), + GFP_KERNEL); + ro_scale = kcalloc(vreg->corner_count * CPR3_RO_COUNT, + sizeof(*ro_scale), GFP_KERNEL); + if (!volt_adjust || !ro_scale) { + rc = -ENOMEM; + goto done; + } + + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-ro-scaling-factor", CPR3_RO_COUNT, ro_scale); + if (rc) { + cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n", + rc); + goto done; + } + + for (i = 0; i < vreg->corner_count; i++) + memcpy(vreg->corner[i].ro_scale, &ro_scale[i * CPR3_RO_COUNT], + sizeof(*ro_scale) * CPR3_RO_COUNT); + + if (explicit_adjustment) { + rc = cpr3_parse_corner_array_property(vreg, + "qcom,cpr-closed-loop-voltage-adjustment", + 1, volt_adjust); + if (rc) { + cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", + rc); + goto done; + } + + _cpr3_adjust_target_quotients(vreg, volt_adjust, ro_scale, + "from DT"); + cpr3_enforce_inc_quotient_monotonicity(vreg); + } + + if (fused_adjustment && fuse_volt_adjust) { + memset(volt_adjust, 0, + sizeof(*volt_adjust) * vreg->corner_count); + + rc = cpr3_apply_closed_loop_offset_voltages(vreg, volt_adjust, + fuse_volt_adjust); + if (rc) { + cpr3_err(vreg, "could not apply fused closed-loop voltage reductions, rc=%d\n", + rc); + goto done; + } + + is_increasing = _cpr3_adjust_target_quotients(vreg, volt_adjust, + ro_scale, "from fuse"); + if (is_increasing) + cpr3_enforce_inc_quotient_monotonicity(vreg); + else + cpr3_enforce_dec_quotient_monotonicity(vreg); + } + +done: + kfree(volt_adjust); + kfree(ro_scale); + return rc; +} diff --git a/target/linux/ipq807x/files-5.15/drivers/regulator/cpr4-apss-regulator.c b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr4-apss-regulator.c new file mode 100644 index 000000000..114e2acb2 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/drivers/regulator/cpr4-apss-regulator.c @@ -0,0 +1,1819 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpr3-regulator.h" + +#define IPQ807x_APSS_FUSE_CORNERS 4 +#define IPQ817x_APPS_FUSE_CORNERS 2 +#define IPQ6018_APSS_FUSE_CORNERS 4 +#define IPQ9574_APSS_FUSE_CORNERS 4 + +u32 g_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS; + +/** + * struct cpr4_ipq807x_apss_fuses - APSS specific fuse data for IPQ807x + * @ro_sel: Ring oscillator select fuse parameter value for each + * fuse corner + * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value + * for each fuse corner (raw, not converted to a voltage) + * @target_quot: CPR target quotient fuse parameter value for each fuse + * corner + * @quot_offset: CPR target quotient offset fuse parameter value for each + * fuse corner (raw, not unpacked) used for target quotient + * interpolation + * @speed_bin: Application processor speed bin fuse parameter value for + * the given chip + * @cpr_fusing_rev: CPR fusing revision fuse parameter value + * @boost_cfg: CPR boost configuration fuse parameter value + * @boost_voltage: CPR boost voltage fuse parameter value (raw, not + * converted to a voltage) + * + * This struct holds the values for all of the fuses read from memory. + */ +struct cpr4_ipq807x_apss_fuses { + u64 ro_sel[IPQ807x_APSS_FUSE_CORNERS]; + u64 init_voltage[IPQ807x_APSS_FUSE_CORNERS]; + u64 target_quot[IPQ807x_APSS_FUSE_CORNERS]; + u64 quot_offset[IPQ807x_APSS_FUSE_CORNERS]; + u64 speed_bin; + u64 cpr_fusing_rev; + u64 boost_cfg; + u64 boost_voltage; + u64 misc; +}; + +/* + * fuse combo = fusing revision + 8 * (speed bin) + * where: fusing revision = 0 - 7 and speed bin = 0 - 7 + */ +#define CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT 64 + +/* + * Constants which define the name of each fuse corner. + */ +enum cpr4_ipq807x_apss_fuse_corner { + CPR4_IPQ807x_APSS_FUSE_CORNER_SVS = 0, + CPR4_IPQ807x_APSS_FUSE_CORNER_NOM = 1, + CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO = 2, + CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO = 3, +}; + +static const char * const cpr4_ipq807x_apss_fuse_corner_name[] = { + [CPR4_IPQ807x_APSS_FUSE_CORNER_SVS] = "SVS", + [CPR4_IPQ807x_APSS_FUSE_CORNER_NOM] = "NOM", + [CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO] = "TURBO", + [CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO] = "STURBO", +}; + +/* + * IPQ807x APSS fuse parameter locations: + * + * Structs are organized with the following dimensions: + * Outer: 0 to 3 for fuse corners from lowest to highest corner + * Inner: large enough to hold the longest set of parameter segments which + * fully defines a fuse parameter, +1 (for NULL termination). + * Each segment corresponds to a contiguous group of bits from a + * single fuse row. These segments are concatentated together in + * order to form the full fuse parameter value. The segments for + * a given parameter may correspond to different fuse rows. + */ +static struct cpr3_fuse_param +ipq807x_apss_ro_sel_param[IPQ807x_APSS_FUSE_CORNERS][2] = { + {{73, 8, 11}, {} }, + {{73, 4, 7}, {} }, + {{73, 0, 3}, {} }, + {{73, 12, 15}, {} }, +}; + +static struct cpr3_fuse_param +ipq807x_apss_init_voltage_param[IPQ807x_APSS_FUSE_CORNERS][2] = { + {{71, 18, 23}, {} }, + {{71, 12, 17}, {} }, + {{71, 6, 11}, {} }, + {{71, 0, 5}, {} }, +}; + +static struct cpr3_fuse_param +ipq807x_apss_target_quot_param[IPQ807x_APSS_FUSE_CORNERS][2] = { + {{72, 32, 43}, {} }, + {{72, 20, 31}, {} }, + {{72, 8, 19}, {} }, + {{72, 44, 55}, {} }, +}; + +static struct cpr3_fuse_param +ipq807x_apss_quot_offset_param[IPQ807x_APSS_FUSE_CORNERS][2] = { + {{} }, + {{71, 46, 52}, {} }, + {{71, 39, 45}, {} }, + {{71, 32, 38}, {} }, +}; + +static struct cpr3_fuse_param ipq807x_cpr_fusing_rev_param[] = { + {71, 53, 55}, + {}, +}; + +static struct cpr3_fuse_param ipq807x_apss_speed_bin_param[] = { + {36, 40, 42}, + {}, +}; + +static struct cpr3_fuse_param ipq807x_cpr_boost_fuse_cfg_param[] = { + {36, 43, 45}, + {}, +}; + +static struct cpr3_fuse_param ipq807x_apss_boost_fuse_volt_param[] = { + {71, 0, 5}, + {}, +}; + +static struct cpr3_fuse_param ipq807x_misc_fuse_volt_adj_param[] = { + {36, 54, 54}, + {}, +}; + +static struct cpr3_fuse_parameters ipq807x_fuse_params = { + .apss_ro_sel_param = ipq807x_apss_ro_sel_param, + .apss_init_voltage_param = ipq807x_apss_init_voltage_param, + .apss_target_quot_param = ipq807x_apss_target_quot_param, + .apss_quot_offset_param = ipq807x_apss_quot_offset_param, + .cpr_fusing_rev_param = ipq807x_cpr_fusing_rev_param, + .apss_speed_bin_param = ipq807x_apss_speed_bin_param, + .cpr_boost_fuse_cfg_param = ipq807x_cpr_boost_fuse_cfg_param, + .apss_boost_fuse_volt_param = ipq807x_apss_boost_fuse_volt_param, + .misc_fuse_volt_adj_param = ipq807x_misc_fuse_volt_adj_param +}; + +/* + * The number of possible values for misc fuse is + * 2^(#bits defined for misc fuse) + */ +#define IPQ807x_MISC_FUSE_VAL_COUNT BIT(1) + +/* + * Open loop voltage fuse reference voltages in microvolts for IPQ807x + */ +static int ipq807x_apss_fuse_ref_volt + [IPQ807x_APSS_FUSE_CORNERS] = { + 720000, + 864000, + 992000, + 1064000, +}; + +#define IPQ807x_APSS_FUSE_STEP_VOLT 8000 +#define IPQ807x_APSS_VOLTAGE_FUSE_SIZE 6 +#define IPQ807x_APSS_QUOT_OFFSET_SCALE 5 + +#define IPQ807x_APSS_CPR_SENSOR_COUNT 6 + +#define IPQ807x_APSS_CPR_CLOCK_RATE 19200000 + +#define IPQ807x_APSS_MAX_TEMP_POINTS 3 +#define IPQ807x_APSS_TEMP_SENSOR_ID_START 4 +#define IPQ807x_APSS_TEMP_SENSOR_ID_END 13 +/* + * Boost voltage fuse reference and ceiling voltages in microvolts for + * IPQ807x. + */ +#define IPQ807x_APSS_BOOST_FUSE_REF_VOLT 1140000 +#define IPQ807x_APSS_BOOST_CEILING_VOLT 1140000 +#define IPQ807x_APSS_BOOST_FLOOR_VOLT 900000 +#define MAX_BOOST_CONFIG_FUSE_VALUE 8 + +#define IPQ807x_APSS_CPR_SDELTA_CORE_COUNT 15 + +#define IPQ807x_APSS_CPR_TCSR_START 8 +#define IPQ807x_APSS_CPR_TCSR_END 9 + +/* + * Array of integer values mapped to each of the boost config fuse values to + * indicate boost enable/disable status. + */ +static bool boost_fuse[MAX_BOOST_CONFIG_FUSE_VALUE] = {0, 1, 1, 1, 1, 1, 1, 1}; + +/* + * IPQ6018 (Few parameters are changed, remaining are same as IPQ807x) + */ +#define IPQ6018_APSS_FUSE_STEP_VOLT 12500 +#define IPQ6018_APSS_CPR_CLOCK_RATE 24000000 + +static struct cpr3_fuse_param +ipq6018_apss_ro_sel_param[IPQ6018_APSS_FUSE_CORNERS][2] = { + {{75, 8, 11}, {} }, + {{75, 4, 7}, {} }, + {{75, 0, 3}, {} }, + {{75, 12, 15}, {} }, +}; + +static struct cpr3_fuse_param +ipq6018_apss_init_voltage_param[IPQ6018_APSS_FUSE_CORNERS][2] = { + {{73, 18, 23}, {} }, + {{73, 12, 17}, {} }, + {{73, 6, 11}, {} }, + {{73, 0, 5}, {} }, +}; + +static struct cpr3_fuse_param +ipq6018_apss_target_quot_param[IPQ6018_APSS_FUSE_CORNERS][2] = { + {{74, 32, 43}, {} }, + {{74, 20, 31}, {} }, + {{74, 8, 19}, {} }, + {{74, 44, 55}, {} }, +}; + +static struct cpr3_fuse_param +ipq6018_apss_quot_offset_param[IPQ6018_APSS_FUSE_CORNERS][2] = { + {{} }, + {{73, 48, 55}, {} }, + {{73, 40, 47}, {} }, + {{73, 32, 39}, {} }, +}; + +static struct cpr3_fuse_param ipq6018_cpr_fusing_rev_param[] = { + {75, 16, 18}, + {}, +}; + +static struct cpr3_fuse_param ipq6018_apss_speed_bin_param[] = { + {36, 40, 42}, + {}, +}; + +static struct cpr3_fuse_param ipq6018_cpr_boost_fuse_cfg_param[] = { + {36, 43, 45}, + {}, +}; + +static struct cpr3_fuse_param ipq6018_apss_boost_fuse_volt_param[] = { + {73, 0, 5}, + {}, +}; + +static struct cpr3_fuse_param ipq6018_misc_fuse_volt_adj_param[] = { + {36, 54, 54}, + {}, +}; + +static struct cpr3_fuse_parameters ipq6018_fuse_params = { + .apss_ro_sel_param = ipq6018_apss_ro_sel_param, + .apss_init_voltage_param = ipq6018_apss_init_voltage_param, + .apss_target_quot_param = ipq6018_apss_target_quot_param, + .apss_quot_offset_param = ipq6018_apss_quot_offset_param, + .cpr_fusing_rev_param = ipq6018_cpr_fusing_rev_param, + .apss_speed_bin_param = ipq6018_apss_speed_bin_param, + .cpr_boost_fuse_cfg_param = ipq6018_cpr_boost_fuse_cfg_param, + .apss_boost_fuse_volt_param = ipq6018_apss_boost_fuse_volt_param, + .misc_fuse_volt_adj_param = ipq6018_misc_fuse_volt_adj_param +}; + + +/* + * Boost voltage fuse reference and ceiling voltages in microvolts for + * IPQ6018. + */ +#define IPQ6018_APSS_BOOST_FUSE_REF_VOLT 1140000 +#define IPQ6018_APSS_BOOST_CEILING_VOLT 1140000 +#define IPQ6018_APSS_BOOST_FLOOR_VOLT 900000 + +/* + * Open loop voltage fuse reference voltages in microvolts for IPQ807x + */ +static int ipq6018_apss_fuse_ref_volt + [IPQ6018_APSS_FUSE_CORNERS] = { + 725000, + 862500, + 987500, + 1062500, +}; + +/* + * IPQ6018 Memory ACC settings on TCSR + * + * Turbo_L1: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x10 + * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x1 + * Other modes: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x0 + * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x0 + * + */ +#define IPQ6018_APSS_MEM_ACC_TCSR_COUNT 2 +#define TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x1946178 +#define TCSR_CUSTOM_VDDAPC0_ACC_1 0x1946124 + +struct mem_acc_tcsr { + u32 phy_addr; + void __iomem *ioremap_addr; + u32 value; +}; + +static struct mem_acc_tcsr ipq6018_mem_acc_tcsr[IPQ6018_APSS_MEM_ACC_TCSR_COUNT] = { + {TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0, NULL, 0x10}, + {TCSR_CUSTOM_VDDAPC0_ACC_1, NULL, 0x1}, +}; + +/* + * IPQ9574 (Few parameters are changed, remaining are same as IPQ6018) + */ +#define IPQ9574_APSS_FUSE_STEP_VOLT 10000 + +static struct cpr3_fuse_param +ipq9574_apss_ro_sel_param[IPQ9574_APSS_FUSE_CORNERS][2] = { + {{107, 4, 7}, {} }, + {{107, 0, 3}, {} }, + {{106, 4, 7}, {} }, + {{106, 0, 3}, {} }, +}; + +static struct cpr3_fuse_param +ipq9574_apss_init_voltage_param[IPQ9574_APSS_FUSE_CORNERS][2] = { + {{104, 24, 29}, {} }, + {{104, 18, 23}, {} }, + {{104, 12, 17}, {} }, + {{104, 6, 11}, {} }, +}; + +static struct cpr3_fuse_param +ipq9574_apss_target_quot_param[IPQ9574_APSS_FUSE_CORNERS][2] = { + {{106, 32, 43}, {} }, + {{106, 20, 31}, {} }, + {{106, 8, 19}, {} }, + {{106, 44, 55}, {} }, +}; + +static struct cpr3_fuse_param +ipq9574_apss_quot_offset_param[IPQ9574_APSS_FUSE_CORNERS][2] = { + {{} }, + {{105, 48, 55}, {} }, + {{105, 40, 47}, {} }, + {{105, 32, 39}, {} }, +}; + +static struct cpr3_fuse_param ipq9574_cpr_fusing_rev_param[] = { + {107, 8, 10}, + {}, +}; + +static struct cpr3_fuse_param ipq9574_apss_speed_bin_param[] = { + {0, 40, 42}, + {}, +}; + +static struct cpr3_fuse_param ipq9574_cpr_boost_fuse_cfg_param[] = { + {0, 43, 45}, + {}, +}; + +static struct cpr3_fuse_param ipq9574_apss_boost_fuse_volt_param[] = { + {104, 0, 5}, + {}, +}; + +static struct cpr3_fuse_param ipq9574_misc_fuse_volt_adj_param[] = { + {0, 54, 54}, + {}, +}; + +static struct cpr3_fuse_parameters ipq9574_fuse_params = { + .apss_ro_sel_param = ipq9574_apss_ro_sel_param, + .apss_init_voltage_param = ipq9574_apss_init_voltage_param, + .apss_target_quot_param = ipq9574_apss_target_quot_param, + .apss_quot_offset_param = ipq9574_apss_quot_offset_param, + .cpr_fusing_rev_param = ipq9574_cpr_fusing_rev_param, + .apss_speed_bin_param = ipq9574_apss_speed_bin_param, + .cpr_boost_fuse_cfg_param = ipq9574_cpr_boost_fuse_cfg_param, + .apss_boost_fuse_volt_param = ipq9574_apss_boost_fuse_volt_param, + .misc_fuse_volt_adj_param = ipq9574_misc_fuse_volt_adj_param +}; + +/* + * Open loop voltage fuse reference voltages in microvolts for IPQ9574 + */ +static int ipq9574_apss_fuse_ref_volt + [IPQ9574_APSS_FUSE_CORNERS] = { + 725000, + 862500, + 987500, + 1062500, +}; + +/** + * cpr4_ipq807x_apss_read_fuse_data() - load APSS specific fuse parameter values + * @vreg: Pointer to the CPR3 regulator + * + * This function allocates a cpr4_ipq807x_apss_fuses struct, fills it with + * values read out of hardware fuses, and finally copies common fuse values + * into the CPR3 regulator struct. + * + * Return: 0 on success, errno on failure + */ +static int cpr4_ipq807x_apss_read_fuse_data(struct cpr3_regulator *vreg) +{ + void __iomem *base = vreg->thread->ctrl->fuse_base; + struct cpr4_ipq807x_apss_fuses *fuse; + int i, rc; + + fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); + if (!fuse) + return -ENOMEM; + + rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->apss_speed_bin_param, + &fuse->speed_bin); + if (rc) { + cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc); + return rc; + } + cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin); + + rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_fusing_rev_param, + &fuse->cpr_fusing_rev); + if (rc) { + cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", + rc); + return rc; + } + cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); + + rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->misc_fuse_volt_adj_param, + &fuse->misc); + if (rc) { + cpr3_err(vreg, "Unable to read misc voltage adjustment fuse, rc=%d\n", + rc); + return rc; + } + cpr3_info(vreg, "CPR misc fuse value = %llu\n", fuse->misc); + if (fuse->misc >= IPQ807x_MISC_FUSE_VAL_COUNT) { + cpr3_err(vreg, "CPR misc fuse value = %llu, should be < %lu\n", + fuse->misc, IPQ807x_MISC_FUSE_VAL_COUNT); + return -EINVAL; + } + + for (i = 0; i < g_valid_fuse_count; i++) { + rc = cpr3_read_fuse_param(base, + vreg->cpr4_regulator_data->cpr3_fuse_params->apss_init_voltage_param[i], + &fuse->init_voltage[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + vreg->cpr4_regulator_data->cpr3_fuse_params->apss_target_quot_param[i], + &fuse->target_quot[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d target quotient fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + vreg->cpr4_regulator_data->cpr3_fuse_params->apss_ro_sel_param[i], + &fuse->ro_sel[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d RO select fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + vreg->cpr4_regulator_data->cpr3_fuse_params->apss_quot_offset_param[i], + &fuse->quot_offset[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d quotient offset fuse, rc=%d\n", + i, rc); + return rc; + } + } + + rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_boost_fuse_cfg_param, + &fuse->boost_cfg); + if (rc) { + cpr3_err(vreg, "Unable to read CPR boost config fuse, rc=%d\n", + rc); + return rc; + } + cpr3_info(vreg, "Voltage boost fuse config = %llu boost = %s\n", + fuse->boost_cfg, boost_fuse[fuse->boost_cfg] + ? "enable" : "disable"); + + rc = cpr3_read_fuse_param(base, + vreg->cpr4_regulator_data->cpr3_fuse_params->apss_boost_fuse_volt_param, + &fuse->boost_voltage); + if (rc) { + cpr3_err(vreg, "failed to read boost fuse voltage, rc=%d\n", + rc); + return rc; + } + + vreg->fuse_combo = fuse->cpr_fusing_rev + 8 * fuse->speed_bin; + if (vreg->fuse_combo >= CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT) { + cpr3_err(vreg, "invalid CPR fuse combo = %d found\n", + vreg->fuse_combo); + return -EINVAL; + } + + vreg->speed_bin_fuse = fuse->speed_bin; + vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; + vreg->fuse_corner_count = g_valid_fuse_count; + vreg->platform_fuses = fuse; + + return 0; +} + +/** + * cpr4_apss_parse_corner_data() - parse APSS corner data from device tree + * properties of the CPR3 regulator's device node + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_parse_corner_data(struct cpr3_regulator *vreg) +{ + struct device_node *node = vreg->of_node; + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + u32 *temp = NULL; + int i, rc; + + rc = cpr3_parse_common_corner_data(vreg); + if (rc) { + cpr3_err(vreg, "error reading corner data, rc=%d\n", rc); + return rc; + } + + /* If fuse has incorrect RO Select values and dtsi has "qcom,cpr-ro-sel" + * entry with RO select values other than zero, then dtsi values will + * be used. + */ + if (of_find_property(node, "qcom,cpr-ro-sel", NULL)) { + temp = kcalloc(vreg->fuse_corner_count, sizeof(*temp), + GFP_KERNEL); + if (!temp) + return -ENOMEM; + + rc = cpr3_parse_array_property(vreg, "qcom,cpr-ro-sel", + vreg->fuse_corner_count, temp); + if (rc) + goto done; + + for (i = 0; i < vreg->fuse_corner_count; i++) { + if (temp[i] != 0) + fuse->ro_sel[i] = temp[i]; + } + } +done: + kfree(temp); + return rc; +} + +/** + * cpr4_apss_parse_misc_fuse_voltage_adjustments() - fill an array from a + * portion of the voltage adjustments specified based on + * miscellaneous fuse bits. + * @vreg: Pointer to the CPR3 regulator + * @volt_adjust: Voltage adjustment output data array which must be + * of size vreg->corner_count + * + * cpr3_parse_common_corner_data() must be called for vreg before this function + * is called so that speed bin size elements are initialized. + * + * Two formats are supported for the device tree property: + * 1. Length == tuple_list_size * vreg->corner_count + * (reading begins at index 0) + * 2. Length == tuple_list_size * vreg->speed_bin_corner_sum + * (reading begins at index tuple_list_size * vreg->speed_bin_offset) + * + * Here, tuple_list_size is the number of possible values for misc fuse. + * All other property lengths are treated as errors. + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_parse_misc_fuse_voltage_adjustments( + struct cpr3_regulator *vreg, u32 *volt_adjust) +{ + struct device_node *node = vreg->of_node; + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + int tuple_list_size = IPQ807x_MISC_FUSE_VAL_COUNT; + int i, offset, rc, len = 0; + const char *prop_name = "qcom,cpr-misc-fuse-voltage-adjustment"; + + if (!of_find_property(node, prop_name, &len)) { + cpr3_err(vreg, "property %s is missing\n", prop_name); + return -EINVAL; + } + + if (len == tuple_list_size * vreg->corner_count * sizeof(u32)) { + offset = 0; + } else if (vreg->speed_bin_corner_sum > 0 && + len == tuple_list_size * vreg->speed_bin_corner_sum + * sizeof(u32)) { + offset = tuple_list_size * vreg->speed_bin_offset + + fuse->misc * vreg->corner_count; + } else { + if (vreg->speed_bin_corner_sum > 0) + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", + prop_name, len, + tuple_list_size * vreg->corner_count + * sizeof(u32), + tuple_list_size * vreg->speed_bin_corner_sum + * sizeof(u32)); + else + cpr3_err(vreg, "property %s has invalid length=%d, should be %zu\n", + prop_name, len, + tuple_list_size * vreg->corner_count + * sizeof(u32)); + return -EINVAL; + } + + for (i = 0; i < vreg->corner_count; i++) { + rc = of_property_read_u32_index(node, prop_name, offset + i, + &volt_adjust[i]); + if (rc) { + cpr3_err(vreg, "error reading property %s, rc=%d\n", + prop_name, rc); + return rc; + } + } + + return 0; +} + +/** + * cpr4_ipq807x_apss_calculate_open_loop_voltages() - calculate the open-loop + * voltage for each corner of a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * + * If open-loop voltage interpolation is allowed in device tree, then + * this function calculates the open-loop voltage for a given corner using + * linear interpolation. This interpolation is performed using the processor + * frequencies of the lower and higher Fmax corners along with their fused + * open-loop voltages. + * + * If open-loop voltage interpolation is not allowed, then this function uses + * the Fmax fused open-loop voltage for all of the corners associated with a + * given fuse corner. + * + * Return: 0 on success, errno on failure + */ +static int cpr4_ipq807x_apss_calculate_open_loop_voltages( + struct cpr3_regulator *vreg) +{ + struct device_node *node = vreg->of_node; + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + struct cpr3_controller *ctrl = vreg->thread->ctrl; + int i, j, rc = 0; + bool allow_interpolation; + u64 freq_low, volt_low, freq_high, volt_high; + int *fuse_volt, *misc_adj_volt; + int *fmax_corner; + + fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt), + GFP_KERNEL); + fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), + GFP_KERNEL); + if (!fuse_volt || !fmax_corner) { + rc = -ENOMEM; + goto done; + } + + for (i = 0; i < vreg->fuse_corner_count; i++) { + if (ctrl->cpr_global_setting == CPR_DISABLED) + fuse_volt[i] = vreg->cpr4_regulator_data->fuse_ref_volt[i]; + else + fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( + vreg->cpr4_regulator_data->fuse_ref_volt[i], + vreg->cpr4_regulator_data->fuse_step_volt, + fuse->init_voltage[i], + IPQ807x_APSS_VOLTAGE_FUSE_SIZE); + + /* Log fused open-loop voltage values for debugging purposes. */ + cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", + cpr4_ipq807x_apss_fuse_corner_name[i], + fuse_volt[i]); + } + + rc = cpr3_determine_part_type(vreg, + fuse_volt[vreg->fuse_corner_count - 1]); + if (rc) { + cpr3_err(vreg, "fused part type detection failed failed, rc=%d\n", + rc); + goto done; + } + + rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt); + if (rc) { + cpr3_err(vreg, "fused open-loop voltage adjustment failed, rc=%d\n", + rc); + goto done; + } + + allow_interpolation = of_property_read_bool(node, + "qcom,allow-voltage-interpolation"); + + for (i = 1; i < vreg->fuse_corner_count; i++) { + if (fuse_volt[i] < fuse_volt[i - 1]) { + cpr3_info(vreg, "fuse corner %d voltage=%d uV < fuse corner %d voltage=%d uV; overriding: fuse corner %d voltage=%d\n", + i, fuse_volt[i], i - 1, fuse_volt[i - 1], + i, fuse_volt[i - 1]); + fuse_volt[i] = fuse_volt[i - 1]; + } + } + + if (!allow_interpolation) { + /* Use fused open-loop voltage for lower frequencies. */ + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].open_loop_volt + = fuse_volt[vreg->corner[i].cpr_fuse_corner]; + goto done; + } + + /* Determine highest corner mapped to each fuse corner */ + j = vreg->fuse_corner_count - 1; + for (i = vreg->corner_count - 1; i >= 0; i--) { + if (vreg->corner[i].cpr_fuse_corner == j) { + fmax_corner[j] = i; + j--; + } + } + if (j >= 0) { + cpr3_err(vreg, "invalid fuse corner mapping\n"); + rc = -EINVAL; + goto done; + } + + /* + * Interpolation is not possible for corners mapped to the lowest fuse + * corner so use the fuse corner value directly. + */ + for (i = 0; i <= fmax_corner[0]; i++) + vreg->corner[i].open_loop_volt = fuse_volt[0]; + + /* Interpolate voltages for the higher fuse corners. */ + for (i = 1; i < vreg->fuse_corner_count; i++) { + freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; + volt_low = fuse_volt[i - 1]; + freq_high = vreg->corner[fmax_corner[i]].proc_freq; + volt_high = fuse_volt[i]; + + for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) + vreg->corner[j].open_loop_volt = cpr3_interpolate( + freq_low, volt_low, freq_high, volt_high, + vreg->corner[j].proc_freq); + } + +done: + if (rc == 0) { + cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n"); + for (i = 0; i < vreg->corner_count; i++) + cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i, + vreg->corner[i].open_loop_volt); + + rc = cpr3_adjust_open_loop_voltages(vreg); + if (rc) + cpr3_err(vreg, "open-loop voltage adjustment failed, rc=%d\n", + rc); + + if (of_find_property(node, + "qcom,cpr-misc-fuse-voltage-adjustment", + NULL)) { + misc_adj_volt = kcalloc(vreg->corner_count, + sizeof(*misc_adj_volt), GFP_KERNEL); + if (!misc_adj_volt) { + rc = -ENOMEM; + goto _exit; + } + + rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg, + misc_adj_volt); + if (rc) { + cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n", + rc); + kfree(misc_adj_volt); + goto _exit; + } + + for (i = 0; i < vreg->corner_count; i++) + vreg->corner[i].open_loop_volt + += misc_adj_volt[i]; + kfree(misc_adj_volt); + } + } + +_exit: + kfree(fuse_volt); + kfree(fmax_corner); + return rc; +} + +/** + * cpr4_ipq807x_apss_set_no_interpolation_quotients() - use the fused target + * quotient values for lower frequencies. + * @vreg: Pointer to the CPR3 regulator + * @volt_adjust: Pointer to array of per-corner closed-loop adjustment + * voltages + * @volt_adjust_fuse: Pointer to array of per-fuse-corner closed-loop + * adjustment voltages + * @ro_scale: Pointer to array of per-fuse-corner RO scaling factor + * values with units of QUOT/V + * + * Return: 0 on success, errno on failure + */ +static int cpr4_ipq807x_apss_set_no_interpolation_quotients( + struct cpr3_regulator *vreg, int *volt_adjust, + int *volt_adjust_fuse, int *ro_scale) +{ + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + u32 quot, ro; + int quot_adjust; + int i, fuse_corner; + + for (i = 0; i < vreg->corner_count; i++) { + fuse_corner = vreg->corner[i].cpr_fuse_corner; + quot = fuse->target_quot[fuse_corner]; + quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner], + volt_adjust_fuse[fuse_corner] + + volt_adjust[i]); + ro = fuse->ro_sel[fuse_corner]; + vreg->corner[i].target_quot[ro] = quot + quot_adjust; + cpr3_debug(vreg, "corner=%d RO=%u target quot=%u\n", + i, ro, quot); + + if (quot_adjust) + cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %u --> %u (%d uV)\n", + i, ro, quot, vreg->corner[i].target_quot[ro], + volt_adjust_fuse[fuse_corner] + + volt_adjust[i]); + } + + return 0; +} + +/** + * cpr4_ipq807x_apss_calculate_target_quotients() - calculate the CPR target + * quotient for each corner of a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * + * If target quotient interpolation is allowed in device tree, then this + * function calculates the target quotient for a given corner using linear + * interpolation. This interpolation is performed using the processor + * frequencies of the lower and higher Fmax corners along with the fused + * target quotient and quotient offset of the higher Fmax corner. + * + * If target quotient interpolation is not allowed, then this function uses + * the Fmax fused target quotient for all of the corners associated with a + * given fuse corner. + * + * Return: 0 on success, errno on failure + */ +static int cpr4_ipq807x_apss_calculate_target_quotients( + struct cpr3_regulator *vreg) +{ + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + int rc; + bool allow_interpolation; + u64 freq_low, freq_high, prev_quot; + u64 *quot_low; + u64 *quot_high; + u32 quot, ro; + int i, j, fuse_corner, quot_adjust; + int *fmax_corner; + int *volt_adjust, *volt_adjust_fuse, *ro_scale; + int *voltage_adj_misc; + + /* Log fused quotient values for debugging purposes. */ + for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS; + i < vreg->fuse_corner_count; i++) + cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu, quot_offset[%2llu]=%4llu\n", + cpr4_ipq807x_apss_fuse_corner_name[i], + fuse->ro_sel[i], fuse->target_quot[i], + fuse->ro_sel[i], fuse->quot_offset[i] * + IPQ807x_APSS_QUOT_OFFSET_SCALE); + + allow_interpolation = of_property_read_bool(vreg->of_node, + "qcom,allow-quotient-interpolation"); + + volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), + GFP_KERNEL); + volt_adjust_fuse = kcalloc(vreg->fuse_corner_count, + sizeof(*volt_adjust_fuse), GFP_KERNEL); + ro_scale = kcalloc(vreg->fuse_corner_count, sizeof(*ro_scale), + GFP_KERNEL); + fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), + GFP_KERNEL); + quot_low = kcalloc(vreg->fuse_corner_count, sizeof(*quot_low), + GFP_KERNEL); + quot_high = kcalloc(vreg->fuse_corner_count, sizeof(*quot_high), + GFP_KERNEL); + if (!volt_adjust || !volt_adjust_fuse || !ro_scale || + !fmax_corner || !quot_low || !quot_high) { + rc = -ENOMEM; + goto done; + } + + rc = cpr3_parse_closed_loop_voltage_adjustments(vreg, &fuse->ro_sel[0], + volt_adjust, volt_adjust_fuse, ro_scale); + if (rc) { + cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", + rc); + goto done; + } + + if (of_find_property(vreg->of_node, + "qcom,cpr-misc-fuse-voltage-adjustment", NULL)) { + voltage_adj_misc = kcalloc(vreg->corner_count, + sizeof(*voltage_adj_misc), GFP_KERNEL); + if (!voltage_adj_misc) { + rc = -ENOMEM; + goto done; + } + + rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg, + voltage_adj_misc); + if (rc) { + cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n", + rc); + kfree(voltage_adj_misc); + goto done; + } + + for (i = 0; i < vreg->corner_count; i++) + volt_adjust[i] += voltage_adj_misc[i]; + + kfree(voltage_adj_misc); + } + + if (!allow_interpolation) { + /* Use fused target quotients for lower frequencies. */ + return cpr4_ipq807x_apss_set_no_interpolation_quotients( + vreg, volt_adjust, volt_adjust_fuse, ro_scale); + } + + /* Determine highest corner mapped to each fuse corner */ + j = vreg->fuse_corner_count - 1; + for (i = vreg->corner_count - 1; i >= 0; i--) { + if (vreg->corner[i].cpr_fuse_corner == j) { + fmax_corner[j] = i; + j--; + } + } + if (j >= 0) { + cpr3_err(vreg, "invalid fuse corner mapping\n"); + rc = -EINVAL; + goto done; + } + + /* + * Interpolation is not possible for corners mapped to the lowest fuse + * corner so use the fuse corner value directly. + */ + i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS; + quot_adjust = cpr3_quot_adjustment(ro_scale[i], volt_adjust_fuse[i]); + quot = fuse->target_quot[i] + quot_adjust; + quot_high[i] = quot_low[i] = quot; + ro = fuse->ro_sel[i]; + if (quot_adjust) + cpr3_debug(vreg, "adjusted fuse corner %d RO%u target quot: %llu --> %u (%d uV)\n", + i, ro, fuse->target_quot[i], quot, volt_adjust_fuse[i]); + + for (i = 0; i <= fmax_corner[CPR4_IPQ807x_APSS_FUSE_CORNER_SVS]; + i++) + vreg->corner[i].target_quot[ro] = quot; + + for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_NOM; + i < vreg->fuse_corner_count; i++) { + quot_high[i] = fuse->target_quot[i]; + if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) + quot_low[i] = quot_high[i - 1]; + else + quot_low[i] = quot_high[i] + - fuse->quot_offset[i] + * IPQ807x_APSS_QUOT_OFFSET_SCALE; + if (quot_high[i] < quot_low[i]) { + cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu; overriding: quot_high[%d]=%llu\n", + i, quot_high[i], i, quot_low[i], + i, quot_low[i]); + quot_high[i] = quot_low[i]; + } + } + + /* Perform per-fuse-corner target quotient adjustment */ + for (i = 1; i < vreg->fuse_corner_count; i++) { + quot_adjust = cpr3_quot_adjustment(ro_scale[i], + volt_adjust_fuse[i]); + if (quot_adjust) { + prev_quot = quot_high[i]; + quot_high[i] += quot_adjust; + cpr3_debug(vreg, "adjusted fuse corner %d RO%llu target quot: %llu --> %llu (%d uV)\n", + i, fuse->ro_sel[i], prev_quot, quot_high[i], + volt_adjust_fuse[i]); + } + + if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) + quot_low[i] = quot_high[i - 1]; + else + quot_low[i] += cpr3_quot_adjustment(ro_scale[i], + volt_adjust_fuse[i - 1]); + + if (quot_high[i] < quot_low[i]) { + cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu after adjustment; overriding: quot_high[%d]=%llu\n", + i, quot_high[i], i, quot_low[i], + i, quot_low[i]); + quot_high[i] = quot_low[i]; + } + } + + /* Interpolate voltages for the higher fuse corners. */ + for (i = 1; i < vreg->fuse_corner_count; i++) { + freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; + freq_high = vreg->corner[fmax_corner[i]].proc_freq; + + ro = fuse->ro_sel[i]; + for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) + vreg->corner[j].target_quot[ro] = cpr3_interpolate( + freq_low, quot_low[i], freq_high, quot_high[i], + vreg->corner[j].proc_freq); + } + + /* Perform per-corner target quotient adjustment */ + for (i = 0; i < vreg->corner_count; i++) { + fuse_corner = vreg->corner[i].cpr_fuse_corner; + ro = fuse->ro_sel[fuse_corner]; + quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner], + volt_adjust[i]); + if (quot_adjust) { + prev_quot = vreg->corner[i].target_quot[ro]; + vreg->corner[i].target_quot[ro] += quot_adjust; + cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %llu --> %u (%d uV)\n", + i, ro, prev_quot, + vreg->corner[i].target_quot[ro], + volt_adjust[i]); + } + } + + /* Ensure that target quotients increase monotonically */ + for (i = 1; i < vreg->corner_count; i++) { + ro = fuse->ro_sel[vreg->corner[i].cpr_fuse_corner]; + if (fuse->ro_sel[vreg->corner[i - 1].cpr_fuse_corner] == ro + && vreg->corner[i].target_quot[ro] + < vreg->corner[i - 1].target_quot[ro]) { + cpr3_debug(vreg, "adjusted corner %d RO%u target quot=%u < adjusted corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", + i, ro, vreg->corner[i].target_quot[ro], + i - 1, ro, vreg->corner[i - 1].target_quot[ro], + i, ro, vreg->corner[i - 1].target_quot[ro]); + vreg->corner[i].target_quot[ro] + = vreg->corner[i - 1].target_quot[ro]; + } + } + +done: + kfree(volt_adjust); + kfree(volt_adjust_fuse); + kfree(ro_scale); + kfree(fmax_corner); + kfree(quot_low); + kfree(quot_high); + return rc; +} + +/** + * cpr4_apss_print_settings() - print out APSS CPR configuration settings into + * the kernel log for debugging purposes + * @vreg: Pointer to the CPR3 regulator + */ +static void cpr4_apss_print_settings(struct cpr3_regulator *vreg) +{ + struct cpr3_corner *corner; + int i; + + cpr3_debug(vreg, "Corner: Frequency (Hz), Fuse Corner, Floor (uV), Open-Loop (uV), Ceiling (uV)\n"); + for (i = 0; i < vreg->corner_count; i++) { + corner = &vreg->corner[i]; + cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n", + i, corner->proc_freq, corner->cpr_fuse_corner, + corner->floor_volt, corner->open_loop_volt, + corner->ceiling_volt); + } + + if (vreg->thread->ctrl->apm) + cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n", + vreg->thread->ctrl->apm_threshold_volt, + vreg->thread->ctrl->apm_adj_volt); +} + +/** + * cpr4_apss_init_thread() - perform steps necessary to initialize the + * configuration data for a CPR3 thread + * @thread: Pointer to the CPR3 thread + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_init_thread(struct cpr3_thread *thread) +{ + int rc; + + rc = cpr3_parse_common_thread_data(thread); + if (rc) { + cpr3_err(thread->ctrl, "thread %u unable to read CPR thread data from device tree, rc=%d\n", + thread->thread_id, rc); + return rc; + } + + return 0; +} + +/** + * cpr4_apss_parse_temp_adj_properties() - parse temperature based + * adjustment properties from device tree. + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_parse_temp_adj_properties(struct cpr3_controller *ctrl) +{ + struct device_node *of_node = ctrl->dev->of_node; + int rc, i, len, temp_point_count; + + if (!of_find_property(of_node, "qcom,cpr-temp-point-map", &len)) { + /* + * Temperature based adjustments are not defined. Single + * temperature band is still valid for per-online-core + * adjustments. + */ + ctrl->temp_band_count = 1; + return 0; + } + + temp_point_count = len / sizeof(u32); + if (temp_point_count <= 0 || + temp_point_count > IPQ807x_APSS_MAX_TEMP_POINTS) { + cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n", + temp_point_count, IPQ807x_APSS_MAX_TEMP_POINTS); + return -EINVAL; + } + + ctrl->temp_points = devm_kcalloc(ctrl->dev, temp_point_count, + sizeof(*ctrl->temp_points), GFP_KERNEL); + if (!ctrl->temp_points) + return -ENOMEM; + + rc = of_property_read_u32_array(of_node, "qcom,cpr-temp-point-map", + ctrl->temp_points, temp_point_count); + if (rc) { + cpr3_err(ctrl, "error reading property qcom,cpr-temp-point-map, rc=%d\n", + rc); + return rc; + } + + for (i = 0; i < temp_point_count; i++) + cpr3_debug(ctrl, "Temperature Point %d=%d\n", i, + ctrl->temp_points[i]); + + /* + * If t1, t2, and t3 are the temperature points, then the temperature + * bands are: (-inf, t1], (t1, t2], (t2, t3], and (t3, inf). + */ + ctrl->temp_band_count = temp_point_count + 1; + cpr3_debug(ctrl, "Number of temp bands =%d\n", ctrl->temp_band_count); + + rc = of_property_read_u32(of_node, "qcom,cpr-initial-temp-band", + &ctrl->initial_temp_band); + if (rc) { + cpr3_err(ctrl, "error reading qcom,cpr-initial-temp-band, rc=%d\n", + rc); + return rc; + } + + if (ctrl->initial_temp_band >= ctrl->temp_band_count) { + cpr3_err(ctrl, "Initial temperature band value %d should be in range [0 - %d]\n", + ctrl->initial_temp_band, ctrl->temp_band_count - 1); + return -EINVAL; + } + + ctrl->temp_sensor_id_start = IPQ807x_APSS_TEMP_SENSOR_ID_START; + ctrl->temp_sensor_id_end = IPQ807x_APSS_TEMP_SENSOR_ID_END; + ctrl->allow_temp_adj = true; + return rc; +} + +/** + * cpr4_apss_parse_boost_properties() - parse configuration data for boost + * voltage adjustment for CPR3 regulator from device tree. + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_parse_boost_properties(struct cpr3_regulator *vreg) +{ + struct cpr3_controller *ctrl = vreg->thread->ctrl; + struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; + struct cpr3_corner *corner; + int i, boost_voltage, final_boost_volt, rc = 0; + int *boost_table = NULL, *boost_temp_adj = NULL; + int boost_voltage_adjust = 0, boost_num_cores = 0; + u32 boost_allowed = 0; + + if (!boost_fuse[fuse->boost_cfg]) + /* Voltage boost is disabled in fuse */ + return 0; + + if (of_find_property(vreg->of_node, "qcom,allow-boost", NULL)) { + rc = cpr3_parse_array_property(vreg, "qcom,allow-boost", 1, + &boost_allowed); + if (rc) + return rc; + } + + if (!boost_allowed) { + /* Voltage boost is not enabled for this regulator */ + return 0; + } + + boost_voltage = cpr3_convert_open_loop_voltage_fuse( + vreg->cpr4_regulator_data->boost_fuse_ref_volt, + vreg->cpr4_regulator_data->fuse_step_volt, + fuse->boost_voltage, + IPQ807x_APSS_VOLTAGE_FUSE_SIZE); + + /* Log boost voltage value for debugging purposes. */ + cpr3_info(vreg, "Boost open-loop=%7d uV\n", boost_voltage); + + if (of_find_property(vreg->of_node, + "qcom,cpr-boost-voltage-fuse-adjustment", NULL)) { + rc = cpr3_parse_array_property(vreg, + "qcom,cpr-boost-voltage-fuse-adjustment", + 1, &boost_voltage_adjust); + if (rc) { + cpr3_err(vreg, "qcom,cpr-boost-voltage-fuse-adjustment reading failed, rc=%d\n", + rc); + return rc; + } + + boost_voltage += boost_voltage_adjust; + /* Log boost voltage value for debugging purposes. */ + cpr3_info(vreg, "Adjusted boost open-loop=%7d uV\n", + boost_voltage); + } + + /* Limit boost voltage value between ceiling and floor voltage limits */ + boost_voltage = min(boost_voltage, vreg->cpr4_regulator_data->boost_ceiling_volt); + boost_voltage = max(boost_voltage, vreg->cpr4_regulator_data->boost_floor_volt); + + /* + * The boost feature can only be used for the highest voltage corner. + * Also, keep core-count adjustments disabled when the boost feature + * is enabled. + */ + corner = &vreg->corner[vreg->corner_count - 1]; + if (!corner->sdelta) { + /* + * If core-count/temp adjustments are not defined, the cpr4 + * sdelta for this corner will not be allocated. Allocate it + * here for boost configuration. + */ + corner->sdelta = devm_kzalloc(ctrl->dev, + sizeof(*corner->sdelta), GFP_KERNEL); + if (!corner->sdelta) + return -ENOMEM; + } + corner->sdelta->temp_band_count = ctrl->temp_band_count; + + rc = of_property_read_u32(vreg->of_node, "qcom,cpr-num-boost-cores", + &boost_num_cores); + if (rc) { + cpr3_err(vreg, "qcom,cpr-num-boost-cores reading failed, rc=%d\n", + rc); + return rc; + } + + if (boost_num_cores <= 0 || + boost_num_cores > IPQ807x_APSS_CPR_SDELTA_CORE_COUNT) { + cpr3_err(vreg, "Invalid boost number of cores = %d\n", + boost_num_cores); + return -EINVAL; + } + corner->sdelta->boost_num_cores = boost_num_cores; + + boost_table = devm_kcalloc(ctrl->dev, corner->sdelta->temp_band_count, + sizeof(*boost_table), GFP_KERNEL); + if (!boost_table) + return -ENOMEM; + + if (of_find_property(vreg->of_node, + "qcom,cpr-boost-temp-adjustment", NULL)) { + boost_temp_adj = kcalloc(corner->sdelta->temp_band_count, + sizeof(*boost_temp_adj), GFP_KERNEL); + if (!boost_temp_adj) + return -ENOMEM; + + rc = cpr3_parse_array_property(vreg, + "qcom,cpr-boost-temp-adjustment", + corner->sdelta->temp_band_count, + boost_temp_adj); + if (rc) { + cpr3_err(vreg, "qcom,cpr-boost-temp-adjustment reading failed, rc=%d\n", + rc); + goto done; + } + } + + for (i = 0; i < corner->sdelta->temp_band_count; i++) { + /* Apply static adjustments to boost voltage */ + final_boost_volt = boost_voltage + (boost_temp_adj == NULL + ? 0 : boost_temp_adj[i]); + /* + * Limit final adjusted boost voltage value between ceiling + * and floor voltage limits + */ + final_boost_volt = min(final_boost_volt, + vreg->cpr4_regulator_data->boost_ceiling_volt); + final_boost_volt = max(final_boost_volt, + vreg->cpr4_regulator_data->boost_floor_volt); + + boost_table[i] = (corner->open_loop_volt - final_boost_volt) + / ctrl->step_volt; + cpr3_debug(vreg, "Adjusted boost voltage margin for temp band %d = %d steps\n", + i, boost_table[i]); + } + + corner->ceiling_volt = vreg->cpr4_regulator_data->boost_ceiling_volt; + corner->sdelta->boost_table = boost_table; + corner->sdelta->allow_boost = true; + corner->sdelta->allow_core_count_adj = false; + vreg->allow_boost = true; + ctrl->allow_boost = true; +done: + kfree(boost_temp_adj); + return rc; +} + +/** + * cpr4_apss_init_regulator() - perform all steps necessary to initialize the + * configuration data for a CPR3 regulator + * @vreg: Pointer to the CPR3 regulator + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_init_regulator(struct cpr3_regulator *vreg) +{ + struct cpr4_ipq807x_apss_fuses *fuse; + int rc; + + rc = cpr4_ipq807x_apss_read_fuse_data(vreg); + if (rc) { + cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); + return rc; + } + + fuse = vreg->platform_fuses; + + rc = cpr4_apss_parse_corner_data(vreg); + if (rc) { + cpr3_err(vreg, "unable to read CPR corner data from device tree, rc=%d\n", + rc); + return rc; + } + + rc = cpr3_mem_acc_init(vreg); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(vreg, "unable to initialize mem-acc regulator settings, rc=%d\n", + rc); + return rc; + } + + rc = cpr4_ipq807x_apss_calculate_open_loop_voltages(vreg); + if (rc) { + cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", + rc); + return rc; + } + + rc = cpr3_limit_open_loop_voltages(vreg); + if (rc) { + cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n", + rc); + return rc; + } + + cpr3_open_loop_voltage_as_ceiling(vreg); + + rc = cpr3_limit_floor_voltages(vreg); + if (rc) { + cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc); + return rc; + } + + rc = cpr4_ipq807x_apss_calculate_target_quotients(vreg); + if (rc) { + cpr3_err(vreg, "unable to calculate target quotients, rc=%d\n", + rc); + return rc; + } + + rc = cpr4_parse_core_count_temp_voltage_adj(vreg, false); + if (rc) { + cpr3_err(vreg, "unable to parse temperature and core count voltage adjustments, rc=%d\n", + rc); + return rc; + } + + if (vreg->allow_core_count_adj && (vreg->max_core_count <= 0 + || vreg->max_core_count > + IPQ807x_APSS_CPR_SDELTA_CORE_COUNT)) { + cpr3_err(vreg, "qcom,max-core-count has invalid value = %d\n", + vreg->max_core_count); + return -EINVAL; + } + + rc = cpr4_apss_parse_boost_properties(vreg); + if (rc) { + cpr3_err(vreg, "unable to parse boost adjustments, rc=%d\n", + rc); + return rc; + } + + cpr4_apss_print_settings(vreg); + + return rc; +} + +/** + * cpr4_apss_init_controller() - perform APSS CPR4 controller specific + * initializations + * @ctrl: Pointer to the CPR3 controller + * + * Return: 0 on success, errno on failure + */ +static int cpr4_apss_init_controller(struct cpr3_controller *ctrl) +{ + int rc; + + rc = cpr3_parse_common_ctrl_data(ctrl); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n", + rc); + return rc; + } + + rc = of_property_read_u32(ctrl->dev->of_node, + "qcom,cpr-down-error-step-limit", + &ctrl->down_error_step_limit); + if (rc) { + cpr3_err(ctrl, "error reading qcom,cpr-down-error-step-limit, rc=%d\n", + rc); + return rc; + } + + rc = of_property_read_u32(ctrl->dev->of_node, + "qcom,cpr-up-error-step-limit", + &ctrl->up_error_step_limit); + if (rc) { + cpr3_err(ctrl, "error reading qcom,cpr-up-error-step-limit, rc=%d\n", + rc); + return rc; + } + + /* + * Use fixed step quotient if specified otherwise use dynamic + * calculated per RO step quotient + */ + of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-step-quot-fixed", + &ctrl->step_quot_fixed); + ctrl->use_dynamic_step_quot = ctrl->step_quot_fixed ? false : true; + + ctrl->saw_use_unit_mV = of_property_read_bool(ctrl->dev->of_node, + "qcom,cpr-saw-use-unit-mV"); + + of_property_read_u32(ctrl->dev->of_node, + "qcom,cpr-voltage-settling-time", + &ctrl->voltage_settling_time); + + if (of_find_property(ctrl->dev->of_node, "vdd-limit-supply", NULL)) { + ctrl->vdd_limit_regulator = + devm_regulator_get(ctrl->dev, "vdd-limit"); + if (IS_ERR(ctrl->vdd_limit_regulator)) { + rc = PTR_ERR(ctrl->vdd_limit_regulator); + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to request vdd-limit regulator, rc=%d\n", + rc); + return rc; + } + } + + rc = cpr3_apm_init(ctrl); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "unable to initialize APM settings, rc=%d\n", + rc); + return rc; + } + + rc = cpr4_apss_parse_temp_adj_properties(ctrl); + if (rc) { + cpr3_err(ctrl, "unable to parse temperature adjustment properties, rc=%d\n", + rc); + return rc; + } + + ctrl->sensor_count = IPQ807x_APSS_CPR_SENSOR_COUNT; + + /* + * APSS only has one thread (0) per controller so the zeroed + * array does not need further modification. + */ + ctrl->sensor_owner = devm_kcalloc(ctrl->dev, ctrl->sensor_count, + sizeof(*ctrl->sensor_owner), GFP_KERNEL); + if (!ctrl->sensor_owner) + return -ENOMEM; + + ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4; + ctrl->supports_hw_closed_loop = false; + ctrl->use_hw_closed_loop = of_property_read_bool(ctrl->dev->of_node, + "qcom,cpr-hw-closed-loop"); + return 0; +} + +static int cpr4_apss_regulator_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct cpr3_controller *ctrl = platform_get_drvdata(pdev); + + return cpr3_regulator_suspend(ctrl); +} + +static int cpr4_apss_regulator_resume(struct platform_device *pdev) +{ + struct cpr3_controller *ctrl = platform_get_drvdata(pdev); + + return cpr3_regulator_resume(ctrl); +} + +static void ipq6018_set_mem_acc(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + + ipq6018_mem_acc_tcsr[0].ioremap_addr = + ioremap(ipq6018_mem_acc_tcsr[0].phy_addr, 0x4); + ipq6018_mem_acc_tcsr[1].ioremap_addr = + ioremap(ipq6018_mem_acc_tcsr[1].phy_addr, 0x4); + + if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) && + (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) && + (vreg->current_corner == (vreg->corner_count - CPR3_CORNER_OFFSET))) { + + writel_relaxed(ipq6018_mem_acc_tcsr[0].value, + ipq6018_mem_acc_tcsr[0].ioremap_addr); + writel_relaxed(ipq6018_mem_acc_tcsr[1].value, + ipq6018_mem_acc_tcsr[1].ioremap_addr); + } +} + +static void ipq6018_clr_mem_acc(struct regulator_dev *rdev) +{ + struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); + + if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) && + (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) && + (vreg->current_corner != vreg->corner_count - CPR3_CORNER_OFFSET)) { + writel_relaxed(0x0, ipq6018_mem_acc_tcsr[0].ioremap_addr); + writel_relaxed(0x0, ipq6018_mem_acc_tcsr[1].ioremap_addr); + } + + iounmap(ipq6018_mem_acc_tcsr[0].ioremap_addr); + iounmap(ipq6018_mem_acc_tcsr[1].ioremap_addr); +} + +static struct cpr4_mem_acc_func ipq6018_mem_acc_funcs = { + .set_mem_acc = ipq6018_set_mem_acc, + .clear_mem_acc = ipq6018_clr_mem_acc +}; + +static const struct cpr4_reg_data ipq807x_cpr_apss = { + .cpr_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS, + .fuse_ref_volt = ipq807x_apss_fuse_ref_volt, + .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE, + .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT, + .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT, + .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT, + .cpr3_fuse_params = &ipq807x_fuse_params, + .mem_acc_funcs = NULL, +}; + +static const struct cpr4_reg_data ipq817x_cpr_apss = { + .cpr_valid_fuse_count = IPQ817x_APPS_FUSE_CORNERS, + .fuse_ref_volt = ipq807x_apss_fuse_ref_volt, + .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE, + .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT, + .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT, + .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT, + .cpr3_fuse_params = &ipq807x_fuse_params, + .mem_acc_funcs = NULL, +}; + +static const struct cpr4_reg_data ipq6018_cpr_apss = { + .cpr_valid_fuse_count = IPQ6018_APSS_FUSE_CORNERS, + .fuse_ref_volt = ipq6018_apss_fuse_ref_volt, + .fuse_step_volt = IPQ6018_APSS_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE, + .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT, + .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT, + .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT, + .cpr3_fuse_params = &ipq6018_fuse_params, + .mem_acc_funcs = &ipq6018_mem_acc_funcs, +}; + +static const struct cpr4_reg_data ipq9574_cpr_apss = { + .cpr_valid_fuse_count = IPQ9574_APSS_FUSE_CORNERS, + .fuse_ref_volt = ipq9574_apss_fuse_ref_volt, + .fuse_step_volt = IPQ9574_APSS_FUSE_STEP_VOLT, + .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE, + .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT, + .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT, + .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT, + .cpr3_fuse_params = &ipq9574_fuse_params, + .mem_acc_funcs = NULL, +}; + +static struct of_device_id cpr4_regulator_match_table[] = { + { + .compatible = "qcom,cpr4-ipq807x-apss-regulator", + .data = &ipq807x_cpr_apss + }, + { + .compatible = "qcom,cpr4-ipq817x-apss-regulator", + .data = &ipq817x_cpr_apss + }, + { + .compatible = "qcom,cpr4-ipq6018-apss-regulator", + .data = &ipq6018_cpr_apss + }, + { + .compatible = "qcom,cpr4-ipq9574-apss-regulator", + .data = &ipq9574_cpr_apss + }, + {} +}; + +static int cpr4_apss_regulator_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cpr3_controller *ctrl; + const struct of_device_id *match; + struct cpr4_reg_data *cpr_data; + int i, rc; + + if (!dev->of_node) { + dev_err(dev, "Device tree node is missing\n"); + return -EINVAL; + } + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + match = of_match_device(cpr4_regulator_match_table, &pdev->dev); + if (!match) + return -ENODEV; + + cpr_data = (struct cpr4_reg_data *)match->data; + g_valid_fuse_count = cpr_data->cpr_valid_fuse_count; + dev_info(dev, "CPR valid fuse count: %d\n", g_valid_fuse_count); + ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate; + + ctrl->dev = dev; + /* Set to false later if anything precludes CPR operation. */ + ctrl->cpr_allowed_hw = true; + + rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name", + &ctrl->name); + if (rc) { + cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n", + rc); + return rc; + } + + rc = cpr3_map_fuse_base(ctrl, pdev); + if (rc) { + cpr3_err(ctrl, "could not map fuse base address\n"); + return rc; + } + + rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_APSS_CPR_TCSR_START, + IPQ807x_APSS_CPR_TCSR_END); + if (rc) { + cpr3_err(ctrl, "could not read CPR tcsr setting\n"); + return rc; + } + + rc = cpr3_allocate_threads(ctrl, 0, 0); + if (rc) { + cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n", + rc); + return rc; + } + + if (ctrl->thread_count != 1) { + cpr3_err(ctrl, "expected 1 thread but found %d\n", + ctrl->thread_count); + return -EINVAL; + } + + rc = cpr4_apss_init_controller(ctrl); + if (rc) { + if (rc != -EPROBE_DEFER) + cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n", + rc); + return rc; + } + + rc = cpr4_apss_init_thread(&ctrl->thread[0]); + if (rc) { + cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc); + return rc; + } + + for (i = 0; i < ctrl->thread[0].vreg_count; i++) { + ctrl->thread[0].vreg[i].cpr4_regulator_data = cpr_data; + rc = cpr4_apss_init_regulator(&ctrl->thread[0].vreg[i]); + if (rc) { + cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n", + rc); + return rc; + } + } + + platform_set_drvdata(pdev, ctrl); + + return cpr3_regulator_register(pdev, ctrl); +} + +static int cpr4_apss_regulator_remove(struct platform_device *pdev) +{ + struct cpr3_controller *ctrl = platform_get_drvdata(pdev); + + return cpr3_regulator_unregister(ctrl); +} + +static struct platform_driver cpr4_apss_regulator_driver = { + .driver = { + .name = "qcom,cpr4-apss-regulator", + .of_match_table = cpr4_regulator_match_table, + .owner = THIS_MODULE, + }, + .probe = cpr4_apss_regulator_probe, + .remove = cpr4_apss_regulator_remove, + .suspend = cpr4_apss_regulator_suspend, + .resume = cpr4_apss_regulator_resume, +}; + +static int cpr4_regulator_init(void) +{ + return platform_driver_register(&cpr4_apss_regulator_driver); +} + +static void cpr4_regulator_exit(void) +{ + platform_driver_unregister(&cpr4_apss_regulator_driver); +} + +MODULE_DESCRIPTION("CPR4 APSS regulator driver"); +MODULE_LICENSE("GPL v2"); + +arch_initcall(cpr4_regulator_init); +module_exit(cpr4_regulator_exit); diff --git a/target/linux/ipq807x/files-5.15/include/linux/power/qcom/apm.h b/target/linux/ipq807x/files-5.15/include/linux/power/qcom/apm.h new file mode 100644 index 000000000..432683578 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/include/linux/power/qcom/apm.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_POWER_QCOM_APM_H__ +#define __LINUX_POWER_QCOM_APM_H__ + +#include +#include + +/** + * enum msm_apm_supply - supported power rails to supply memory arrays + * %MSM_APM_SUPPLY_APCC: to enable selection of VDD_APCC rail as supply + * %MSM_APM_SUPPLY_MX: to enable selection of VDD_MX rail as supply + */ +enum msm_apm_supply { + MSM_APM_SUPPLY_APCC, + MSM_APM_SUPPLY_MX, +}; + +/* Handle used to identify an APM controller device */ +struct msm_apm_ctrl_dev; + +#ifdef CONFIG_QCOM_APM +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev); +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, + enum msm_apm_supply supply); +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev); + +#else +static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev) +{ return ERR_PTR(-EPERM); } +static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, + enum msm_apm_supply supply) +{ return -EPERM; } +static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev) +{ return -EPERM; } +#endif +#endif diff --git a/target/linux/ipq807x/files-5.15/include/soc/qcom/socinfo.h b/target/linux/ipq807x/files-5.15/include/soc/qcom/socinfo.h new file mode 100644 index 000000000..db4344616 --- /dev/null +++ b/target/linux/ipq807x/files-5.15/include/soc/qcom/socinfo.h @@ -0,0 +1,463 @@ +/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_ +#define _ARCH_ARM_MACH_MSM_SOCINFO_H_ + +#include + +#define CPU_IPQ8074 323 +#define CPU_IPQ8072 342 +#define CPU_IPQ8076 343 +#define CPU_IPQ8078 344 +#define CPU_IPQ8070 375 +#define CPU_IPQ8071 376 + +#define CPU_IPQ8072A 389 +#define CPU_IPQ8074A 390 +#define CPU_IPQ8076A 391 +#define CPU_IPQ8078A 392 +#define CPU_IPQ8070A 395 +#define CPU_IPQ8071A 396 + +#define CPU_IPQ8172 397 +#define CPU_IPQ8173 398 +#define CPU_IPQ8174 399 + +#define CPU_IPQ6018 402 +#define CPU_IPQ6028 403 +#define CPU_IPQ6000 421 +#define CPU_IPQ6010 422 +#define CPU_IPQ6005 453 + +#define CPU_IPQ5010 446 +#define CPU_IPQ5018 447 +#define CPU_IPQ5028 448 +#define CPU_IPQ5000 503 +#define CPU_IPQ0509 504 +#define CPU_IPQ0518 505 + +#define CPU_IPQ9514 510 +#define CPU_IPQ9554 512 +#define CPU_IPQ9570 513 +#define CPU_IPQ9574 514 +#define CPU_IPQ9550 511 +#define CPU_IPQ9510 521 + +static inline int read_ipq_soc_version_major(void) +{ + const int *prop; + prop = of_get_property(of_find_node_by_path("/"), "soc_version_major", + NULL); + + if (!prop) + return -EINVAL; + + return le32_to_cpu(*prop); +} + +static inline int read_ipq_cpu_type(void) +{ + const int *prop; + prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL); + /* + * Return Default CPU type if "cpu_type" property is not found in DTSI + */ + if (!prop) + return CPU_IPQ8074; + + return le32_to_cpu(*prop); +} + +static inline int cpu_is_ipq8070(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8070; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8071(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8071; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8072(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8072; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8074(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8074; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8076(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8076; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8078(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8078; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8072a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8072A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8074a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8074A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8076a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8076A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8078a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8078A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8070a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8070A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8071a(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8071A; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8172(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8172; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8173(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8173; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq8174(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ8174; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq6018(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ6018; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq6028(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ6028; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq6000(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ6000; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq6010(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ6010; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq6005(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ6005; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq5010(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ5010; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq5018(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ5018; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq5028(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ5028; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq5000(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ5000; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq0509(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ0509; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq0518(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ0518; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9514(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9514; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9554(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9554; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9570(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9570; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9574(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9574; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9550(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9550; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq9510(void) +{ +#ifdef CONFIG_ARCH_QCOM + return read_ipq_cpu_type() == CPU_IPQ9510; +#else + return 0; +#endif +} + +static inline int cpu_is_ipq807x(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq8072() || cpu_is_ipq8074() || + cpu_is_ipq8076() || cpu_is_ipq8078() || + cpu_is_ipq8070() || cpu_is_ipq8071() || + cpu_is_ipq8072a() || cpu_is_ipq8074a() || + cpu_is_ipq8076a() || cpu_is_ipq8078a() || + cpu_is_ipq8070a() || cpu_is_ipq8071a() || + cpu_is_ipq8172() || cpu_is_ipq8173() || + cpu_is_ipq8174(); +#else + return 0; +#endif +} + +static inline int cpu_is_ipq60xx(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq6018() || cpu_is_ipq6028() || + cpu_is_ipq6000() || cpu_is_ipq6010() || + cpu_is_ipq6005(); +#else + return 0; +#endif +} + +static inline int cpu_is_ipq50xx(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq5010() || cpu_is_ipq5018() || + cpu_is_ipq5028() || cpu_is_ipq5000() || + cpu_is_ipq0509() || cpu_is_ipq0518(); +#else + return 0; +#endif +} + +static inline int cpu_is_ipq95xx(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq9514() || cpu_is_ipq9554() || + cpu_is_ipq9570() || cpu_is_ipq9574() || + cpu_is_ipq9550() || cpu_is_ipq9510(); +#else + return 0; +#endif +} + +static inline int cpu_is_nss_crypto_enabled(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq807x() || cpu_is_ipq60xx() || + cpu_is_ipq50xx() || cpu_is_ipq9570() || + cpu_is_ipq9550() || cpu_is_ipq9574() || + cpu_is_ipq9554(); +#else + return 0; +#endif +} + +static inline int cpu_is_internal_wifi_enabled(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq807x() || cpu_is_ipq60xx() || + cpu_is_ipq50xx() || cpu_is_ipq9514() || + cpu_is_ipq9554() || cpu_is_ipq9574(); +#else + return 0; +#endif +} + +static inline int cpu_is_uniphy1_enabled(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq807x() || cpu_is_ipq60xx() || + cpu_is_ipq9554() || cpu_is_ipq9570() || + cpu_is_ipq9574() || cpu_is_ipq9550(); +#else + return 0; +#endif +} + +static inline int cpu_is_uniphy2_enabled(void) +{ +#ifdef CONFIG_ARCH_QCOM + return cpu_is_ipq807x() || cpu_is_ipq9570() || + cpu_is_ipq9574(); +#else + return 0; +#endif +} + +#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */ diff --git a/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch b/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch index 8f11d4276..37af0767f 100644 --- a/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch +++ b/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch @@ -12,11 +12,13 @@ Signed-off-by: Robert Marko --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -3,6 +3,9 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.d +@@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.d dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8072-301w.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax6.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax3600.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8071-mf269.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8078-xtr10890.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb diff --git a/target/linux/ipq807x/patches-5.15/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch b/target/linux/ipq807x/patches-5.15/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch index 9ff451e01..d9515cef2 100644 --- a/target/linux/ipq807x/patches-5.15/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch +++ b/target/linux/ipq807x/patches-5.15/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch @@ -1,7 +1,7 @@ -From 3f3f712b16c7d374cfb079ca83684f12fda7884c Mon Sep 17 00:00:00 2001 +From 63750607afad67e57841689b01a9425822503e0c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 5 Sep 2021 18:58:16 +0200 -Subject: [PATCH 01/44] arm64: dts: qcom: ipq8074: add SPMI bus +Subject: [PATCH] arm64: dts: qcom: ipq8074: add SPMI bus IPQ8074 uses SPMI for communication with the PMIC, so since its already supported add the DT node for it. diff --git a/target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-Update-BAM-DMA-node-name-per-DT-schem.patch b/target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-Update-BAM-DMA-node-name-per-DT-schem.patch deleted file mode 100644 index 1095739d9..000000000 --- a/target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-Update-BAM-DMA-node-name-per-DT-schem.patch +++ /dev/null @@ -1,27 +0,0 @@ -From e5698ba1e94af28e5f54943bcd6de278efc84500 Mon Sep 17 00:00:00 2001 -From: Shawn Guo -Date: Tue, 31 Aug 2021 13:23:25 +0800 -Subject: [PATCH 02/44] arm64: dts: qcom: Update BAM DMA node name per DT - schema - -Follow dma-controller.yaml schema to use `dma-controller` as node name -of BAM DMA devices. - -Signed-off-by: Shawn Guo -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -212,7 +212,7 @@ - status = "disabled"; - }; - -- cryptobam: dma@704000 { -+ cryptobam: dma-controller@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x00704000 0x20000>; - interrupts = ; diff --git a/target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch b/target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch similarity index 90% rename from target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch rename to target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch index 0bd4a9109..e6ddc9ed2 100644 --- a/target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch +++ b/target/linux/ipq807x/patches-5.15/0002-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch @@ -1,7 +1,7 @@ -From 187368d2936edad6342151ae1ac34d95dc2de2c1 Mon Sep 17 00:00:00 2001 +From 9c0bd8e53774c38bd7859ad4af300a5062430925 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 1 Oct 2021 22:54:21 +0800 -Subject: [PATCH 03/44] arm64: dts: qcom: ipq8074: Add QUP5 I2C node +Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node Add node to support the QUP5 I2C controller inside of IPQ8074. It is exactly the same as QUP2 controllers. diff --git a/target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch b/target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch new file mode 100644 index 000000000..7357f806f --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0003-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch @@ -0,0 +1,134 @@ +From 82d61e19fccbf2fe7c018765b3799791916e7f31 Mon Sep 17 00:00:00 2001 +From: Shawn Guo +Date: Wed, 29 Sep 2021 11:42:46 +0800 +Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY + child node + +'#clock-cells' is a required property of QMP PHY child node, not itself. +Move it to fix the dtbs_check warnings. + +There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because +child nodes already have the property. + +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- + arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- + arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 --- + 4 files changed, 5 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -91,7 +91,6 @@ + ssphy_1: phy@58000 { + compatible = "qcom,ipq8074-qmp-usb3-phy"; + reg = <0x00058000 0x1c4>; +- #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -112,6 +111,7 @@ + <0x00058800 0x1f8>, /* PCS */ + <0x00058600 0x044>; /* PCS misc*/ + #phy-cells = <0>; ++ #clock-cells = <1>; + clocks = <&gcc GCC_USB1_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb1_pipe_clk_src"; +@@ -134,7 +134,6 @@ + ssphy_0: phy@78000 { + compatible = "qcom,ipq8074-qmp-usb3-phy"; + reg = <0x00078000 0x1c4>; +- #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -155,6 +154,7 @@ + <0x00078800 0x1f8>, /* PCS */ + <0x00078600 0x044>; /* PCS misc*/ + #phy-cells = <0>; ++ #clock-cells = <1>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi +@@ -582,7 +582,6 @@ + pcie_phy: phy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x00034000 0x488>; +- #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -604,6 +603,7 @@ + <0x00035400 0x1dc>; + #phy-cells = <0>; + ++ #clock-cells = <1>; + clock-output-names = "pcie_0_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; +@@ -2586,7 +2586,6 @@ + usb3phy: phy@7410000 { + compatible = "qcom,msm8996-qmp-usb3-phy"; + reg = <0x07410000 0x1c4>; +- #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -2607,6 +2606,7 @@ + <0x07410600 0x1a8>; + #phy-cells = <0>; + ++ #clock-cells = <1>; + clock-output-names = "usb3_phy_pipe_clk_src"; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; +--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi +@@ -1985,7 +1985,6 @@ + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x18c>; + status = "disabled"; +- #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -2006,6 +2005,7 @@ + <0xc010600 0x128>, + <0xc010800 0x200>; + #phy-cells = <0>; ++ #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; +--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi +@@ -1070,7 +1070,6 @@ + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; +- #clock-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; +@@ -1205,7 +1204,6 @@ + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; +- #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; +@@ -1238,7 +1236,6 @@ + compatible = "qcom,sm8350-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; +- #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; diff --git a/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch b/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch new file mode 100644 index 000000000..8f5f275f1 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch @@ -0,0 +1,273 @@ +From 1351512f29b4348e6b497f6343896c1033d409b4 Mon Sep 17 00:00:00 2001 +From: Shawn Guo +Date: Wed, 29 Sep 2021 11:42:47 +0800 +Subject: [PATCH] arm64: dts: qcom: Correct QMP PHY child node name + +Many child nodes of QMP PHY are named without following bindings schema +and causing dtbs_check warnings like below. + +phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$' + arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml + +Correct them to fix the warnings. + +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- + arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++----- + arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 +++--- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++++----- + arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++--- + arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++++----- + arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- + 8 files changed, 25 insertions(+), 25 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -401,7 +401,7 @@ + reset-names = "phy", + "common"; + +- pcie_phy0: lane@84200 { ++ pcie_phy0: phy@84200 { + reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -105,7 +105,7 @@ + reset-names = "phy","common"; + status = "disabled"; + +- usb1_ssphy: lane@58200 { ++ usb1_ssphy: phy@58200 { + reg = <0x00058200 0x130>, /* Tx */ + <0x00058400 0x200>, /* Rx */ + <0x00058800 0x1f8>, /* PCS */ +@@ -148,7 +148,7 @@ + reset-names = "phy","common"; + status = "disabled"; + +- usb0_ssphy: lane@78200 { ++ usb0_ssphy: phy@78200 { + reg = <0x00078200 0x130>, /* Tx */ + <0x00078400 0x200>, /* Rx */ + <0x00078800 0x1f8>, /* PCS */ +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi +@@ -597,7 +597,7 @@ + reset-names = "phy", "common", "cfg"; + status = "disabled"; + +- pciephy_0: lane@35000 { ++ pciephy_0: phy@35000 { + reg = <0x00035000 0x130>, + <0x00035200 0x200>, + <0x00035400 0x1dc>; +@@ -611,7 +611,7 @@ + reset-names = "lane0"; + }; + +- pciephy_1: lane@36000 { ++ pciephy_1: phy@36000 { + reg = <0x00036000 0x130>, + <0x00036200 0x200>, + <0x00036400 0x1dc>; +@@ -624,7 +624,7 @@ + reset-names = "lane1"; + }; + +- pciephy_2: lane@37000 { ++ pciephy_2: phy@37000 { + reg = <0x00037000 0x130>, + <0x00037200 0x200>, + <0x00037400 0x1dc>; +@@ -1746,7 +1746,7 @@ + reset-names = "ufsphy"; + status = "disabled"; + +- ufsphy_lane: lanes@627400 { ++ ufsphy_lane: phy@627400 { + reg = <0x627400 0x12c>, + <0x627600 0x200>, + <0x627c00 0x1b4>; +@@ -2600,7 +2600,7 @@ + reset-names = "phy", "common"; + status = "disabled"; + +- ssusb_phy_0: lane@7410200 { ++ ssusb_phy_0: phy@7410200 { + reg = <0x07410200 0x200>, + <0x07410400 0x130>, + <0x07410600 0x1a8>; +--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi +@@ -994,7 +994,7 @@ + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + +- pciephy: lane@1c06800 { ++ pciephy: phy@1c06800 { + reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; + #phy-cells = <0>; + +@@ -1066,7 +1066,7 @@ + reset-names = "ufsphy"; + resets = <&ufshc 0>; + +- ufsphy_lanes: lanes@1da7400 { ++ ufsphy_lanes: phy@1da7400 { + reg = <0x01da7400 0x128>, + <0x01da7600 0x1fc>, + <0x01da7c00 0x1dc>, +@@ -1998,7 +1998,7 @@ + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", "common"; + +- usb1_ssphy: lane@c010200 { ++ usb1_ssphy: phy@c010200 { + reg = <0xc010200 0x128>, + <0xc010400 0x200>, + <0xc010c00 0x20c>, +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -2064,7 +2064,7 @@ + + status = "disabled"; + +- pcie0_lane: lanes@1c06200 { ++ pcie0_lane: phy@1c06200 { + reg = <0 0x01c06200 0 0x128>, + <0 0x01c06400 0 0x1fc>, + <0 0x01c06800 0 0x218>, +@@ -2174,7 +2174,7 @@ + + status = "disabled"; + +- pcie1_lane: lanes@1c06200 { ++ pcie1_lane: phy@1c06200 { + reg = <0 0x01c0a800 0 0x800>, + <0 0x01c0a800 0 0x800>, + <0 0x01c0b800 0 0x400>; +@@ -2302,7 +2302,7 @@ + reset-names = "ufsphy"; + status = "disabled"; + +- ufs_mem_phy_lanes: lanes@1d87400 { ++ ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, +@@ -3699,7 +3699,7 @@ + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + +- usb_1_ssphy: lanes@88e9200 { ++ usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x128>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, +@@ -3732,7 +3732,7 @@ + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + +- usb_2_ssphy: lane@88eb200 { ++ usb_2_ssphy: phy@88eb200 { + reg = <0 0x088eb200 0 0x128>, + <0 0x088eb400 0 0x1fc>, + <0 0x088eb800 0 0x218>, +--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi +@@ -1692,7 +1692,7 @@ + reset-names = "ufsphy"; + status = "disabled"; + +- ufs_mem_phy_lanes: lanes@1d87400 { ++ ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, +@@ -3010,7 +3010,7 @@ + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + +- usb_1_ssphy: lanes@88e9200 { ++ usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, +@@ -3043,7 +3043,7 @@ + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + +- usb_2_ssphy: lane@88eb200 { ++ usb_2_ssphy: phy@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>, +--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi +@@ -1463,7 +1463,7 @@ + + status = "disabled"; + +- pcie0_lane: lanes@1c06200 { ++ pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ +@@ -1567,7 +1567,7 @@ + + status = "disabled"; + +- pcie1_lane: lanes@1c0e200 { ++ pcie1_lane: phy@1c0e200 { + reg = <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ +@@ -1673,7 +1673,7 @@ + + status = "disabled"; + +- pcie2_lane: lanes@1c16200 { ++ pcie2_lane: phy@1c16200 { + reg = <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ +@@ -1750,7 +1750,7 @@ + reset-names = "ufsphy"; + status = "disabled"; + +- ufs_mem_phy_lanes: lanes@1d87400 { ++ ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, +@@ -2330,7 +2330,7 @@ + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + +- usb_2_ssphy: lanes@88eb200 { ++ usb_2_ssphy: phy@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>; +--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi +@@ -1080,7 +1080,7 @@ + reset-names = "ufsphy"; + status = "disabled"; + +- ufs_mem_phy_lanes: lanes@1d87400 { ++ ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, diff --git a/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch b/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch deleted file mode 100644 index a278a3e4a..000000000 --- a/target/linux/ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 4ef751128de689e12e3eccb5d4e2562ef8b42758 Mon Sep 17 00:00:00 2001 -From: Shawn Guo -Date: Wed, 29 Sep 2021 11:42:46 +0800 -Subject: [PATCH 04/44] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP - PHY child node - -'#clock-cells' is a required property of QMP PHY child node, not itself. -Move it to fix the dtbs_check warnings. - -There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because -child nodes already have the property. - -Signed-off-by: Shawn Guo -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -91,7 +91,6 @@ - ssphy_1: phy@58000 { - compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00058000 0x1c4>; -- #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -112,6 +111,7 @@ - <0x00058800 0x1f8>, /* PCS */ - <0x00058600 0x044>; /* PCS misc*/ - #phy-cells = <0>; -+ #clock-cells = <1>; - clocks = <&gcc GCC_USB1_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb1_pipe_clk_src"; -@@ -134,7 +134,6 @@ - ssphy_0: phy@78000 { - compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00078000 0x1c4>; -- #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -155,6 +154,7 @@ - <0x00078800 0x1f8>, /* PCS */ - <0x00078600 0x044>; /* PCS misc*/ - #phy-cells = <0>; -+ #clock-cells = <1>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch b/target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch deleted file mode 100644 index 3e76abe96..000000000 --- a/target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 616ad8e9f89e9f57597cf856697fe1c35cf84e5d Mon Sep 17 00:00:00 2001 -From: Shawn Guo -Date: Wed, 29 Sep 2021 11:42:47 +0800 -Subject: [PATCH 05/44] arm64: dts: qcom: Correct QMP PHY child node name - -Many child nodes of QMP PHY are named without following bindings schema -and causing dtbs_check warnings like below. - -phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$' - arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml - arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml - arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml - arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml - arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml - arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml - -Correct them to fix the warnings. - -Signed-off-by: Shawn Guo -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -105,7 +105,7 @@ - reset-names = "phy","common"; - status = "disabled"; - -- usb1_ssphy: lane@58200 { -+ usb1_ssphy: phy@58200 { - reg = <0x00058200 0x130>, /* Tx */ - <0x00058400 0x200>, /* Rx */ - <0x00058800 0x1f8>, /* PCS */ -@@ -148,7 +148,7 @@ - reset-names = "phy","common"; - status = "disabled"; - -- usb0_ssphy: lane@78200 { -+ usb0_ssphy: phy@78200 { - reg = <0x00078200 0x130>, /* Tx */ - <0x00078400 0x200>, /* Rx */ - <0x00078800 0x1f8>, /* PCS */ diff --git a/target/linux/ipq807x/patches-5.15/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch b/target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch similarity index 95% rename from target/linux/ipq807x/patches-5.15/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch rename to target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch index 6aff21f28..b3dce7dd4 100644 --- a/target/linux/ipq807x/patches-5.15/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch +++ b/target/linux/ipq807x/patches-5.15/0005-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch @@ -1,7 +1,7 @@ -From 2a38228b9ac3f8cb4fdae411abbdd5226b687880 Mon Sep 17 00:00:00 2001 +From 942bcd33ed455ad40b71a59901bd926bbf4a500e Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 29 Sep 2021 11:42:51 +0800 -Subject: [PATCH 06/44] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes +Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes IPQ8074 PCIe PHY nodes are broken in the many ways: diff --git a/target/linux/ipq807x/patches-5.15/0007-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch b/target/linux/ipq807x/patches-5.15/0006-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch similarity index 88% rename from target/linux/ipq807x/patches-5.15/0007-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch rename to target/linux/ipq807x/patches-5.15/0006-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch index 26f27ff79..aeeafbb62 100644 --- a/target/linux/ipq807x/patches-5.15/0007-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch +++ b/target/linux/ipq807x/patches-5.15/0006-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch @@ -1,7 +1,7 @@ -From 9757a0d4e05b807074f6868ed594a9bf0111d74d Mon Sep 17 00:00:00 2001 +From d201f67714a302b12ad3d78b982963342939629c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 7 Oct 2021 13:58:46 +0200 -Subject: [PATCH 07/44] arm64: dts: qcom: ipq8074: add MDIO bus +Subject: [PATCH] arm64: dts: qcom: ipq8074: add MDIO bus IPQ8074 uses an IPQ4019 compatible MDIO controller that is already supported in the kernel, so add the DT node in order to use it. diff --git a/target/linux/ipq807x/patches-5.15/0041-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch b/target/linux/ipq807x/patches-5.15/0007-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch similarity index 90% rename from target/linux/ipq807x/patches-5.15/0041-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch rename to target/linux/ipq807x/patches-5.15/0007-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch index 085fab079..a344a4b27 100644 --- a/target/linux/ipq807x/patches-5.15/0041-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch +++ b/target/linux/ipq807x/patches-5.15/0007-v5.16-soc-qcom-socinfo-Add-IPQ8074-family-ID-s.patch @@ -1,7 +1,7 @@ -From 70835efbc6c9dbc4e652aa60a250ecb1a2160a9b Mon Sep 17 00:00:00 2001 +From adfde5bbb4afd5e47371b74a0a4c9ec02fcc8d58 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 5 Sep 2021 19:11:31 +0200 -Subject: [PATCH 41/44] soc: qcom: socinfo: Add IPQ8074 family ID-s +Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 family ID-s IPQ8074 family SoC ID-s are missing, so lets add them based on the downstream driver. diff --git a/target/linux/ipq807x/patches-5.15/0008-v5.16-soc-qcom-smem-Support-reserved-memory-description.patch b/target/linux/ipq807x/patches-5.15/0008-v5.16-soc-qcom-smem-Support-reserved-memory-description.patch deleted file mode 100644 index c9e354341..000000000 --- a/target/linux/ipq807x/patches-5.15/0008-v5.16-soc-qcom-smem-Support-reserved-memory-description.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 00abf58f0ec5ce9dd947792f65e9d01284a4e9c8 Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Thu, 30 Sep 2021 11:21:10 -0700 -Subject: [PATCH 08/44] soc: qcom: smem: Support reserved-memory description - -Practically all modern Qualcomm platforms has a single reserved-memory -region for SMEM. So rather than having to describe SMEM in the form of a -node with a reference to a reserved-memory node, allow the SMEM device -to be instantiated directly from the reserved-memory node. - -The current means of falling back to dereferencing the "memory-region" -is kept as a fallback, if it's determined that the SMEM node is a -reserved-memory node. - -The "qcom,smem" compatible is added to the reserved_mem_matches list, to -allow the reserved-memory device to be probed. - -In order to retain the readability of the code, the resolution of -resources is split from the actual ioremapping. - -Signed-off-by: Bjorn Andersson -Acked-by: Rob Herring -Reviewed-by: Vladimir Zapolskiy -Link: https://lore.kernel.org/r/20210930182111.57353-4-bjorn.andersson@linaro.org ---- - drivers/of/platform.c | 1 + - drivers/soc/qcom/smem.c | 57 ++++++++++++++++++++++++++++------------- - 2 files changed, 40 insertions(+), 18 deletions(-) - ---- a/drivers/of/platform.c -+++ b/drivers/of/platform.c -@@ -509,6 +509,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_po - static const struct of_device_id reserved_mem_matches[] = { - { .compatible = "qcom,rmtfs-mem" }, - { .compatible = "qcom,cmd-db" }, -+ { .compatible = "qcom,smem" }, - { .compatible = "ramoops" }, - { .compatible = "nvmem-rmem" }, - {} ---- a/drivers/soc/qcom/smem.c -+++ b/drivers/soc/qcom/smem.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -240,7 +241,7 @@ static const u8 SMEM_INFO_MAGIC[] = { 0x - * @size: size of the memory region - */ - struct smem_region { -- u32 aux_base; -+ phys_addr_t aux_base; - void __iomem *virt_base; - size_t size; - }; -@@ -499,7 +500,7 @@ static void *qcom_smem_get_global(struct - for (i = 0; i < smem->num_regions; i++) { - region = &smem->regions[i]; - -- if (region->aux_base == aux_base || !aux_base) { -+ if ((u32)region->aux_base == aux_base || !aux_base) { - if (size != NULL) - *size = le32_to_cpu(entry->size); - return region->virt_base + le32_to_cpu(entry->offset); -@@ -664,7 +665,7 @@ phys_addr_t qcom_smem_virt_to_phys(void - if (p < region->virt_base + region->size) { - u64 offset = p - region->virt_base; - -- return (phys_addr_t)region->aux_base + offset; -+ return region->aux_base + offset; - } - } - -@@ -863,12 +864,12 @@ qcom_smem_enumerate_partitions(struct qc - return 0; - } - --static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, -- const char *name, int i) -+static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, -+ struct smem_region *region) - { -+ struct device *dev = smem->dev; - struct device_node *np; - struct resource r; -- resource_size_t size; - int ret; - - np = of_parse_phandle(dev->of_node, name, 0); -@@ -881,13 +882,9 @@ static int qcom_smem_map_memory(struct q - of_node_put(np); - if (ret) - return ret; -- size = resource_size(&r); - -- smem->regions[i].virt_base = devm_ioremap_wc(dev, r.start, size); -- if (!smem->regions[i].virt_base) -- return -ENOMEM; -- smem->regions[i].aux_base = (u32)r.start; -- smem->regions[i].size = size; -+ region->aux_base = r.start; -+ region->size = resource_size(&r); - - return 0; - } -@@ -895,12 +892,14 @@ static int qcom_smem_map_memory(struct q - static int qcom_smem_probe(struct platform_device *pdev) - { - struct smem_header *header; -+ struct reserved_mem *rmem; - struct qcom_smem *smem; - size_t array_size; - int num_regions; - int hwlock_id; - u32 version; - int ret; -+ int i; - - num_regions = 1; - if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL)) -@@ -914,13 +913,35 @@ static int qcom_smem_probe(struct platfo - smem->dev = &pdev->dev; - smem->num_regions = num_regions; - -- ret = qcom_smem_map_memory(smem, &pdev->dev, "memory-region", 0); -- if (ret) -- return ret; -- -- if (num_regions > 1 && (ret = qcom_smem_map_memory(smem, &pdev->dev, -- "qcom,rpm-msg-ram", 1))) -- return ret; -+ rmem = of_reserved_mem_lookup(pdev->dev.of_node); -+ if (rmem) { -+ smem->regions[0].aux_base = rmem->base; -+ smem->regions[0].size = rmem->size; -+ } else { -+ /* -+ * Fall back to the memory-region reference, if we're not a -+ * reserved-memory node. -+ */ -+ ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]); -+ if (ret) -+ return ret; -+ } -+ -+ if (num_regions > 1) { -+ ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]); -+ if (ret) -+ return ret; -+ } -+ -+ for (i = 0; i < num_regions; i++) { -+ smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, -+ smem->regions[i].aux_base, -+ smem->regions[i].size); -+ if (!smem->regions[i].virt_base) { -+ dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base); -+ return -ENOMEM; -+ } -+ } - - header = smem->regions[0].virt_base; - if (le32_to_cpu(header->initialized) != 1 || diff --git a/target/linux/ipq807x/patches-5.15/0010-v5.18-arm64-dts-qcom-ipq8074-add-the-reserved-memory-node.patch b/target/linux/ipq807x/patches-5.15/0010-v5.18-arm64-dts-qcom-ipq8074-add-the-reserved-memory-node.patch deleted file mode 100644 index 6b617f955..000000000 --- a/target/linux/ipq807x/patches-5.15/0010-v5.18-arm64-dts-qcom-ipq8074-add-the-reserved-memory-node.patch +++ /dev/null @@ -1,30 +0,0 @@ -From d58eeedd46d47db44a5932f7d74efae881d54c9b Mon Sep 17 00:00:00 2001 -From: Kathiravan T -Date: Fri, 7 Jan 2022 18:24:38 +0530 -Subject: [PATCH 10/44] arm64: dts: qcom: ipq8074: add the reserved-memory node - -On IPQ8074, 4MB of memory is needed for TZ. So mark that region -as reserved. - -Signed-off-by: Kathiravan T -[bjorn: Squash with existing reserved-memory node] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -88,6 +88,11 @@ - - hwlocks = <&tcsr_mutex 0>; - }; -+ -+ memory@4ac00000 { -+ no-map; -+ reg = <0x0 0x4ac00000 0x0 0x00400000>; -+ }; - }; - - firmware { diff --git a/target/linux/ipq807x/patches-5.15/0009-v5.18-arm64-dts-qcom-ipq8074-add-SMEM-support.patch b/target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-ipq8074-add-SMEM-support.patch similarity index 76% rename from target/linux/ipq807x/patches-5.15/0009-v5.18-arm64-dts-qcom-ipq8074-add-SMEM-support.patch rename to target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-ipq8074-add-SMEM-support.patch index 1a2bdd07c..940f01531 100644 --- a/target/linux/ipq807x/patches-5.15/0009-v5.18-arm64-dts-qcom-ipq8074-add-SMEM-support.patch +++ b/target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-ipq8074-add-SMEM-support.patch @@ -1,21 +1,21 @@ -From 0064ce4f52ed8fc010c1794114205daa9f598828 Mon Sep 17 00:00:00 2001 +From f63c96c02671c00871d180fb5b436e53f4847d3c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 6 Jan 2022 22:25:12 +0100 -Subject: [PATCH 09/44] arm64: dts: qcom: ipq8074: add SMEM support +Subject: [PATCH] arm64: dts: ipq8074: add SMEM support IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already supported by the kernel add the required DT nodes. Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 91436f0a653a..adce47affbef 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -76,6 +76,20 @@ +@@ -76,6 +76,20 @@ psci { method = "smc"; }; @@ -36,7 +36,7 @@ Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; -@@ -331,6 +345,12 @@ +@@ -331,6 +345,12 @@ gcc: gcc@1800000 { #reset-cells = <0x1>; }; @@ -49,3 +49,6 @@ Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0012-v5.18-arm64-dts-qcom-ipq8074-drop-the-clock-frequency-prop.patch b/target/linux/ipq807x/patches-5.15/0012-v5.18-arm64-dts-qcom-ipq8074-drop-the-clock-frequency-prop.patch deleted file mode 100644 index 9c24d6431..000000000 --- a/target/linux/ipq807x/patches-5.15/0012-v5.18-arm64-dts-qcom-ipq8074-drop-the-clock-frequency-prop.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2e21d1f48dc0d0cdbd53ac33b9859c7cb575eecc Mon Sep 17 00:00:00 2001 -From: Kathiravan T -Date: Wed, 2 Feb 2022 22:05:08 +0530 -Subject: [PATCH 12/44] arm64: dts: qcom: ipq8074: drop the clock-frequency - property - -Drop the clock-frequency property from the MMIO timer node, since it -is already configured by the bootloader. - -Signed-off-by: Kathiravan T -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -670,7 +670,6 @@ - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; -- clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; diff --git a/target/linux/ipq807x/patches-5.15/0013-v5.19-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-sc.patch b/target/linux/ipq807x/patches-5.15/0013-v5.19-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-sc.patch deleted file mode 100644 index 1a6864d94..000000000 --- a/target/linux/ipq807x/patches-5.15/0013-v5.19-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-sc.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 4647475f588c85138ddf47a17305dd41834e1105 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 5 Apr 2022 08:34:43 +0200 -Subject: [PATCH 13/44] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT - schema - -The DT schema expects dma channels in tx-rx order. No functional -change. - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -471,8 +471,8 @@ - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; -- dmas = <&blsp_dma 15>, <&blsp_dma 14>; -- dma-names = "rx", "tx"; -+ dmas = <&blsp_dma 14>, <&blsp_dma 15>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "disabled"; -@@ -488,8 +488,8 @@ - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; -- dmas = <&blsp_dma 17>, <&blsp_dma 16>; -- dma-names = "rx", "tx"; -+ dmas = <&blsp_dma 16>, <&blsp_dma 17>; -+ dma-names = "tx", "rx"; - status = "disabled"; - }; - -@@ -503,8 +503,8 @@ - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; -- dmas = <&blsp_dma 21>, <&blsp_dma 20>; -- dma-names = "rx", "tx"; -+ dmas = <&blsp_dma 20>, <&blsp_dma 21>; -+ dma-names = "tx", "rx"; - status = "disabled"; - }; - -@@ -518,8 +518,8 @@ - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; -- dmas = <&blsp_dma 23>, <&blsp_dma 22>; -- dma-names = "rx", "tx"; -+ dmas = <&blsp_dma 22>, <&blsp_dma 23>; -+ dma-names = "tx", "rx"; - status = "disabled"; - }; - diff --git a/target/linux/ipq807x/patches-5.15/0014-v5.19-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schem.patch b/target/linux/ipq807x/patches-5.15/0014-v5.19-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schem.patch deleted file mode 100644 index 616ccf171..000000000 --- a/target/linux/ipq807x/patches-5.15/0014-v5.19-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schem.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 553f1ea4128453cead2d38d5773ec6044c6e7626 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 5 Apr 2022 08:34:44 +0200 -Subject: [PATCH 14/44] arm64: dts: qcom: align clocks in I2C/SPI with DT - schema - -The DT schema expects clocks core-iface order. No functional change. - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------ - 1 file changed, 12 insertions(+), 12 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -467,9 +467,9 @@ - #size-cells = <0>; - reg = <0x078b6000 0x600>; - interrupts = ; -- clocks = <&gcc GCC_BLSP1_AHB_CLK>, -- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; -- clock-names = "iface", "core"; -+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; - clock-frequency = <400000>; - dmas = <&blsp_dma 14>, <&blsp_dma 15>; - dma-names = "tx", "rx"; -@@ -484,9 +484,9 @@ - #size-cells = <0>; - reg = <0x078b7000 0x600>; - interrupts = ; -- clocks = <&gcc GCC_BLSP1_AHB_CLK>, -- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; -- clock-names = "iface", "core"; -+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; - clock-frequency = <100000>; - dmas = <&blsp_dma 16>, <&blsp_dma 17>; - dma-names = "tx", "rx"; -@@ -499,9 +499,9 @@ - #size-cells = <0>; - reg = <0x78b9000 0x600>; - interrupts = ; -- clocks = <&gcc GCC_BLSP1_AHB_CLK>, -- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; -- clock-names = "iface", "core"; -+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; - clock-frequency = <400000>; - dmas = <&blsp_dma 20>, <&blsp_dma 21>; - dma-names = "tx", "rx"; -@@ -514,9 +514,9 @@ - #size-cells = <0>; - reg = <0x078ba000 0x600>; - interrupts = ; -- clocks = <&gcc GCC_BLSP1_AHB_CLK>, -- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; -- clock-names = "iface", "core"; -+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; - clock-frequency = <100000>; - dmas = <&blsp_dma 22>, <&blsp_dma 23>; - dma-names = "tx", "rx"; diff --git a/target/linux/ipq807x/patches-5.15/0015-v5.19-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addr.patch b/target/linux/ipq807x/patches-5.15/0015-v5.19-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addr.patch deleted file mode 100644 index f5077d9e0..000000000 --- a/target/linux/ipq807x/patches-5.15/0015-v5.19-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addr.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 04e91eb95f7a0a9dceed2c1fcb47fbbe7f96ec52 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 4 May 2022 15:19:16 +0200 -Subject: [PATCH 15/44] arm64: dts: qcom: correct DWC3 node names and unit - addresses - -Align DWC3 USB node names with DT schema ("usb" is expected) and correct -the unit addresses to match the "reg" property. This also implies -overriding nodes by label, instead of full path. - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -578,7 +578,7 @@ - resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; - -- dwc_0: dwc3@8a00000 { -+ dwc_0: usb@8a00000 { - compatible = "snps,dwc3"; - reg = <0x8a00000 0xcd00>; - interrupts = ; -@@ -618,7 +618,7 @@ - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - -- dwc_1: dwc3@8c00000 { -+ dwc_1: usb@8c00000 { - compatible = "snps,dwc3"; - reg = <0x8c00000 0xcd00>; - interrupts = ; diff --git a/target/linux/ipq807x/patches-5.15/0016-v5.19-arm64-dts-qcom-ipq8074-add-dedicated-qcom-ipq8074-dw.patch b/target/linux/ipq807x/patches-5.15/0016-v5.19-arm64-dts-qcom-ipq8074-add-dedicated-qcom-ipq8074-dw.patch deleted file mode 100644 index fd035e1a6..000000000 --- a/target/linux/ipq807x/patches-5.15/0016-v5.19-arm64-dts-qcom-ipq8074-add-dedicated-qcom-ipq8074-dw.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 65b572a6c5bad2c9f3c784ff42d4eddedcfd85cd Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 4 May 2022 15:19:17 +0200 -Subject: [PATCH 16/44] arm64: dts: qcom: ipq8074: add dedicated - qcom,ipq8074-dwc3 compatible - -Add dedicated compatible for DWC3 USB node name to allow more accurate -DT schema matching. - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220504131923.214367-8-krzysztof.kozlowski@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -553,7 +553,7 @@ - }; - - usb_0: usb@8af8800 { -- compatible = "qcom,dwc3"; -+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; -@@ -593,7 +593,7 @@ - }; - - usb_1: usb@8cf8800 { -- compatible = "qcom,dwc3"; -+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; - reg = <0x08cf8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/ipq807x/patches-5.15/0017-v5.19-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch b/target/linux/ipq807x/patches-5.15/0017-v5.19-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch deleted file mode 100644 index ca68245d5..000000000 --- a/target/linux/ipq807x/patches-5.15/0017-v5.19-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch +++ /dev/null @@ -1,39 +0,0 @@ -From e8949160470080b4c24139cfb88accc25e589f70 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 4 May 2022 15:19:22 +0200 -Subject: [PATCH 17/44] arm64: dts: qcom: align DWC3 USB clocks with DT schema - -Align order of clocks and their names with Qualcomm DWC3 USB DT schema. -No functional impact expected. - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -563,8 +563,8 @@ - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; -- clock-names = "sys_noc_axi", -- "master", -+ clock-names = "cfg_noc", -+ "core", - "sleep", - "mock_utmi"; - -@@ -603,8 +603,8 @@ - <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_SLEEP_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; -- clock-names = "sys_noc_axi", -- "master", -+ clock-names = "cfg_noc", -+ "core", - "sleep", - "mock_utmi"; - diff --git a/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-adjust-whitespace-around.patch b/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-adjust-whitespace-around.patch deleted file mode 100644 index c1ef33807..000000000 --- a/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-adjust-whitespace-around.patch +++ /dev/null @@ -1,36 +0,0 @@ -From af38dc1085f574d575c886c0800645c8b7d4b874 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Thu, 26 May 2022 22:42:47 +0200 -Subject: [PATCH 18/44] arm64: dts: qcom: adjust whitespace around '=' - -Fix whitespace coding style: use single space instead of tabs or -multiple spaces around '=' sign in property assignment. No functional -changes (same DTB). - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -119,7 +119,7 @@ - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - -- resets = <&gcc GCC_USB1_PHY_BCR>, -+ resets = <&gcc GCC_USB1_PHY_BCR>, - <&gcc GCC_USB3PHY_1_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; -@@ -162,7 +162,7 @@ - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - -- resets = <&gcc GCC_USB0_PHY_BCR>, -+ resets = <&gcc GCC_USB0_PHY_BCR>, - <&gcc GCC_USB3PHY_0_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; diff --git a/target/linux/ipq807x/patches-5.15/0019-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch b/target/linux/ipq807x/patches-5.15/0019-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch deleted file mode 100644 index 6afe50725..000000000 --- a/target/linux/ipq807x/patches-5.15/0019-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0d7e4bd5d554ac7471724f80aa67b664f3539f47 Mon Sep 17 00:00:00 2001 -From: Bhupesh Sharma -Date: Sun, 15 May 2022 03:24:19 +0530 -Subject: [PATCH 19/44] arm64: dts: qcom: Fix sdhci node names - use 'mmc@' - -Since the Qualcomm sdhci-msm device-tree binding has been converted -to yaml format, 'make dtbs_check' reports issues with -inconsistent 'sdhci@' convention used for specifying the -sdhci nodes. The generic mmc bindings expect 'mmc@' format -instead. - -Fix the same. - -Cc: Bjorn Andersson -Cc: Rob Herring -Signed-off-by: Bhupesh Sharma -[bjorn: Moved non-arm64 changes to separate commit] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -375,7 +375,7 @@ - cell-index = <0>; - }; - -- sdhc_1: sdhci@7824900 { -+ sdhc_1: mmc@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; diff --git a/target/linux/ipq807x/patches-5.15/0020-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch b/target/linux/ipq807x/patches-5.15/0020-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch deleted file mode 100644 index f26d01bc3..000000000 --- a/target/linux/ipq807x/patches-5.15/0020-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d923ec8397673773a3d22dc3ac0c5fccd22cd405 Mon Sep 17 00:00:00 2001 -From: Bhupesh Sharma -Date: Sun, 15 May 2022 03:24:22 +0530 -Subject: [PATCH 20/44] arm64: dts: qcom: Fix ordering of 'clocks' & - 'clock-names' for sdhci nodes - -Since the Qualcomm sdhci-msm device-tree binding has been converted -to yaml format, 'make dtbs_check' reports a number of issues with -ordering of 'clocks' & 'clock-names' for sdhci nodes: - - arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: - clock-names:0: 'iface' was expected - - arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: - clock-names:1: 'core' was expected - - arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: - clock-names:2: 'xo' was expected - -Fix the same by updating the offending 'dts' files. - -Cc: Bjorn Andersson -Cc: Rob Herring -Signed-off-by: Bhupesh Sharma -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -384,10 +384,10 @@ - ; - interrupt-names = "hc_irq", "pwr_irq"; - -- clocks = <&xo>, -- <&gcc GCC_SDCC1_AHB_CLK>, -- <&gcc GCC_SDCC1_APPS_CLK>; -- clock-names = "xo", "iface", "core"; -+ clocks = <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_SDCC1_APPS_CLK>, -+ <&xo>; -+ clock-names = "iface", "core", "xo"; - max-frequency = <384000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; diff --git a/target/linux/ipq807x/patches-5.15/0021-v6.0-dt-bindings-clock-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq807x/patches-5.15/0021-v6.0-dt-bindings-clock-qcom-ipq8074-add-PPE-crypto-clock.patch deleted file mode 100644 index 3985f363a..000000000 --- a/target/linux/ipq807x/patches-5.15/0021-v6.0-dt-bindings-clock-qcom-ipq8074-add-PPE-crypto-clock.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f56aefe67c7652d38293afa83333c9228a9fbc35 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 15 May 2022 23:00:41 +0200 -Subject: [PATCH 21/44] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock - -Add binding for the PPE crypto clock in IPQ8074. - -Signed-off-by: Robert Marko -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com ---- - include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + - 1 file changed, 1 insertion(+) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -233,6 +233,7 @@ - #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 - #define GCC_PCIE0_RCHNG_CLK_SRC 225 - #define GCC_PCIE0_RCHNG_CLK 226 -+#define GCC_CRYPTO_PPE_CLK 227 - - #define GCC_BLSP1_BCR 0 - #define GCC_BLSP1_QUP1_BCR 1 diff --git a/target/linux/ipq807x/patches-5.15/0023-v6.0-dt-bindings-clock-qcom-ipq8074-add-USB-GDSCs.patch b/target/linux/ipq807x/patches-5.15/0023-v6.0-dt-bindings-clock-qcom-ipq8074-add-USB-GDSCs.patch deleted file mode 100644 index f3253edae..000000000 --- a/target/linux/ipq807x/patches-5.15/0023-v6.0-dt-bindings-clock-qcom-ipq8074-add-USB-GDSCs.patch +++ /dev/null @@ -1,25 +0,0 @@ -From c0823201046e5a79823e3ff5fa4f0a9b5fcda14d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 15 May 2022 23:00:45 +0200 -Subject: [PATCH 23/44] dt-bindings: clock: qcom: ipq8074: add USB GDSCs - -Add bindings for the USB GDSCs found in IPQ8074 GCC. - -Signed-off-by: Robert Marko -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com ---- - include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -368,4 +368,7 @@ - #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 - #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 - -+#define USB0_GDSC 0 -+#define USB1_GDSC 1 -+ - #endif diff --git a/target/linux/ipq807x/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch b/target/linux/ipq807x/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch deleted file mode 100644 index 7eca353d2..000000000 --- a/target/linux/ipq807x/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 248fb3267c23749059baa231e21650a68771abef Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 15 May 2022 23:00:46 +0200 -Subject: [PATCH 24/44] clk: qcom: ipq8074: add USB GDSCs - -Add GDSC-s for each of the two USB controllers built-in the IPQ8074. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com ---- - drivers/clk/qcom/Kconfig | 1 + - drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ - 2 files changed, 25 insertions(+) - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -166,6 +166,7 @@ config IPQ_LCC_806X - - config IPQ_GCC_8074 - tristate "IPQ8074 Global Clock Controller" -+ select QCOM_GDSC - help - Support for global clock controller on ipq8074 devices. - Say Y if you want to use peripheral devices such as UART, SPI, ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -22,6 +22,7 @@ - #include "clk-alpha-pll.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "gdsc.h" - #include "reset.h" - - enum { -@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s - }, - }; - -+static struct gdsc usb0_gdsc = { -+ .gdscr = 0x3e078, -+ .pd = { -+ .name = "usb0_gdsc", -+ }, -+ .pwrsts = PWRSTS_OFF_ON, -+}; -+ -+static struct gdsc usb1_gdsc = { -+ .gdscr = 0x3f078, -+ .pd = { -+ .name = "usb1_gdsc", -+ }, -+ .pwrsts = PWRSTS_OFF_ON, -+}; -+ - static const struct alpha_pll_config ubi32_pll_config = { - .l = 0x4e, - .config_ctl_val = 0x200d4aa8, -@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i - [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, - }; - -+static struct gdsc *gcc_ipq8074_gdscs[] = { -+ [USB0_GDSC] = &usb0_gdsc, -+ [USB1_GDSC] = &usb1_gdsc, -+}; -+ - static const struct of_device_id gcc_ipq8074_match_table[] = { - { .compatible = "qcom,gcc-ipq8074" }, - { } -@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq - .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), - .clk_hws = gcc_ipq8074_hws, - .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), -+ .gdscs = gcc_ipq8074_gdscs, -+ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), - }; - - static int gcc_ipq8074_probe(struct platform_device *pdev) diff --git a/target/linux/ipq807x/patches-5.15/0025-v6.0-arm64-dts-qcom-ipq8074-add-USB-power-domains.patch b/target/linux/ipq807x/patches-5.15/0025-v6.0-arm64-dts-qcom-ipq8074-add-USB-power-domains.patch deleted file mode 100644 index 9e356189b..000000000 --- a/target/linux/ipq807x/patches-5.15/0025-v6.0-arm64-dts-qcom-ipq8074-add-USB-power-domains.patch +++ /dev/null @@ -1,43 +0,0 @@ -From e8516c04110438230314ddbe94879ecb4a5db5df Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 15 May 2022 23:00:48 +0200 -Subject: [PATCH 25/44] arm64: dts: qcom: ipq8074: add USB power domains - -Add USB power domains provided by GCC GDSCs. -Add the required #power-domain-cells to the GCC as well. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220515210048.483898-11-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -347,6 +347,7 @@ - compatible = "qcom,gcc-ipq8074"; - reg = <0x01800000 0x80000>; - #clock-cells = <0x1>; -+ #power-domain-cells = <1>; - #reset-cells = <0x1>; - }; - -@@ -575,6 +576,8 @@ - <133330000>, - <19200000>; - -+ power-domains = <&gcc USB0_GDSC>; -+ - resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; - -@@ -615,6 +618,8 @@ - <133330000>, - <19200000>; - -+ power-domains = <&gcc USB1_GDSC>; -+ - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - diff --git a/target/linux/ipq807x/patches-5.15/0026-v6.0-arm64-dts-qcom-ipq8074-move-ARMv8-timer-out-of-SoC-n.patch b/target/linux/ipq807x/patches-5.15/0026-v6.0-arm64-dts-qcom-ipq8074-move-ARMv8-timer-out-of-SoC-n.patch deleted file mode 100644 index 539db4d71..000000000 --- a/target/linux/ipq807x/patches-5.15/0026-v6.0-arm64-dts-qcom-ipq8074-move-ARMv8-timer-out-of-SoC-n.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 510f246cf8f6af8c0d7a46d22448b812fd9a14a4 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 4 Jul 2022 13:33:18 +0200 -Subject: [PATCH 26/44] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC - node - -The ARM timer is usually considered not part of SoC node, just like -other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: - -arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} - From schema: dtschema/schemas/simple-bus.yaml - -Signed-off-by: Robert Marko -Acked-by: Krzysztof Kozlowski -[bjorn: Moved node after "soc" for alphabetical ordering] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -653,14 +653,6 @@ - }; - }; - -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- ; -- }; -- - watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt"; - reg = <0xb017000 0x1000>; -@@ -852,4 +844,12 @@ - status = "disabled"; - }; - }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; - }; diff --git a/target/linux/ipq807x/patches-5.15/0027-v6.0-arm64-dts-qcom-ipq8074-add-reset-to-SDHCI.patch b/target/linux/ipq807x/patches-5.15/0027-v6.0-arm64-dts-qcom-ipq8074-add-reset-to-SDHCI.patch deleted file mode 100644 index faaf1b663..000000000 --- a/target/linux/ipq807x/patches-5.15/0027-v6.0-arm64-dts-qcom-ipq8074-add-reset-to-SDHCI.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8cef5828706a1584b4dadf3f4b707a392bc8c231 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 4 Jul 2022 16:35:54 +0200 -Subject: [PATCH 27/44] arm64: dts: qcom: ipq8074: add reset to SDHCI - -Add reset to SDHCI controller so it can be reset to avoid timeout issues -after software reset due to bootloader set configuration. - -Signed-off-by: Robert Marko -Reviewed-by: Konrad Dybcio -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -389,6 +389,7 @@ - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo>; - clock-names = "iface", "core", "xo"; -+ resets = <&gcc GCC_SDCC1_BCR>; - max-frequency = <384000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; diff --git a/target/linux/ipq807x/patches-5.15/0028-v6.0-arm64-dts-qcom-ipq8074-drop-USB-PHY-clock-index.patch b/target/linux/ipq807x/patches-5.15/0028-v6.0-arm64-dts-qcom-ipq8074-drop-USB-PHY-clock-index.patch deleted file mode 100644 index 4f5148d16..000000000 --- a/target/linux/ipq807x/patches-5.15/0028-v6.0-arm64-dts-qcom-ipq8074-drop-USB-PHY-clock-index.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 2bf80b5de7c2598972af28adc09e8e667b528d11 Mon Sep 17 00:00:00 2001 -From: Johan Hovold -Date: Tue, 5 Jul 2022 13:40:22 +0200 -Subject: [PATCH 28/44] arm64: dts: qcom: ipq8074: drop USB PHY clock index - -The QMP USB PHY provides a single clock so drop the redundant clock -index. - -Signed-off-by: Johan Hovold -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -130,7 +130,7 @@ - <0x00058800 0x1f8>, /* PCS */ - <0x00058600 0x044>; /* PCS misc*/ - #phy-cells = <0>; -- #clock-cells = <1>; -+ #clock-cells = <0>; - clocks = <&gcc GCC_USB1_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb1_pipe_clk_src"; -@@ -173,7 +173,7 @@ - <0x00078800 0x1f8>, /* PCS */ - <0x00078600 0x044>; /* PCS misc*/ - #phy-cells = <0>; -- #clock-cells = <1>; -+ #clock-cells = <0>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/target/linux/ipq807x/patches-5.15/0029-v6.0-arm64-dts-qcom-ipq8074-add-APCS-node.patch b/target/linux/ipq807x/patches-5.15/0029-v6.0-arm64-dts-qcom-ipq8074-add-APCS-node.patch deleted file mode 100644 index edb9faf69..000000000 --- a/target/linux/ipq807x/patches-5.15/0029-v6.0-arm64-dts-qcom-ipq8074-add-APCS-node.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 73ea147a5caa82c94486076186af2c7dc1894a97 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 7 Jul 2022 19:37:33 +0200 -Subject: [PATCH 29/44] arm64: dts: qcom: ipq8074: add APCS node - -APCS now has support for providing the APSS clocks as the child device -for IPQ8074. - -So, add the required DT node for it as it will later be used as the CPU -clocksource. - -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov -[bjorn: Sorted node based on address] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -662,6 +662,14 @@ - timeout-sec = <30>; - }; - -+ apcs_glb: mailbox@b111000 { -+ compatible = "qcom,ipq8074-apcs-apps-global"; -+ reg = <0x0b111000 0x6000>; -+ -+ #clock-cells = <1>; -+ #mbox-cells = <1>; -+ }; -+ - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/ipq807x/patches-5.15/0030-v6.0-arm64-dts-qcom-ipq8074-add-size-address-cells-to-DTS.patch b/target/linux/ipq807x/patches-5.15/0030-v6.0-arm64-dts-qcom-ipq8074-add-size-address-cells-to-DTS.patch deleted file mode 100644 index 02db52eae..000000000 --- a/target/linux/ipq807x/patches-5.15/0030-v6.0-arm64-dts-qcom-ipq8074-add-size-address-cells-to-DTS.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 254bf23fe2e0c73d75a0bf4f37579e15433b75e0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 8 Jul 2022 15:38:45 +0200 -Subject: [PATCH 30/44] arm64: dts: qcom: ipq8074: add #size/address-cells to - DTSI - -Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating -the same properties in board DTS files. - -Remove the mentioned properties from current board DTS files. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 -- - arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++ - 3 files changed, 3 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -@@ -5,8 +5,6 @@ - #include "ipq8074.dtsi" - - / { -- #address-cells = <0x2>; -- #size-cells = <0x2>; - model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; - compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; - interrupt-parent = <&intc>; ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi -@@ -7,9 +7,6 @@ - #include "ipq8074.dtsi" - - / { -- #address-cells = <0x2>; -- #size-cells = <0x2>; -- - interrupt-parent = <&intc>; - - aliases { ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -7,6 +7,9 @@ - #include - - / { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ - model = "Qualcomm Technologies, Inc. IPQ8074"; - compatible = "qcom,ipq8074"; - diff --git a/target/linux/ipq807x/patches-5.15/0031-v6.0-arm64-dts-qcom-ipq8074-add-interrupt-parent-to-DTSI.patch b/target/linux/ipq807x/patches-5.15/0031-v6.0-arm64-dts-qcom-ipq8074-add-interrupt-parent-to-DTSI.patch deleted file mode 100644 index bbe4bf1bd..000000000 --- a/target/linux/ipq807x/patches-5.15/0031-v6.0-arm64-dts-qcom-ipq8074-add-interrupt-parent-to-DTSI.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 520877b4d26ba4e6d08b5e9579f166ca2a934e81 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 8 Jul 2022 15:38:46 +0200 -Subject: [PATCH 31/44] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI - -Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board -DTS file. - -Remove interrupt-parent from existing board DTS files. - -Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com ---- - arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 1 - - arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 -- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + - 3 files changed, 1 insertion(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -@@ -7,7 +7,6 @@ - / { - model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; - compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; -- interrupt-parent = <&intc>; - - aliases { - serial0 = &blsp1_uart5; ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi -@@ -7,8 +7,6 @@ - #include "ipq8074.dtsi" - - / { -- interrupt-parent = <&intc>; -- - aliases { - serial0 = &blsp1_uart5; - }; ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -12,6 +12,7 @@ - - model = "Qualcomm Technologies, Inc. IPQ8074"; - compatible = "qcom,ipq8074"; -+ interrupt-parent = <&intc>; - - clocks { - sleep_clk: sleep_clk { diff --git a/target/linux/ipq807x/patches-5.15/0032-v6.0-regulator-qcom_spmi-add-support-for-HT_P150.patch b/target/linux/ipq807x/patches-5.15/0032-v6.0-regulator-qcom_spmi-add-support-for-HT_P150.patch deleted file mode 100644 index be0479714..000000000 --- a/target/linux/ipq807x/patches-5.15/0032-v6.0-regulator-qcom_spmi-add-support-for-HT_P150.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 8928dcb644461e72608dbea26af4d072868ae41b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 4 Jul 2022 23:23:54 +0200 -Subject: [PATCH 32/44] regulator: qcom_spmi: add support for HT_P150 - -HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout -found in PMP8074 and PMS405 PMIC-s. - -Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V -but the actual MAX output voltage depends on the exact LDO in each of -the PMIC-s. - -It has a max current of 150mA, voltage step of 8mV. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20220704212402.1715182-4-robimarko@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/qcom_spmi-regulator.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/regulator/qcom_spmi-regulator.c -+++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -164,6 +164,7 @@ enum spmi_regulator_subtype { - SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, - SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, - SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, -+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, - }; - - enum spmi_common_regulator_registers { -@@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_ - SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), - }; - -+static struct spmi_voltage_range ht_p150_ranges[] = { -+ SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000), -+}; -+ - static DEFINE_SPMI_SET_POINTS(pldo); - static DEFINE_SPMI_SET_POINTS(nldo1); - static DEFINE_SPMI_SET_POINTS(nldo2); -@@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660); - static DEFINE_SPMI_SET_POINTS(ht_lvpldo); - static DEFINE_SPMI_SET_POINTS(ht_nldo); - static DEFINE_SPMI_SET_POINTS(hfs430); -+static DEFINE_SPMI_SET_POINTS(ht_p150); - - static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, - int len) -@@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_h - - static const struct spmi_regulator_mapping supported_regulators[] = { - /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ -+ SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), - SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), - SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), - SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), diff --git a/target/linux/ipq807x/patches-5.15/0033-v6.0-regulator-qcom_spmi-add-support-for-HT_P600.patch b/target/linux/ipq807x/patches-5.15/0033-v6.0-regulator-qcom_spmi-add-support-for-HT_P600.patch deleted file mode 100644 index a326481ea..000000000 --- a/target/linux/ipq807x/patches-5.15/0033-v6.0-regulator-qcom_spmi-add-support-for-HT_P600.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 2ba036ce8e99673073adc5ac62e7768a47725567 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 4 Jul 2022 23:23:55 +0200 -Subject: [PATCH 33/44] regulator: qcom_spmi: add support for HT_P600 - -HT_P600 is a LDO PMOS regulator based on LV P600 using HFS430 layout -found in PMP8074 and PMS405 PMIC-s. - -Both PMP8074 and PMS405 define the programmable range as 1.704 to 1.896V -but the actual MAX output voltage depends on the exact LDO in each of -the PMIC-s. -Their usual voltage that they are used is 1.8V. - -It has a max current of 600mA, voltage step of 8mV. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20220704212402.1715182-5-robimarko@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/qcom_spmi-regulator.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/regulator/qcom_spmi-regulator.c -+++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -165,6 +165,7 @@ enum spmi_regulator_subtype { - SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, - SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, - SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, -+ SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d, - }; - - enum spmi_common_regulator_registers { -@@ -549,6 +550,10 @@ static struct spmi_voltage_range ht_p150 - SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000), - }; - -+static struct spmi_voltage_range ht_p600_ranges[] = { -+ SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000), -+}; -+ - static DEFINE_SPMI_SET_POINTS(pldo); - static DEFINE_SPMI_SET_POINTS(nldo1); - static DEFINE_SPMI_SET_POINTS(nldo2); -@@ -570,6 +575,7 @@ static DEFINE_SPMI_SET_POINTS(ht_lvpldo) - static DEFINE_SPMI_SET_POINTS(ht_nldo); - static DEFINE_SPMI_SET_POINTS(hfs430); - static DEFINE_SPMI_SET_POINTS(ht_p150); -+static DEFINE_SPMI_SET_POINTS(ht_p600); - - static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, - int len) -@@ -1464,6 +1470,7 @@ static const struct regulator_ops spmi_h - - static const struct spmi_regulator_mapping supported_regulators[] = { - /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ -+ SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000), - SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), - SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), - SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), diff --git a/target/linux/ipq807x/patches-5.15/0034-v6.0-regulator-qcom_spmi-add-support-for-PMP8074-regulato.patch b/target/linux/ipq807x/patches-5.15/0034-v6.0-regulator-qcom_spmi-add-support-for-PMP8074-regulato.patch deleted file mode 100644 index 49eac1065..000000000 --- a/target/linux/ipq807x/patches-5.15/0034-v6.0-regulator-qcom_spmi-add-support-for-PMP8074-regulato.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 933b687758646242fc7410edb06da70fe7540cdc Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 4 Jul 2022 23:23:57 +0200 -Subject: [PATCH 34/44] regulator: qcom_spmi: add support for PMP8074 - regulators - -PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s. - -It features 5 HF-SMPS and 13 LDO regulators. - -HF-SMPS regulators are Buck HFS430 regulators. -L1, L2 and L3 are HT_N1200_ST subtype LDO regulators. -L4 is HT_N300_ST subtype LDO regulator. -L5 and L6 are HT_P600 subtype LDO regulators. -L7, L11, L12 and L13 are HT_P150 subtype LDO regulators. -L10 is HT_P50 subtype LDO regulator. - -This commit adds support for all of the buck regulators and LDO-s except -for L10 as I dont have documentation on its output voltage range. - -S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores -and L11 is the SDIO/eMMC I/O voltage regulator required for high speeds. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20220704212402.1715182-7-robimarko@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/qcom_spmi-regulator.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/regulator/qcom_spmi-regulator.c -+++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -2101,6 +2101,28 @@ static const struct spmi_regulator_data - { } - }; - -+static const struct spmi_regulator_data pmp8074_regulators[] = { -+ { "s1", 0x1400, "vdd_s1"}, -+ { "s2", 0x1700, "vdd_s2"}, -+ { "s3", 0x1a00, "vdd_s3"}, -+ { "s4", 0x1d00, "vdd_s4"}, -+ { "s5", 0x2000, "vdd_s5"}, -+ { "l1", 0x4000, "vdd_l1_l2"}, -+ { "l2", 0x4100, "vdd_l1_l2"}, -+ { "l3", 0x4200, "vdd_l3_l8"}, -+ { "l4", 0x4300, "vdd_l4"}, -+ { "l5", 0x4400, "vdd_l5_l6_l15"}, -+ { "l6", 0x4500, "vdd_l5_l6_l15"}, -+ { "l7", 0x4600, "vdd_l7"}, -+ { "l8", 0x4700, "vdd_l3_l8"}, -+ { "l9", 0x4800, "vdd_l9"}, -+ /* l10 is currently unsupported HT_P50 */ -+ { "l11", 0x4a00, "vdd_l10_l11_l12_l13"}, -+ { "l12", 0x4b00, "vdd_l10_l11_l12_l13"}, -+ { "l13", 0x4c00, "vdd_l10_l11_l12_l13"}, -+ { } -+}; -+ - static const struct spmi_regulator_data pms405_regulators[] = { - { "s3", 0x1a00, "vdd_s3"}, - { } -@@ -2117,6 +2139,7 @@ static const struct of_device_id qcom_sp - { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, - { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, - { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, -+ { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, - { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, - { } - }; diff --git a/target/linux/ipq807x/patches-5.15/0035-v6.0-pinctrl-qcom-pmic-gpio-add-support-for-PMP8074.patch b/target/linux/ipq807x/patches-5.15/0035-v6.0-pinctrl-qcom-pmic-gpio-add-support-for-PMP8074.patch deleted file mode 100644 index 565d0513c..000000000 --- a/target/linux/ipq807x/patches-5.15/0035-v6.0-pinctrl-qcom-pmic-gpio-add-support-for-PMP8074.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 55545dc54f015387dccfb3c8fe20115c5f21b8a7 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 11 Jul 2022 22:34:05 +0200 -Subject: [PATCH 35/44] pinctrl: qcom-pmic-gpio: add support for PMP8074 - -PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c -+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c -@@ -1167,6 +1167,8 @@ static const struct of_device_id pmic_gp - { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, - { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, -+ /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ -+ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, - { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, - /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ diff --git a/target/linux/ipq807x/patches-5.15/0036-v5.16-mfd-qcom-spmi-pmic-Sort-compatibles-in-the-driver.patch b/target/linux/ipq807x/patches-5.15/0036-v5.16-mfd-qcom-spmi-pmic-Sort-compatibles-in-the-driver.patch deleted file mode 100644 index bbfb22614..000000000 --- a/target/linux/ipq807x/patches-5.15/0036-v5.16-mfd-qcom-spmi-pmic-Sort-compatibles-in-the-driver.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f76d65737cff6f41f0fab7a46a742d89c08fd652 Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Sun, 17 Oct 2021 09:12:16 -0700 -Subject: [PATCH 36/44] mfd: qcom-spmi-pmic: Sort compatibles in the driver - -Sort the compatibles in the driver, to make it easier to validate that -the DT binding and driver are in sync. - -Signed-off-by: Bjorn Andersson -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20211017161218.2378176-2-bjorn.andersson@linaro.org ---- - drivers/mfd/qcom-spmi-pmic.c | 30 +++++++++++++++--------------- - 1 file changed, 15 insertions(+), 15 deletions(-) - ---- a/drivers/mfd/qcom-spmi-pmic.c -+++ b/drivers/mfd/qcom-spmi-pmic.c -@@ -40,27 +40,27 @@ - #define PM660_SUBTYPE 0x1B - - static const struct of_device_id pmic_spmi_id_table[] = { -- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE }, -- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE }, -- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE }, -+ { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, -+ { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE }, -+ { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE }, -+ { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE }, - { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE }, -- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE }, - { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE }, -- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE }, -- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE }, -- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE }, -- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE }, -- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE }, -- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE }, -- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE }, -+ { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE }, -+ { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE }, - { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE }, -+ { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE }, -+ { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE }, - { .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE }, -- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE }, -+ { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE }, - { .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE }, -+ { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE }, -+ { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE }, -+ { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE }, -+ { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE }, -+ { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE }, - { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE }, -- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE }, -- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE }, -- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, -+ { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE }, - { } - }; - diff --git a/target/linux/ipq807x/patches-5.15/0037-v5.16-mfd-qcom-spmi-pmic-Add-missing-PMICs-supported-by-so.patch b/target/linux/ipq807x/patches-5.15/0037-v5.16-mfd-qcom-spmi-pmic-Add-missing-PMICs-supported-by-so.patch deleted file mode 100644 index b7fa5d03a..000000000 --- a/target/linux/ipq807x/patches-5.15/0037-v5.16-mfd-qcom-spmi-pmic-Add-missing-PMICs-supported-by-so.patch +++ /dev/null @@ -1,66 +0,0 @@ -From b4f85660d09360b2ef9f04e51890fbf9935bf759 Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Sun, 17 Oct 2021 09:12:18 -0700 -Subject: [PATCH 37/44] mfd: qcom-spmi-pmic: Add missing PMICs supported by - socinfo - -The Qualcomm socinfo driver has eight more PMICs described, add these to -the SPMI PMIC driver as well. - -Signed-off-by: Bjorn Andersson -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20211017161218.2378176-4-bjorn.andersson@linaro.org ---- - drivers/mfd/qcom-spmi-pmic.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/mfd/qcom-spmi-pmic.c -+++ b/drivers/mfd/qcom-spmi-pmic.c -@@ -31,6 +31,8 @@ - #define PM8916_SUBTYPE 0x0b - #define PM8004_SUBTYPE 0x0c - #define PM8909_SUBTYPE 0x0d -+#define PM8028_SUBTYPE 0x0e -+#define PM8901_SUBTYPE 0x0f - #define PM8950_SUBTYPE 0x10 - #define PMI8950_SUBTYPE 0x11 - #define PM8998_SUBTYPE 0x14 -@@ -38,6 +40,13 @@ - #define PM8005_SUBTYPE 0x18 - #define PM660L_SUBTYPE 0x1A - #define PM660_SUBTYPE 0x1B -+#define PM8150_SUBTYPE 0x1E -+#define PM8150L_SUBTYPE 0x1f -+#define PM8150B_SUBTYPE 0x20 -+#define PMK8002_SUBTYPE 0x21 -+#define PM8009_SUBTYPE 0x24 -+#define PM8150C_SUBTYPE 0x26 -+#define SMB2351_SUBTYPE 0x29 - - static const struct of_device_id pmic_spmi_id_table[] = { - { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, -@@ -45,9 +54,15 @@ static const struct of_device_id pmic_sp - { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE }, - { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE }, - { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE }, -+ { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE }, - { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE }, -+ { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE }, -+ { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE }, -+ { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE }, -+ { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE }, - { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE }, - { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE }, -+ { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE }, - { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE }, - { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE }, - { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE }, -@@ -60,6 +75,8 @@ static const struct of_device_id pmic_sp - { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE }, - { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE }, - { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE }, -+ { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE }, -+ { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE }, - { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE }, - { } - }; diff --git a/target/linux/ipq807x/patches-5.15/0038-v6.0-iio-adc-qcom-spmi-adc5-add-ADC5_VREF_VADC-to-rev2-AD.patch b/target/linux/ipq807x/patches-5.15/0038-v6.0-iio-adc-qcom-spmi-adc5-add-ADC5_VREF_VADC-to-rev2-AD.patch deleted file mode 100644 index a619a291f..000000000 --- a/target/linux/ipq807x/patches-5.15/0038-v6.0-iio-adc-qcom-spmi-adc5-add-ADC5_VREF_VADC-to-rev2-AD.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 1aa9a70ca9a1d3bb5139030fd9fc340d8525a7d7 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 19 Aug 2022 00:18:13 +0200 -Subject: [PATCH 38/44] iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2 - ADC5 - -Add support for ADC5_VREF_VADC channel to rev2 ADC5 channel list. -This channel measures the VADC reference LDO output. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20220818221815.346233-3-robimarko@gmail.com -Signed-off-by: Jonathan Cameron ---- - drivers/iio/adc/qcom-spmi-adc5.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/iio/adc/qcom-spmi-adc5.c -+++ b/drivers/iio/adc/qcom-spmi-adc5.c -@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_c - SCALE_HW_CALIB_DEFAULT) - [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, - SCALE_HW_CALIB_DEFAULT) -+ [ADC5_VREF_VADC] = ADC5_CHAN_VOLT("vref_vadc", 0, -+ SCALE_HW_CALIB_DEFAULT) - [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, - SCALE_HW_CALIB_DEFAULT) - [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1, diff --git a/target/linux/ipq807x/patches-5.15/0039-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch b/target/linux/ipq807x/patches-5.15/0039-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch deleted file mode 100644 index 390dc52b0..000000000 --- a/target/linux/ipq807x/patches-5.15/0039-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 8454872e52992108308e44aa974b441558fa1fc9 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 23 Aug 2022 22:43:51 +0200 -Subject: [PATCH 39/44] phy: qcom-qmp-pcie: make pipe clock rate configurable - -IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz -like every other PCIe QMP PHY does, so make it configurable as part of the -qmp_phy_cfg. - -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/phy/qualcomm/phy-qcom-qmp.c -+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c -@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg { - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; - -+ /* QMP PHY pipe clock interface rate */ -+ unsigned long pipe_clock_rate; -+ - /* true, if PCS block has no separate SW_RESET register */ - bool no_pcs_sw_reset; - }; -@@ -5138,8 +5141,15 @@ static int phy_pipe_clk_register(struct - - init.ops = &clk_fixed_rate_ops; - -- /* controllers using QMP phys use 125MHz pipe clock interface */ -- fixed->fixed_rate = 125000000; -+ /* -+ * Controllers using QMP PHY-s use 125MHz pipe clock interface -+ * unless other frequency is specified in the PHY config. -+ */ -+ if (qmp->phys[0]->cfg->pipe_clock_rate) -+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; -+ else -+ fixed->fixed_rate = 125000000; -+ - fixed->hw.init = &init; - - ret = devm_clk_hw_register(qmp->dev, &fixed->hw); diff --git a/target/linux/ipq807x/patches-5.15/0040-v6.0-phy-qcom-qmp-pcie-add-IPQ8074-PCIe-Gen3-QMP-PHY-supp.patch b/target/linux/ipq807x/patches-5.15/0040-v6.0-phy-qcom-qmp-pcie-add-IPQ8074-PCIe-Gen3-QMP-PHY-supp.patch deleted file mode 100644 index 655d4d24a..000000000 --- a/target/linux/ipq807x/patches-5.15/0040-v6.0-phy-qcom-qmp-pcie-add-IPQ8074-PCIe-Gen3-QMP-PHY-supp.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 6702bed8d48e29bd51c4b702b0baf18c5b1814c1 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 23 Aug 2022 22:47:40 +0200 -Subject: [PATCH 40/44] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY - support - -IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. -Gen2 one is already supported, so add the support for the Gen3 one. -It uses the same register layout as IPQ6018. - -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++ - 1 file changed, 160 insertions(+) - ---- a/drivers/phy/qualcomm/phy-qcom-qmp.c -+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c -@@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq - QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), - }; - -+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { -+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), -+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), -+}; -+ -+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { -+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), -+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), -+ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10), -+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), -+}; -+ -+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { -+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), -+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), -+}; -+ -+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { -+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83), -+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9), -+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42), -+ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40), -+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), -+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), -+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), -+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), -+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), -+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), -+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), -+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), -+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), -+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb), -+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), -+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), -+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), -+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), -+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), -+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), -+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), -+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), -+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), -+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), -+}; -+ - static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), -@@ -3167,6 +3294,36 @@ static const struct qmp_phy_cfg ipq8074_ - .pwrdn_delay_max = 1005, /* us */ - }; - -+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { -+ .type = PHY_TYPE_PCIE, -+ .nlanes = 1, -+ -+ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, -+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), -+ .tx_tbl = ipq8074_pcie_gen3_tx_tbl, -+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), -+ .rx_tbl = ipq8074_pcie_gen3_rx_tbl, -+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), -+ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, -+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), -+ .clk_list = ipq8074_pciephy_clk_l, -+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), -+ .reset_list = ipq8074_pciephy_reset_l, -+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), -+ .vreg_list = NULL, -+ .num_vregs = 0, -+ .regs = ipq_pciephy_gen3_regs_layout, -+ -+ .start_ctrl = SERDES_START | PCS_START, -+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, -+ -+ .has_pwrdn_delay = true, -+ .pwrdn_delay_min = 995, /* us */ -+ .pwrdn_delay_max = 1005, /* us */ -+ -+ .pipe_clock_rate = 250000000, -+}; -+ - static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, -@@ -5543,6 +5700,9 @@ static const struct of_device_id qcom_qm - .compatible = "qcom,ipq8074-qmp-pcie-phy", - .data = &ipq8074_pciephy_cfg, - }, { -+ .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", -+ .data = &ipq8074_pciephy_gen3_cfg, -+ }, { - .compatible = "qcom,ipq6018-qmp-pcie-phy", - .data = &ipq6018_pciephy_cfg, - }, { diff --git a/target/linux/ipq807x/patches-5.15/0045-v5.17-mtd-parsers-qcom-Don-t-print-error-message-on-EPROBE.patch b/target/linux/ipq807x/patches-5.15/0045-v5.17-mtd-parsers-qcom-Don-t-print-error-message-on-EPROBE.patch deleted file mode 100644 index 41150986c..000000000 --- a/target/linux/ipq807x/patches-5.15/0045-v5.17-mtd-parsers-qcom-Don-t-print-error-message-on-EPROBE.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9fbfce710333c5ee674a5cad4cbb12ea5f969769 Mon Sep 17 00:00:00 2001 -From: Bryan O'Donoghue -Date: Mon, 3 Jan 2022 03:03:16 +0000 -Subject: [PATCH] mtd: parsers: qcom: Don't print error message on - -EPROBE_DEFER - -Its possible for the main smem driver to not be loaded by the time we come -along to parse the smem partition description but, this is a perfectly -normal thing. - -No need to print out an error message in this case. - -Signed-off-by: Bryan O'Donoghue -Reviewed-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220103030316.58301-3-bryan.odonoghue@linaro.org ---- - drivers/mtd/parsers/qcomsmempart.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/qcomsmempart.c -+++ b/drivers/mtd/parsers/qcomsmempart.c -@@ -75,7 +75,8 @@ static int parse_qcomsmem_part(struct mt - pr_debug("Parsing partition table info from SMEM\n"); - ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); - if (IS_ERR(ptable)) { -- pr_err("Error reading partition table header\n"); -+ if (PTR_ERR(ptable) != -EPROBE_DEFER) -+ pr_err("Error reading partition table header\n"); - return PTR_ERR(ptable); - } - diff --git a/target/linux/ipq807x/patches-5.15/0100-arm64-dts-ipq8074-add-reserved-memory-nodes.patch b/target/linux/ipq807x/patches-5.15/0101-arm64-dts-ipq8074-add-reserved-memory-nodes.patch similarity index 71% rename from target/linux/ipq807x/patches-5.15/0100-arm64-dts-ipq8074-add-reserved-memory-nodes.patch rename to target/linux/ipq807x/patches-5.15/0101-arm64-dts-ipq8074-add-reserved-memory-nodes.patch index 314db03b2..f4a964d83 100644 --- a/target/linux/ipq807x/patches-5.15/0100-arm64-dts-ipq8074-add-reserved-memory-nodes.patch +++ b/target/linux/ipq807x/patches-5.15/0101-arm64-dts-ipq8074-add-reserved-memory-nodes.patch @@ -1,7 +1,7 @@ -From 2dc8319c43ccc511a38f441ab4f7aa120af9a9fb Mon Sep 17 00:00:00 2001 +From 4b6d5caa1747bbe0eca15d4d20f028748c544cd0 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 22 Dec 2021 12:23:34 +0100 -Subject: [PATCH 100/137] arm64: dts: ipq8074: add reserved memory nodes +Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes IPQ8074 has multiple reserved memory ranges, if they are not defined then weird things tend to happen, board hangs and resets when PCI or @@ -14,12 +14,14 @@ devices with lower ammounts can override the Q6 node. Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 40 +++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index adce47affbef..94de2bd6596f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -85,6 +85,26 @@ +@@ -81,6 +81,31 @@ reserved-memory { #size-cells = <2>; ranges; @@ -42,13 +44,18 @@ Signed-off-by: Robert Marko + no-map; + reg = <0x0 0x4aa00000 0x0 0x00100000>; + }; ++ ++ tz@4ac00000 { ++ no-map; ++ reg = <0x0 0x4ac00000 0x0 0x00400000>; ++ }; + smem@4ab00000 { compatible = "qcom,smem"; reg = <0x0 0x4ab00000 0x0 0x00100000>; -@@ -97,6 +117,21 @@ - no-map; - reg = <0x0 0x4ac00000 0x0 0x00400000>; +@@ -88,6 +113,21 @@ smem@4ab00000 { + + hwlocks = <&tcsr_mutex 0>; }; + + q6_region: wcnss@4b000000 { @@ -68,3 +75,6 @@ Signed-off-by: Robert Marko }; firmware { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch b/target/linux/ipq807x/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch deleted file mode 100644 index 6e210c430..000000000 --- a/target/linux/ipq807x/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 9d38e110e23ce0b858ccd67a8a819dc187529a33 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 8 Jul 2022 23:24:25 +0200 -Subject: [PATCH 101/137] clk: qcom: clk-rcg2: add rcg2 mux ops - -An RCG may act as a mux that switch between 2 parents. -This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds -the CPU cluster clock just switches between XO and the PLL that feeds it. - -Add the required ops to add support for this special configuration and use -the generic mux function to determine the rate. - -This way we dont have to keep a essentially dummy frequency table to use -RCG2 as a mux. - -Signed-off-by: Christian Marangi -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov ---- - drivers/clk/qcom/clk-rcg.h | 1 + - drivers/clk/qcom/clk-rcg2.c | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d { - - extern const struct clk_ops clk_rcg2_ops; - extern const struct clk_ops clk_rcg2_floor_ops; -+extern const struct clk_ops clk_rcg2_mux_closest_ops; - extern const struct clk_ops clk_edp_pixel_ops; - extern const struct clk_ops clk_byte_ops; - extern const struct clk_ops clk_byte2_ops; ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops - }; - EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); - -+const struct clk_ops clk_rcg2_mux_closest_ops = { -+ .determine_rate = __clk_mux_determine_rate_closest, -+ .get_parent = clk_rcg2_get_parent, -+ .set_parent = clk_rcg2_set_parent, -+}; -+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops); -+ - struct frac_entry { - int num; - int den; diff --git a/target/linux/ipq807x/patches-5.15/0102-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch b/target/linux/ipq807x/patches-5.15/0102-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch deleted file mode 100644 index 9f05a72f1..000000000 --- a/target/linux/ipq807x/patches-5.15/0102-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch +++ /dev/null @@ -1,61 +0,0 @@ -From d2b31da4eae2175ff86f28f596b54abde08d382f Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 9 Jul 2022 00:18:45 +0200 -Subject: [PATCH 102/137] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src - -While working on IPQ8074 APSS driver it was discovered that IPQ6018 and -IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is -currently broken. - -More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux -clock. -However after debugging why it was always stuck at 800Mhz, it was figured -out that its not regmap_mux compatible at all. -It is a simple mux but it uses RCG2 register layout and control bits, so -utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not -having to provide a dummy frequency table. - -While we are here, use ARRAY_SIZE for number of parents. - -Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. - -Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov ---- - drivers/clk/qcom/apss-ipq6018.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - ---- a/drivers/clk/qcom/apss-ipq6018.c -+++ b/drivers/clk/qcom/apss-ipq6018.c -@@ -16,7 +16,7 @@ - #include "clk-regmap.h" - #include "clk-branch.h" - #include "clk-alpha-pll.h" --#include "clk-regmap-mux.h" -+#include "clk-rcg.h" - - enum { - P_XO, -@@ -33,16 +33,15 @@ static const struct parent_map parents_a - { P_APSS_PLL_EARLY, 5 }, - }; - --static struct clk_regmap_mux apcs_alias0_clk_src = { -- .reg = 0x0050, -- .width = 3, -- .shift = 7, -+static struct clk_rcg2 apcs_alias0_clk_src = { -+ .cmd_rcgr = 0x0050, -+ .hid_width = 5, - .parent_map = parents_apcs_alias0_clk_src_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "apcs_alias0_clk_src", - .parent_data = parents_apcs_alias0_clk_src, -- .num_parents = 2, -- .ops = &clk_regmap_mux_closest_ops, -+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), -+ .ops = &clk_rcg2_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }; diff --git a/target/linux/ipq807x/patches-5.15/0103-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch b/target/linux/ipq807x/patches-5.15/0103-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch new file mode 100644 index 000000000..8f562e2a6 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0103-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch @@ -0,0 +1,377 @@ +From 6fe752e3927ee9d9cad6ad197d5fe58c23a61935 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Wed, 29 Jul 2020 21:00:04 +0530 +Subject: [PATCH] phy: qcom-qmp: Add IPQ8074 PCIe Gen3 QMP PHY support + +IPQ8074 has two PCIe ports, One Gen2 and one Gen3 port. +Since support for Gen2 PHY is already available, add support for +PCIe Gen3 PHY. + +Co-developed-by: Selvam Sathappan Periakaruppan +Signed-off-by: Selvam Sathappan Periakaruppan +Signed-off-by: Sivaprakash Murugesan +Signed-off-by: Robert Marko +--- + drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 ++++++++++++++++++ + drivers/phy/qualcomm/phy-qcom-qmp.c | 171 +++++++++++++++++++++- + 2 files changed, 308 insertions(+), 2 deletions(-) + create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h + +diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h +new file mode 100644 +index 000000000000..070bde355836 +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h +@@ -0,0 +1,139 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++/* ++ * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef PHY_QCOM_PCIE_H ++#define PHY_QCOM_PCIE_H ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */ ++#define QSERDES_PLL_BG_TIMER 0x00c ++#define QSERDES_PLL_SSC_PER1 0x01c ++#define QSERDES_PLL_SSC_PER2 0x020 ++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 ++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 ++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c ++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 ++#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c ++#define QSERDES_PLL_CLK_ENABLE1 0x040 ++#define QSERDES_PLL_SYS_CLK_CTRL 0x044 ++#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 ++#define QSERDES_PLL_PLL_IVCO 0x050 ++#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 ++#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 ++#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 ++#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 ++#define QSERDES_PLL_BG_TRIM 0x074 ++#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 ++#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c ++#define QSERDES_PLL_CP_CTRL_MODE0 0x080 ++#define QSERDES_PLL_CP_CTRL_MODE1 0x084 ++#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 ++#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C ++#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 ++#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 ++#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 ++#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 ++#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 ++#define QSERDES_PLL_LOCK_CMP_EN 0x0c4 ++#define QSERDES_PLL_DEC_START_MODE0 0x0cc ++#define QSERDES_PLL_DEC_START_MODE1 0x0d0 ++#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 ++#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc ++#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 ++#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 ++#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 ++#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC ++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 ++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 ++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 ++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c ++#define QSERDES_PLL_VCO_TUNE_MAP 0x120 ++#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 ++#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 ++#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c ++#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 ++#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c ++#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 ++#define QSERDES_PLL_CLK_SELECT 0x16c ++#define QSERDES_PLL_HSCLK_SEL 0x170 ++#define QSERDES_PLL_CORECLK_DIV 0x17c ++#define QSERDES_PLL_CORE_CLK_EN 0x184 ++#define QSERDES_PLL_CMN_CONFIG 0x18c ++#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 ++#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */ ++#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c ++#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 ++#define QSERDES_TX0_LANE_MODE_1 0x084 ++#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */ ++#define QSERDES_RX0_UCDR_FO_GAIN 0x008 ++#define QSERDES_RX0_UCDR_SO_GAIN 0x014 ++#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 ++#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 ++#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 ++#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc ++#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 ++#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 ++#define QSERDES_RX0_SIGDET_ENABLES 0x118 ++#define QSERDES_RX0_SIGDET_CNTRL 0x11c ++#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 ++#define QSERDES_RX0_RX_MODE_00_LOW 0x170 ++#define QSERDES_RX0_RX_MODE_00_HIGH 0x174 ++#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 ++#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c ++#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 ++#define QSERDES_RX0_RX_MODE_01_LOW 0x184 ++#define QSERDES_RX0_RX_MODE_01_HIGH 0x188 ++#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c ++#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 ++#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 ++#define QSERDES_RX0_RX_MODE_10_LOW 0x198 ++#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c ++#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 ++#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 ++#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 ++#define QSERDES_RX0_DFE_EN_TIMER 0x1b4 ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS registers */ ++ ++#define PCS_COM_FLL_CNTRL1 0x098 ++#define PCS_COM_FLL_CNTRL2 0x09c ++#define PCS_COM_FLL_CNT_VAL_L 0x0a0 ++#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 ++#define PCS_COM_FLL_MAN_CODE 0x0a8 ++#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc ++#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c ++#define PCS_COM_RX_SIGDET_LVL 0x188 ++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 ++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 ++#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 ++#define PCS_COM_EQ_CONFIG5 0x1ec ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS Misc registers */ ++ ++#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c ++#define PCS_PCIE_POWER_STATE_CONFIG4 0x414 ++#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c ++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 ++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 ++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 ++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c ++#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 ++#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 ++#define PCS_PCIE_EQ_CONFIG1 0x4a0 ++#define PCS_PCIE_EQ_CONFIG2 0x4a4 ++#define PCS_PCIE_PRESET_P10_PRE 0x4bc ++#define PCS_PCIE_PRESET_P10_POST 0x4e0 ++ ++#endif +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c +index 06b04606dd7e..7d139754889a 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +@@ -23,6 +23,7 @@ + #include + + #include "phy-qcom-qmp.h" ++#include "phy-qcom-pcie3-qmp.h" + + /* QPHY_SW_RESET bit */ + #define SW_RESET BIT(0) +@@ -812,6 +813,132 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), + }; + ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +@@ -3194,6 +3321,36 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { + .pwrdn_delay_max = 1005, /* us */ + }; + ++static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_gen3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx_tbl = ipq8074_pcie_gen3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ + static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, +@@ -5138,8 +5295,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) + + init.ops = &clk_fixed_rate_ops; + +- /* controllers using QMP phys use 125MHz pipe clock interface */ +- fixed->fixed_rate = 125000000; ++ /* ++ * controllers using QMP phys use 125MHz pipe clock interface unless ++ * other frequency is specified in dts ++ */ ++ ret = of_property_read_u32(np, "clock-output-rate", ++ (u32 *)&fixed->fixed_rate); ++ if (ret) ++ fixed->fixed_rate = 125000000; ++ + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); +@@ -5529,6 +5693,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + }, { + .compatible = "qcom,ipq6018-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-gen3-phy", ++ .data = &ipq8074_pciephy_gen3_cfg, + }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch b/target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch similarity index 72% rename from target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch rename to target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch index 274940d40..7cfb7d967 100644 --- a/target/linux/ipq807x/patches-5.15/0011-v5.18-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch +++ b/target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch @@ -1,21 +1,21 @@ -From 4f0959ded385c8ed518659aa08cedbd83ae0726a Mon Sep 17 00:00:00 2001 +From 110bec39320cbfd23ac869af4aa231cda9c5f74a Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 8 Feb 2022 21:05:24 +0530 -Subject: [PATCH 11/44] arm64: dts: qcom: ipq8074: enable the GICv2m support +Subject: [PATCH] arm64: dts: qcom: ipq8074: enable the GICv2m support GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 452a81d288f4..777c6267e777 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -634,9 +634,18 @@ +@@ -669,9 +669,18 @@ dwc_1: dwc3@8c00000 { intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; @@ -34,3 +34,6 @@ Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@ }; timer { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0104-clk-qcom-apss-ipq-pll-use-OF-match-data-for-Alpha-PL.patch b/target/linux/ipq807x/patches-5.15/0104-clk-qcom-apss-ipq-pll-use-OF-match-data-for-Alpha-PL.patch deleted file mode 100644 index 18ba654a0..000000000 --- a/target/linux/ipq807x/patches-5.15/0104-clk-qcom-apss-ipq-pll-use-OF-match-data-for-Alpha-PL.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 8878f39722eeacbb40babe82ad763d8d20214018 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 9 Jul 2022 00:32:04 +0200 -Subject: [PATCH 104/137] clk: qcom: apss-ipq-pll: use OF match data for Alpha - PLL config - -Convert the driver to use OF match data for providing the Alpha PLL config -per compatible. -This is required for IPQ8074 support since it uses a different Alpha PLL -config. - -While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make -it clear that it is for IPQ6018 only. - -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/apss-ipq-pll.c | 12 +++++++++--- - 1 file changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -2,6 +2,7 @@ - // Copyright (c) 2018, The Linux Foundation. All rights reserved. - #include - #include -+#include - #include - #include - -@@ -36,7 +37,7 @@ static struct clk_alpha_pll ipq_pll = { - }, - }; - --static const struct alpha_pll_config ipq_pll_config = { -+static const struct alpha_pll_config ipq6018_pll_config = { - .l = 0x37, - .config_ctl_val = 0x04141200, - .config_ctl_hi_val = 0x0, -@@ -54,6 +55,7 @@ static const struct regmap_config ipq_pl - - static int apss_ipq_pll_probe(struct platform_device *pdev) - { -+ const struct alpha_pll_config *ipq_pll_config; - struct device *dev = &pdev->dev; - struct regmap *regmap; - void __iomem *base; -@@ -67,7 +69,11 @@ static int apss_ipq_pll_probe(struct pla - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - -- clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config); -+ ipq_pll_config = of_device_get_match_data(&pdev->dev); -+ if (!ipq_pll_config) -+ return -ENODEV; -+ -+ clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config); - - ret = devm_clk_register_regmap(dev, &ipq_pll.clkr); - if (ret) -@@ -78,7 +84,7 @@ static int apss_ipq_pll_probe(struct pla - } - - static const struct of_device_id apss_ipq_pll_match_table[] = { -- { .compatible = "qcom,ipq6018-a53pll" }, -+ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config }, - { } - }; - MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); diff --git a/target/linux/ipq807x/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch b/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch similarity index 78% rename from target/linux/ipq807x/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch rename to target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch index 716e3a908..8655d60c8 100644 --- a/target/linux/ipq807x/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch +++ b/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch @@ -1,8 +1,8 @@ -From 66dafdaad281e0a0eb2045ffb1f8dcf72e25989f Mon Sep 17 00:00:00 2001 +From dae5693368998da74d3a460da739677c02c9c6af Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 7 Feb 2022 16:51:24 +0200 -Subject: [PATCH 42/44] PCI: dwc: tegra: move GEN3_RELATED DBI register to - common header +Subject: [PATCH] PCI: dwc: tegra: move GEN3_RELATED DBI register to common + header These are common dwc macros that will be used for other platforms. @@ -13,6 +13,8 @@ Signed-off-by: Baruch Siach drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index 7d6e9b7576be..ea87809ee298 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -74,6 +74,12 @@ @@ -28,6 +30,8 @@ Signed-off-by: Baruch Siach #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) +diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c +index 904976913081..846c9d154f49 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -193,12 +193,6 @@ @@ -43,3 +47,6 @@ Signed-off-by: Baruch Siach #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0105-clk-qcom-apss-ipq-pll-update-IPQ6018-Alpha-PLL-confi.patch b/target/linux/ipq807x/patches-5.15/0105-clk-qcom-apss-ipq-pll-update-IPQ6018-Alpha-PLL-confi.patch deleted file mode 100644 index 6a84c13cc..000000000 --- a/target/linux/ipq807x/patches-5.15/0105-clk-qcom-apss-ipq-pll-update-IPQ6018-Alpha-PLL-confi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 426edd7e45e9eaf18c433739ceeb51e6f2f8e190 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 11 Jul 2022 22:40:52 +0200 -Subject: [PATCH 105/137] clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL - config - -Update the IPQ6018 Alpha PLL config to the latest one from the downstream -5.4 kernel[1]. - -This one should match the production SoC-s. - -Tested on IPQ6018 CP01-C1 reference board. - -[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41 -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/apss-ipq-pll.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -39,10 +39,14 @@ static struct clk_alpha_pll ipq_pll = { - - static const struct alpha_pll_config ipq6018_pll_config = { - .l = 0x37, -- .config_ctl_val = 0x04141200, -- .config_ctl_hi_val = 0x0, -+ .config_ctl_val = 0x240d4828, -+ .config_ctl_hi_val = 0x6, - .early_output_mask = BIT(3), -+ .aux2_output_mask = BIT(2), -+ .aux_output_mask = BIT(1), - .main_output_mask = BIT(0), -+ .test_ctl_val = 0x1c0000C0, -+ .test_ctl_hi_val = 0x4000, - }; - - static const struct regmap_config ipq_pll_regmap_config = { diff --git a/target/linux/ipq807x/patches-5.15/0043-v6.0-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch b/target/linux/ipq807x/patches-5.15/0106-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch similarity index 80% rename from target/linux/ipq807x/patches-5.15/0043-v6.0-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch rename to target/linux/ipq807x/patches-5.15/0106-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch index d84839f2b..b158e65b3 100644 --- a/target/linux/ipq807x/patches-5.15/0043-v6.0-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch +++ b/target/linux/ipq807x/patches-5.15/0106-PCI-qcom-Define-slot-capabilities-using-PCI_EXP_SLTC.patch @@ -1,8 +1,7 @@ -From 55299da8c17f23249497ee8868a5a268c6e3fbcc Mon Sep 17 00:00:00 2001 +From 70261569da66997eb4c6057b136af417ed06716e Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 7 Feb 2022 16:51:25 +0200 -Subject: [PATCH 43/44] PCI: qcom: Define slot capabilities using - PCI_EXP_SLTCAP_* +Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better @@ -13,6 +12,8 @@ Signed-off-by: Baruch Siach drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index 8a7a300163e5..f5101258d73b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -69,7 +69,18 @@ @@ -35,7 +36,7 @@ Signed-off-by: Baruch Siach #define PCIE20_PARF_Q2A_FLUSH 0x1AC -@@ -1125,7 +1136,7 @@ static int qcom_pcie_post_init_2_3_3(str +@@ -1102,7 +1113,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); @@ -44,3 +45,6 @@ Signed-off-by: Baruch Siach val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); val &= ~PCI_EXP_LNKCAP_ASPMS; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0106-clk-qcom-apss-ipq-pll-add-support-for-IPQ8074.patch b/target/linux/ipq807x/patches-5.15/0106-clk-qcom-apss-ipq-pll-add-support-for-IPQ8074.patch deleted file mode 100644 index f59ce60c8..000000000 --- a/target/linux/ipq807x/patches-5.15/0106-clk-qcom-apss-ipq-pll-add-support-for-IPQ8074.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c633afe32123157370f21aeaf3d705ca584fc754 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 11 Jul 2022 14:23:08 +0200 -Subject: [PATCH 106/137] clk: qcom: apss-ipq-pll: add support for IPQ8074 - -Add support for IPQ8074 since it uses the same PLL setup, however it uses -slightly different Alpha PLL config. - -Alpha PLL config was obtained by dumping PLL registers from a running -device. - -Signed-off-by: Robert Marko ---- -Changes in v2: -* Drop hardcoded compatible check for IPQ6018 to do the PLL config and -utilize match data provided by previous commit -* Add IPQ8074 Alpha PLL config using match data -* Update commit description to reflect changes ---- - drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -49,6 +49,18 @@ static const struct alpha_pll_config ipq - .test_ctl_hi_val = 0x4000, - }; - -+static const struct alpha_pll_config ipq8074_pll_config = { -+ .l = 0x48, -+ .config_ctl_val = 0x200d4828, -+ .config_ctl_hi_val = 0x6, -+ .early_output_mask = BIT(3), -+ .aux2_output_mask = BIT(2), -+ .aux_output_mask = BIT(1), -+ .main_output_mask = BIT(0), -+ .test_ctl_val = 0x1c000000, -+ .test_ctl_hi_val = 0x4000, -+}; -+ - static const struct regmap_config ipq_pll_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -89,6 +101,7 @@ static int apss_ipq_pll_probe(struct pla - - static const struct of_device_id apss_ipq_pll_match_table[] = { - { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config }, -+ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config }, - { } - }; - MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); diff --git a/target/linux/ipq807x/patches-5.15/0044-v6.0-PCI-qcom-Add-IPQ60xx-support.patch b/target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-IPQ60xx-support.patch similarity index 90% rename from target/linux/ipq807x/patches-5.15/0044-v6.0-PCI-qcom-Add-IPQ60xx-support.patch rename to target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-IPQ60xx-support.patch index 93bec2f04..501498a0a 100644 --- a/target/linux/ipq807x/patches-5.15/0044-v6.0-PCI-qcom-Add-IPQ60xx-support.patch +++ b/target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-IPQ60xx-support.patch @@ -1,7 +1,7 @@ -From b9d02fcefdf166671356a08dd621429e63541b22 Mon Sep 17 00:00:00 2001 +From 5d15adca10588019810505a07ed3f6758e4413be Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Thu, 10 Feb 2022 18:02:47 +0100 -Subject: [PATCH 44/44] PCI: qcom: Add IPQ60xx support +Subject: [PATCH] PCI: qcom: Add IPQ60xx support IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform. @@ -21,6 +21,8 @@ Signed-off-by: Baruch Siach drivers/pci/controller/dwc/pcie-qcom.c | 135 +++++++++++++++++++ 2 files changed, 136 insertions(+) +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index ea87809ee298..279c3778a13b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -76,6 +76,7 @@ @@ -31,6 +33,8 @@ Signed-off-by: Baruch Siach #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index f5101258d73b..05359cfc0e34 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -52,6 +52,10 @@ @@ -64,7 +68,7 @@ Signed-off-by: Baruch Siach }; struct qcom_pcie; -@@ -1276,6 +1286,121 @@ static void qcom_pcie_post_deinit_2_7_0( +@@ -1277,6 +1287,121 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->pipe_clk); } @@ -186,7 +190,7 @@ Signed-off-by: Baruch Siach static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); -@@ -1467,6 +1592,15 @@ static const struct qcom_pcie_ops ops_1_ +@@ -1467,6 +1592,15 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -202,7 +206,7 @@ Signed-off-by: Baruch Siach static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, -@@ -1565,6 +1699,7 @@ static const struct of_device_id qcom_pc +@@ -1566,6 +1700,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, @@ -210,3 +214,6 @@ Signed-off-by: Baruch Siach { } }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0107-arm64-dts-qcom-ipq8074-correct-APCS-register-space-s.patch b/target/linux/ipq807x/patches-5.15/0107-arm64-dts-qcom-ipq8074-correct-APCS-register-space-s.patch deleted file mode 100644 index 01a4acc9a..000000000 --- a/target/linux/ipq807x/patches-5.15/0107-arm64-dts-qcom-ipq8074-correct-APCS-register-space-s.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f3d524334069e69554eaecd8adf75284dff7c9d9 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 18 Aug 2022 23:15:43 +0200 -Subject: [PATCH 107/137] arm64: dts: qcom: ipq8074: correct APCS register - space size - -APCS DTS addition that was merged, was not supposed to get merged as it -was part of patch series that was superseded by 2 more patch series -that resolved issues with this one and greatly simplified things. - -Since it already got merged, start by correcting the register space -size as APCS will not be providing regmap for PLL and it will conflict -with the standalone A53 PLL node. - -Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node") -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -703,7 +703,7 @@ - - apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq8074-apcs-apps-global"; -- reg = <0x0b111000 0x6000>; -+ reg = <0x0b111000 0x1000>; - - #clock-cells = <1>; - #mbox-cells = <1>; diff --git a/target/linux/ipq807x/patches-5.15/0111-PCI-qcom-add-IPQ8074-Gen3-support.patch b/target/linux/ipq807x/patches-5.15/0108-PCI-qcom-add-IPQ8074-Gen3-support.patch similarity index 74% rename from target/linux/ipq807x/patches-5.15/0111-PCI-qcom-add-IPQ8074-Gen3-support.patch rename to target/linux/ipq807x/patches-5.15/0108-PCI-qcom-add-IPQ8074-Gen3-support.patch index 3a3c5b84a..0112eef31 100644 --- a/target/linux/ipq807x/patches-5.15/0111-PCI-qcom-add-IPQ8074-Gen3-support.patch +++ b/target/linux/ipq807x/patches-5.15/0108-PCI-qcom-add-IPQ8074-Gen3-support.patch @@ -1,7 +1,7 @@ -From f086c5659cd54946b618ae4c695a8c05096f267a Mon Sep 17 00:00:00 2001 +From 4e93203281f4b0c82bf36afd5f316e37991d6456 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 20 Dec 2021 15:01:36 +0100 -Subject: [PATCH 111/137] PCI: qcom: add IPQ8074 Gen3 support +Subject: [PATCH] PCI: qcom: add IPQ8074 Gen3 support IPQ8074 has one Gen2 and one Gen3 port, Gen3 port is the same one as in IPQ6018, so reuse the support but just add the missing clocks. @@ -11,6 +11,8 @@ Signed-off-by: Robert Marko drivers/pci/controller/dwc/pcie-qcom.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index 05359cfc0e34..5556859eed18 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -184,7 +184,7 @@ struct qcom_pcie_resources_2_7_0 { @@ -22,7 +24,7 @@ Signed-off-by: Robert Marko struct reset_control *rst; }; -@@ -1296,8 +1296,10 @@ static int qcom_pcie_get_resources_2_9_0 +@@ -1297,8 +1297,10 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) res->clks[0].id = "iface"; res->clks[1].id = "axi_m"; res->clks[2].id = "axi_s"; @@ -35,7 +37,7 @@ Signed-off-by: Robert Marko ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); if (ret < 0) -@@ -1700,6 +1702,7 @@ static const struct of_device_id qcom_pc +@@ -1701,6 +1703,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 }, @@ -43,3 +45,6 @@ Signed-off-by: Robert Marko { } }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch b/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch deleted file mode 100644 index fbbe3fd97..000000000 --- a/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch +++ /dev/null @@ -1,30 +0,0 @@ -From be028f5f79b8af6ea16ffeea486e216acdf80789 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 18 Aug 2022 23:21:06 +0200 -Subject: [PATCH 108/137] arm64: dts: qcom: ipq8074: add A53 PLL node - -Add the required node for A53 PLL which will be used to provide the CPU -clock via APCS for APSS scaling. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -709,6 +709,14 @@ - #mbox-cells = <1>; - }; - -+ a53pll: clock@b116000 { -+ compatible = "qcom,ipq8074-a53pll"; -+ reg = <0x0b116000 0x40>; -+ #clock-cells = <0>; -+ clocks = <&xo>; -+ clock-names = "xo"; -+ }; -+ - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/ipq807x/patches-5.15/0109-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-support.patch b/target/linux/ipq807x/patches-5.15/0109-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-support.patch deleted file mode 100644 index 32a9faafe..000000000 --- a/target/linux/ipq807x/patches-5.15/0109-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From ded0538937e9edf8b217d2082fd30af3bf7bd10b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 28 Dec 2021 20:59:18 +0100 -Subject: [PATCH 109/137] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock - support - -IPQ8074 has the APSS clock controller utilizing the same register space as -the APCS, so provide access to the APSS utilizing a child device like -IPQ6018. - -IPQ6018 and IPQ8074 use the same controller and driver, so just utilize -IPQ6018 match data for IPQ8074. - -Signed-off-by: Robert Marko -Reviewed-by: Dmitry Baryshkov ---- -Changes in v7: -* Dont max_register modifications -* Drop custom IPQ8074 match data and use IPQ6018 one as they share the -controller and driver - -Changes in v5: -* Use lower case hex for max_register -* Update the APSS clock name to match the new one without commas ---- - drivers/mailbox/qcom-apcs-ipc-mailbox.c | 6 +----- - 1 file changed, 1 insertion(+), 5 deletions(-) - ---- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c -+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c -@@ -33,10 +33,6 @@ static const struct qcom_apcs_ipc_data i - .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" - }; - --static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { -- .offset = 8, .clk_name = NULL --}; -- - static const struct qcom_apcs_ipc_data msm8916_apcs_data = { - .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" - }; -@@ -160,7 +156,7 @@ static int qcom_apcs_ipc_remove(struct p - /* .data is the offset of the ipc register within the global block */ - static const struct of_device_id qcom_apcs_ipc_of_match[] = { - { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, -- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, -+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data }, - { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, - { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, - { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, diff --git a/target/linux/ipq807x/patches-5.15/0112-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch b/target/linux/ipq807x/patches-5.15/0110-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch similarity index 78% rename from target/linux/ipq807x/patches-5.15/0112-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch rename to target/linux/ipq807x/patches-5.15/0110-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch index fa31c462f..392838149 100644 --- a/target/linux/ipq807x/patches-5.15/0112-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch +++ b/target/linux/ipq807x/patches-5.15/0110-arm64-dts-ipq8074-fix-PCI-related-DT-nodes.patch @@ -1,7 +1,7 @@ -From 184c9b73285f05ebc013205d54ed11cd968cb38e Mon Sep 17 00:00:00 2001 +From 9e280276de874970d03cdc124d8bfa7afbb6aef1 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 20 Dec 2021 15:08:04 +0100 -Subject: [PATCH 112/137] arm64: dts: ipq8074: fix PCI related DT nodes +Subject: [PATCH] arm64: dts: ipq8074: fix PCI related DT nodes Currently present PCI PHY and PCI controller nodes are not working and are incorrect for the v2 of IPQ8074 which is the only version @@ -11,12 +11,14 @@ So, correct the PCI related nodes. Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 93 +++++++++++++++------------ - 1 file changed, 52 insertions(+), 41 deletions(-) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 73 +++++++++++++++------------ + 1 file changed, 42 insertions(+), 31 deletions(-) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 777c6267e777..2f553b82ca12 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -232,59 +232,61 @@ +@@ -228,9 +228,9 @@ qusb_phy_0: phy@79000 { status = "disabled"; }; @@ -24,24 +26,13 @@ Signed-off-by: Robert Marko - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1000>; + pcie_qmp0: phy@84000 { -+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; ++ compatible = "qcom,ipq8074-qmp-pcie-gen3-phy"; + reg = <0x00084000 0x1bc>; #address-cells = <1>; #size-cells = <1>; ranges; - - clocks = <&gcc GCC_PCIE0_AUX_CLK>, -- <&gcc GCC_PCIE0_AHB_CLK>; -+ <&gcc GCC_PCIE0_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; -+ - resets = <&gcc GCC_PCIE0_PHY_BCR>, -- <&gcc GCC_PCIE0PHY_PHY_BCR>; -- reset-names = "phy", -- "common"; -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ reset-names = "phy", "common"; -+ +@@ -244,21 +244,22 @@ pcie_qmp0: phy@86000 { + "common"; status = "disabled"; - pcie_phy0: phy@86200 { @@ -56,8 +47,8 @@ Signed-off-by: Robert Marko #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "pipe0"; -- clock-output-names = "pcie_0_pipe_clk"; -+ clock-output-names = "gcc_pcie0_pipe_clk_src"; + clock-output-names = "pcie_0_pipe_clk"; ++ clock-output-rate = <250000000>; }; }; @@ -68,19 +59,7 @@ Signed-off-by: Robert Marko #address-cells = <1>; #size-cells = <1>; ranges; - - clocks = <&gcc GCC_PCIE1_AUX_CLK>, -- <&gcc GCC_PCIE1_AHB_CLK>; -+ <&gcc GCC_PCIE1_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; -+ - resets = <&gcc GCC_PCIE1_PHY_BCR>, -- <&gcc GCC_PCIE1PHY_PHY_BCR>; -- reset-names = "phy", -- "common"; -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ reset-names = "phy", "common"; -+ +@@ -273,14 +274,15 @@ pcie_qmp1: phy@8e000 { status = "disabled"; pcie_phy1: phy@8e200 { @@ -93,12 +72,12 @@ Signed-off-by: Robert Marko #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "pipe0"; -- clock-output-names = "pcie_1_pipe_clk"; -+ clock-output-names = "gcc_pcie1_pipe_clk_src"; + clock-output-names = "pcie_1_pipe_clk"; ++ clock-output-rate = <125000000>; }; }; -@@ -686,7 +688,7 @@ +@@ -676,7 +678,7 @@ intc: interrupt-controller@b000000 { reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; ranges = <0 0xb00a000 0xffd>; @@ -107,7 +86,7 @@ Signed-off-by: Robert Marko compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xffd>; -@@ -787,6 +789,7 @@ +@@ -769,6 +771,7 @@ pcie1: pci@10000000 { linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; @@ -115,7 +94,7 @@ Signed-off-by: Robert Marko #address-cells = <3>; #size-cells = <2>; -@@ -794,12 +797,12 @@ +@@ -776,12 +779,12 @@ pcie1: pci@10000000 { phy-names = "pciephy"; ranges = <0x81000000 0 0x10200000 0x10200000 @@ -133,7 +112,7 @@ Signed-off-by: Robert Marko #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 142 -@@ -839,16 +842,18 @@ +@@ -821,16 +824,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ }; pcie0: pci@20000000 { @@ -158,7 +137,7 @@ Signed-off-by: Robert Marko #address-cells = <3>; #size-cells = <2>; -@@ -856,12 +861,12 @@ +@@ -838,12 +843,12 @@ pcie0: pci@20000000 { phy-names = "pciephy"; ranges = <0x81000000 0 0x20200000 0x20200000 @@ -176,7 +155,7 @@ Signed-off-by: Robert Marko #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 75 -@@ -877,27 +882,33 @@ +@@ -859,27 +864,33 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, <&gcc GCC_PCIE0_AHB_CLK>, @@ -214,3 +193,6 @@ Signed-off-by: Robert Marko status = "disabled"; }; }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0110-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch b/target/linux/ipq807x/patches-5.15/0110-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch deleted file mode 100644 index 70f8da091..000000000 --- a/target/linux/ipq807x/patches-5.15/0110-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0a36a586424feabf9ce9436379f9d061b7844155 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 18 Aug 2022 23:25:00 +0200 -Subject: [PATCH 110/137] arm64: dts: qcom: ipq8074: add clocks to APCS - -APCS now has support for providing the APSS clocks as the child device -for IPQ8074. - -So, add the A53 PLL and XO clocks in order to use APCS as the CPU -clocksource for APSS scaling. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -704,8 +704,9 @@ - apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq8074-apcs-apps-global"; - reg = <0x0b111000 0x1000>; -- - #clock-cells = <1>; -+ clocks = <&a53pll>, <&xo>; -+ clock-names = "pll", "xo"; - #mbox-cells = <1>; - }; - diff --git a/target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-PRNG-proxy-clock.patch b/target/linux/ipq807x/patches-5.15/0111-remoteproc-qcom-Add-PRNG-proxy-clock.patch similarity index 83% rename from target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-PRNG-proxy-clock.patch rename to target/linux/ipq807x/patches-5.15/0111-remoteproc-qcom-Add-PRNG-proxy-clock.patch index 2a12cec48..0e9157c99 100644 --- a/target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-PRNG-proxy-clock.patch +++ b/target/linux/ipq807x/patches-5.15/0111-remoteproc-qcom-Add-PRNG-proxy-clock.patch @@ -1,7 +1,7 @@ -From 84e13a5267e43bb0a6a1f764211fda7769dc9cbe Mon Sep 17 00:00:00 2001 +From ddc957c5eee78cf41d04040b6de3e3437830b473 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:05 +0530 -Subject: [PATCH 113/137] remoteproc: qcom: Add PRNG proxy clock +Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock PRNG clock is needed by the secure PIL, support for the same is added in subsequent patches. @@ -13,6 +13,8 @@ Signed-off-by: Nikhil Prakash V drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 18 deletions(-) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index 20d50ec7eff1..0e5484020296 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -91,19 +91,6 @@ enum { @@ -65,7 +67,7 @@ Signed-off-by: Nikhil Prakash V static int q6v5_wcss_reset(struct q6v5_wcss *wcss) { int ret; -@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc +@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; @@ -78,7 +80,7 @@ Signed-off-by: Nikhil Prakash V qcom_q6v5_prepare(&wcss->q6v5); /* Release Q6 and WCSS reset */ -@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc * +@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } @@ -86,7 +88,7 @@ Signed-off-by: Nikhil Prakash V qcom_q6v5_unprepare(&wcss->q6v5); return 0; -@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(stru +@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) return 0; } @@ -109,7 +111,7 @@ Signed-off-by: Nikhil Prakash V { int ret; -@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q +@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) return 0; } @@ -118,7 +120,7 @@ Signed-off-by: Nikhil Prakash V { wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); if (IS_ERR(wcss->cx_supply)) -@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platfo +@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) goto free_rproc; @@ -136,7 +138,7 @@ Signed-off-by: Nikhil Prakash V if (ret) goto free_rproc; } -@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platf +@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) } static const struct wcss_data wcss_ipq8074_res_init = { @@ -144,7 +146,7 @@ Signed-off-by: Nikhil Prakash V .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, -@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq80 +@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq8074_res_init = { }; static const struct wcss_data wcss_qcs404_res_init = { @@ -153,3 +155,6 @@ Signed-off-by: Nikhil Prakash V .crash_reason_smem = WCSS_CRASH_REASON, .firmware_name = "wcnss.mdt", .version = WCSS_QCS404, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-secure-PIL-support.patch b/target/linux/ipq807x/patches-5.15/0112-remoteproc-qcom-Add-secure-PIL-support.patch similarity index 80% rename from target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-secure-PIL-support.patch rename to target/linux/ipq807x/patches-5.15/0112-remoteproc-qcom-Add-secure-PIL-support.patch index 7f466b45e..d3165de82 100644 --- a/target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-secure-PIL-support.patch +++ b/target/linux/ipq807x/patches-5.15/0112-remoteproc-qcom-Add-secure-PIL-support.patch @@ -1,7 +1,7 @@ -From cb3b9e284104fd7fe4aa92a37df005577aed2c40 Mon Sep 17 00:00:00 2001 +From 3151bf7eb1350e3dd8a51424942d7365673a6e25 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:06 +0530 -Subject: [PATCH 114/137] remoteproc: qcom: Add secure PIL support +Subject: [PATCH] remoteproc: qcom: Add secure PIL support IPQ8074 uses secure PIL. Hence, adding the support for the same. @@ -12,6 +12,8 @@ Signed-off-by: Nikhil Prakash V drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index 0e5484020296..7d173b7816b8 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -18,6 +18,7 @@ @@ -48,7 +50,7 @@ Signed-off-by: Nikhil Prakash V }; static int q6v5_wcss_reset(struct q6v5_wcss *wcss) -@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc +@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc *rproc) qcom_q6v5_prepare(&wcss->q6v5); @@ -64,7 +66,7 @@ Signed-off-by: Nikhil Prakash V /* Release Q6 and WCSS reset */ ret = reset_control_deassert(wcss->wcss_reset); if (ret) { -@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc +@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc *rproc) if (ret) goto wcss_q6_reset; @@ -72,7 +74,7 @@ Signed-off-by: Nikhil Prakash V ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); if (ret == -ETIMEDOUT) dev_err(wcss->dev, "start timed out\n"); -@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc * +@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; @@ -88,7 +90,7 @@ Signed-off-by: Nikhil Prakash V /* WCSS powerdown */ if (wcss->requires_force_stop) { ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); -@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc * +@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } @@ -96,7 +98,7 @@ Signed-off-by: Nikhil Prakash V clk_disable_unprepare(wcss->prng_clk); qcom_q6v5_unprepare(&wcss->q6v5); -@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc * +@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) struct q6v5_wcss *wcss = rproc->priv; int ret; @@ -115,7 +117,7 @@ Signed-off-by: Nikhil Prakash V if (ret) return ret; -@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platfo +@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (!desc) return -EINVAL; @@ -125,7 +127,7 @@ Signed-off-by: Nikhil Prakash V rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, desc->firmware_name, sizeof(*wcss)); if (!rproc) { -@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platfo +@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss->version = desc->version; wcss->requires_force_stop = desc->requires_force_stop; @@ -133,7 +135,7 @@ Signed-off-by: Nikhil Prakash V ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) -@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq80 +@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq8074_res_init = { .wcss_q6_reset_required = true, .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, @@ -141,3 +143,6 @@ Signed-off-by: Nikhil Prakash V }; static const struct wcss_data wcss_qcs404_res_init = { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch b/target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch similarity index 81% rename from target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch rename to target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch index 86b9c514f..9bd59775d 100644 --- a/target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch +++ b/target/linux/ipq807x/patches-5.15/0113-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch @@ -1,8 +1,7 @@ -From bcb2c37f265924ac43642f1f97c964dd546b3cb5 Mon Sep 17 00:00:00 2001 +From 0915eaecd5e06227c9e4e3a4a931c45942e7b4ed Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:07 +0530 -Subject: [PATCH 115/137] remoteproc: qcom: Add support for split q6 + m3 wlan - firmware +Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware IPQ8074 supports split firmware for q6 and m3 as well. So add support for loading the m3 firmware before q6. @@ -16,6 +15,8 @@ Signed-off-by: Nikhil Prakash V drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index 7d173b7816b8..60ed0c046693 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -139,6 +139,7 @@ struct q6v5_wcss { @@ -36,7 +37,7 @@ Signed-off-by: Nikhil Prakash V unsigned int crash_reason_smem; u32 version; bool aon_reset_required; -@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct r +@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *i static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5_wcss *wcss = rproc->priv; @@ -66,7 +67,7 @@ Signed-off-by: Nikhil Prakash V if (wcss->need_mem_protection) ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware, WCNSS_PAS_ID, wcss->mem_region, -@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platfo +@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) return -EPROBE_DEFER; rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, @@ -75,7 +76,7 @@ Signed-off-by: Nikhil Prakash V if (!rproc) { dev_err(&pdev->dev, "failed to allocate rproc\n"); return -ENOMEM; -@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platfo +@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss->version = desc->version; wcss->requires_force_stop = desc->requires_force_stop; wcss->need_mem_protection = desc->need_mem_protection; @@ -83,7 +84,7 @@ Signed-off-by: Nikhil Prakash V ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) -@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platf +@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platform_device *pdev) static const struct wcss_data wcss_ipq8074_res_init = { .init_clock = ipq8074_init_clock, @@ -93,7 +94,7 @@ Signed-off-by: Nikhil Prakash V .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, .wcss_q6_reset_required = true, -@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs40 +@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs404_res_init = { .init_clock = qcs404_init_clock, .init_regulator = qcs404_init_regulator, .crash_reason_smem = WCSS_CRASH_REASON, @@ -102,3 +103,6 @@ Signed-off-by: Nikhil Prakash V .version = WCSS_QCS404, .aon_reset_required = false, .wcss_q6_reset_required = false, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0116-remoteproc-qcom-Add-ssr-subdevice-identifier.patch b/target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-ssr-subdevice-identifier.patch similarity index 67% rename from target/linux/ipq807x/patches-5.15/0116-remoteproc-qcom-Add-ssr-subdevice-identifier.patch rename to target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-ssr-subdevice-identifier.patch index 53bafa82b..d52a0ff79 100644 --- a/target/linux/ipq807x/patches-5.15/0116-remoteproc-qcom-Add-ssr-subdevice-identifier.patch +++ b/target/linux/ipq807x/patches-5.15/0114-remoteproc-qcom-Add-ssr-subdevice-identifier.patch @@ -1,7 +1,7 @@ -From 5b717749ce49853f495ebac227c72013622b0810 Mon Sep 17 00:00:00 2001 +From a0774816e1e76c47fe47a4e0fa7e0a84811dd62f Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:08 +0530 -Subject: [PATCH 116/137] remoteproc: qcom: Add ssr subdevice identifier +Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier Add name for ssr subdevice on IPQ8074 SoC. @@ -12,9 +12,11 @@ Signed-off-by: Nikhil Prakash V drivers/remoteproc/qcom_q6v5_wcss.c | 1 + 1 file changed, 1 insertion(+) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index 60ed0c046693..e32efdc660d2 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq80 +@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq8074_res_init = { .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, .wcss_q6_reset_required = true, @@ -22,3 +24,6 @@ Signed-off-by: Nikhil Prakash V .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, .need_mem_protection = true, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0117-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch b/target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch similarity index 77% rename from target/linux/ipq807x/patches-5.15/0117-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch rename to target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch index 243cfe7e0..54116c5e2 100644 --- a/target/linux/ipq807x/patches-5.15/0117-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch +++ b/target/linux/ipq807x/patches-5.15/0115-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch @@ -1,8 +1,7 @@ -From 3bc5b97ecbb003e413ae76b332b0ccdba05ef6bc Mon Sep 17 00:00:00 2001 +From e99af92362058cfec70569057c1b15da9a1acb5f Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:09 +0530 -Subject: [PATCH 117/137] remoteproc: qcom: Update regmap offsets for halt - register +Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register Fixed issue in reading halt-regs parameter from device-tree. @@ -12,6 +11,8 @@ Signed-off-by: Sricharan R drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index e32efdc660d2..16fc5a33adaf 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -86,7 +86,7 @@ @@ -31,7 +32,7 @@ Signed-off-by: Sricharan R const char *ssr_name; const char *sysmon_name; int ssctl_id; -@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q +@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, } } @@ -49,7 +50,7 @@ Signed-off-by: Sricharan R } return 0; -@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6 +@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, return -EINVAL; } @@ -62,7 +63,7 @@ Signed-off-by: Sricharan R return 0; } -@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq80 +@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq8074_res_init = { .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, .wcss_q6_reset_required = true, @@ -70,7 +71,7 @@ Signed-off-by: Sricharan R .ssr_name = "q6wcss", .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, -@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs40 +@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs404_res_init = { .version = WCSS_QCS404, .aon_reset_required = false, .wcss_q6_reset_required = false, @@ -78,3 +79,6 @@ Signed-off-by: Sricharan R .ssr_name = "mpss", .sysmon_name = "wcnss", .ssctl_id = 0x12, +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0128-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch b/target/linux/ipq807x/patches-5.15/0116-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch similarity index 71% rename from target/linux/ipq807x/patches-5.15/0128-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch rename to target/linux/ipq807x/patches-5.15/0116-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch index b91b7565d..2f6c68b1d 100644 --- a/target/linux/ipq807x/patches-5.15/0128-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch +++ b/target/linux/ipq807x/patches-5.15/0116-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch @@ -1,7 +1,7 @@ -From aa0c4a764d290cceba0a27fd5d81b30b54c5c81f Mon Sep 17 00:00:00 2001 +From 25e8ae5b960f45e9e19aa24cc023603375f44db0 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:10 +0530 -Subject: [PATCH 128/137] dt-bindings: clock: qcom: Add reset for WCSSAON +Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. @@ -14,13 +14,17 @@ Acked-by: Stephen Boyd include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) +diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +index 8e2bec1c91bf..9b1c42bc430c 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -367,6 +367,7 @@ +@@ -366,5 +366,6 @@ #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define GCC_WCSSAON_RESET 132 - #define USB0_GDSC 0 - #define USB1_GDSC 1 + #endif +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch similarity index 64% rename from target/linux/ipq807x/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch rename to target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch index c90eb7bef..026f780bc 100644 --- a/target/linux/ipq807x/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch +++ b/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch @@ -1,7 +1,7 @@ -From 1377fc72a67c8684237fa9b1f246257fd073b2b1 Mon Sep 17 00:00:00 2001 +From 1a279695f52e8ab438fde5dbfbb762da8980e037 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:11 +0530 -Subject: [PATCH 129/137] clk: qcom: Add WCSSAON reset +Subject: [PATCH] clk: qcom: Add WCSSAON reset Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. @@ -13,13 +13,18 @@ Acked-by: Stephen Boyd drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index b09d99343e09..4d6e8c47515f 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4826,6 +4826,7 @@ static const struct qcom_reset_map gcc_i +@@ -4744,6 +4744,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_WCSSAON_RESET] = { 0x59010, 0 }, }; - static struct gdsc *gcc_ipq8074_gdscs[] = { + static const struct of_device_id gcc_ipq8074_match_table[] = { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0118-drivers-thermal-tsens-Add-support-for-combined-inter.patch b/target/linux/ipq807x/patches-5.15/0118-drivers-thermal-tsens-Add-support-for-combined-inter.patch deleted file mode 100644 index 5260c528e..000000000 --- a/target/linux/ipq807x/patches-5.15/0118-drivers-thermal-tsens-Add-support-for-combined-inter.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 24a47e4619d90266188d26be04c0c29854294f06 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 28 Apr 2022 14:58:16 +0200 -Subject: [PATCH 118/137] drivers: thermal: tsens: Add support for combined - interrupt - -Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for -signaling both up/low and critical trips. - -Signed-off-by: Robert Marko ---- -Changes in v7: -* Rebase to apply on next-20220818 - -Changes in v6: -* Check critical IRQ handler return, simplify up/low return ---- - drivers/thermal/qcom/tsens-8960.c | 1 + - drivers/thermal/qcom/tsens-v0_1.c | 1 + - drivers/thermal/qcom/tsens-v1.c | 1 + - drivers/thermal/qcom/tsens-v2.c | 1 + - drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++----- - drivers/thermal/qcom/tsens.h | 2 ++ - 6 files changed, 38 insertions(+), 6 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 = - static struct tsens_features tsens_8960_feat = { - .ver_major = VER_0, - .crit_int = 0, -+ .combo_int = 0, - .adc = 1, - .srot_split = 0, - .max_sensors = 11, ---- a/drivers/thermal/qcom/tsens-v0_1.c -+++ b/drivers/thermal/qcom/tsens-v0_1.c -@@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_p - static struct tsens_features tsens_v0_1_feat = { - .ver_major = VER_0_1, - .crit_int = 0, -+ .combo_int = 0, - .adc = 1, - .srot_split = 1, - .max_sensors = 11, ---- a/drivers/thermal/qcom/tsens-v1.c -+++ b/drivers/thermal/qcom/tsens-v1.c -@@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_p - static struct tsens_features tsens_v1_feat = { - .ver_major = VER_1_X, - .crit_int = 0, -+ .combo_int = 0, - .adc = 1, - .srot_split = 1, - .max_sensors = 11, ---- a/drivers/thermal/qcom/tsens-v2.c -+++ b/drivers/thermal/qcom/tsens-v2.c -@@ -31,6 +31,7 @@ - static struct tsens_features tsens_v2_feat = { - .ver_major = VER_2_X, - .crit_int = 1, -+ .combo_int = 0, - .adc = 0, - .srot_split = 1, - .max_sensors = 16, ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -531,6 +531,27 @@ static irqreturn_t tsens_irq_thread(int - return IRQ_HANDLED; - } - -+/** -+ * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts -+ * @irq: irq number -+ * @data: tsens controller private data -+ * -+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the -+ * critical handler first and then the up/low one. -+ * -+ * Return: IRQ_HANDLED -+ */ -+static irqreturn_t tsens_combined_irq_thread(int irq, void *data) -+{ -+ irqreturn_t ret; -+ -+ ret = tsens_critical_irq_thread(irq, data); -+ if (ret != IRQ_HANDLED) -+ return ret; -+ -+ return tsens_irq_thread(irq, data); -+} -+ - static int tsens_set_trips(void *_sensor, int low, int high) - { - struct tsens_sensor *s = _sensor; -@@ -1075,13 +1096,18 @@ static int tsens_register(struct tsens_p - tsens_mC_to_hw(priv->sensor, 0)); - } - -- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); -- if (ret < 0) -- return ret; -+ if (priv->feat->combo_int) { -+ ret = tsens_register_irq(priv, "combined", -+ tsens_combined_irq_thread); -+ } else { -+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); -+ if (ret < 0) -+ return ret; - -- if (priv->feat->crit_int) -- ret = tsens_register_irq(priv, "critical", -- tsens_critical_irq_thread); -+ if (priv->feat->crit_int) -+ ret = tsens_register_irq(priv, "critical", -+ tsens_critical_irq_thread); -+ } - - return ret; - } ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -495,6 +495,7 @@ enum regfield_ids { - * struct tsens_features - Features supported by the IP - * @ver_major: Major number of IP version - * @crit_int: does the IP support critical interrupts? -+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds? - * @adc: do the sensors only output adc code (instead of temperature)? - * @srot_split: does the IP neatly splits the register space into SROT and TM, - * with SROT only being available to secure boot firmware? -@@ -504,6 +505,7 @@ enum regfield_ids { - struct tsens_features { - unsigned int ver_major; - unsigned int crit_int:1; -+ unsigned int combo_int:1; - unsigned int adc:1; - unsigned int srot_split:1; - unsigned int has_watchdog:1; diff --git a/target/linux/ipq807x/patches-5.15/0130-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch b/target/linux/ipq807x/patches-5.15/0118-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch similarity index 70% rename from target/linux/ipq807x/patches-5.15/0130-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch rename to target/linux/ipq807x/patches-5.15/0118-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch index 869ed45a0..e7400c427 100644 --- a/target/linux/ipq807x/patches-5.15/0130-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch +++ b/target/linux/ipq807x/patches-5.15/0118-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch @@ -1,7 +1,7 @@ -From d9965ec6f02f71609d837d33d4bae20fb7dec1fd Mon Sep 17 00:00:00 2001 +From 76126149a2a76a0cf9895224dbb4dacf69ebb06a Mon Sep 17 00:00:00 2001 From: Sivaprakash Murugesan Date: Fri, 17 Apr 2020 16:37:10 +0530 -Subject: [PATCH 130/137] remoteproc: wcss: disable auto boot for IPQ8074 +Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074 auto boot is disabled for IPQ8074 the wifi driver brings up the wcss. @@ -11,6 +11,8 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++ 1 file changed, 4 insertions(+) +diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c +index 16fc5a33adaf..92c240976f55 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -161,6 +161,7 @@ struct wcss_data { @@ -21,7 +23,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 }; static int q6v5_wcss_reset(struct q6v5_wcss *wcss) -@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platfo +@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) desc->sysmon_name, desc->ssctl_id); @@ -29,7 +31,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 ret = rproc_add(rproc); if (ret) goto free_rproc; -@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq80 +@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq8074_res_init = { .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, .need_mem_protection = true, @@ -37,7 +39,7 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 }; static const struct wcss_data wcss_qcs404_res_init = { -@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs40 +@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs404_res_init = { .ssctl_id = 0x12, .ops = &q6v5_wcss_qcs404_ops, .requires_force_stop = false, @@ -45,3 +47,6 @@ Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 }; static const struct of_device_id q6v5_wcss_of_match[] = { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0131-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch b/target/linux/ipq807x/patches-5.15/0119-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch similarity index 80% rename from target/linux/ipq807x/patches-5.15/0131-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch rename to target/linux/ipq807x/patches-5.15/0119-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch index 3a3a9e73a..3a19b0d27 100644 --- a/target/linux/ipq807x/patches-5.15/0131-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch +++ b/target/linux/ipq807x/patches-5.15/0119-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch @@ -1,7 +1,7 @@ -From 45dfcd1ecf0910e4e45fec5f26f2fc80a47732f9 Mon Sep 17 00:00:00 2001 +From 1078ef8be64de03a2dbd78d17c87af0472748079 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:13 +0530 -Subject: [PATCH 131/137] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC +Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC Enable remoteproc WCSS PIL driver with glink and ssr subdevices. Also enables smp2p and mailboxes required for IPC. @@ -11,12 +11,14 @@ Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++ - 1 file changed, 81 insertions(+) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 88 +++++++++++++++++++++++++++ + 1 file changed, 88 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 2f553b82ca12..947064465fc0 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -153,6 +153,32 @@ +@@ -136,6 +136,32 @@ scm { }; }; @@ -49,7 +51,7 @@ Signed-off-by: Robert Marko soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; -@@ -421,6 +447,11 @@ +@@ -393,6 +419,11 @@ tcsr_mutex: hwlock@1905000 { #hwlock-cells = <1>; }; @@ -61,11 +63,18 @@ Signed-off-by: Robert Marko spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, -@@ -934,6 +965,56 @@ +@@ -893,5 +924,62 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_s_sticky"; status = "disabled"; }; + ++ apcs_glb: mailbox@b111000 { ++ compatible = "qcom,ipq8074-apcs-apps-global"; ++ reg = <0x0b111000 0x1000>; ++ ++ #mbox-cells = <1>; ++ }; ++ + q6v5_wcss: q6v5_wcss@cd00000 { + compatible = "qcom,ipq8074-wcss-pil"; + reg = <0x0cd00000 0x4040>, @@ -116,5 +125,7 @@ Signed-off-by: Robert Marko + }; + }; }; - - timer { + }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0119-drivers-thermal-tsens-allow-configuring-min-and-max-.patch b/target/linux/ipq807x/patches-5.15/0119-drivers-thermal-tsens-allow-configuring-min-and-max-.patch deleted file mode 100644 index 36219c30c..000000000 --- a/target/linux/ipq807x/patches-5.15/0119-drivers-thermal-tsens-allow-configuring-min-and-max-.patch +++ /dev/null @@ -1,100 +0,0 @@ -From f035a370b770831f1c4a5d5b5b4387391ee3f71a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 28 Apr 2022 19:06:29 +0200 -Subject: [PATCH 119/137] drivers: thermal: tsens: allow configuring min and - max trips - -IPQ8074 and IPQ6018 dont support negative trip temperatures and support -up to 204 degrees C as the max trip temperature. - -So, instead of always setting the -40 as min and 120 degrees C as max -allow it to be configured as part of the features. - -Signed-off-by: Robert Marko -Reviewed-by: Bjorn Andersson ---- - drivers/thermal/qcom/tsens-8960.c | 2 ++ - drivers/thermal/qcom/tsens-v0_1.c | 2 ++ - drivers/thermal/qcom/tsens-v1.c | 2 ++ - drivers/thermal/qcom/tsens-v2.c | 2 ++ - drivers/thermal/qcom/tsens.c | 4 ++-- - drivers/thermal/qcom/tsens.h | 4 ++++ - 6 files changed, 14 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_ - .adc = 1, - .srot_split = 0, - .max_sensors = 11, -+ .trip_min_temp = -40000, -+ .trip_max_temp = 120000, - }; - - struct tsens_plat_data data_8960 = { ---- a/drivers/thermal/qcom/tsens-v0_1.c -+++ b/drivers/thermal/qcom/tsens-v0_1.c -@@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_ - .adc = 1, - .srot_split = 1, - .max_sensors = 11, -+ .trip_min_temp = -40000, -+ .trip_max_temp = 120000, - }; - - static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { ---- a/drivers/thermal/qcom/tsens-v1.c -+++ b/drivers/thermal/qcom/tsens-v1.c -@@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_fe - .adc = 1, - .srot_split = 1, - .max_sensors = 11, -+ .trip_min_temp = -40000, -+ .trip_max_temp = 120000, - }; - - static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { ---- a/drivers/thermal/qcom/tsens-v2.c -+++ b/drivers/thermal/qcom/tsens-v2.c -@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe - .adc = 0, - .srot_split = 1, - .max_sensors = 16, -+ .trip_min_temp = -40000, -+ .trip_max_temp = 120000, - }; - - static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor - dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", - hw_id, __func__, low, high); - -- cl_high = clamp_val(high, -40000, 120000); -- cl_low = clamp_val(low, -40000, 120000); -+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp); -+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp); - - high_val = tsens_mC_to_hw(s, cl_high); - low_val = tsens_mC_to_hw(s, cl_low); ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -501,6 +501,8 @@ enum regfield_ids { - * with SROT only being available to secure boot firmware? - * @has_watchdog: does this IP support watchdog functionality? - * @max_sensors: maximum sensors supported by this version of the IP -+ * @trip_min_temp: minimum trip temperature supported by this version of the IP -+ * @trip_max_temp: maximum trip temperature supported by this version of the IP - */ - struct tsens_features { - unsigned int ver_major; -@@ -510,6 +512,8 @@ struct tsens_features { - unsigned int srot_split:1; - unsigned int has_watchdog:1; - unsigned int max_sensors; -+ int trip_min_temp; -+ int trip_max_temp; - }; - - /** diff --git a/target/linux/ipq807x/patches-5.15/0132-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/ipq807x/patches-5.15/0120-arm64-dts-ipq8074-Add-WLAN-node.patch similarity index 93% rename from target/linux/ipq807x/patches-5.15/0132-arm64-dts-ipq8074-Add-WLAN-node.patch rename to target/linux/ipq807x/patches-5.15/0120-arm64-dts-ipq8074-Add-WLAN-node.patch index d93cf1c28..42ebab26d 100644 --- a/target/linux/ipq807x/patches-5.15/0132-arm64-dts-ipq8074-Add-WLAN-node.patch +++ b/target/linux/ipq807x/patches-5.15/0120-arm64-dts-ipq8074-Add-WLAN-node.patch @@ -1,7 +1,7 @@ -From d8e8adbf99ed4a3b50f87a665661a8cad84918ff Mon Sep 17 00:00:00 2001 +From 4645129811d46fbd18100e0b76fffe88795a54da Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 21 Dec 2021 14:49:36 +0100 -Subject: [PATCH 132/137] arm64: dts: ipq8074: Add WLAN node +Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported by the ath11k. @@ -13,9 +13,11 @@ Signed-off-by: Robert Marko arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 947064465fc0..57daacff929c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -1015,6 +1015,117 @@ +@@ -981,5 +981,116 @@ rpm_requests { }; }; }; @@ -131,5 +133,7 @@ Signed-off-by: Robert Marko + status = "disabled"; + }; }; - - timer { + }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0120-drivers-thermal-tsens-add-IPQ8074-support.patch b/target/linux/ipq807x/patches-5.15/0120-drivers-thermal-tsens-add-IPQ8074-support.patch deleted file mode 100644 index 88a3f56f9..000000000 --- a/target/linux/ipq807x/patches-5.15/0120-drivers-thermal-tsens-add-IPQ8074-support.patch +++ /dev/null @@ -1,72 +0,0 @@ -From ffc91d0fc802e58f44c7f888f44643847b6dfa3a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 28 Apr 2022 20:26:13 +0200 -Subject: [PATCH 120/137] drivers: thermal: tsens: add IPQ8074 support - -Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP -it only has one IRQ, that is used for up/low as well as critical. -It also does not support negative trip temperatures. - -Signed-off-by: Robert Marko -Reviewed-by: Bjorn Andersson ---- - drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++ - drivers/thermal/qcom/tsens.c | 3 +++ - drivers/thermal/qcom/tsens.h | 2 +- - 3 files changed, 21 insertions(+), 1 deletion(-) - ---- a/drivers/thermal/qcom/tsens-v2.c -+++ b/drivers/thermal/qcom/tsens-v2.c -@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe - .trip_max_temp = 120000, - }; - -+static struct tsens_features ipq8074_feat = { -+ .ver_major = VER_2_X, -+ .crit_int = 1, -+ .combo_int = 1, -+ .adc = 0, -+ .srot_split = 1, -+ .max_sensors = 16, -+ .trip_min_temp = 0, -+ .trip_max_temp = 204000, -+}; -+ - static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { - /* ----- SROT ------ */ - /* VERSION */ -@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = { - .fields = tsens_v2_regfields, - }; - -+struct tsens_plat_data data_ipq8074 = { -+ .ops = &ops_generic_v2, -+ .feat = &ipq8074_feat, -+ .fields = tsens_v2_regfields, -+}; -+ - /* Kept around for backward compatibility with old msm8996.dtsi */ - struct tsens_plat_data data_8996 = { - .num_sensors = 13, ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -991,6 +991,9 @@ static const struct of_device_id tsens_t - .compatible = "qcom,ipq8064-tsens", - .data = &data_8960, - }, { -+ .compatible = "qcom,ipq8074-tsens", -+ .data = &data_ipq8074, -+ }, { - .compatible = "qcom,mdm9607-tsens", - .data = &data_9607, - }, { ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916, - extern struct tsens_plat_data data_tsens_v1, data_8976; - - /* TSENS v2 targets */ --extern struct tsens_plat_data data_8996, data_tsens_v2; -+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; - - #endif /* __QCOM_TSENS_H__ */ diff --git a/target/linux/ipq807x/patches-5.15/0121-thermal-qcom-tsens-Add-IPQ8074-support.patch b/target/linux/ipq807x/patches-5.15/0121-thermal-qcom-tsens-Add-IPQ8074-support.patch new file mode 100644 index 000000000..f6c4add0f --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0121-thermal-qcom-tsens-Add-IPQ8074-support.patch @@ -0,0 +1,108 @@ +From b7bf74840dcffd209d4fc26a6d16d669bcda8f1d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 20 Nov 2020 13:52:43 +0100 +Subject: [PATCH] thermal: qcom: tsens: Add IPQ8074 support + +Qualcomm IPQ807x SoC-s use tsens v2.3.0 IP, but they +only have one interrupt and not a dedicated critical interrupt. + +Signed-off-by: Robert Marko +--- + drivers/thermal/qcom/tsens-v2.c | 14 ++++++++++++++ + drivers/thermal/qcom/tsens.c | 27 ++++++++++++++++++--------- + drivers/thermal/qcom/tsens.h | 2 +- + 3 files changed, 33 insertions(+), 10 deletions(-) + +diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c +index b293ed32174b..d9e70d8e0e3b 100644 +--- a/drivers/thermal/qcom/tsens-v2.c ++++ b/drivers/thermal/qcom/tsens-v2.c +@@ -36,6 +36,14 @@ static struct tsens_features tsens_v2_feat = { + .max_sensors = 16, + }; + ++static struct tsens_features tsens_ipq8074_feat = { ++ .ver_major = VER_2_X, ++ .crit_int = 0, ++ .adc = 0, ++ .srot_split = 1, ++ .max_sensors = 16, ++}; ++ + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { + /* ----- SROT ------ */ + /* VERSION */ +@@ -101,6 +109,12 @@ struct tsens_plat_data data_tsens_v2 = { + .fields = tsens_v2_regfields, + }; + ++struct tsens_plat_data data_tsens_ipq8074 = { ++ .ops = &ops_generic_v2, ++ .feat = &tsens_ipq8074_feat, ++ .fields = tsens_v2_regfields, ++}; ++ + /* Kept around for backward compatibility with old msm8996.dtsi */ + struct tsens_plat_data data_8996 = { + .num_sensors = 13, +diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c +index 99a8d9f3e03c..b828befafa8e 100644 +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -325,16 +325,22 @@ static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id, + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; +- ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id], +- &d->crit_irq_clear); +- if (ret) +- return ret; +- ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id], +- &d->crit_irq_mask); +- if (ret) +- return ret; ++ if (priv->feat->crit_int) { ++ ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id], ++ &d->crit_irq_clear); ++ if (ret) ++ return ret; ++ ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id], ++ &d->crit_irq_mask); ++ if (ret) ++ return ret; + +- d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id); ++ d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id); ++ } else { ++ d->crit_irq_clear = 0; ++ d->crit_irq_mask = 0; ++ d->crit_thresh = 0; ++ } + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; +@@ -993,6 +999,9 @@ static const struct of_device_id tsens_table[] = { + }, { + .compatible = "qcom,tsens-v2", + .data = &data_tsens_v2, ++ }, { ++ .compatible = "qcom,ipq8074-tsens", ++ .data = &data_tsens_ipq8074, + }, + {} + }; +diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h +index 1471a2c00f15..00a1c897e721 100644 +--- a/drivers/thermal/qcom/tsens.h ++++ b/drivers/thermal/qcom/tsens.h +@@ -593,6 +593,6 @@ extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; + extern struct tsens_plat_data data_tsens_v1, data_8976; + + /* TSENS v2 targets */ +-extern struct tsens_plat_data data_8996, data_tsens_v2; ++extern struct tsens_plat_data data_8996, data_tsens_v2, data_tsens_ipq8074; + + #endif /* __QCOM_TSENS_H__ */ +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0121-arm64-dts-ipq8074-add-thermal-nodes.patch b/target/linux/ipq807x/patches-5.15/0122-arm64-dts-ipq8074-add-thermal-nodes.patch similarity index 85% rename from target/linux/ipq807x/patches-5.15/0121-arm64-dts-ipq8074-add-thermal-nodes.patch rename to target/linux/ipq807x/patches-5.15/0122-arm64-dts-ipq8074-add-thermal-nodes.patch index 206a85ffa..cff9460ad 100644 --- a/target/linux/ipq807x/patches-5.15/0121-arm64-dts-ipq8074-add-thermal-nodes.patch +++ b/target/linux/ipq807x/patches-5.15/0122-arm64-dts-ipq8074-add-thermal-nodes.patch @@ -1,7 +1,7 @@ -From 1cdc1eaed3ea5b2cab82dee4c72c3cea23356ca6 Mon Sep 17 00:00:00 2001 +From bf718a63d90b0921064892fa0e4dcf3db5233b1a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 24 Dec 2021 20:33:59 +0100 -Subject: [PATCH 121/137] arm64: dts: ipq8074: add thermal nodes +Subject: [PATCH] arm64: dts: ipq8074: add thermal nodes IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the @@ -12,16 +12,15 @@ CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko ---- -Changes in v5: -* Rebase to apply on next-20220708 --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 57daacff929c..f5c5778f8ab9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -310,6 +310,16 @@ +@@ -332,6 +332,16 @@ prng: rng@e3000 { status = "disabled"; }; @@ -30,17 +29,17 @@ Changes in v5: + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + interrupts = ; -+ interrupt-names = "combined"; ++ interrupt-names = "uplow"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + - cryptobam: dma-controller@704000 { + cryptobam: dma@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; -@@ -920,4 +930,90 @@ - , - ; +@@ -1093,4 +1103,90 @@ wifi: wifi@c0000000 { + status = "disabled"; + }; }; + + thermal-zones { @@ -129,3 +128,6 @@ Changes in v5: + }; + }; }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0122-mfd-qcom-spmi-pmic-add-support-for-PMP8074.patch b/target/linux/ipq807x/patches-5.15/0122-mfd-qcom-spmi-pmic-add-support-for-PMP8074.patch deleted file mode 100644 index 07a31af89..000000000 --- a/target/linux/ipq807x/patches-5.15/0122-mfd-qcom-spmi-pmic-add-support-for-PMP8074.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0d176e7d075fb7deeb1b137fec56304a402f2f25 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 19 May 2022 14:51:53 +0200 -Subject: [PATCH 122/137] mfd: qcom-spmi-pmic: add support for PMP8074 - -Add support for PMP8074 PMIC which is a companion PMIC for the Qualcomm -IPQ8074 SoC-s. - -It shares the same subtype identifier as PM8901. - -Signed-off-by: Robert Marko ---- - drivers/mfd/qcom-spmi-pmic.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mfd/qcom-spmi-pmic.c -+++ b/drivers/mfd/qcom-spmi-pmic.c -@@ -76,6 +76,7 @@ static const struct of_device_id pmic_sp - { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE }, - { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE }, - { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE }, -+ { .compatible = "qcom,pmp8074", .data = (void *)PM8901_SUBTYPE }, - { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE }, - { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE }, - { } diff --git a/target/linux/ipq807x/patches-5.15/0123-arm64-dts-qcom-add-PMP8074-DTSI.patch b/target/linux/ipq807x/patches-5.15/0123-arm64-dts-qcom-add-PMP8074-DTSI.patch deleted file mode 100644 index 8c2c68616..000000000 --- a/target/linux/ipq807x/patches-5.15/0123-arm64-dts-qcom-add-PMP8074-DTSI.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 2abf33c722b4ade9438dc91a652f294ada68a50e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 18 May 2022 16:36:42 +0200 -Subject: [PATCH 123/137] arm64: dts: qcom: add PMP8074 DTSI - -PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is -controlled via SPMI. - -Add DTSI for it providing GPIO, regulator, RTC and VADC support. - -RTC is disabled by default as there is no built-in battery so it will -loose time unless board vendor added a battery, so make it optional. - -Signed-off-by: Robert Marko ---- -Changes in v7: -* Dual license with BSD-3-Clause -* Use "-" instead of underscores in node names - -Changes in v6: -* Add RTC and GPIO nodes - -Changes in v5: -* Remove #address-cells and #size-cells as they are not required for -regulator subnodes ---- - arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++ - 1 file changed, 125 insertions(+) - create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi -@@ -0,0 +1,125 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause -+ -+#include -+#include -+ -+&spmi_bus { -+ pmic@0 { -+ compatible = "qcom,pmp8074", "qcom,spmi-pmic"; -+ reg = <0x0 SPMI_USID>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pmp8074_adc: adc@3100 { -+ compatible = "qcom,spmi-adc-rev2"; -+ reg = <0x3100>; -+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #io-channel-cells = <1>; -+ -+ ref-gnd@0 { -+ reg = ; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ vref-1p25@1 { -+ reg = ; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ vref-vadc@2 { -+ reg = ; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ pmic_die: die-temp@6 { -+ reg = ; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ xo_therm: xo-temp@76 { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ pa_therm1: thermistor1@77 { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ pa_therm2: thermistor2@78 { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ pa_therm3: thermistor3@79 { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ qcom,pre-scaling = <1 1>; -+ }; -+ -+ vph-pwr@131 { -+ reg = ; -+ qcom,pre-scaling = <1 3>; -+ }; -+ }; -+ -+ pmp8074_rtc: rtc@6000 { -+ compatible = "qcom,pm8941-rtc"; -+ reg = <0x6000>; -+ reg-names = "rtc", "alarm"; -+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; -+ allow-set-time; -+ status = "disabled"; -+ }; -+ -+ pmp8074_gpios: gpio@c000 { -+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio"; -+ reg = <0xc000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&pmp8074_gpios 0 0 12>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ }; -+ -+ pmic@1 { -+ compatible = "qcom,pmp8074", "qcom,spmi-pmic"; -+ reg = <0x1 SPMI_USID>; -+ -+ regulators { -+ compatible = "qcom,pmp8074-regulators"; -+ -+ s3: s3 { -+ regulator-name = "vdd_s3"; -+ regulator-min-microvolt = <592000>; -+ regulator-max-microvolt = <1064000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ s4: s4 { -+ regulator-name = "vdd_s4"; -+ regulator-min-microvolt = <712000>; -+ regulator-max-microvolt = <992000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ l11: l11 { -+ regulator-name = "l11"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/ipq807x/patches-5.15/0123-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch b/target/linux/ipq807x/patches-5.15/0123-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch new file mode 100644 index 000000000..11c30788f --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0123-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch @@ -0,0 +1,43 @@ +From cb5dc874a8f0740eb988c2851a97d214e463eeb1 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Tue, 31 Mar 2020 22:00:27 +0530 +Subject: [PATCH] regulator: qcom_spmi: Add PMD9655 SPMI regulator + +PMD9655 is used in IPQ8074 and provides S3 for cores, +S4 for UBI core and LDO11 for SDIO/eMMC. + +Signed-off-by: Praveenkumar I +Signed-off-by: Robert Marko +--- + drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index 41424a3366d0..fbb5eeb3f802 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -2092,6 +2092,13 @@ static const struct spmi_regulator_data pms405_regulators[] = { + { } + }; + ++static const struct spmi_regulator_data pmd9655_regulators[] = { ++ { "s3", 0x1a00, "vdd_s3",}, ++ { "s4", 0x1d00, "vdd_s4",}, ++ { "ldo11", 0x4a00, "vdd_ldo11",}, ++ { } ++}; ++ + static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, + { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, +@@ -2104,6 +2111,7 @@ static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, + { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, + { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, ++ { .compatible = "qcom,pmd9655-regulators", .data = &pmd9655_regulators }, + { } + }; + MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0124-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch b/target/linux/ipq807x/patches-5.15/0124-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch deleted file mode 100644 index 0d1aea992..000000000 --- a/target/linux/ipq807x/patches-5.15/0124-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 89f8d101005ee40b3a6c689ba1765403d3617672 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 19 May 2022 13:34:03 +0200 -Subject: [PATCH 124/137] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply - -Since now we have control over the PMP8074 PMIC providing various system -voltages including L11 which provides the SDIO/eMMC I/O voltage set it as -the SDHCI VQMMC supply. - -This allows SDHCI controller to switch to 1.8V I/O mode and support high -speed modes like HS200 and HS400. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -@@ -3,6 +3,7 @@ - /* Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - #include "ipq8074.dtsi" -+#include "pmp8074.dtsi" - - / { - model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; -@@ -82,6 +83,7 @@ - - &sdhc_1 { - status = "okay"; -+ vqmmc-supply = <&l11>; - }; - - &qusb_phy_0 { diff --git a/target/linux/ipq807x/patches-5.15/0124-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch b/target/linux/ipq807x/patches-5.15/0124-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch new file mode 100644 index 000000000..c70b1d03b --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0124-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch @@ -0,0 +1,27 @@ +From 3c5e2d0c4149c287b9992e156a15ff881895bf00 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Mon, 4 May 2020 19:31:00 +0530 +Subject: [PATCH] regulator: qcom_spmi: SMPS range is added to support PMD9655 + PMIC + +Signed-off-by: Praveenkumar I +Change-Id: I5571801debec25527fd763d95aff27cc42f53bde +--- + drivers/regulator/qcom_spmi-regulator.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index fbb5eeb3f802..bb10a325e5e7 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -481,6 +481,7 @@ static struct spmi_voltage_range ln_ldo_ranges[] = { + }; + + static struct spmi_voltage_range smps_ranges[] = { ++ SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), + }; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0125-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch b/target/linux/ipq807x/patches-5.15/0125-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch new file mode 100644 index 000000000..e35c391a4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0125-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch @@ -0,0 +1,39 @@ +From 7475c4cd8898ba5bdf3021a23d3087d7a9747ec4 Mon Sep 17 00:00:00 2001 +From: PRAVEENKUMAR I +Date: Tue, 5 May 2020 07:57:21 +0530 +Subject: [PATCH] regulator: qcom_spmi: Initialize slew rate only if required + +Initialize slew rate only if set_voltage_time_sel in ops +is defined. + +Change-Id: I661c88d2f4a8f26cc85b1e2d4c8aa3170420ba6c +Signed-off-by: Rajith Cherian +(cherry picked from commit 608a6f171ef4017197fbe2069b5910b582923027) +Signed-off-by: Praveenkumar I + +Change-Id: Ida3cf3d754e1207e34a164d6d86c6e1aa109ef1e +--- + drivers/regulator/qcom_spmi-regulator.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index bb10a325e5e7..d9fef082a34e 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -1617,6 +1617,13 @@ static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) + int step, delay, slew_rate, step_delay; + const struct spmi_voltage_range *range; + ++ /* ++ * Slew rate need not be initialized if ++ * set_voltage_time_sel in the ops is not defined. ++ */ ++ if (!vreg->desc.ops->set_voltage_time_sel) ++ return 0; ++ + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); + if (ret) { + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0126-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch b/target/linux/ipq807x/patches-5.15/0126-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch new file mode 100644 index 000000000..75729c3f7 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0126-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch @@ -0,0 +1,164 @@ +From 29d356f93a44cd96a2618ffcc08968a1a0dff828 Mon Sep 17 00:00:00 2001 +From: PRAVEENKUMAR I +Date: Tue, 5 May 2020 07:57:52 +0530 +Subject: [PATCH] regulator: qcom_spmi: Add support for VMPWM_CTL subtype + +Support for Voltage Mode PWM Controller (VMPWM_CTL). +Set/Get microvolts functions added. Function to find the +voltage range for this particular subtype added. + +Change-Id: Ib4bf35ee65de17a917f01e63208368c7770401d4 +Signed-off-by: Rajith Cherian +(cherry picked from commit 31e7e4183b5afaf18dbca3548f4988c420ebb58b) +Signed-off-by: Praveenkumar I + +Change-Id: Id7a3caef84499b9e2eefda9f57576923c84234f0 +--- + drivers/regulator/qcom_spmi-regulator.c | 82 +++++++++++++++++++++++++ + 1 file changed, 82 insertions(+) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index d9fef082a34e..6176a09df345 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -164,6 +164,7 @@ enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, ++ SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, + }; + + enum spmi_common_regulator_registers { +@@ -289,6 +290,10 @@ enum spmi_common_control_register_index { + #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 + #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 + ++#define SPMI_SMPS_VMPWM_VSET_UB_SHIFT 8 ++#define SPMI_SMPS_VMPWM_VSET_UB_MASK 0xf00 ++#define SPMI_SMPS_VMPWM_VSET_LB_MASK 0xff ++ + /* Clock rate in kHz of the FTSMPS regulator reference clock. */ + #define SPMI_FTSMPS_CLOCK_RATE 19200 + +@@ -486,6 +491,10 @@ static struct spmi_voltage_range smps_ranges[] = { + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), + }; + ++static struct spmi_voltage_range smps_vmpwm_ranges[] = { ++ SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++}; ++ + static struct spmi_voltage_range ftsmps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), + SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), +@@ -551,6 +560,7 @@ static DEFINE_SPMI_SET_POINTS(nldo2); + static DEFINE_SPMI_SET_POINTS(nldo3); + static DEFINE_SPMI_SET_POINTS(ln_ldo); + static DEFINE_SPMI_SET_POINTS(smps); ++static DEFINE_SPMI_SET_POINTS(smps_vmpwm); + static DEFINE_SPMI_SET_POINTS(ftsmps); + static DEFINE_SPMI_SET_POINTS(ftsmps2p5); + static DEFINE_SPMI_SET_POINTS(ftsmps426); +@@ -745,6 +755,24 @@ spmi_regulator_find_range(struct spmi_regulator *vreg) + return NULL; + } + ++static const struct spmi_voltage_range * ++spmi_regulator_find_uV_range(struct spmi_regulator *vreg, int min, int max) ++{ ++ const struct spmi_voltage_range *range, *end; ++ ++ if (!vreg->set_points || !vreg->set_points->count) ++ return 0; ++ ++ range = vreg->set_points->range; ++ end = range + vreg->set_points->count; ++ ++ for (; range < end; range++) ++ if ((range->min_uV <= min) && (range->max_uV >= max)) ++ return range; ++ ++ return 0; ++} ++ + static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, + int min_uV, int max_uV) + { +@@ -966,6 +994,47 @@ static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) + return spmi_hw_selector_to_sw(vreg, voltage_sel, range); + } + ++static int spmi_regulator_smps_vmpwm_set_vol_uV(struct regulator_dev *rdev, ++ int min_uV, int max_uV, unsigned *selector) ++{ ++ struct spmi_regulator *vreg = rdev_get_drvdata(rdev); ++ const struct spmi_voltage_range *range; ++ int req_vol; ++ u8 reg[2]; ++ ++ range = spmi_regulator_find_uV_range(vreg, min_uV, max_uV); ++ if (!range) ++ return -EINVAL; ++ ++ *selector = spmi_regulator_select_voltage(vreg, min_uV, max_uV); ++ req_vol = range->set_point_min_uV + (range->step_uV * (*selector)); ++ ++ /* Convert uV to mV as the register supports mV */ ++ req_vol = req_vol/1000; ++ ++ /* ++ * Voltage set point bits<7:0>. 2-Byte Word (lower byte word) ++ */ ++ reg[0] = req_vol & SPMI_SMPS_VMPWM_VSET_LB_MASK; ++ /* ++ * Voltage set point bit <11:8>. 2-Byte Word (upper byte word) ++ */ ++ reg[1] = (req_vol & SPMI_SMPS_VMPWM_VSET_UB_MASK) ++ >> SPMI_SMPS_VMPWM_VSET_UB_SHIFT; ++ ++ return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2); ++} ++ ++static int spmi_regulator_smps_vmpwm_get_vol_uV(struct regulator_dev *rdev) ++{ ++ struct spmi_regulator *vreg = rdev_get_drvdata(rdev); ++ u8 reg[2]; ++ ++ spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2); ++ ++ return ((reg[1] << SPMI_SMPS_VMPWM_VSET_UB_SHIFT) | reg[0]) * 1000; ++} ++ + static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, + unsigned selector) + { +@@ -1314,6 +1383,18 @@ static const struct regulator_ops spmi_smps_ops = { + .set_pull_down = spmi_regulator_common_set_pull_down, + }; + ++static const struct regulator_ops spmi_smps_vmpwm_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .set_voltage = spmi_regulator_smps_vmpwm_set_vol_uV, ++ .get_voltage = spmi_regulator_smps_vmpwm_get_vol_uV, ++ .map_voltage = spmi_regulator_common_map_voltage, ++ .list_voltage = spmi_regulator_common_list_voltage, ++ .set_mode = spmi_regulator_common_set_mode, ++ .get_mode = spmi_regulator_common_get_mode, ++}; ++ + static const struct regulator_ops spmi_ldo_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, +@@ -1459,6 +1540,7 @@ static const struct regulator_ops spmi_hfs430_ops = { + + static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ ++ SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), + SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0127-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch b/target/linux/ipq807x/patches-5.15/0127-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch new file mode 100644 index 000000000..55e523c99 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0127-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch @@ -0,0 +1,47 @@ +From 6ac91c1597dfd688b5e818708aa4f8c55a41eefb Mon Sep 17 00:00:00 2001 +From: Vasudevan Murugesan +Date: Thu, 8 Jun 2017 19:13:48 +0530 +Subject: [PATCH] ipq807x: sdhc: Fixed SDR104 mode card detection + +Change-Id: I353356284d28d09d79bf7d318c4ebcdbc15e5b02 +Signed-off-by: Vasudevan Murugesan +Signed-off-by: Saravanan Jaganathan +(cherry picked from commit 080d3f390aa409ef2b5adf59a175b6bb2aa863fd) +Signed-off-by: Praveenkumar I + +Change-Id: Ie5edb7b3d972e06f3eb2525e10597b49e9bae14d +--- + drivers/regulator/qcom_spmi-regulator.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index 6176a09df345..1cdf2117a2fe 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -165,6 +165,7 @@ enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, + SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, ++ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, + }; + + enum spmi_common_regulator_registers { +@@ -493,6 +494,7 @@ static struct spmi_voltage_range smps_ranges[] = { + + static struct spmi_voltage_range smps_vmpwm_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++ SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -1540,6 +1542,7 @@ static const struct regulator_ops spmi_hfs430_ops = { + + static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ ++ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0128-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch b/target/linux/ipq807x/patches-5.15/0128-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch new file mode 100644 index 000000000..95e9a79a2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0128-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch @@ -0,0 +1,53 @@ +From 93ed08e80c610330f90b20415093fe388835f355 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Mon, 13 Jul 2020 18:13:48 +0530 +Subject: [PATCH] ipq807x: spmi regulator: Add separate voltage range for LDO + +When LDO voltage range added in SMPS voltage range structure, +selector value used during set voltage is wrongly calculated. +Because the SMPS voltage range is also taken into account for LDO. + +So, a separate voltage range structure is introduced for LDO. + +Signed-off-by: Praveenkumar I +Change-Id: I883518ae0686762a3774750b1dd480c4fe7298f3 +--- + drivers/regulator/qcom_spmi-regulator.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c +index 1cdf2117a2fe..ca5f28225b1c 100644 +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -494,7 +494,10 @@ static struct spmi_voltage_range smps_ranges[] = { + + static struct spmi_voltage_range smps_vmpwm_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), +- SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), ++}; ++ ++static struct spmi_voltage_range ldo_vmpwm_ranges[] = { ++ SPMI_VOLTAGE_RANGE(0, 1104000, 1104000, 3300000, 3300000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -563,6 +566,7 @@ static DEFINE_SPMI_SET_POINTS(nldo3); + static DEFINE_SPMI_SET_POINTS(ln_ldo); + static DEFINE_SPMI_SET_POINTS(smps); + static DEFINE_SPMI_SET_POINTS(smps_vmpwm); ++static DEFINE_SPMI_SET_POINTS(ldo_vmpwm); + static DEFINE_SPMI_SET_POINTS(ftsmps); + static DEFINE_SPMI_SET_POINTS(ftsmps2p5); + static DEFINE_SPMI_SET_POINTS(ftsmps426); +@@ -1542,7 +1546,7 @@ static const struct regulator_ops spmi_hfs430_ops = { + + static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ +- SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), ++ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, ldo_vmpwm, 0), + SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0129-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch b/target/linux/ipq807x/patches-5.15/0129-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch new file mode 100644 index 000000000..331570a38 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0129-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch @@ -0,0 +1,70 @@ +From c175f32484c75d0d3fe9c4024226c1067957d0a8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 26 Dec 2021 19:04:26 +0100 +Subject: [PATCH] arm64: dts: ipq8074: add SPMI PMIC regulators + +PMD9655 is used in IPQ8074 and provides S3 for cores, +S4 for UBI core and LDO11 for SDIO/eMMC. + +So, lets add the nodes in preparation for DVFS later. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 34 +++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index f5c5778f8ab9..b821f1d37f9c 100644 +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -5,6 +5,7 @@ + + #include + #include ++#include + + / { + model = "Qualcomm Technologies, Inc. IPQ8074"; +@@ -451,6 +452,39 @@ spmi_bus: spmi@200f000 { + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; ++ ++ pmic@1 { ++ compatible ="qcom,spmi-pmic"; ++ reg = <0x1 SPMI_USID>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ regulators { ++ compatible = "qcom,pmd9655-regulators"; ++ ++ s3: s3 { ++ regulator-name = "pmd9655_s3"; ++ regulator-min-microvolt = <592000>; ++ regulator-max-microvolt = <1064000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ s4: s4 { ++ regulator-name = "pmd9655_s4"; ++ regulator-min-microvolt = <712000>; ++ regulator-max-microvolt = <992000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo11: ldo11 { ++ regulator-name = "pmd9655_ldo11"; ++ regulator-min-microvolt = <1104000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ }; ++ }; + }; + + sdhc_1: sdhci@7824900 { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0130-clk-qcom-clk-alpha-pll-add-support-for-APSS-PLL.patch b/target/linux/ipq807x/patches-5.15/0130-clk-qcom-clk-alpha-pll-add-support-for-APSS-PLL.patch new file mode 100644 index 000000000..7a652322a --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0130-clk-qcom-clk-alpha-pll-add-support-for-APSS-PLL.patch @@ -0,0 +1,54 @@ +From 5a127450125f71247b7384930459b892da227e28 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 28 Dec 2021 20:32:46 +0100 +Subject: [PATCH] clk: qcom: clk-alpha-pll: add support for APSS PLL + +APSS PLL type will be used by the IPQ8074 APSS driver for providing the +CPU core clocks and enabling CPU Frequency scaling. + +This is ported from the downstream 5.4 kernel. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ + drivers/clk/qcom/clk-alpha-pll.h | 1 + + 2 files changed, 13 insertions(+) + +diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c +index 8f65b9bdafce..d2c3eb4cf4af 100644 +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -139,6 +139,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { + [PLL_OFF_OPMODE] = 0x28, + [PLL_OFF_STATUS] = 0x38, + }, ++ [CLK_ALPHA_PLL_TYPE_APSS] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_ALPHA_VAL_U] = 0xff, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_USER_CTL_U] = 0xff, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_CONFIG_CTL_U] = 0x24, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ [PLL_OFF_STATUS] = 0x28, ++ }, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + +diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h +index 55e4fa47912f..45e4b93253a9 100644 +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -17,6 +17,7 @@ enum { + CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, + CLK_ALPHA_PLL_TYPE_AGERA, + CLK_ALPHA_PLL_TYPE_ZONDA, ++ CLK_ALPHA_PLL_TYPE_APSS, + CLK_ALPHA_PLL_TYPE_MAX, + }; + +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0131-clk-qcom-Add-DT-bindings-for-IPQ8074-APSS-clock-cont.patch b/target/linux/ipq807x/patches-5.15/0131-clk-qcom-Add-DT-bindings-for-IPQ8074-APSS-clock-cont.patch new file mode 100644 index 000000000..c9da7813a --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0131-clk-qcom-Add-DT-bindings-for-IPQ8074-APSS-clock-cont.patch @@ -0,0 +1,36 @@ +From ab17c6d31f07271b42c6c36c9ad785bdc2871e62 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 28 Dec 2021 20:36:45 +0100 +Subject: [PATCH] clk: qcom: Add DT bindings for IPQ8074 APSS clock controller + +Add DT-binding for the IPQ8074 APSS clock controller. + +Signed-off-by: Robert Marko +--- + include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h + +diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h +new file mode 100644 +index 000000000000..df07766b0146 +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H ++#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H ++ ++#define APSS_PLL_EARLY 0 ++#define APSS_PLL 1 ++#define APCS_ALIAS0_CLK_SRC 2 ++#define APCS_ALIAS0_CORE_CLK 3 ++ ++#endif +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch b/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch new file mode 100644 index 000000000..38403d629 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch @@ -0,0 +1,230 @@ +From c0333749b53881e61ecdfc62f253e24b01dda129 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 28 Dec 2021 20:37:55 +0100 +Subject: [PATCH] clk: qcom: Add IPQ8074 APSS clock controller + +IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU +cores, thus also providing support for CPU frequency scaling. + +It looks like they are clocked by the XO and a custom APSS type PLL. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/Kconfig | 10 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/apss-ipq8074.c | 170 ++++++++++++++++++++++++++++++++ + 3 files changed, 181 insertions(+) + create mode 100644 drivers/clk/qcom/apss-ipq8074.c + +diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig +index 9ef007b3cf9b..76f3c999e507 100644 +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -134,6 +134,16 @@ config IPQ_APSS_6018 + Say Y if you want to support CPU frequency scaling on + ipq based devices. + ++config IPQ_APSS_8074 ++ tristate "IPQ8074 APSS Clock Controller" ++ depends on QCOM_APCS_IPC || COMPILE_TEST ++ help ++ Support for APSS clock controller on IPQ8074 platforms. The ++ APSS clock controller manages the Mux and enable block that feeds the ++ CPUs. ++ Say Y if you want to support CPU frequency scaling on ++ ipq based devices. ++ + config IPQ_GCC_4019 + tristate "IPQ4019 Global Clock Controller" + help +diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile +index 9825ef843f4a..a47b0dcc0add 100644 +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o + obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o + obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o + obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o ++obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o + obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o + obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o +diff --git a/drivers/clk/qcom/apss-ipq8074.c b/drivers/clk/qcom/apss-ipq8074.c +new file mode 100644 +index 000000000000..51548539194c +--- /dev/null ++++ b/drivers/clk/qcom/apss-ipq8074.c +@@ -0,0 +1,170 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "common.h" ++#include "clk-regmap.h" ++#include "clk-pll.h" ++#include "clk-rcg.h" ++#include "clk-branch.h" ++#include "clk-alpha-pll.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++ ++#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } ++ ++enum { ++ P_XO, ++ P_GPLL0, ++ P_GPLL2, ++ P_GPLL4, ++ P_APSS_PLL_EARLY, ++ P_APSS_PLL ++}; ++ ++static struct clk_alpha_pll apss_pll_early = { ++ .offset = 0x5000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], ++ .clkr = { ++ .enable_reg = 0x5000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "apss_pll_early", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_huayra_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv apss_pll = { ++ .offset = 0x5000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], ++ .width = 2, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apss_pll", ++ .parent_names = (const char *[]){ "apss_pll_early" }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ ++static const char * const parents_apcs_alias0_clk_src[] = { ++ "xo", ++ "gpll0", ++ "gpll2", ++ "gpll4", ++ "apss_pll", ++ "apss_pll_early", ++}; ++ ++static const struct parent_map parents_apcs_alias0_clk_src_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 4 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL4, 1 }, ++ { P_APSS_PLL, 3 }, ++ { P_APSS_PLL_EARLY, 5 }, ++}; ++ ++struct freq_tbl ftbl_apcs_alias0_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 apcs_alias0_clk_src = { ++ .cmd_rcgr = 0x0050, ++ .freq_tbl = ftbl_apcs_alias0_clk_src, ++ .hid_width = 5, ++ .parent_map = parents_apcs_alias0_clk_src_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_clk_src", ++ .parent_names = parents_apcs_alias0_clk_src, ++ .num_parents = 6, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_branch apcs_alias0_core_clk = { ++ .halt_reg = 0x0058, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x0058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_core_clk", ++ .parent_names = (const char *[]){ ++ "apcs_alias0_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | ++ CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap *apss_ipq8074_clks[] = { ++ [APSS_PLL_EARLY] = &apss_pll_early.clkr, ++ [APSS_PLL] = &apss_pll.clkr, ++ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, ++ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, ++}; ++ ++static const struct regmap_config apss_ipq8074_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x5ffc, ++ .fast_io = true, ++}; ++ ++static const struct qcom_cc_desc apss_ipq8074_desc = { ++ .config = &apss_ipq8074_regmap_config, ++ .clks = apss_ipq8074_clks, ++ .num_clks = ARRAY_SIZE(apss_ipq8074_clks), ++}; ++ ++static int apss_ipq8074_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ ++ regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!regmap) ++ return -ENODEV; ++ ++ return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); ++} ++ ++static struct platform_driver apss_ipq8074_driver = { ++ .probe = apss_ipq8074_probe, ++ .driver = { ++ .name = "qcom,apss-ipq8074-clk", ++ }, ++}; ++ ++module_platform_driver(apss_ipq8074_driver); ++ ++MODULE_DESCRIPTION("Qualcomm IPQ8074 APSS clock driver"); ++MODULE_LICENSE("GPLv2"); +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0133-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-control.patch b/target/linux/ipq807x/patches-5.15/0133-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-control.patch new file mode 100644 index 000000000..ba61a9aaf --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0133-mailbox-qcom-apcs-ipc-add-IPQ8074-APSS-clock-control.patch @@ -0,0 +1,44 @@ +From cef0d7940ff741590c638ced909cb9e58b9d8bb0 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 28 Dec 2021 20:59:18 +0100 +Subject: [PATCH] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller + support + +IPQ8074 has the APSS clock controller utilizing the same register space as +the APCS, so provide acess to the APSS utilizing a child device like +IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS +clock driver. + +Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be +updated to 0x5FFC. + +Signed-off-by: Robert Marko +--- + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c +index 82ccfaf14b24..23407280580f 100644 +--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c ++++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c +@@ -34,7 +34,7 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { + }; + + static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { +- .offset = 8, .clk_name = NULL ++ .offset = 8, .clk_name = "qcom,apss-ipq8074-clk" + }; + + static const struct qcom_apcs_ipc_data msm8916_apcs_data = { +@@ -73,7 +73,7 @@ static const struct regmap_config apcs_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, +- .max_register = 0x1008, ++ .max_register = 0x5FFC, + .fast_io = true, + }; + +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0134-arm64-dts-ipq8074-update-APCS-node-due-to-clock-supp.patch b/target/linux/ipq807x/patches-5.15/0134-arm64-dts-ipq8074-update-APCS-node-due-to-clock-supp.patch new file mode 100644 index 000000000..133022d0d --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0134-arm64-dts-ipq8074-update-APCS-node-due-to-clock-supp.patch @@ -0,0 +1,33 @@ +From 89b34e0f57eaa18fc04ff038372c8d1facf55fa8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 28 Dec 2021 21:07:17 +0100 +Subject: [PATCH] arm64: dts: ipq8074: update APCS node due to clock support + +APCS now has support for providing the APSS clocks as the child device +for IPQ8074, so update the DT node to reflect the expanded register space +as well as add #clock-cells property as it now provides the APSS clock +that will be used for CPU scaling. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index b821f1d37f9c..b2dd418891e6 100644 +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -971,8 +971,9 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; +- reg = <0x0b111000 0x1000>; ++ reg = <0x0b111000 0x6000>; + ++ #clock-cells = <1>; + #mbox-cells = <1>; + }; + +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0125-arm64-dts-ipq8074-add-CPU-clock.patch b/target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-CPU-clock-and-regulator.patch similarity index 53% rename from target/linux/ipq807x/patches-5.15/0125-arm64-dts-ipq8074-add-CPU-clock.patch rename to target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-CPU-clock-and-regulator.patch index 29d0b3890..4e792d6a4 100644 --- a/target/linux/ipq807x/patches-5.15/0125-arm64-dts-ipq8074-add-CPU-clock.patch +++ b/target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-CPU-clock-and-regulator.patch @@ -1,59 +1,71 @@ -From 7b7941649605363d0eebc9fdfb84a13a95522cfb Mon Sep 17 00:00:00 2001 +From c8cda381dfd1fd083d6d2f56f71d33144c042a43 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 31 Dec 2021 17:56:14 +0100 -Subject: [PATCH 125/137] arm64: dts: ipq8074: add CPU clock +Subject: [PATCH] arm64: dts: ipq8074: add CPU clock and regulator -Now that CPU clock is exposed and can be controlled, add the necessary -properties to the CPU nodes. +Now that we have drivers for both the CPU voltage regulator and clock +controller, add the required DT properties to CPU cores. + +OPP tables are not added as they are different for the IPQ8072/4/6/8 and +IPQ8070/1 SoC-s Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index b2dd418891e6..49a2a7d79c40 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -5,6 +5,7 @@ +@@ -4,6 +4,7 @@ + */ #include ++#include #include -+#include + #include - / { - #address-cells = <2>; -@@ -38,6 +39,8 @@ +@@ -35,6 +36,9 @@ CPU0: cpu@0 { reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; ++ cpu-supply = <&s3>; }; CPU1: cpu@1 { -@@ -46,6 +49,8 @@ +@@ -43,6 +47,9 @@ CPU1: cpu@1 { enable-method = "psci"; reg = <0x1>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; ++ cpu-supply = <&s3>; }; CPU2: cpu@2 { -@@ -54,6 +59,8 @@ +@@ -51,6 +58,9 @@ CPU2: cpu@2 { enable-method = "psci"; reg = <0x2>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; ++ cpu-supply = <&s3>; }; CPU3: cpu@3 { -@@ -62,6 +69,8 @@ +@@ -59,6 +69,9 @@ CPU3: cpu@3 { enable-method = "psci"; reg = <0x3>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; ++ cpu-supply = <&s3>; }; L2_0: l2-cache { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0126-arm64-dts-ipq8074-add-label-to-cpus.patch b/target/linux/ipq807x/patches-5.15/0136-arm64-dts-ipq8074-add-label-to-cpus.patch similarity index 66% rename from target/linux/ipq807x/patches-5.15/0126-arm64-dts-ipq8074-add-label-to-cpus.patch rename to target/linux/ipq807x/patches-5.15/0136-arm64-dts-ipq8074-add-label-to-cpus.patch index 45a560ee0..aff316b0e 100644 --- a/target/linux/ipq807x/patches-5.15/0126-arm64-dts-ipq8074-add-label-to-cpus.patch +++ b/target/linux/ipq807x/patches-5.15/0136-arm64-dts-ipq8074-add-label-to-cpus.patch @@ -1,7 +1,7 @@ -From ff74c990c4b671f17d0dfc2c93bae9e23b017472 Mon Sep 17 00:00:00 2001 +From 9fb45b1b02930be459d5722250c84532ce53b787 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 31 Dec 2021 18:42:53 +0100 -Subject: [PATCH 126/137] arm64: dts: ipq8074: add label to cpus +Subject: [PATCH] arm64: dts: ipq8074: add label to cpus Add label to cpus node as that makes it easy to add OPP table in SoC model specific DTSI as IPQ8074 family has differing clocks and voltages based on @@ -12,9 +12,11 @@ Signed-off-by: Robert Marko arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 49a2a7d79c40..ab683526159e 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -29,7 +29,7 @@ +@@ -26,7 +26,7 @@ xo: xo { }; }; @@ -23,3 +25,6 @@ Signed-off-by: Robert Marko #address-cells = <0x1>; #size-cells = <0x0>; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0136-power-Add-Qualcomm-APM.patch b/target/linux/ipq807x/patches-5.15/0136-power-Add-Qualcomm-APM.patch deleted file mode 100644 index e73afce71..000000000 --- a/target/linux/ipq807x/patches-5.15/0136-power-Add-Qualcomm-APM.patch +++ /dev/null @@ -1,1047 +0,0 @@ -From 715f1016a6083b2a7509cb08a4f5ea0bc9661020 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 11 Apr 2022 14:38:08 +0200 -Subject: [PATCH 136/137] power: Add Qualcomm APM - -Allow building Qualcomm APM. - -Signed-off-by: Robert Marko ---- - drivers/power/Kconfig | 1 + - drivers/power/Makefile | 1 + - drivers/power/qcom/Kconfig | 7 + - drivers/power/qcom/Makefile | 1 + - drivers/power/qcom/apm.c | 944 +++++++++++++++++++++++++++++++++ - include/linux/power/qcom/apm.h | 48 ++ - 6 files changed, 1002 insertions(+) - create mode 100644 drivers/power/qcom/Kconfig - create mode 100644 drivers/power/qcom/Makefile - create mode 100644 drivers/power/qcom/apm.c - create mode 100644 include/linux/power/qcom/apm.h - ---- a/drivers/power/Kconfig -+++ b/drivers/power/Kconfig -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - source "drivers/power/reset/Kconfig" - source "drivers/power/supply/Kconfig" -+source "drivers/power/qcom/Kconfig" ---- a/drivers/power/Makefile -+++ b/drivers/power/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_POWER_RESET) += reset/ - obj-$(CONFIG_POWER_SUPPLY) += supply/ -+obj-$(CONFIG_QCOM_APM) += qcom/ ---- /dev/null -+++ b/drivers/power/qcom/Kconfig -@@ -0,0 +1,7 @@ -+config QCOM_APM -+ bool "Qualcomm Technologies Inc platform specific APM driver" -+ help -+ Platform specific driver to manage the power source of -+ memory arrays. Interfaces with regulator drivers to ensure -+ SRAM Vmin requirements are met across different performance -+ levels. ---- /dev/null -+++ b/drivers/power/qcom/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_QCOM_APM) += apm.o ---- /dev/null -+++ b/drivers/power/qcom/apm.c -@@ -0,0 +1,944 @@ -+/* -+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#define pr_fmt(fmt) "%s: " fmt, __func__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * VDD_APCC -+ * ============================================================= -+ * | VDD_MX | | -+ * | ==========================|============= | -+ * ___|___ ___|___ ___|___ ___|___ ___|___ ___|___ -+ * | | | | | | | | | | | | -+ * | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC | -+ * | HS | | | | | | HS | | | | HS | -+ * |_______| |_______| |_______| |_______| |_______| |_______| -+ * |_________| |_________| |__________| -+ * | | | -+ * ______|_____ ______|_____ _______|_____ -+ * | | | | | | -+ * | | | | | | -+ * | CPU MEM | | L2 MEM | | L3 MEM | -+ * | Arrays | | Arrays | | Arrays | -+ * | | | | | | -+ * |____________| |____________| |_____________| -+ * -+ */ -+ -+/* Register value definitions */ -+#define APCS_GFMUXA_SEL_VAL 0x13 -+#define APCS_GFMUXA_DESEL_VAL 0x03 -+#define MSM_APM_MX_MODE_VAL 0x00 -+#define MSM_APM_APCC_MODE_VAL 0x10 -+#define MSM_APM_MX_DONE_VAL 0x00 -+#define MSM_APM_APCC_DONE_VAL 0x03 -+#define MSM_APM_OVERRIDE_SEL_VAL 0xb0 -+#define MSM_APM_SEC_CLK_SEL_VAL 0x30 -+#define SPM_EVENT_SET_VAL 0x01 -+#define SPM_EVENT_CLEAR_VAL 0x00 -+ -+/* Register bit mask definitions */ -+#define MSM_APM_CTL_STS_MASK 0x0f -+ -+/* Register offset definitions */ -+#define APCC_APM_MODE 0x00000098 -+#define APCC_APM_CTL_STS 0x000000a8 -+#define APCS_SPARE 0x00000068 -+#define APCS_VERSION 0x00000fd0 -+ -+#define HMSS_VERSION_1P2 0x10020000 -+ -+#define MSM_APM_SWITCH_TIMEOUT_US 10 -+#define SPM_WAKEUP_DELAY_US 2 -+#define SPM_EVENT_NUM 6 -+ -+#define MSM_APM_DRIVER_NAME "qcom,msm-apm" -+ -+enum { -+ MSM8996_ID, -+ MSM8953_ID, -+ IPQ807x_ID, -+}; -+ -+struct msm_apm_ctrl_dev { -+ struct list_head list; -+ struct device *dev; -+ enum msm_apm_supply supply; -+ spinlock_t lock; -+ void __iomem *reg_base; -+ void __iomem *apcs_csr_base; -+ void __iomem **apcs_spm_events_addr; -+ void __iomem *apc0_pll_ctl_addr; -+ void __iomem *apc1_pll_ctl_addr; -+ u32 version; -+ struct dentry *debugfs; -+ u32 msm_id; -+}; -+ -+#if defined(CONFIG_DEBUG_FS) -+static struct dentry *apm_debugfs_base; -+#endif -+ -+static DEFINE_MUTEX(apm_ctrl_list_mutex); -+static LIST_HEAD(apm_ctrl_list); -+ -+/* -+ * Get the resources associated with the APM controller from device tree -+ * and remap all I/O addresses that are relevant to this HW revision. -+ */ -+static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev, -+ struct msm_apm_ctrl_dev *ctrl) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ static const char *res_name[SPM_EVENT_NUM] = { -+ "apc0-l2-spm", -+ "apc1-l2-spm", -+ "apc0-cpu0-spm", -+ "apc0-cpu1-spm", -+ "apc1-cpu0-spm", -+ "apc1-cpu1-spm" -+ }; -+ int i, ret = 0; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb"); -+ if (!res) { -+ dev_err(dev, "Missing PM APCC Global register physical address"); -+ return -EINVAL; -+ } -+ ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!ctrl->reg_base) { -+ dev_err(dev, "Failed to map PM APCC Global registers\n"); -+ return -ENOMEM; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr"); -+ if (!res) { -+ dev_err(dev, "Missing APCS CSR physical base address"); -+ return -EINVAL; -+ } -+ ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!ctrl->apcs_csr_base) { -+ dev_err(dev, "Failed to map APCS CSR registers\n"); -+ return -ENOMEM; -+ } -+ -+ ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION); -+ -+ if (ctrl->version >= HMSS_VERSION_1P2) -+ return ret; -+ -+ ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev, -+ SPM_EVENT_NUM -+ * sizeof(void __iomem *), -+ GFP_KERNEL); -+ if (!ctrl->apcs_spm_events_addr) { -+ dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < SPM_EVENT_NUM; i++) { -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ res_name[i]); -+ if (!res) { -+ dev_err(dev, "Missing address for %s\n", res_name[i]); -+ ret = -EINVAL; -+ goto free_events; -+ } -+ -+ ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start, -+ resource_size(res)); -+ if (!ctrl->apcs_spm_events_addr[i]) { -+ dev_err(dev, "Failed to map %s\n", res_name[i]); -+ ret = -ENOMEM; -+ goto free_events; -+ } -+ -+ dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i], -+ &res->start, ctrl->apcs_spm_events_addr[i]); -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "apc0-pll-ctl"); -+ if (!res) { -+ dev_err(dev, "Missing APC0 PLL CTL physical address\n"); -+ ret = -EINVAL; -+ goto free_events; -+ } -+ -+ ctrl->apc0_pll_ctl_addr = devm_ioremap(dev, -+ res->start, -+ resource_size(res)); -+ if (!ctrl->apc0_pll_ctl_addr) { -+ dev_err(dev, "Failed to map APC0 PLL CTL register\n"); -+ ret = -ENOMEM; -+ goto free_events; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "apc1-pll-ctl"); -+ if (!res) { -+ dev_err(dev, "Missing APC1 PLL CTL physical address\n"); -+ ret = -EINVAL; -+ goto free_events; -+ } -+ -+ ctrl->apc1_pll_ctl_addr = devm_ioremap(dev, -+ res->start, -+ resource_size(res)); -+ if (!ctrl->apc1_pll_ctl_addr) { -+ dev_err(dev, "Failed to map APC1 PLL CTL register\n"); -+ ret = -ENOMEM; -+ goto free_events; -+ } -+ -+ return ret; -+ -+free_events: -+ devm_kfree(dev, ctrl->apcs_spm_events_addr); -+ return ret; -+} -+ -+/* 8953 register offset definition */ -+#define MSM8953_APM_DLY_CNTR 0x2ac -+ -+/* Register field shift definitions */ -+#define APM_CTL_SEL_SWITCH_DLY_SHIFT 0 -+#define APM_CTL_RESUME_CLK_DLY_SHIFT 8 -+#define APM_CTL_HALT_CLK_DLY_SHIFT 16 -+#define APM_CTL_POST_HALT_DLY_SHIFT 24 -+ -+/* Register field mask definitions */ -+#define APM_CTL_SEL_SWITCH_DLY_MASK GENMASK(7, 0) -+#define APM_CTL_RESUME_CLK_DLY_MASK GENMASK(15, 8) -+#define APM_CTL_HALT_CLK_DLY_MASK GENMASK(23, 16) -+#define APM_CTL_POST_HALT_DLY_MASK GENMASK(31, 24) -+ -+/* -+ * Get the resources associated with the msm8953 APM controller from -+ * device tree, remap all I/O addresses, and program the initial -+ * register configuration required for the 8953 APM controller device. -+ */ -+static int msm8953_apm_ctrl_init(struct platform_device *pdev, -+ struct msm_apm_ctrl_dev *ctrl) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ u32 delay_counter, val = 0, regval = 0; -+ int rc = 0; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb"); -+ if (!res) { -+ dev_err(dev, "Missing PM APCC Global register physical address\n"); -+ return -ENODEV; -+ } -+ ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!ctrl->reg_base) { -+ dev_err(dev, "Failed to map PM APCC Global registers\n"); -+ return -ENOMEM; -+ } -+ -+ /* -+ * Initial APM register configuration required before starting -+ * APM HW controller. -+ */ -+ regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR); -+ val = regval; -+ -+ if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) { -+ rc = of_property_read_u32(dev->of_node, -+ "qcom,apm-post-halt-delay", &delay_counter); -+ if (rc < 0) { -+ dev_err(dev, "apm-post-halt-delay read failed, rc = %d", -+ rc); -+ return rc; -+ } -+ -+ val &= ~APM_CTL_POST_HALT_DLY_MASK; -+ val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT) -+ & APM_CTL_POST_HALT_DLY_MASK; -+ } -+ -+ if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) { -+ rc = of_property_read_u32(dev->of_node, -+ "qcom,apm-halt-clk-delay", &delay_counter); -+ if (rc < 0) { -+ dev_err(dev, "apm-halt-clk-delay read failed, rc = %d", -+ rc); -+ return rc; -+ } -+ -+ val &= ~APM_CTL_HALT_CLK_DLY_MASK; -+ val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT) -+ & APM_CTL_HALT_CLK_DLY_MASK; -+ } -+ -+ if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) { -+ rc = of_property_read_u32(dev->of_node, -+ "qcom,apm-resume-clk-delay", &delay_counter); -+ if (rc < 0) { -+ dev_err(dev, "apm-resume-clk-delay read failed, rc = %d", -+ rc); -+ return rc; -+ } -+ -+ val &= ~APM_CTL_RESUME_CLK_DLY_MASK; -+ val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT) -+ & APM_CTL_RESUME_CLK_DLY_MASK; -+ } -+ -+ if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) { -+ rc = of_property_read_u32(dev->of_node, -+ "qcom,apm-sel-switch-delay", &delay_counter); -+ if (rc < 0) { -+ dev_err(dev, "apm-sel-switch-delay read failed, rc = %d", -+ rc); -+ return rc; -+ } -+ -+ val &= ~APM_CTL_SEL_SWITCH_DLY_MASK; -+ val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT) -+ & APM_CTL_SEL_SWITCH_DLY_MASK; -+ } -+ -+ if (val != regval) { -+ writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR); -+ /* make sure write completes before return */ -+ mb(); -+ } -+ -+ return rc; -+} -+ -+static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int i, timeout = MSM_APM_SWITCH_TIMEOUT_US; -+ u32 regval; -+ int ret = 0; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ctrl_dev->lock, flags); -+ -+ /* Perform revision-specific programming steps */ -+ if (ctrl_dev->version < HMSS_VERSION_1P2) { -+ /* Clear SPM events */ -+ for (i = 0; i < SPM_EVENT_NUM; i++) -+ writel_relaxed(SPM_EVENT_CLEAR_VAL, -+ ctrl_dev->apcs_spm_events_addr[i]); -+ -+ udelay(SPM_WAKEUP_DELAY_US); -+ -+ /* Switch APC/CBF to GPLL0 clock */ -+ writel_relaxed(APCS_GFMUXA_SEL_VAL, -+ ctrl_dev->apcs_csr_base + APCS_SPARE); -+ ndelay(200); -+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, -+ ctrl_dev->apc0_pll_ctl_addr); -+ ndelay(200); -+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, -+ ctrl_dev->apc1_pll_ctl_addr); -+ -+ /* Ensure writes complete before proceeding */ -+ mb(); -+ } -+ -+ /* Switch arrays to MX supply and wait for its completion */ -+ writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base + -+ APCC_APM_MODE); -+ -+ /* Ensure write above completes before delaying */ -+ mb(); -+ -+ while (timeout > 0) { -+ regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS); -+ if ((regval & MSM_APM_CTL_STS_MASK) == -+ MSM_APM_MX_DONE_VAL) -+ break; -+ -+ udelay(1); -+ timeout--; -+ } -+ -+ if (timeout == 0) { -+ ret = -ETIMEDOUT; -+ dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n", -+ regval); -+ } -+ -+ /* Perform revision-specific programming steps */ -+ if (ctrl_dev->version < HMSS_VERSION_1P2) { -+ /* Switch APC/CBF clocks to original source */ -+ writel_relaxed(APCS_GFMUXA_DESEL_VAL, -+ ctrl_dev->apcs_csr_base + APCS_SPARE); -+ ndelay(200); -+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, -+ ctrl_dev->apc0_pll_ctl_addr); -+ ndelay(200); -+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, -+ ctrl_dev->apc1_pll_ctl_addr); -+ -+ /* Complete clock source switch before SPM event sequence */ -+ mb(); -+ -+ /* Set SPM events */ -+ for (i = 0; i < SPM_EVENT_NUM; i++) -+ writel_relaxed(SPM_EVENT_SET_VAL, -+ ctrl_dev->apcs_spm_events_addr[i]); -+ } -+ -+ if (!ret) { -+ ctrl_dev->supply = MSM_APM_SUPPLY_MX; -+ dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n"); -+ } -+ -+ spin_unlock_irqrestore(&ctrl_dev->lock, flags); -+ -+ return ret; -+} -+ -+static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int i, timeout = MSM_APM_SWITCH_TIMEOUT_US; -+ u32 regval; -+ int ret = 0; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ctrl_dev->lock, flags); -+ -+ /* Perform revision-specific programming steps */ -+ if (ctrl_dev->version < HMSS_VERSION_1P2) { -+ /* Clear SPM events */ -+ for (i = 0; i < SPM_EVENT_NUM; i++) -+ writel_relaxed(SPM_EVENT_CLEAR_VAL, -+ ctrl_dev->apcs_spm_events_addr[i]); -+ -+ udelay(SPM_WAKEUP_DELAY_US); -+ -+ /* Switch APC/CBF to GPLL0 clock */ -+ writel_relaxed(APCS_GFMUXA_SEL_VAL, -+ ctrl_dev->apcs_csr_base + APCS_SPARE); -+ ndelay(200); -+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, -+ ctrl_dev->apc0_pll_ctl_addr); -+ ndelay(200); -+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL, -+ ctrl_dev->apc1_pll_ctl_addr); -+ -+ /* Ensure previous writes complete before proceeding */ -+ mb(); -+ } -+ -+ /* Switch arrays to APCC supply and wait for its completion */ -+ writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base + -+ APCC_APM_MODE); -+ -+ /* Ensure write above completes before delaying */ -+ mb(); -+ -+ while (timeout > 0) { -+ regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS); -+ if ((regval & MSM_APM_CTL_STS_MASK) == -+ MSM_APM_APCC_DONE_VAL) -+ break; -+ -+ udelay(1); -+ timeout--; -+ } -+ -+ if (timeout == 0) { -+ ret = -ETIMEDOUT; -+ dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n", -+ regval); -+ } -+ -+ /* Perform revision-specific programming steps */ -+ if (ctrl_dev->version < HMSS_VERSION_1P2) { -+ /* Set SPM events */ -+ for (i = 0; i < SPM_EVENT_NUM; i++) -+ writel_relaxed(SPM_EVENT_SET_VAL, -+ ctrl_dev->apcs_spm_events_addr[i]); -+ -+ /* Complete SPM event sequence before clock source switch */ -+ mb(); -+ -+ /* Switch APC/CBF clocks to original source */ -+ writel_relaxed(APCS_GFMUXA_DESEL_VAL, -+ ctrl_dev->apcs_csr_base + APCS_SPARE); -+ ndelay(200); -+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, -+ ctrl_dev->apc0_pll_ctl_addr); -+ ndelay(200); -+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL, -+ ctrl_dev->apc1_pll_ctl_addr); -+ } -+ -+ if (!ret) { -+ ctrl_dev->supply = MSM_APM_SUPPLY_APCC; -+ dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n"); -+ } -+ -+ spin_unlock_irqrestore(&ctrl_dev->lock, flags); -+ -+ return ret; -+} -+ -+/* 8953 register value definitions */ -+#define MSM8953_APM_MX_MODE_VAL 0x00 -+#define MSM8953_APM_APCC_MODE_VAL 0x02 -+#define MSM8953_APM_MX_DONE_VAL 0x00 -+#define MSM8953_APM_APCC_DONE_VAL 0x03 -+ -+/* 8953 register offset definitions */ -+#define MSM8953_APCC_APM_MODE 0x000002a8 -+#define MSM8953_APCC_APM_CTL_STS 0x000002b0 -+ -+/* 8953 constants */ -+#define MSM8953_APM_SWITCH_TIMEOUT_US 500 -+ -+/* Register bit mask definitions */ -+#define MSM8953_APM_CTL_STS_MASK 0x1f -+ -+static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int timeout = MSM8953_APM_SWITCH_TIMEOUT_US; -+ u32 regval; -+ int ret = 0; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ctrl_dev->lock, flags); -+ -+ /* Switch arrays to MX supply and wait for its completion */ -+ writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base + -+ MSM8953_APCC_APM_MODE); -+ -+ /* Ensure write above completes before delaying */ -+ mb(); -+ -+ while (timeout > 0) { -+ regval = readl_relaxed(ctrl_dev->reg_base + -+ MSM8953_APCC_APM_CTL_STS); -+ if ((regval & MSM8953_APM_CTL_STS_MASK) == -+ MSM8953_APM_MX_DONE_VAL) -+ break; -+ -+ udelay(1); -+ timeout--; -+ } -+ -+ if (timeout == 0) { -+ ret = -ETIMEDOUT; -+ dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n", -+ regval); -+ } else { -+ ctrl_dev->supply = MSM_APM_SUPPLY_MX; -+ dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n"); -+ } -+ -+ spin_unlock_irqrestore(&ctrl_dev->lock, flags); -+ -+ return ret; -+} -+ -+static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int timeout = MSM8953_APM_SWITCH_TIMEOUT_US; -+ u32 regval; -+ int ret = 0; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ctrl_dev->lock, flags); -+ -+ /* Switch arrays to APCC supply and wait for its completion */ -+ writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base + -+ MSM8953_APCC_APM_MODE); -+ -+ /* Ensure write above completes before delaying */ -+ mb(); -+ -+ while (timeout > 0) { -+ regval = readl_relaxed(ctrl_dev->reg_base + -+ MSM8953_APCC_APM_CTL_STS); -+ if ((regval & MSM8953_APM_CTL_STS_MASK) == -+ MSM8953_APM_APCC_DONE_VAL) -+ break; -+ -+ udelay(1); -+ timeout--; -+ } -+ -+ if (timeout == 0) { -+ ret = -ETIMEDOUT; -+ dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n", -+ regval); -+ } else { -+ ctrl_dev->supply = MSM_APM_SUPPLY_APCC; -+ dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n"); -+ } -+ -+ spin_unlock_irqrestore(&ctrl_dev->lock, flags); -+ -+ return ret; -+} -+ -+static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int ret = 0; -+ -+ switch (ctrl_dev->msm_id) { -+ case MSM8996_ID: -+ ret = msm8996_apm_switch_to_mx(ctrl_dev); -+ break; -+ case MSM8953_ID: -+ case IPQ807x_ID: -+ ret = msm8953_apm_switch_to_mx(ctrl_dev); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ int ret = 0; -+ -+ switch (ctrl_dev->msm_id) { -+ case MSM8996_ID: -+ ret = msm8996_apm_switch_to_apcc(ctrl_dev); -+ break; -+ case MSM8953_ID: -+ case IPQ807x_ID: -+ ret = msm8953_apm_switch_to_apcc(ctrl_dev); -+ break; -+ } -+ -+ return ret; -+} -+ -+/** -+ * msm_apm_get_supply() - Returns the supply that is currently -+ * powering the memory arrays -+ * @ctrl_dev: Pointer to an MSM APM controller device -+ * -+ * Returns the supply currently selected by the APM. -+ */ -+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ return ctrl_dev->supply; -+} -+EXPORT_SYMBOL(msm_apm_get_supply); -+ -+/** -+ * msm_apm_set_supply() - Perform the necessary steps to switch the voltage -+ * source of the memory arrays to a given supply -+ * @ctrl_dev: Pointer to an MSM APM controller device -+ * @supply: Power rail to use as supply for the memory -+ * arrays -+ * -+ * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if -+ * the supply is not supported. -+ */ -+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, -+ enum msm_apm_supply supply) -+{ -+ int ret; -+ -+ switch (supply) { -+ case MSM_APM_SUPPLY_APCC: -+ ret = msm_apm_switch_to_apcc(ctrl_dev); -+ break; -+ case MSM_APM_SUPPLY_MX: -+ ret = msm_apm_switch_to_mx(ctrl_dev); -+ break; -+ default: -+ ret = -EPERM; -+ break; -+ } -+ -+ return ret; -+} -+EXPORT_SYMBOL(msm_apm_set_supply); -+ -+/** -+ * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to -+ * the device in device tree -+ * @dev: Pointer to the device -+ * -+ * The device must specify "qcom,apm-ctrl" property in its device tree -+ * node which points to an MSM APM controller device node. -+ * -+ * Returns an MSM APM controller handle if successful or ERR_PTR on any error. -+ * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is -+ * returned. -+ */ -+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev) -+{ -+ struct msm_apm_ctrl_dev *ctrl_dev = NULL; -+ struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER); -+ struct device_node *ctrl_node; -+ -+ if (!dev || !dev->of_node) { -+ pr_err("Invalid device node\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0); -+ if (!ctrl_node) { -+ pr_err("Could not find qcom,apm-ctrl property in %s\n", -+ dev->of_node->full_name); -+ return ERR_PTR(-ENXIO); -+ } -+ -+ mutex_lock(&apm_ctrl_list_mutex); -+ list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) { -+ if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) { -+ dev_found = ctrl_dev; -+ break; -+ } -+ } -+ mutex_unlock(&apm_ctrl_list_mutex); -+ -+ of_node_put(ctrl_node); -+ return dev_found; -+} -+EXPORT_SYMBOL(msm_apm_ctrl_dev_get); -+ -+#if defined(CONFIG_DEBUG_FS) -+ -+static int apm_supply_dbg_open(struct inode *inode, struct file *filep) -+{ -+ filep->private_data = inode->i_private; -+ -+ return 0; -+} -+ -+static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf, -+ size_t count, loff_t *ppos) -+{ -+ struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data; -+ char buf[10]; -+ int len; -+ -+ if (!ctrl_dev) { -+ pr_err("invalid apm ctrl handle\n"); -+ return -ENODEV; -+ } -+ -+ if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC) -+ len = snprintf(buf, sizeof(buf), "APCC\n"); -+ else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX) -+ len = snprintf(buf, sizeof(buf), "MX\n"); -+ else -+ len = snprintf(buf, sizeof(buf), "ERR\n"); -+ -+ return simple_read_from_buffer(ubuf, count, ppos, buf, len); -+} -+ -+static const struct file_operations apm_supply_fops = { -+ .open = apm_supply_dbg_open, -+ .read = apm_supply_dbg_read, -+}; -+ -+static void apm_debugfs_base_init(void) -+{ -+ apm_debugfs_base = debugfs_create_dir("msm-apm", NULL); -+ -+ if (IS_ERR_OR_NULL(apm_debugfs_base)) -+ pr_err("msm-apm debugfs base directory creation failed\n"); -+} -+ -+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ struct dentry *temp; -+ -+ if (IS_ERR_OR_NULL(apm_debugfs_base)) { -+ pr_err("Base directory missing, cannot create apm debugfs nodes\n"); -+ return; -+ } -+ -+ ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev), -+ apm_debugfs_base); -+ if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) { -+ pr_err("%s debugfs directory creation failed\n", -+ dev_name(ctrl_dev->dev)); -+ return; -+ } -+ -+ temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs, -+ ctrl_dev, &apm_supply_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ pr_err("supply mode creation failed\n"); -+ return; -+ } -+} -+ -+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev) -+{ -+ if (!IS_ERR_OR_NULL(ctrl_dev->debugfs)) -+ debugfs_remove_recursive(ctrl_dev->debugfs); -+} -+ -+static void apm_debugfs_base_remove(void) -+{ -+ debugfs_remove_recursive(apm_debugfs_base); -+} -+#else -+ -+static void apm_debugfs_base_init(void) -+{} -+ -+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev) -+{} -+ -+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev) -+{} -+ -+static void apm_debugfs_base_remove(void) -+{} -+ -+#endif -+ -+static struct of_device_id msm_apm_match_table[] = { -+ { -+ .compatible = "qcom,msm-apm", -+ .data = (void *)(uintptr_t)MSM8996_ID, -+ }, -+ { -+ .compatible = "qcom,msm8953-apm", -+ .data = (void *)(uintptr_t)MSM8953_ID, -+ }, -+ { -+ .compatible = "qcom,ipq807x-apm", -+ .data = (void *)(uintptr_t)IPQ807x_ID, -+ }, -+ {} -+}; -+ -+static int msm_apm_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct msm_apm_ctrl_dev *ctrl; -+ const struct of_device_id *match; -+ int ret = 0; -+ -+ dev_dbg(dev, "probing MSM Array Power Mux driver\n"); -+ -+ if (!dev->of_node) { -+ dev_err(dev, "Device tree node is missing\n"); -+ return -ENODEV; -+ } -+ -+ match = of_match_device(msm_apm_match_table, dev); -+ if (!match) -+ return -ENODEV; -+ -+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -+ if (!ctrl) { -+ dev_err(dev, "MSM APM controller memory allocation failed\n"); -+ return -ENOMEM; -+ } -+ -+ INIT_LIST_HEAD(&ctrl->list); -+ spin_lock_init(&ctrl->lock); -+ ctrl->dev = dev; -+ ctrl->msm_id = (uintptr_t)match->data; -+ platform_set_drvdata(pdev, ctrl); -+ -+ switch (ctrl->msm_id) { -+ case MSM8996_ID: -+ ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl); -+ if (ret) { -+ dev_err(dev, "Failed to add APM controller device\n"); -+ return ret; -+ } -+ break; -+ case MSM8953_ID: -+ case IPQ807x_ID: -+ ret = msm8953_apm_ctrl_init(pdev, ctrl); -+ if (ret) { -+ dev_err(dev, "Failed to initialize APM controller device: ret=%d\n", -+ ret); -+ return ret; -+ } -+ break; -+ default: -+ dev_err(dev, "unable to add APM controller device for msm_id:%d\n", -+ ctrl->msm_id); -+ return -ENODEV; -+ } -+ -+ apm_debugfs_init(ctrl); -+ mutex_lock(&apm_ctrl_list_mutex); -+ list_add_tail(&ctrl->list, &apm_ctrl_list); -+ mutex_unlock(&apm_ctrl_list_mutex); -+ -+ dev_dbg(dev, "MSM Array Power Mux driver probe successful"); -+ -+ return ret; -+} -+ -+static int msm_apm_remove(struct platform_device *pdev) -+{ -+ struct msm_apm_ctrl_dev *ctrl_dev; -+ -+ ctrl_dev = platform_get_drvdata(pdev); -+ if (ctrl_dev) { -+ mutex_lock(&apm_ctrl_list_mutex); -+ list_del(&ctrl_dev->list); -+ mutex_unlock(&apm_ctrl_list_mutex); -+ apm_debugfs_deinit(ctrl_dev); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver msm_apm_driver = { -+ .driver = { -+ .name = MSM_APM_DRIVER_NAME, -+ .of_match_table = msm_apm_match_table, -+ .owner = THIS_MODULE, -+ }, -+ .probe = msm_apm_probe, -+ .remove = msm_apm_remove, -+}; -+ -+static int __init msm_apm_init(void) -+{ -+ apm_debugfs_base_init(); -+ return platform_driver_register(&msm_apm_driver); -+} -+ -+static void __exit msm_apm_exit(void) -+{ -+ platform_driver_unregister(&msm_apm_driver); -+ apm_debugfs_base_remove(); -+} -+ -+arch_initcall(msm_apm_init); -+module_exit(msm_apm_exit); -+ -+MODULE_DESCRIPTION("MSM Array Power Mux driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/linux/power/qcom/apm.h -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __LINUX_POWER_QCOM_APM_H__ -+#define __LINUX_POWER_QCOM_APM_H__ -+ -+#include -+#include -+ -+/** -+ * enum msm_apm_supply - supported power rails to supply memory arrays -+ * %MSM_APM_SUPPLY_APCC: to enable selection of VDD_APCC rail as supply -+ * %MSM_APM_SUPPLY_MX: to enable selection of VDD_MX rail as supply -+ */ -+enum msm_apm_supply { -+ MSM_APM_SUPPLY_APCC, -+ MSM_APM_SUPPLY_MX, -+}; -+ -+/* Handle used to identify an APM controller device */ -+struct msm_apm_ctrl_dev; -+ -+#ifdef CONFIG_QCOM_APM -+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev); -+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, -+ enum msm_apm_supply supply); -+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev); -+ -+#else -+static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev) -+{ return ERR_PTR(-EPERM); } -+static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev, -+ enum msm_apm_supply supply) -+{ return -EPERM; } -+static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev) -+{ return -EPERM; } -+#endif -+#endif diff --git a/target/linux/ipq807x/patches-5.15/0127-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch b/target/linux/ipq807x/patches-5.15/0137-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch similarity index 66% rename from target/linux/ipq807x/patches-5.15/0127-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch rename to target/linux/ipq807x/patches-5.15/0137-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch index b49e1b8df..d203b700b 100644 --- a/target/linux/ipq807x/patches-5.15/0127-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch +++ b/target/linux/ipq807x/patches-5.15/0137-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch @@ -1,7 +1,7 @@ -From 8ddd2743d7bd30165b0c5e1abb6990da15c181d4 Mon Sep 17 00:00:00 2001 +From 26fe80d67ab1351faa2e745a20152de71d38124f Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 31 Dec 2021 20:38:06 +0100 -Subject: [PATCH 127/137] arm64: dts: ipq8074: add cooling cells to CPU nodes +Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes Since there is CPU Freq support as well as thermal sensor support now for the IPQ8074, add cooling cells to CPU nodes so that they can @@ -12,37 +12,42 @@ Signed-off-by: Robert Marko arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++ 1 file changed, 4 insertions(+) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index ab683526159e..69234f39ac8c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -41,6 +41,7 @@ - enable-method = "psci"; +@@ -39,6 +39,7 @@ CPU0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + cpu-supply = <&s3>; + #cooling-cells = <2>; }; CPU1: cpu@1 { -@@ -51,6 +52,7 @@ - next-level-cache = <&L2_0>; +@@ -50,6 +51,7 @@ CPU1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + cpu-supply = <&s3>; + #cooling-cells = <2>; }; CPU2: cpu@2 { -@@ -61,6 +63,7 @@ - next-level-cache = <&L2_0>; +@@ -61,6 +63,7 @@ CPU2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + cpu-supply = <&s3>; + #cooling-cells = <2>; }; CPU3: cpu@3 { -@@ -71,6 +74,7 @@ - next-level-cache = <&L2_0>; +@@ -72,6 +75,7 @@ CPU3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + cpu-supply = <&s3>; + #cooling-cells = <2>; }; L2_0: l2-cache { +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0137-regulator-add-Qualcomm-CPR-regulators.patch b/target/linux/ipq807x/patches-5.15/0137-regulator-add-Qualcomm-CPR-regulators.patch deleted file mode 100644 index 2f997e23a..000000000 --- a/target/linux/ipq807x/patches-5.15/0137-regulator-add-Qualcomm-CPR-regulators.patch +++ /dev/null @@ -1,12146 +0,0 @@ -From 15db7a6341e0d01c12cd9a76c1d9f51a6bca56cf Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 11 Apr 2022 14:35:36 +0200 -Subject: [PATCH 137/137] regulator: add Qualcomm CPR regulators - -Allow building Qualcomm CPR regulators. - -Signed-off-by: Robert Marko ---- - drivers/regulator/Kconfig | 33 + - drivers/regulator/Makefile | 3 + - drivers/regulator/cpr3-npu-regulator.c | 695 +++ - drivers/regulator/cpr3-regulator.c | 5112 +++++++++++++++++++++++ - drivers/regulator/cpr3-regulator.h | 1211 ++++++ - drivers/regulator/cpr3-util.c | 2750 ++++++++++++ - drivers/regulator/cpr4-apss-regulator.c | 1819 ++++++++ - include/soc/qcom/socinfo.h | 463 ++ - 8 files changed, 12086 insertions(+) - create mode 100644 drivers/regulator/cpr3-npu-regulator.c - create mode 100644 drivers/regulator/cpr3-regulator.c - create mode 100644 drivers/regulator/cpr3-regulator.h - create mode 100644 drivers/regulator/cpr3-util.c - create mode 100644 drivers/regulator/cpr4-apss-regulator.c - create mode 100644 include/soc/qcom/socinfo.h - ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1423,5 +1423,38 @@ config REGULATOR_QCOM_LABIBB - boost regulator and IBB can be used as a negative boost regulator - for LCD display panel. - -+config REGULATOR_CPR3 -+ bool "QCOM CPR3 regulator core support" -+ help -+ This driver supports Core Power Reduction (CPR) version 3 controllers -+ which are used by some Qualcomm Technologies, Inc. SoCs to -+ manage important voltage regulators. CPR3 controllers are capable of -+ monitoring several ring oscillator sensing loops simultaneously. The -+ CPR3 controller informs software when the silicon conditions require -+ the supply voltage to be increased or decreased. On certain supply -+ rails, the CPR3 controller is able to propagate the voltage increase -+ or decrease requests all the way to the PMIC without software -+ involvement. -+ -+config REGULATOR_CPR3_NPU -+ bool "QCOM CPR3 regulator for NPU" -+ depends on OF && REGULATOR_CPR3 -+ help -+ This driver supports Qualcomm Technologies, Inc. NPU CPR3 -+ regulator Which will always operate in open loop. -+ -+config REGULATOR_CPR4_APSS -+ bool "QCOM CPR4 regulator for APSS" -+ depends on OF && REGULATOR_CPR3 -+ help -+ This driver supports Qualcomm Technologies, Inc. APSS application -+ processor specific features including memory array power mux (APM) -+ switching, one CPR4 thread which monitor the two APSS clusters that -+ are both powered by a shared supply, hardware closed-loop auto -+ voltage stepping, voltage adjustments based on online core count, -+ voltage adjustments based on temperature readings, and voltage -+ adjustments for performance boost mode. This driver reads both initial -+ voltage and CPR target quotient values out of hardware fuses. -+ - endif - ---- a/drivers/regulator/Makefile -+++ b/drivers/regulator/Makefile -@@ -105,6 +105,9 @@ obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qco - obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o - obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o - obj-$(CONFIG_REGULATOR_QCOM_USB_VBUS) += qcom_usb_vbus-regulator.o -+obj-$(CONFIG_REGULATOR_CPR3) += cpr3-regulator.o cpr3-util.o -+obj-$(CONFIG_REGULATOR_CPR3_NPU) += cpr3-npu-regulator.o -+obj-$(CONFIG_REGULATOR_CPR4_APSS) += cpr4-apss-regulator.o - obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o - obj-$(CONFIG_REGULATOR_PCA9450) += pca9450-regulator.o - obj-$(CONFIG_REGULATOR_PF8X00) += pf8x00-regulator.o ---- /dev/null -+++ b/drivers/regulator/cpr3-npu-regulator.c -@@ -0,0 +1,695 @@ -+/* -+ * Copyright (c) 2017, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cpr3-regulator.h" -+ -+#define IPQ807x_NPU_FUSE_CORNERS 2 -+#define IPQ817x_NPU_FUSE_CORNERS 1 -+#define IPQ807x_NPU_FUSE_STEP_VOLT 8000 -+#define IPQ807x_NPU_VOLTAGE_FUSE_SIZE 6 -+#define IPQ807x_NPU_CPR_CLOCK_RATE 19200000 -+ -+#define IPQ807x_NPU_CPR_TCSR_START 6 -+#define IPQ807x_NPU_CPR_TCSR_END 7 -+ -+#define NPU_TSENS 5 -+ -+u32 g_valid_npu_fuse_count = IPQ807x_NPU_FUSE_CORNERS; -+/** -+ * struct cpr3_ipq807x_npu_fuses - NPU specific fuse data for IPQ807x -+ * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value -+ * for each fuse corner (raw, not converted to a voltage) -+ * This struct holds the values for all of the fuses read from memory. -+ */ -+struct cpr3_ipq807x_npu_fuses { -+ u64 init_voltage[IPQ807x_NPU_FUSE_CORNERS]; -+}; -+ -+/* -+ * Constants which define the name of each fuse corner. -+ */ -+enum cpr3_ipq807x_npu_fuse_corner { -+ CPR3_IPQ807x_NPU_FUSE_CORNER_NOM = 0, -+ CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO = 1, -+}; -+ -+static const char * const cpr3_ipq807x_npu_fuse_corner_name[] = { -+ [CPR3_IPQ807x_NPU_FUSE_CORNER_NOM] = "NOM", -+ [CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO] = "TURBO", -+}; -+ -+/* -+ * IPQ807x NPU fuse parameter locations: -+ * -+ * Structs are organized with the following dimensions: -+ * Outer: 0 to 1 for fuse corners from lowest to highest corner -+ * Inner: large enough to hold the longest set of parameter segments which -+ * fully defines a fuse parameter, +1 (for NULL termination). -+ * Each segment corresponds to a contiguous group of bits from a -+ * single fuse row. These segments are concatentated together in -+ * order to form the full fuse parameter value. The segments for -+ * a given parameter may correspond to different fuse rows. -+ */ -+static struct cpr3_fuse_param -+ipq807x_npu_init_voltage_param[IPQ807x_NPU_FUSE_CORNERS][2] = { -+ {{73, 22, 27}, {} }, -+ {{73, 16, 21}, {} }, -+}; -+ -+/* -+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x -+ */ -+static int -+ipq807x_npu_fuse_ref_volt [IPQ807x_NPU_FUSE_CORNERS] = { -+ 912000, -+ 992000, -+}; -+ -+/* -+ * IPQ9574 (Few parameters are changed, remaining are same as IPQ807x) -+ */ -+#define IPQ9574_NPU_FUSE_CORNERS 2 -+#define IPQ9574_NPU_FUSE_STEP_VOLT 10000 -+#define IPQ9574_NPU_CPR_CLOCK_RATE 24000000 -+ -+/* -+ * fues parameters for IPQ9574 -+ */ -+static struct cpr3_fuse_param -+ipq9574_npu_init_voltage_param[IPQ9574_NPU_FUSE_CORNERS][2] = { -+ {{105, 12, 17}, {} }, -+ {{105, 6, 11}, {} }, -+}; -+ -+/* -+ * Open loop voltage fuse reference voltages in microvolts for IPQ9574 -+ */ -+static int -+ipq9574_npu_fuse_ref_volt [IPQ9574_NPU_FUSE_CORNERS] = { -+ 862500, -+ 987500, -+}; -+ -+struct cpr3_controller *g_ctrl; -+ -+void cpr3_npu_temp_notify(int sensor, int temp, int low_notif) -+{ -+ u32 prev_sensor_state; -+ -+ if (sensor != NPU_TSENS) -+ return; -+ -+ prev_sensor_state = g_ctrl->cur_sensor_state; -+ if (low_notif) -+ g_ctrl->cur_sensor_state |= BIT(sensor); -+ else -+ g_ctrl->cur_sensor_state &= ~BIT(sensor); -+ -+ if (!prev_sensor_state && g_ctrl->cur_sensor_state) -+ cpr3_handle_temp_open_loop_adjustment(g_ctrl, true); -+ else if (prev_sensor_state && !g_ctrl->cur_sensor_state) -+ cpr3_handle_temp_open_loop_adjustment(g_ctrl, false); -+} -+ -+/** -+ * cpr3_ipq807x_npu_read_fuse_data() - load NPU specific fuse parameter values -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function allocates a cpr3_ipq807x_npu_fuses struct, fills it with -+ * values read out of hardware fuses, and finally copies common fuse values -+ * into the CPR3 regulator struct. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_ipq807x_npu_read_fuse_data(struct cpr3_regulator *vreg) -+{ -+ void __iomem *base = vreg->thread->ctrl->fuse_base; -+ struct cpr3_ipq807x_npu_fuses *fuse; -+ int i, rc; -+ -+ fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); -+ if (!fuse) -+ return -ENOMEM; -+ -+ for (i = 0; i < g_valid_npu_fuse_count; i++) { -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr3_regulator_data->init_voltage_param[i], -+ &fuse->init_voltage[i]); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", -+ i, rc); -+ return rc; -+ } -+ } -+ -+ vreg->fuse_corner_count = g_valid_npu_fuse_count; -+ vreg->platform_fuses = fuse; -+ -+ return 0; -+} -+ -+/** -+ * cpr3_npu_parse_corner_data() - parse NPU corner data from device tree -+ * properties of the CPR3 regulator's device node -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_npu_parse_corner_data(struct cpr3_regulator *vreg) -+{ -+ int rc; -+ -+ rc = cpr3_parse_common_corner_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, "error reading corner data, rc=%d\n", rc); -+ return rc; -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_ipq807x_npu_calculate_open_loop_voltages() - calculate the open-loop -+ * voltage for each corner of a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * @temp_correction: Temperature based correction -+ * -+ * If open-loop voltage interpolation is allowed in device tree, then -+ * this function calculates the open-loop voltage for a given corner using -+ * linear interpolation. This interpolation is performed using the processor -+ * frequencies of the lower and higher Fmax corners along with their fused -+ * open-loop voltages. -+ * -+ * If open-loop voltage interpolation is not allowed, then this function uses -+ * the Fmax fused open-loop voltage for all of the corners associated with a -+ * given fuse corner. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_ipq807x_npu_calculate_open_loop_voltages( -+ struct cpr3_regulator *vreg, bool temp_correction) -+{ -+ struct cpr3_ipq807x_npu_fuses *fuse = vreg->platform_fuses; -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ int i, j, rc = 0; -+ u64 freq_low, volt_low, freq_high, volt_high; -+ int *fuse_volt; -+ int *fmax_corner; -+ -+ fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt), -+ GFP_KERNEL); -+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), -+ GFP_KERNEL); -+ if (!fuse_volt || !fmax_corner) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ if (ctrl->cpr_global_setting == CPR_DISABLED) -+ fuse_volt[i] = vreg->cpr3_regulator_data->fuse_ref_volt[i]; -+ else -+ fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( -+ vreg->cpr3_regulator_data->fuse_ref_volt[i], -+ vreg->cpr3_regulator_data->fuse_step_volt, -+ fuse->init_voltage[i], -+ IPQ807x_NPU_VOLTAGE_FUSE_SIZE); -+ -+ /* Log fused open-loop voltage values for debugging purposes. */ -+ cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", -+ cpr3_ipq807x_npu_fuse_corner_name[i], -+ fuse_volt[i]); -+ } -+ -+ rc = cpr3_determine_part_type(vreg, -+ fuse_volt[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]); -+ if (rc) { -+ cpr3_err(vreg, -+ "fused part type detection failed failed, rc=%d\n", rc); -+ goto done; -+ } -+ -+ rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt); -+ if (rc) { -+ cpr3_err(vreg, -+ "fused open-loop voltage adjustment failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ if (temp_correction) { -+ rc = cpr3_determine_temp_base_open_loop_correction(vreg, -+ fuse_volt); -+ if (rc) { -+ cpr3_err(vreg, -+ "temp open-loop voltage adj. failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ if (fuse_volt[i] < fuse_volt[i - 1]) { -+ cpr3_info(vreg, -+ "fuse corner %d voltage=%d uV < fuse corner %d \ -+ voltage=%d uV; overriding: fuse corner %d \ -+ voltage=%d\n", -+ i, fuse_volt[i], i - 1, fuse_volt[i - 1], -+ i, fuse_volt[i - 1]); -+ fuse_volt[i] = fuse_volt[i - 1]; -+ } -+ } -+ -+ /* Determine highest corner mapped to each fuse corner */ -+ j = vreg->fuse_corner_count - 1; -+ for (i = vreg->corner_count - 1; i >= 0; i--) { -+ if (vreg->corner[i].cpr_fuse_corner == j) { -+ fmax_corner[j] = i; -+ j--; -+ } -+ } -+ -+ if (j >= 0) { -+ cpr3_err(vreg, "invalid fuse corner mapping\n"); -+ rc = -EINVAL; -+ goto done; -+ } -+ -+ /* -+ * Interpolation is not possible for corners mapped to the lowest fuse -+ * corner so use the fuse corner value directly. -+ */ -+ for (i = 0; i <= fmax_corner[0]; i++) -+ vreg->corner[i].open_loop_volt = fuse_volt[0]; -+ -+ /* Interpolate voltages for the higher fuse corners. */ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; -+ volt_low = fuse_volt[i - 1]; -+ freq_high = vreg->corner[fmax_corner[i]].proc_freq; -+ volt_high = fuse_volt[i]; -+ -+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) -+ vreg->corner[j].open_loop_volt = cpr3_interpolate( -+ freq_low, volt_low, freq_high, volt_high, -+ vreg->corner[j].proc_freq); -+ } -+ -+done: -+ if (rc == 0) { -+ cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n"); -+ for (i = 0; i < vreg->corner_count; i++) -+ cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i, -+ vreg->corner[i].open_loop_volt); -+ -+ rc = cpr3_adjust_open_loop_voltages(vreg); -+ if (rc) -+ cpr3_err(vreg, -+ "open-loop voltage adjustment failed, rc=%d\n", -+ rc); -+ } -+ -+ kfree(fuse_volt); -+ kfree(fmax_corner); -+ return rc; -+} -+ -+/** -+ * cpr3_npu_print_settings() - print out NPU CPR configuration settings into -+ * the kernel log for debugging purposes -+ * @vreg: Pointer to the CPR3 regulator -+ */ -+static void cpr3_npu_print_settings(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_corner *corner; -+ int i; -+ -+ cpr3_debug(vreg, -+ "Corner: Frequency (Hz), Fuse Corner, Floor (uV), \ -+ Open-Loop (uV), Ceiling (uV)\n"); -+ for (i = 0; i < vreg->corner_count; i++) { -+ corner = &vreg->corner[i]; -+ cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n", -+ i, corner->proc_freq, corner->cpr_fuse_corner, -+ corner->floor_volt, corner->open_loop_volt, -+ corner->ceiling_volt); -+ } -+ -+ if (vreg->thread->ctrl->apm) -+ cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n", -+ vreg->thread->ctrl->apm_threshold_volt, -+ vreg->thread->ctrl->apm_adj_volt); -+} -+ -+/** -+ * cpr3_ipq807x_npu_calc_temp_based_ol_voltages() - Calculate the open loop -+ * voltages based on temperature based correction margins -+ * @vreg: Pointer to the CPR3 regulator -+ */ -+ -+static int -+cpr3_ipq807x_npu_calc_temp_based_ol_voltages(struct cpr3_regulator *vreg, -+ bool temp_correction) -+{ -+ int rc, i; -+ -+ rc = cpr3_ipq807x_npu_calculate_open_loop_voltages(vreg, -+ temp_correction); -+ if (rc) { -+ cpr3_err(vreg, -+ "unable to calculate open-loop voltages, rc=%d\n", rc); -+ return rc; -+ } -+ -+ rc = cpr3_limit_open_loop_voltages(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ cpr3_open_loop_voltage_as_ceiling(vreg); -+ -+ rc = cpr3_limit_floor_voltages(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc); -+ return rc; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ if (temp_correction) -+ vreg->corner[i].cold_temp_open_loop_volt = -+ vreg->corner[i].open_loop_volt; -+ else -+ vreg->corner[i].normal_temp_open_loop_volt = -+ vreg->corner[i].open_loop_volt; -+ } -+ -+ cpr3_npu_print_settings(vreg); -+ -+ return rc; -+} -+ -+/** -+ * cpr3_npu_init_thread() - perform steps necessary to initialize the -+ * configuration data for a CPR3 thread -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_npu_init_thread(struct cpr3_thread *thread) -+{ -+ int rc; -+ -+ rc = cpr3_parse_common_thread_data(thread); -+ if (rc) { -+ cpr3_err(thread->ctrl, -+ "thread %u CPR thread data from DT- failed, rc=%d\n", -+ thread->thread_id, rc); -+ return rc; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_npu_init_regulator() - perform all steps necessary to initialize the -+ * configuration data for a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_npu_init_regulator(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_ipq807x_npu_fuses *fuse; -+ int rc, cold_temp = 0; -+ bool can_adj_cold_temp = cpr3_can_adjust_cold_temp(vreg); -+ -+ rc = cpr3_ipq807x_npu_read_fuse_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); -+ return rc; -+ } -+ -+ fuse = vreg->platform_fuses; -+ -+ rc = cpr3_npu_parse_corner_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, -+ "Cannot read CPR corner data from DT, rc=%d\n", rc); -+ return rc; -+ } -+ -+ rc = cpr3_mem_acc_init(vreg); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(vreg, -+ "Cannot initialize mem-acc regulator settings, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (can_adj_cold_temp) { -+ rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, true); -+ if (rc) { -+ cpr3_err(vreg, -+ "unable to calculate open-loop voltages, rc=%d\n", rc); -+ return rc; -+ } -+ } -+ -+ rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, false); -+ if (rc) { -+ cpr3_err(vreg, -+ "unable to calculate open-loop voltages, rc=%d\n", rc); -+ return rc; -+ } -+ -+ if (can_adj_cold_temp) { -+ cpr3_info(vreg, -+ "Normal and Cold condition init done. Default to normal.\n"); -+ -+ rc = cpr3_get_cold_temp_threshold(vreg, &cold_temp); -+ if (rc) { -+ cpr3_err(vreg, -+ "Get cold temperature threshold failed, rc=%d\n", rc); -+ return rc; -+ } -+ register_low_temp_notif(NPU_TSENS, cold_temp, -+ cpr3_npu_temp_notify); -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_npu_init_controller() - perform NPU CPR3 controller specific -+ * initializations -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_npu_init_controller(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = cpr3_parse_open_loop_common_ctrl_data(ctrl); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ ctrl->ctrl_type = CPR_CTRL_TYPE_CPR3; -+ ctrl->supports_hw_closed_loop = false; -+ -+ return 0; -+} -+ -+static const struct cpr3_reg_data ipq807x_cpr_npu = { -+ .cpr_valid_fuse_count = IPQ807x_NPU_FUSE_CORNERS, -+ .init_voltage_param = ipq807x_npu_init_voltage_param, -+ .fuse_ref_volt = ipq807x_npu_fuse_ref_volt, -+ .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE, -+}; -+ -+static const struct cpr3_reg_data ipq817x_cpr_npu = { -+ .cpr_valid_fuse_count = IPQ817x_NPU_FUSE_CORNERS, -+ .init_voltage_param = ipq807x_npu_init_voltage_param, -+ .fuse_ref_volt = ipq807x_npu_fuse_ref_volt, -+ .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE, -+}; -+ -+static const struct cpr3_reg_data ipq9574_cpr_npu = { -+ .cpr_valid_fuse_count = IPQ9574_NPU_FUSE_CORNERS, -+ .init_voltage_param = ipq9574_npu_init_voltage_param, -+ .fuse_ref_volt = ipq9574_npu_fuse_ref_volt, -+ .fuse_step_volt = IPQ9574_NPU_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ9574_NPU_CPR_CLOCK_RATE, -+}; -+ -+static struct of_device_id cpr3_regulator_match_table[] = { -+ { -+ .compatible = "qcom,cpr3-ipq807x-npu-regulator", -+ .data = &ipq807x_cpr_npu -+ }, -+ { -+ .compatible = "qcom,cpr3-ipq817x-npu-regulator", -+ .data = &ipq817x_cpr_npu -+ }, -+ { -+ .compatible = "qcom,cpr3-ipq9574-npu-regulator", -+ .data = &ipq9574_cpr_npu -+ }, -+ {} -+}; -+ -+static int cpr3_npu_regulator_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct cpr3_controller *ctrl; -+ int i, rc; -+ const struct of_device_id *match; -+ struct cpr3_reg_data *cpr_data; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "Device tree node is missing\n"); -+ return -EINVAL; -+ } -+ -+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -+ if (!ctrl) -+ return -ENOMEM; -+ g_ctrl = ctrl; -+ -+ match = of_match_device(cpr3_regulator_match_table, &pdev->dev); -+ if (!match) -+ return -ENODEV; -+ -+ cpr_data = (struct cpr3_reg_data *)match->data; -+ g_valid_npu_fuse_count = cpr_data->cpr_valid_fuse_count; -+ dev_info(dev, "NPU CPR valid fuse count: %d\n", g_valid_npu_fuse_count); -+ ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate; -+ -+ ctrl->dev = dev; -+ /* Set to false later if anything precludes CPR operation. */ -+ ctrl->cpr_allowed_hw = true; -+ -+ rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name", -+ &ctrl->name); -+ if (rc) { -+ cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr3_map_fuse_base(ctrl, pdev); -+ if (rc) { -+ cpr3_err(ctrl, "could not map fuse base address\n"); -+ return rc; -+ } -+ -+ rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_NPU_CPR_TCSR_START, -+ IPQ807x_NPU_CPR_TCSR_END); -+ if (rc) { -+ cpr3_err(ctrl, "could not read CPR tcsr rsetting\n"); -+ return rc; -+ } -+ -+ rc = cpr3_allocate_threads(ctrl, 0, 0); -+ if (rc) { -+ cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (ctrl->thread_count != 1) { -+ cpr3_err(ctrl, "expected 1 thread but found %d\n", -+ ctrl->thread_count); -+ return -EINVAL; -+ } -+ -+ rc = cpr3_npu_init_controller(ctrl); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr3_npu_init_thread(&ctrl->thread[0]); -+ if (rc) { -+ cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ for (i = 0; i < ctrl->thread[0].vreg_count; i++) { -+ ctrl->thread[0].vreg[i].cpr3_regulator_data = cpr_data; -+ rc = cpr3_npu_init_regulator(&ctrl->thread[0].vreg[i]); -+ if (rc) { -+ cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ platform_set_drvdata(pdev, ctrl); -+ -+ return cpr3_open_loop_regulator_register(pdev, ctrl); -+} -+ -+static int cpr3_npu_regulator_remove(struct platform_device *pdev) -+{ -+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev); -+ -+ return cpr3_open_loop_regulator_unregister(ctrl); -+} -+ -+static struct platform_driver cpr3_npu_regulator_driver = { -+ .driver = { -+ .name = "qcom,cpr3-npu-regulator", -+ .of_match_table = cpr3_regulator_match_table, -+ .owner = THIS_MODULE, -+ }, -+ .probe = cpr3_npu_regulator_probe, -+ .remove = cpr3_npu_regulator_remove, -+}; -+ -+static int cpr3_regulator_init(void) -+{ -+ return platform_driver_register(&cpr3_npu_regulator_driver); -+} -+arch_initcall(cpr3_regulator_init); -+ -+static void cpr3_regulator_exit(void) -+{ -+ platform_driver_unregister(&cpr3_npu_regulator_driver); -+} -+module_exit(cpr3_regulator_exit); -+ -+MODULE_DESCRIPTION("QCOM CPR3 NPU regulator driver"); -+MODULE_LICENSE("Dual BSD/GPLv2"); -+MODULE_ALIAS("platform:npu-ipq807x"); ---- /dev/null -+++ b/drivers/regulator/cpr3-regulator.c -@@ -0,0 +1,5112 @@ -+/* -+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#define pr_fmt(fmt) "%s: " fmt, __func__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cpr3-regulator.h" -+ -+#define CPR3_REGULATOR_CORNER_INVALID (-1) -+#define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0) -+ -+/* CPR3 registers */ -+#define CPR3_REG_CPR_CTL 0x4 -+#define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0) -+#define CPR3_CPR_CTL_LOOP_ENABLE BIT(0) -+#define CPR3_CPR_CTL_LOOP_DISABLE 0 -+#define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1) -+#define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1 -+#define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6) -+#define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6 -+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0 -+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1 -+#define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2 -+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3 -+#define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9) -+#define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9 -+ -+#define CPR3_REG_CPR_STATUS 0x8 -+#define CPR3_CPR_STATUS_BUSY_MASK BIT(0) -+#define CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK BIT(1) -+ -+/* -+ * This register is not present on controllers that support HW closed-loop -+ * except CPR4 APSS controller. -+ */ -+#define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC -+ -+#define CPR3_REG_CPR_STEP_QUOT 0x14 -+#define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0) -+#define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0 -+#define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6) -+#define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6 -+ -+#define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro)) -+ -+#define CPR3_REG_SENSOR_BYPASS_WRITE(sensor) (0xE0 + 0x4 * ((sensor) / 32)) -+#define CPR3_REG_SENSOR_BYPASS_WRITE_BANK(bank) (0xE0 + 0x4 * (bank)) -+ -+#define CPR3_REG_SENSOR_MASK_WRITE(sensor) (0x120 + 0x4 * ((sensor) / 32)) -+#define CPR3_REG_SENSOR_MASK_WRITE_BANK(bank) (0x120 + 0x4 * (bank)) -+#define CPR3_REG_SENSOR_MASK_READ(sensor) (0x140 + 0x4 * ((sensor) / 32)) -+ -+#define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor)) -+ -+#define CPR3_REG_CONT_CMD 0x800 -+#define CPR3_CONT_CMD_ACK 0x1 -+#define CPR3_CONT_CMD_NACK 0x0 -+ -+#define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread)) -+#define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0) -+#define CPR3_THRESH_CONS_DOWN_SHIFT 0 -+#define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4) -+#define CPR3_THRESH_CONS_UP_SHIFT 4 -+#define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8) -+#define CPR3_THRESH_DOWN_THRESH_SHIFT 8 -+#define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13) -+#define CPR3_THRESH_UP_THRESH_SHIFT 13 -+ -+#define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread)) -+ -+#define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread)) -+#define CPR3_RESULT0_BUSY_MASK BIT(0) -+#define CPR3_RESULT0_STEP_DN_MASK BIT(1) -+#define CPR3_RESULT0_STEP_UP_MASK BIT(2) -+#define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3) -+#define CPR3_RESULT0_ERROR_STEPS_SHIFT 3 -+#define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8) -+#define CPR3_RESULT0_ERROR_SHIFT 8 -+#define CPR3_RESULT0_NEGATIVE_MASK BIT(20) -+ -+#define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread)) -+#define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0) -+#define CPR3_RESULT1_QUOT_MIN_SHIFT 0 -+#define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12) -+#define CPR3_RESULT1_QUOT_MAX_SHIFT 12 -+#define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24) -+#define CPR3_RESULT1_RO_MIN_SHIFT 24 -+#define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28) -+#define CPR3_RESULT1_RO_MAX_SHIFT 28 -+ -+#define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread)) -+#define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0) -+#define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0 -+#define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6) -+#define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6 -+#define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16) -+#define CPR3_RESULT2_SENSOR_MIN_SHIFT 16 -+#define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24) -+#define CPR3_RESULT2_SENSOR_MAX_SHIFT 24 -+ -+#define CPR3_REG_IRQ_EN 0x81C -+#define CPR3_REG_IRQ_CLEAR 0x820 -+#define CPR3_REG_IRQ_STATUS 0x824 -+#define CPR3_IRQ_UP BIT(3) -+#define CPR3_IRQ_MID BIT(2) -+#define CPR3_IRQ_DOWN BIT(1) -+ -+#define CPR3_REG_TARGET_QUOT(thread, ro) \ -+ (0x840 + 0x440 * (thread) + 0x4 * (ro)) -+ -+/* Registers found only on controllers that support HW closed-loop. */ -+#define CPR3_REG_PD_THROTTLE 0xE8 -+#define CPR3_PD_THROTTLE_DISABLE 0x0 -+ -+#define CPR3_REG_HW_CLOSED_LOOP 0x3000 -+#define CPR3_HW_CLOSED_LOOP_ENABLE 0x0 -+#define CPR3_HW_CLOSED_LOOP_DISABLE 0x1 -+ -+#define CPR3_REG_CPR_TIMER_MID_CONT 0x3004 -+#define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008 -+ -+#define CPR3_REG_LAST_MEASUREMENT 0x7F8 -+#define CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT 0 -+#define CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT 4 -+#define CPR3_LAST_MEASUREMENT_THREAD_DN(thread) \ -+ (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT) -+#define CPR3_LAST_MEASUREMENT_THREAD_UP(thread) \ -+ (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT) -+#define CPR3_LAST_MEASUREMENT_AGGR_DN BIT(8) -+#define CPR3_LAST_MEASUREMENT_AGGR_MID BIT(9) -+#define CPR3_LAST_MEASUREMENT_AGGR_UP BIT(10) -+#define CPR3_LAST_MEASUREMENT_VALID BIT(11) -+#define CPR3_LAST_MEASUREMENT_SAW_ERROR BIT(12) -+#define CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK GENMASK(23, 16) -+#define CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT 16 -+ -+/* CPR4 controller specific registers and bit definitions */ -+#define CPR4_REG_CPR_TIMER_CLAMP 0x10 -+#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27) -+ -+#define CPR4_REG_MISC 0x700 -+#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20) -+#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20 -+#define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24) -+#define CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT 24 -+#define CPR4_MISC_TEMP_SENSOR_ID_END_MASK GENMASK(31, 28) -+#define CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT 28 -+ -+#define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4 -+#define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0) -+#define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0 -+#define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5) -+#define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5 -+ -+#define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8 -+#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18) -+#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT 18 -+ -+#define CPR4_REG_MARGIN_TEMP_CORE(core) (0x7AC + 0x4 * (core)) -+#define CPR4_MARGIN_TEMP_CORE_ADJ_MASK GENMASK(7, 0) -+#define CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT 8 -+ -+#define CPR4_REG_MARGIN_TEMP_POINT0N1 0x7F0 -+#define CPR4_MARGIN_TEMP_POINT0_MASK GENMASK(11, 0) -+#define CPR4_MARGIN_TEMP_POINT0_SHIFT 0 -+#define CPR4_MARGIN_TEMP_POINT1_MASK GENMASK(23, 12) -+#define CPR4_MARGIN_TEMP_POINT1_SHIFT 12 -+#define CPR4_REG_MARGIN_TEMP_POINT2 0x7F4 -+#define CPR4_MARGIN_TEMP_POINT2_MASK GENMASK(11, 0) -+#define CPR4_MARGIN_TEMP_POINT2_SHIFT 0 -+ -+#define CPR4_REG_MARGIN_ADJ_CTL 0x7F8 -+#define CPR4_MARGIN_ADJ_CTL_BOOST_EN BIT(0) -+#define CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN BIT(1) -+#define CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN BIT(2) -+#define CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN BIT(3) -+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK BIT(4) -+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE BIT(4) -+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE 0 -+#define CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN BIT(7) -+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN BIT(8) -+#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK GENMASK(16, 12) -+#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT 12 -+#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK GENMASK(21, 19) -+#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT 19 -+#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK GENMASK(25, 22) -+#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT 22 -+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26) -+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26 -+ -+#define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread)) -+#define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31) -+#define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0) -+ -+/* -+ * The amount of time to wait for the CPR controller to become idle when -+ * performing an aging measurement. -+ */ -+#define CPR3_AGING_MEASUREMENT_TIMEOUT_NS 5000000 -+ -+/* -+ * The number of individual aging measurements to perform which are then -+ * averaged together in order to determine the final aging adjustment value. -+ */ -+#define CPR3_AGING_MEASUREMENT_ITERATIONS 16 -+ -+/* -+ * Aging measurements for the aged and unaged ring oscillators take place a few -+ * microseconds apart. If the vdd-supply voltage fluctuates between the two -+ * measurements, then the difference between them will be incorrect. The -+ * difference could end up too high or too low. This constant defines the -+ * number of lowest and highest measurements to ignore when averaging. -+ */ -+#define CPR3_AGING_MEASUREMENT_FILTER 3 -+ -+/* -+ * The number of times to attempt the full aging measurement sequence before -+ * declaring a measurement failure. -+ */ -+#define CPR3_AGING_RETRY_COUNT 5 -+ -+/* -+ * The maximum time to wait in microseconds for a CPR register write to -+ * complete. -+ */ -+#define CPR3_REGISTER_WRITE_DELAY_US 200 -+ -+static DEFINE_MUTEX(cpr3_controller_list_mutex); -+static LIST_HEAD(cpr3_controller_list); -+static struct dentry *cpr3_debugfs_base; -+ -+/** -+ * cpr3_read() - read four bytes from the memory address specified -+ * @ctrl: Pointer to the CPR3 controller -+ * @offset: Offset in bytes from the CPR3 controller's base address -+ * -+ * Return: memory address value -+ */ -+static inline u32 cpr3_read(struct cpr3_controller *ctrl, u32 offset) -+{ -+ if (!ctrl->cpr_enabled) { -+ cpr3_err(ctrl, "CPR register reads are not possible when CPR clocks are disabled\n"); -+ return 0; -+ } -+ -+ return readl_relaxed(ctrl->cpr_ctrl_base + offset); -+} -+ -+/** -+ * cpr3_write() - write four bytes to the memory address specified -+ * @ctrl: Pointer to the CPR3 controller -+ * @offset: Offset in bytes from the CPR3 controller's base address -+ * @value: Value to write to the memory address -+ * -+ * Return: none -+ */ -+static inline void cpr3_write(struct cpr3_controller *ctrl, u32 offset, -+ u32 value) -+{ -+ if (!ctrl->cpr_enabled) { -+ cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); -+ return; -+ } -+ -+ writel_relaxed(value, ctrl->cpr_ctrl_base + offset); -+} -+ -+/** -+ * cpr3_masked_write() - perform a read-modify-write sequence so that only -+ * masked bits are modified -+ * @ctrl: Pointer to the CPR3 controller -+ * @offset: Offset in bytes from the CPR3 controller's base address -+ * @mask: Mask identifying the bits that should be modified -+ * @value: Value to write to the memory address -+ * -+ * Return: none -+ */ -+static inline void cpr3_masked_write(struct cpr3_controller *ctrl, u32 offset, -+ u32 mask, u32 value) -+{ -+ u32 reg_val, orig_val; -+ -+ if (!ctrl->cpr_enabled) { -+ cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); -+ return; -+ } -+ -+ reg_val = orig_val = readl_relaxed(ctrl->cpr_ctrl_base + offset); -+ reg_val &= ~mask; -+ reg_val |= value & mask; -+ -+ if (reg_val != orig_val) -+ writel_relaxed(reg_val, ctrl->cpr_ctrl_base + offset); -+} -+ -+/** -+ * cpr3_ctrl_loop_enable() - enable the CPR sensing loop for a given controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: none -+ */ -+static inline void cpr3_ctrl_loop_enable(struct cpr3_controller *ctrl) -+{ -+ if (ctrl->cpr_enabled && !(ctrl->aggr_corner.sdelta -+ && ctrl->aggr_corner.sdelta->allow_boost)) -+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, -+ CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_ENABLE); -+} -+ -+/** -+ * cpr3_ctrl_loop_disable() - disable the CPR sensing loop for a given -+ * controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: none -+ */ -+static inline void cpr3_ctrl_loop_disable(struct cpr3_controller *ctrl) -+{ -+ if (ctrl->cpr_enabled) -+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, -+ CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_DISABLE); -+} -+ -+/** -+ * cpr3_clock_enable() - prepare and enable all clocks used by this CPR3 -+ * controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_clock_enable(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = clk_prepare_enable(ctrl->bus_clk); -+ if (rc) { -+ cpr3_err(ctrl, "failed to enable bus clock, rc=%d\n", rc); -+ return rc; -+ } -+ -+ rc = clk_prepare_enable(ctrl->iface_clk); -+ if (rc) { -+ cpr3_err(ctrl, "failed to enable interface clock, rc=%d\n", rc); -+ clk_disable_unprepare(ctrl->bus_clk); -+ return rc; -+ } -+ -+ rc = clk_prepare_enable(ctrl->core_clk); -+ if (rc) { -+ cpr3_err(ctrl, "failed to enable core clock, rc=%d\n", rc); -+ clk_disable_unprepare(ctrl->iface_clk); -+ clk_disable_unprepare(ctrl->bus_clk); -+ return rc; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_clock_disable() - disable and unprepare all clocks used by this CPR3 -+ * controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: none -+ */ -+static void cpr3_clock_disable(struct cpr3_controller *ctrl) -+{ -+ clk_disable_unprepare(ctrl->core_clk); -+ clk_disable_unprepare(ctrl->iface_clk); -+ clk_disable_unprepare(ctrl->bus_clk); -+} -+ -+/** -+ * cpr3_ctrl_clear_cpr4_config() - clear the CPR4 register configuration -+ * programmed for current aggregated corner of a given controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static inline int cpr3_ctrl_clear_cpr4_config(struct cpr3_controller *ctrl) -+{ -+ struct cpr4_sdelta *aggr_sdelta = ctrl->aggr_corner.sdelta; -+ bool cpr_enabled = ctrl->cpr_enabled; -+ int i, rc = 0; -+ -+ if (!aggr_sdelta || !(aggr_sdelta->allow_core_count_adj -+ || aggr_sdelta->allow_temp_adj || aggr_sdelta->allow_boost)) -+ /* cpr4 features are not enabled */ -+ return 0; -+ -+ /* Ensure that CPR clocks are enabled before writing to registers. */ -+ if (!cpr_enabled) { -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); -+ return rc; -+ } -+ ctrl->cpr_enabled = true; -+ } -+ -+ /* -+ * Clear feature enable configuration made for current -+ * aggregated corner. -+ */ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK -+ | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_BOOST_EN -+ | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, 0); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MISC, -+ CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, -+ 0 << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); -+ -+ for (i = 0; i <= aggr_sdelta->max_core_count; i++) { -+ /* Clear voltage margin adjustments programmed in TEMP_COREi */ -+ cpr3_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE(i), 0); -+ } -+ -+ /* Turn off CPR clocks if they were off before this function call. */ -+ if (!cpr_enabled) { -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_closed_loop_enable() - enable logical CPR closed-loop operation -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_closed_loop_enable(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ if (!ctrl->cpr_allowed_hw || !ctrl->cpr_allowed_sw) { -+ cpr3_err(ctrl, "cannot enable closed-loop CPR operation because it is disallowed\n"); -+ return -EPERM; -+ } else if (ctrl->cpr_enabled) { -+ /* Already enabled */ -+ return 0; -+ } else if (ctrl->cpr_suspended) { -+ /* -+ * CPR must remain disabled as the system is entering suspend. -+ */ -+ return 0; -+ } -+ -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "unable to enable CPR clocks, rc=%d\n", rc); -+ return rc; -+ } -+ -+ ctrl->cpr_enabled = true; -+ cpr3_debug(ctrl, "CPR closed-loop operation enabled\n"); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_closed_loop_disable() - disable logical CPR closed-loop operation -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static inline int cpr3_closed_loop_disable(struct cpr3_controller *ctrl) -+{ -+ if (!ctrl->cpr_enabled) { -+ /* Already disabled */ -+ return 0; -+ } -+ -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ cpr3_debug(ctrl, "CPR closed-loop operation disabled\n"); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_get_gcnt() - returns the GCNT register value corresponding -+ * to the clock rate and sensor time of the CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: GCNT value -+ */ -+static u32 cpr3_regulator_get_gcnt(struct cpr3_controller *ctrl) -+{ -+ u64 temp; -+ unsigned int remainder; -+ u32 gcnt; -+ -+ temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->sensor_time; -+ remainder = do_div(temp, 1000000000); -+ if (remainder) -+ temp++; -+ /* -+ * GCNT == 0 corresponds to a single ref clock measurement interval so -+ * offset GCNT values by 1. -+ */ -+ gcnt = temp - 1; -+ -+ return gcnt; -+} -+ -+/** -+ * cpr3_regulator_init_thread() - performs hardware initialization of CPR -+ * thread registers -+ * @thread: Pointer to the CPR3 thread -+ * -+ * CPR interface/bus clocks must be enabled before calling this function. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_init_thread(struct cpr3_thread *thread) -+{ -+ u32 reg; -+ -+ reg = (thread->consecutive_up << CPR3_THRESH_CONS_UP_SHIFT) -+ & CPR3_THRESH_CONS_UP_MASK; -+ reg |= (thread->consecutive_down << CPR3_THRESH_CONS_DOWN_SHIFT) -+ & CPR3_THRESH_CONS_DOWN_MASK; -+ reg |= (thread->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT) -+ & CPR3_THRESH_UP_THRESH_MASK; -+ reg |= (thread->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT) -+ & CPR3_THRESH_DOWN_THRESH_MASK; -+ -+ cpr3_write(thread->ctrl, CPR3_REG_THRESH(thread->thread_id), reg); -+ -+ /* -+ * Mask all RO's initially so that unused thread doesn't contribute -+ * to closed-loop voltage. -+ */ -+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), -+ CPR3_RO_MASK); -+ -+ return 0; -+} -+ -+/** -+ * cpr4_regulator_init_temp_points() - performs hardware initialization of CPR4 -+ * registers to track tsen temperature data and also specify the -+ * temperature band range values to apply different voltage margins -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * CPR interface/bus clocks must be enabled before calling this function. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_regulator_init_temp_points(struct cpr3_controller *ctrl) -+{ -+ if (!ctrl->allow_temp_adj) -+ return 0; -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MISC, -+ CPR4_MISC_TEMP_SENSOR_ID_START_MASK, -+ ctrl->temp_sensor_id_start -+ << CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MISC, -+ CPR4_MISC_TEMP_SENSOR_ID_END_MASK, -+ ctrl->temp_sensor_id_end -+ << CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT2, -+ CPR4_MARGIN_TEMP_POINT2_MASK, -+ (ctrl->temp_band_count == 4 ? ctrl->temp_points[2] : 0x7FF) -+ << CPR4_MARGIN_TEMP_POINT2_SHIFT); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, -+ CPR4_MARGIN_TEMP_POINT1_MASK, -+ (ctrl->temp_band_count >= 3 ? ctrl->temp_points[1] : 0x7FF) -+ << CPR4_MARGIN_TEMP_POINT1_SHIFT); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, -+ CPR4_MARGIN_TEMP_POINT0_MASK, -+ (ctrl->temp_band_count >= 2 ? ctrl->temp_points[0] : 0x7FF) -+ << CPR4_MARGIN_TEMP_POINT0_SHIFT); -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_init_cpr4() - performs hardware initialization at the -+ * controller and thread level required for CPR4 operation. -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * CPR interface/bus clocks must be enabled before calling this function. -+ * This function allocates sdelta structures and sdelta tables for aggregated -+ * corners of the controller and its threads. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_init_cpr4(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_thread *thread; -+ struct cpr3_regulator *vreg; -+ struct cpr4_sdelta *sdelta; -+ int i, j, ctrl_max_core_count, thread_max_core_count, rc = 0; -+ bool ctrl_valid_sdelta, thread_valid_sdelta; -+ u32 pmic_step_size = 1; -+ int thread_id = 0; -+ u64 temp; -+ -+ if (ctrl->supports_hw_closed_loop) { -+ if (ctrl->saw_use_unit_mV) -+ pmic_step_size = ctrl->step_volt / 1000; -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK, -+ (pmic_step_size -+ << CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT)); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, -+ CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK, -+ (ctrl->down_error_step_limit -+ << CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT)); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, -+ CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK, -+ (ctrl->up_error_step_limit -+ << CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT)); -+ -+ /* -+ * Enable thread aggregation regardless of which threads are -+ * enabled or disabled. -+ */ -+ cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP, -+ CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN, -+ CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN); -+ -+ switch (ctrl->thread_count) { -+ case 0: -+ /* Disable both threads */ -+ cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(0), -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(1), -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); -+ break; -+ case 1: -+ /* Disable unused thread */ -+ thread_id = ctrl->thread[0].thread_id ? 0 : 1; -+ cpr3_masked_write(ctrl, -+ CPR4_REG_CPR_MASK_THREAD(thread_id), -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, -+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD -+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); -+ break; -+ } -+ } -+ -+ if (!ctrl->allow_core_count_adj && !ctrl->allow_temp_adj -+ && !ctrl->allow_boost) { -+ /* -+ * Skip below configuration as none of the features -+ * are enabled. -+ */ -+ return rc; -+ } -+ -+ if (ctrl->supports_hw_closed_loop) -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN, -+ CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK, -+ ctrl->step_quot_fixed -+ << CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN, -+ (ctrl->use_dynamic_step_quot -+ ? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0)); -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK, -+ ctrl->initial_temp_band -+ << CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT); -+ -+ rc = cpr4_regulator_init_temp_points(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "initialize temp points failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ if (ctrl->voltage_settling_time) { -+ /* -+ * Configure the settling timer used to account for -+ * one VDD supply step. -+ */ -+ temp = (u64)ctrl->cpr_clock_rate -+ * (u64)ctrl->voltage_settling_time; -+ do_div(temp, 1000000000); -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS, -+ CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK, -+ temp -+ << CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT); -+ } -+ -+ /* -+ * Allocate memory for cpr4_sdelta structure and sdelta table for -+ * controller aggregated corner by finding the maximum core count -+ * used by any cpr3 regulators. -+ */ -+ ctrl_max_core_count = 1; -+ ctrl_valid_sdelta = false; -+ for (i = 0; i < ctrl->thread_count; i++) { -+ thread = &ctrl->thread[i]; -+ -+ /* -+ * Allocate memory for cpr4_sdelta structure and sdelta table -+ * for thread aggregated corner by finding the maximum core -+ * count used by any cpr3 regulators of the thread. -+ */ -+ thread_max_core_count = 1; -+ thread_valid_sdelta = false; -+ for (j = 0; j < thread->vreg_count; j++) { -+ vreg = &thread->vreg[j]; -+ thread_max_core_count = max(thread_max_core_count, -+ vreg->max_core_count); -+ thread_valid_sdelta |= (vreg->allow_core_count_adj -+ | vreg->allow_temp_adj -+ | vreg->allow_boost); -+ } -+ if (thread_valid_sdelta) { -+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), -+ GFP_KERNEL); -+ if (!sdelta) -+ return -ENOMEM; -+ -+ sdelta->table = devm_kcalloc(ctrl->dev, -+ thread_max_core_count -+ * ctrl->temp_band_count, -+ sizeof(*sdelta->table), -+ GFP_KERNEL); -+ if (!sdelta->table) -+ return -ENOMEM; -+ -+ sdelta->boost_table = devm_kcalloc(ctrl->dev, -+ ctrl->temp_band_count, -+ sizeof(*sdelta->boost_table), -+ GFP_KERNEL); -+ if (!sdelta->boost_table) -+ return -ENOMEM; -+ -+ thread->aggr_corner.sdelta = sdelta; -+ } -+ -+ ctrl_valid_sdelta |= thread_valid_sdelta; -+ ctrl_max_core_count = max(ctrl_max_core_count, -+ thread_max_core_count); -+ } -+ -+ if (ctrl_valid_sdelta) { -+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), GFP_KERNEL); -+ if (!sdelta) -+ return -ENOMEM; -+ -+ sdelta->table = devm_kcalloc(ctrl->dev, ctrl_max_core_count -+ * ctrl->temp_band_count, -+ sizeof(*sdelta->table), GFP_KERNEL); -+ if (!sdelta->table) -+ return -ENOMEM; -+ -+ sdelta->boost_table = devm_kcalloc(ctrl->dev, -+ ctrl->temp_band_count, -+ sizeof(*sdelta->boost_table), -+ GFP_KERNEL); -+ if (!sdelta->boost_table) -+ return -ENOMEM; -+ -+ ctrl->aggr_corner.sdelta = sdelta; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_write_temp_core_margin() - programs hardware SDELTA registers with -+ * the voltage margin adjustments that need to be applied for -+ * different online core-count and temperature bands. -+ * @ctrl: Pointer to the CPR3 controller -+ * @addr: SDELTA register address -+ * @temp_core_adj: Array of voltage margin values for different temperature -+ * bands. -+ * -+ * CPR interface/bus clocks must be enabled before calling this function. -+ * -+ * Return: none -+ */ -+static void cpr3_write_temp_core_margin(struct cpr3_controller *ctrl, -+ int addr, int *temp_core_adj) -+{ -+ int i, margin_steps; -+ u32 reg = 0; -+ -+ for (i = 0; i < ctrl->temp_band_count; i++) { -+ margin_steps = max(min(temp_core_adj[i], 127), -128); -+ reg |= (margin_steps & CPR4_MARGIN_TEMP_CORE_ADJ_MASK) << -+ (i * CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT); -+ } -+ -+ cpr3_write(ctrl, addr, reg); -+ cpr3_debug(ctrl, "sdelta offset=0x%08x, val=0x%08x\n", addr, reg); -+} -+ -+/** -+ * cpr3_controller_program_sdelta() - programs hardware SDELTA registers with -+ * the voltage margin adjustments that need to be applied at -+ * different online core-count and temperature bands. Also, -+ * programs hardware register configuration for per-online-core -+ * and per-temperature based adjustments. -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * CPR interface/bus clocks must be enabled before calling this function. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_controller_program_sdelta(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_corner *corner = &ctrl->aggr_corner; -+ struct cpr4_sdelta *sdelta = corner->sdelta; -+ int i, index, max_core_count, rc = 0; -+ bool cpr_enabled = ctrl->cpr_enabled; -+ -+ if (!sdelta) -+ /* cpr4_sdelta not defined for current aggregated corner */ -+ return 0; -+ -+ if (ctrl->supports_hw_closed_loop && ctrl->cpr_enabled) { -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, -+ (ctrl->use_hw_closed_loop && !sdelta->allow_boost) -+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0); -+ } -+ -+ if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj -+ && !sdelta->allow_boost) { -+ /* -+ * Per-online-core, per-temperature and voltage boost -+ * adjustments are disabled for this aggregation corner. -+ */ -+ return 0; -+ } -+ -+ /* Ensure that CPR clocks are enabled before writing to registers. */ -+ if (!cpr_enabled) { -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); -+ return rc; -+ } -+ ctrl->cpr_enabled = true; -+ } -+ -+ max_core_count = sdelta->max_core_count; -+ -+ if (sdelta->allow_core_count_adj || sdelta->allow_temp_adj) { -+ if (sdelta->allow_core_count_adj) { -+ /* Program TEMP_CORE0 to same margins as TEMP_CORE1 */ -+ cpr3_write_temp_core_margin(ctrl, -+ CPR4_REG_MARGIN_TEMP_CORE(0), -+ &sdelta->table[0]); -+ } -+ -+ for (i = 0; i < max_core_count; i++) { -+ index = i * sdelta->temp_band_count; -+ /* -+ * Program TEMP_COREi with voltage margin adjustments -+ * that need to be applied when the number of cores -+ * becomes i. -+ */ -+ cpr3_write_temp_core_margin(ctrl, -+ CPR4_REG_MARGIN_TEMP_CORE( -+ sdelta->allow_core_count_adj -+ ? i + 1 : max_core_count), -+ &sdelta->table[index]); -+ } -+ } -+ -+ if (sdelta->allow_boost) { -+ /* Program only boost_num_cores row of SDELTA */ -+ cpr3_write_temp_core_margin(ctrl, -+ CPR4_REG_MARGIN_TEMP_CORE(sdelta->boost_num_cores), -+ &sdelta->boost_table[0]); -+ } -+ -+ if (!sdelta->allow_core_count_adj && !sdelta->allow_boost) { -+ cpr3_masked_write(ctrl, CPR4_REG_MISC, -+ CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, -+ max_core_count -+ << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); -+ } -+ -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK -+ | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN -+ | CPR4_MARGIN_ADJ_CTL_BOOST_EN, -+ max_core_count << CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT -+ | ((sdelta->allow_core_count_adj || sdelta->allow_boost) -+ ? CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN : 0) -+ | ((sdelta->allow_temp_adj && ctrl->supports_hw_closed_loop) -+ ? CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN : 0) -+ | (((ctrl->use_hw_closed_loop && !sdelta->allow_boost) -+ || !ctrl->supports_hw_closed_loop) -+ ? CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN : 0) -+ | (sdelta->allow_boost -+ ? CPR4_MARGIN_ADJ_CTL_BOOST_EN : 0)); -+ -+ /* -+ * Ensure that all previous CPR register writes have completed before -+ * continuing. -+ */ -+ mb(); -+ -+ /* Turn off CPR clocks if they were off before this function call. */ -+ if (!cpr_enabled) { -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_init_ctrl() - performs hardware initialization of CPR -+ * controller registers -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_init_ctrl(struct cpr3_controller *ctrl) -+{ -+ int i, j, k, m, rc; -+ u32 ro_used = 0; -+ u32 gcnt, cont_dly, up_down_dly, val; -+ u64 temp; -+ char *mode; -+ -+ if (ctrl->core_clk) { -+ rc = clk_set_rate(ctrl->core_clk, ctrl->cpr_clock_rate); -+ if (rc) { -+ cpr3_err(ctrl, "clk_set_rate(core_clk, %u) failed, rc=%d\n", -+ ctrl->cpr_clock_rate, rc); -+ return rc; -+ } -+ } -+ -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); -+ return rc; -+ } -+ ctrl->cpr_enabled = true; -+ -+ /* Find all RO's used by any corner of any regulator. */ -+ for (i = 0; i < ctrl->thread_count; i++) -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) -+ for (k = 0; k < ctrl->thread[i].vreg[j].corner_count; -+ k++) -+ for (m = 0; m < CPR3_RO_COUNT; m++) -+ if (ctrl->thread[i].vreg[j].corner[k]. -+ target_quot[m]) -+ ro_used |= BIT(m); -+ -+ /* Configure the GCNT of the RO's that will be used */ -+ gcnt = cpr3_regulator_get_gcnt(ctrl); -+ for (i = 0; i < CPR3_RO_COUNT; i++) -+ if (ro_used & BIT(i)) -+ cpr3_write(ctrl, CPR3_REG_GCNT(i), gcnt); -+ -+ /* Configure the loop delay time */ -+ temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->loop_time; -+ do_div(temp, 1000000000); -+ cont_dly = temp; -+ if (ctrl->supports_hw_closed_loop -+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly); -+ else -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, cont_dly); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ temp = (u64)ctrl->cpr_clock_rate * -+ (u64)ctrl->up_down_delay_time; -+ do_div(temp, 1000000000); -+ up_down_dly = temp; -+ if (ctrl->supports_hw_closed_loop) -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, -+ up_down_dly); -+ cpr3_debug(ctrl, "up_down_dly=%u, up_down_delay_time=%u ns\n", -+ up_down_dly, ctrl->up_down_delay_time); -+ } -+ -+ cpr3_debug(ctrl, "cpr_clock_rate=%u HZ, sensor_time=%u ns, loop_time=%u ns, gcnt=%u, cont_dly=%u\n", -+ ctrl->cpr_clock_rate, ctrl->sensor_time, ctrl->loop_time, -+ gcnt, cont_dly); -+ -+ /* Configure CPR sensor operation */ -+ val = (ctrl->idle_clocks << CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT) -+ & CPR3_CPR_CTL_IDLE_CLOCKS_MASK; -+ val |= (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) -+ & CPR3_CPR_CTL_COUNT_MODE_MASK; -+ val |= (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT) -+ & CPR3_CPR_CTL_COUNT_REPEAT_MASK; -+ cpr3_write(ctrl, CPR3_REG_CPR_CTL, val); -+ -+ cpr3_debug(ctrl, "idle_clocks=%u, count_mode=%u, count_repeat=%u; CPR_CTL=0x%08X\n", -+ ctrl->idle_clocks, ctrl->count_mode, ctrl->count_repeat, val); -+ -+ /* Configure CPR default step quotients */ -+ val = (ctrl->step_quot_init_min << CPR3_CPR_STEP_QUOT_MIN_SHIFT) -+ & CPR3_CPR_STEP_QUOT_MIN_MASK; -+ val |= (ctrl->step_quot_init_max << CPR3_CPR_STEP_QUOT_MAX_SHIFT) -+ & CPR3_CPR_STEP_QUOT_MAX_MASK; -+ cpr3_write(ctrl, CPR3_REG_CPR_STEP_QUOT, val); -+ -+ cpr3_debug(ctrl, "step_quot_min=%u, step_quot_max=%u; STEP_QUOT=0x%08X\n", -+ ctrl->step_quot_init_min, ctrl->step_quot_init_max, val); -+ -+ /* Configure the CPR sensor ownership */ -+ for (i = 0; i < ctrl->sensor_count; i++) -+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(i), -+ ctrl->sensor_owner[i]); -+ -+ /* Configure per-thread registers */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ rc = cpr3_regulator_init_thread(&ctrl->thread[i]); -+ if (rc) { -+ cpr3_err(ctrl, "CPR thread register initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ if (ctrl->supports_hw_closed_loop) { -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, -+ ctrl->use_hw_closed_loop -+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE -+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); -+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, -+ ctrl->use_hw_closed_loop -+ ? CPR3_HW_CLOSED_LOOP_ENABLE -+ : CPR3_HW_CLOSED_LOOP_DISABLE); -+ -+ cpr3_debug(ctrl, "PD_THROTTLE=0x%08X\n", -+ ctrl->proc_clock_throttle); -+ } -+ -+ if ((ctrl->use_hw_closed_loop || -+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) && -+ ctrl->vdd_limit_regulator) { -+ rc = regulator_enable(ctrl->vdd_limit_regulator); -+ if (rc) { -+ cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ } -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_regulator_init_cpr4(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "CPR4-specific controller initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ /* Ensure that all register writes complete before disabling clocks. */ -+ wmb(); -+ -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ -+ if (!ctrl->cpr_allowed_sw || !ctrl->cpr_allowed_hw) -+ mode = "open-loop"; -+ else if (ctrl->supports_hw_closed_loop) -+ mode = ctrl->use_hw_closed_loop -+ ? "HW closed-loop" : "SW closed-loop"; -+ else -+ mode = "closed-loop"; -+ -+ cpr3_info(ctrl, "Default CPR mode = %s", mode); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_set_target_quot() - configure the target quotient for each -+ * RO of the CPR3 thread and set the RO mask -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_set_target_quot(struct cpr3_thread *thread) -+{ -+ u32 new_quot, last_quot; -+ int i; -+ -+ if (thread->aggr_corner.ro_mask == CPR3_RO_MASK -+ && thread->last_closed_loop_aggr_corner.ro_mask == CPR3_RO_MASK) { -+ /* Avoid writing target quotients since all RO's are masked. */ -+ return; -+ } else if (thread->aggr_corner.ro_mask == CPR3_RO_MASK) { -+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), -+ CPR3_RO_MASK); -+ thread->last_closed_loop_aggr_corner.ro_mask = CPR3_RO_MASK; -+ /* -+ * Only the RO_MASK register needs to be written since all -+ * RO's are masked. -+ */ -+ return; -+ } else if (thread->aggr_corner.ro_mask -+ != thread->last_closed_loop_aggr_corner.ro_mask) { -+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), -+ thread->aggr_corner.ro_mask); -+ } -+ -+ for (i = 0; i < CPR3_RO_COUNT; i++) { -+ new_quot = thread->aggr_corner.target_quot[i]; -+ last_quot = thread->last_closed_loop_aggr_corner.target_quot[i]; -+ if (new_quot != last_quot) -+ cpr3_write(thread->ctrl, -+ CPR3_REG_TARGET_QUOT(thread->thread_id, i), -+ new_quot); -+ } -+ -+ thread->last_closed_loop_aggr_corner = thread->aggr_corner; -+ -+ return; -+} -+ -+/** -+ * cpr3_update_vreg_closed_loop_volt() - update the last known settled -+ * closed loop voltage for a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * @vdd_volt: Last known settled voltage in microvolts for the -+ * VDD supply -+ * @reg_last_measurement: Value read from the LAST_MEASUREMENT register -+ * -+ * Return: none -+ */ -+static void cpr3_update_vreg_closed_loop_volt(struct cpr3_regulator *vreg, -+ int vdd_volt, u32 reg_last_measurement) -+{ -+ bool step_dn, step_up, aggr_step_up, aggr_step_dn, aggr_step_mid; -+ bool valid, pd_valid, saw_error; -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct cpr3_corner *corner; -+ u32 id; -+ -+ if (vreg->last_closed_loop_corner == CPR3_REGULATOR_CORNER_INVALID) -+ return; -+ else -+ corner = &vreg->corner[vreg->last_closed_loop_corner]; -+ -+ if (vreg->thread->last_closed_loop_aggr_corner.ro_mask -+ == CPR3_RO_MASK || !vreg->aggregated) { -+ return; -+ } else if (!ctrl->cpr_enabled || !ctrl->last_corner_was_closed_loop) { -+ return; -+ } else if (ctrl->thread_count == 1 -+ && vdd_volt >= corner->floor_volt -+ && vdd_volt <= corner->ceiling_volt) { -+ corner->last_volt = vdd_volt; -+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", -+ vreg->last_closed_loop_corner, corner->last_volt, -+ vreg->last_closed_loop_corner, -+ corner->ceiling_volt, -+ vreg->last_closed_loop_corner, -+ corner->floor_volt); -+ return; -+ } else if (!ctrl->supports_hw_closed_loop) { -+ return; -+ } else if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPR3) { -+ corner->last_volt = vdd_volt; -+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", -+ vreg->last_closed_loop_corner, corner->last_volt, -+ vreg->last_closed_loop_corner, -+ corner->ceiling_volt, -+ vreg->last_closed_loop_corner, -+ corner->floor_volt); -+ return; -+ } -+ -+ /* CPR clocks are on and HW closed loop is supported */ -+ valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); -+ if (!valid) { -+ cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X valid bit not set\n", -+ reg_last_measurement); -+ return; -+ } -+ -+ id = vreg->thread->thread_id; -+ -+ step_dn -+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_DN(id)); -+ step_up -+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_UP(id)); -+ aggr_step_dn = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_DN); -+ aggr_step_mid -+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_MID); -+ aggr_step_up = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_UP); -+ saw_error = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_SAW_ERROR); -+ pd_valid -+ = !((((reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) -+ >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT) -+ & vreg->pd_bypass_mask) == vreg->pd_bypass_mask); -+ -+ if (!pd_valid) { -+ cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X, all power domains bypassed\n", -+ reg_last_measurement); -+ return; -+ } else if (step_dn && step_up) { -+ cpr3_err(vreg, "both up and down status bits set, CPR_LAST_VALID_MEASUREMENT=0x%X\n", -+ reg_last_measurement); -+ return; -+ } else if (aggr_step_dn && step_dn && vdd_volt < corner->last_volt -+ && vdd_volt >= corner->floor_volt) { -+ corner->last_volt = vdd_volt; -+ } else if (aggr_step_up && step_up && vdd_volt > corner->last_volt -+ && vdd_volt <= corner->ceiling_volt) { -+ corner->last_volt = vdd_volt; -+ } else if (aggr_step_mid -+ && vdd_volt >= corner->floor_volt -+ && vdd_volt <= corner->ceiling_volt) { -+ corner->last_volt = vdd_volt; -+ } else if (saw_error && (vdd_volt == corner->ceiling_volt -+ || vdd_volt == corner->floor_volt)) { -+ corner->last_volt = vdd_volt; -+ } else { -+ cpr3_debug(vreg, "last_volt not updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, vdd_volt=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", -+ vreg->last_closed_loop_corner, corner->last_volt, -+ vreg->last_closed_loop_corner, -+ corner->ceiling_volt, -+ vreg->last_closed_loop_corner, corner->floor_volt, -+ vdd_volt, reg_last_measurement); -+ return; -+ } -+ -+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", -+ vreg->last_closed_loop_corner, corner->last_volt, -+ vreg->last_closed_loop_corner, corner->ceiling_volt, -+ vreg->last_closed_loop_corner, corner->floor_volt, -+ reg_last_measurement); -+} -+ -+/** -+ * cpr3_regulator_mem_acc_bhs_used() - determines if mem-acc regulators powered -+ * through a BHS are associated with the CPR3 controller or any of -+ * the CPR3 regulators it controls. -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * This function determines if the CPR3 controller or any of its CPR3 regulators -+ * need to manage mem-acc regulators that are currently powered through a BHS -+ * and whose corner selection is based upon a particular voltage threshold. -+ * -+ * Return: true or false -+ */ -+static bool cpr3_regulator_mem_acc_bhs_used(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_regulator *vreg; -+ int i, j; -+ -+ if (!ctrl->mem_acc_threshold_volt) -+ return false; -+ -+ if (ctrl->mem_acc_regulator) -+ return true; -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ -+ if (vreg->mem_acc_regulator) -+ return true; -+ } -+ } -+ -+ return false; -+} -+ -+/** -+ * cpr3_regulator_config_bhs_mem_acc() - configure the mem-acc regulator -+ * settings for hardware blocks currently powered through the BHS. -+ * @ctrl: Pointer to the CPR3 controller -+ * @new_volt: New voltage in microvolts that VDD supply needs to -+ * end up at -+ * @last_volt: Pointer to the last known voltage in microvolts for the -+ * VDD supply -+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max -+ * corner aggregated from all CPR3 threads managed by the -+ * CPR3 controller -+ * -+ * This function programs the mem-acc regulator corners for CPR3 regulators -+ * whose LDO regulators are in bypassed state. The function also handles -+ * CPR3 controllers which utilize mem-acc regulators that operate independently -+ * from the LDO hardware and that must be programmed when the VDD supply -+ * crosses a particular voltage threshold. -+ * -+ * Return: 0 on success, errno on failure. If the VDD supply voltage is -+ * modified, last_volt is updated to reflect the new voltage setpoint. -+ */ -+static int cpr3_regulator_config_bhs_mem_acc(struct cpr3_controller *ctrl, -+ int new_volt, int *last_volt, -+ struct cpr3_corner *aggr_corner) -+{ -+ struct cpr3_regulator *vreg; -+ int i, j, rc, mem_acc_corn, safe_volt; -+ int mem_acc_volt = ctrl->mem_acc_threshold_volt; -+ int ref_volt; -+ -+ if (!cpr3_regulator_mem_acc_bhs_used(ctrl)) -+ return 0; -+ -+ ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : -+ new_volt; -+ -+ if (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || -+ (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt))) { -+ if (ref_volt < *last_volt) -+ safe_volt = max(mem_acc_volt, aggr_corner->last_volt); -+ else -+ safe_volt = max(mem_acc_volt, *last_volt); -+ -+ rc = regulator_set_voltage(ctrl->vdd_regulator, safe_volt, -+ new_volt < *last_volt ? -+ ctrl->aggr_corner.ceiling_volt : -+ new_volt); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", -+ safe_volt, rc); -+ return rc; -+ } -+ -+ *last_volt = safe_volt; -+ -+ mem_acc_corn = ref_volt < mem_acc_volt ? -+ ctrl->mem_acc_corner_map[CPR3_MEM_ACC_LOW_CORNER] : -+ ctrl->mem_acc_corner_map[CPR3_MEM_ACC_HIGH_CORNER]; -+ -+ if (ctrl->mem_acc_regulator) { -+ rc = regulator_set_voltage(ctrl->mem_acc_regulator, -+ mem_acc_corn, mem_acc_corn); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", -+ mem_acc_corn, rc); -+ return rc; -+ } -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ -+ if (!vreg->mem_acc_regulator) -+ continue; -+ -+ rc = regulator_set_voltage( -+ vreg->mem_acc_regulator, mem_acc_corn, -+ mem_acc_corn); -+ if (rc) { -+ cpr3_err(vreg, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", -+ mem_acc_corn, rc); -+ return rc; -+ } -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_switch_apm_mode() - switch the mode of the APM controller -+ * associated with a given CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * @new_volt: New voltage in microvolts that VDD supply needs to -+ * end up at -+ * @last_volt: Pointer to the last known voltage in microvolts for the -+ * VDD supply -+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max -+ * corner aggregated from all CPR3 threads managed by the -+ * CPR3 controller -+ * -+ * This function requests a switch of the APM mode while guaranteeing -+ * any LDO regulator hardware requirements are satisfied. The function must -+ * be called once it is known a new VDD supply setpoint crosses the APM -+ * voltage threshold. -+ * -+ * Return: 0 on success, errno on failure. If the VDD supply voltage is -+ * modified, last_volt is updated to reflect the new voltage setpoint. -+ */ -+static int cpr3_regulator_switch_apm_mode(struct cpr3_controller *ctrl, -+ int new_volt, int *last_volt, -+ struct cpr3_corner *aggr_corner) -+{ -+ struct regulator *vdd = ctrl->vdd_regulator; -+ int apm_volt = ctrl->apm_threshold_volt; -+ int orig_last_volt = *last_volt; -+ int rc; -+ -+ rc = regulator_set_voltage(vdd, apm_volt, apm_volt); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", -+ apm_volt, rc); -+ return rc; -+ } -+ -+ *last_volt = apm_volt; -+ -+ rc = msm_apm_set_supply(ctrl->apm, new_volt >= apm_volt -+ ? ctrl->apm_high_supply : ctrl->apm_low_supply); -+ if (rc) { -+ cpr3_err(ctrl, "APM switch failed, rc=%d\n", rc); -+ /* Roll back the voltage. */ -+ regulator_set_voltage(vdd, orig_last_volt, INT_MAX); -+ *last_volt = orig_last_volt; -+ return rc; -+ } -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_config_voltage_crossings() - configure APM and mem-acc -+ * settings depending upon a new VDD supply setpoint -+ * -+ * @ctrl: Pointer to the CPR3 controller -+ * @new_volt: New voltage in microvolts that VDD supply needs to -+ * end up at -+ * @last_volt: Pointer to the last known voltage in microvolts for the -+ * VDD supply -+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max -+ * corner aggregated from all CPR3 threads managed by the -+ * CPR3 controller -+ * -+ * This function handles the APM and mem-acc regulator reconfiguration if -+ * the new VDD supply voltage will result in crossing their respective voltage -+ * thresholds. -+ * -+ * Return: 0 on success, errno on failure. If the VDD supply voltage is -+ * modified, last_volt is updated to reflect the new voltage setpoint. -+ */ -+static int cpr3_regulator_config_voltage_crossings(struct cpr3_controller *ctrl, -+ int new_volt, int *last_volt, -+ struct cpr3_corner *aggr_corner) -+{ -+ bool apm_crossing = false, mem_acc_crossing = false; -+ bool mem_acc_bhs_used; -+ int apm_volt = ctrl->apm_threshold_volt; -+ int mem_acc_volt = ctrl->mem_acc_threshold_volt; -+ int ref_volt, rc; -+ -+ if (ctrl->apm && apm_volt > 0 -+ && ((*last_volt < apm_volt && apm_volt <= new_volt) -+ || (*last_volt >= apm_volt && apm_volt > new_volt))) -+ apm_crossing = true; -+ -+ mem_acc_bhs_used = cpr3_regulator_mem_acc_bhs_used(ctrl); -+ -+ ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : -+ new_volt; -+ -+ if (mem_acc_bhs_used && -+ (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || -+ (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt)))) -+ mem_acc_crossing = true; -+ -+ if (apm_crossing && mem_acc_crossing) { -+ if ((new_volt < *last_volt && apm_volt >= mem_acc_volt) || -+ (new_volt >= *last_volt && apm_volt < mem_acc_volt)) { -+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, -+ last_volt, -+ aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to switch APM mode\n"); -+ return rc; -+ } -+ -+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, -+ last_volt, aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); -+ return rc; -+ } -+ } else { -+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, -+ last_volt, aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); -+ return rc; -+ } -+ -+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, -+ last_volt, -+ aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to switch APM mode\n"); -+ return rc; -+ } -+ } -+ } else if (apm_crossing) { -+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, last_volt, -+ aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to switch APM mode\n"); -+ return rc; -+ } -+ } else if (mem_acc_crossing) { -+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, -+ last_volt, aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_config_mem_acc() - configure the corner of the mem-acc -+ * regulator associated with the CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max -+ * corner aggregated from all CPR3 threads managed by the -+ * CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_config_mem_acc(struct cpr3_controller *ctrl, -+ struct cpr3_corner *aggr_corner) -+{ -+ int rc; -+ -+ if (ctrl->mem_acc_regulator && aggr_corner->mem_acc_volt) { -+ rc = regulator_set_voltage(ctrl->mem_acc_regulator, -+ aggr_corner->mem_acc_volt, -+ aggr_corner->mem_acc_volt); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", -+ aggr_corner->mem_acc_volt, rc); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_scale_vdd_voltage() - scale the CPR controlled VDD supply -+ * voltage to the new level while satisfying any other hardware -+ * requirements -+ * @ctrl: Pointer to the CPR3 controller -+ * @new_volt: New voltage in microvolts that VDD supply needs to end -+ * up at -+ * @last_volt: Last known voltage in microvolts for the VDD supply -+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max -+ * corner aggregated from all CPR3 threads managed by the -+ * CPR3 controller -+ * -+ * This function scales the CPR controlled VDD supply voltage from its -+ * current level to the new voltage that is specified. If the supply is -+ * configured to use the APM and the APM threshold is crossed as a result of -+ * the voltage scaling, then this function also stops at the APM threshold, -+ * switches the APM source, and finally sets the final new voltage. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_scale_vdd_voltage(struct cpr3_controller *ctrl, -+ int new_volt, int last_volt, -+ struct cpr3_corner *aggr_corner) -+{ -+ struct regulator *vdd = ctrl->vdd_regulator; -+ int rc; -+ -+ if (new_volt < last_volt) { -+ rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); -+ if (rc) -+ return rc; -+ } else { -+ /* Increasing VDD voltage */ -+ if (ctrl->system_regulator) { -+ rc = regulator_set_voltage(ctrl->system_regulator, -+ aggr_corner->system_volt, INT_MAX); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", -+ aggr_corner->system_volt, rc); -+ return rc; -+ } -+ } -+ } -+ -+ rc = cpr3_regulator_config_voltage_crossings(ctrl, new_volt, &last_volt, -+ aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "unable to handle voltage threshold crossing configurations, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ /* -+ * Subtract a small amount from the min_uV parameter so that the -+ * set voltage request is not dropped by the framework due to being -+ * duplicate. This is needed in order to switch from hardware -+ * closed-loop to open-loop successfully. -+ */ -+ rc = regulator_set_voltage(vdd, new_volt - (ctrl->cpr_enabled ? 0 : 1), -+ aggr_corner->ceiling_volt); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", -+ new_volt, rc); -+ return rc; -+ } -+ -+ if (new_volt == last_volt && ctrl->supports_hw_closed_loop -+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ /* -+ * CPR4 features enforce voltage reprogramming when the last -+ * set voltage and new set voltage are same. This way, we can -+ * ensure that SAW PMIC STATUS register is updated with newly -+ * programmed voltage. -+ */ -+ rc = regulator_sync_voltage(vdd); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_sync_voltage(vdd) == %d failed, rc=%d\n", -+ new_volt, rc); -+ return rc; -+ } -+ } -+ -+ if (new_volt >= last_volt) { -+ rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); -+ if (rc) -+ return rc; -+ } else { -+ /* Decreasing VDD voltage */ -+ if (ctrl->system_regulator) { -+ rc = regulator_set_voltage(ctrl->system_regulator, -+ aggr_corner->system_volt, INT_MAX); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", -+ aggr_corner->system_volt, rc); -+ return rc; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_get_dynamic_floor_volt() - returns the current dynamic floor -+ * voltage based upon static configurations and the state of all -+ * power domains during the last CPR measurement -+ * @ctrl: Pointer to the CPR3 controller -+ * @reg_last_measurement: Value read from the LAST_MEASUREMENT register -+ * -+ * When using HW closed-loop, the dynamic floor voltage is always returned -+ * regardless of the current state of the power domains. -+ * -+ * Return: dynamic floor voltage in microvolts or 0 if dynamic floor is not -+ * currently required -+ */ -+static int cpr3_regulator_get_dynamic_floor_volt(struct cpr3_controller *ctrl, -+ u32 reg_last_measurement) -+{ -+ int dynamic_floor_volt = 0; -+ struct cpr3_regulator *vreg; -+ bool valid, pd_valid; -+ u32 bypass_bits; -+ int i, j; -+ -+ if (!ctrl->supports_hw_closed_loop) -+ return 0; -+ -+ if (likely(!ctrl->use_hw_closed_loop)) { -+ valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); -+ bypass_bits -+ = (reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) -+ >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT; -+ } else { -+ /* -+ * Ensure that the dynamic floor voltage is always used for -+ * HW closed-loop since the conditions below cannot be evaluated -+ * after each CPR measurement. -+ */ -+ valid = false; -+ bypass_bits = 0; -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ -+ if (!vreg->uses_dynamic_floor) -+ continue; -+ -+ pd_valid = !((bypass_bits & vreg->pd_bypass_mask) -+ == vreg->pd_bypass_mask); -+ -+ if (!valid || !pd_valid) -+ dynamic_floor_volt = max(dynamic_floor_volt, -+ vreg->corner[ -+ vreg->dynamic_floor_corner].last_volt); -+ } -+ } -+ -+ return dynamic_floor_volt; -+} -+ -+/** -+ * cpr3_regulator_max_sdelta_diff() - returns the maximum voltage difference in -+ * microvolts that can result from different operating conditions -+ * for the specified sdelta struct -+ * @sdelta: Pointer to the sdelta structure -+ * @step_volt: Step size in microvolts between available set -+ * points of the VDD supply. -+ * -+ * Return: voltage difference between the highest and lowest adjustments if -+ * sdelta and sdelta->table are valid, else 0. -+ */ -+static int cpr3_regulator_max_sdelta_diff(const struct cpr4_sdelta *sdelta, -+ int step_volt) -+{ -+ int i, j, index, sdelta_min = INT_MAX, sdelta_max = INT_MIN; -+ -+ if (!sdelta || !sdelta->table) -+ return 0; -+ -+ for (i = 0; i < sdelta->max_core_count; i++) { -+ for (j = 0; j < sdelta->temp_band_count; j++) { -+ index = i * sdelta->temp_band_count + j; -+ sdelta_min = min(sdelta_min, sdelta->table[index]); -+ sdelta_max = max(sdelta_max, sdelta->table[index]); -+ } -+ } -+ -+ return (sdelta_max - sdelta_min) * step_volt; -+} -+ -+/** -+ * cpr3_regulator_aggregate_sdelta() - check open-loop voltages of current -+ * aggregated corner and current corner of a given regulator -+ * and adjust the sdelta strucuture data of aggregate corner. -+ * @aggr_corner: Pointer to accumulated aggregated corner which -+ * is both an input and an output -+ * @corner: Pointer to the corner to be aggregated with -+ * aggr_corner -+ * @step_volt: Step size in microvolts between available set -+ * points of the VDD supply. -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_aggregate_sdelta( -+ struct cpr3_corner *aggr_corner, -+ const struct cpr3_corner *corner, int step_volt) -+{ -+ struct cpr4_sdelta *aggr_sdelta, *sdelta; -+ int aggr_core_count, core_count, temp_band_count; -+ u32 aggr_index, index; -+ int i, j, sdelta_size, cap_steps, adjust_sdelta; -+ -+ aggr_sdelta = aggr_corner->sdelta; -+ sdelta = corner->sdelta; -+ -+ if (aggr_corner->open_loop_volt < corner->open_loop_volt) { -+ /* -+ * Found the new dominant regulator as its open-loop requirement -+ * is higher than previous dominant regulator. Calculate cap -+ * voltage to limit the SDELTA values to make sure the runtime -+ * (Core-count/temp) adjustments do not violate other -+ * regulators' voltage requirements. Use cpr4_sdelta values of -+ * new dominant regulator. -+ */ -+ aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, -+ (corner->open_loop_volt - -+ aggr_corner->open_loop_volt)); -+ -+ /* Clear old data in the sdelta table */ -+ sdelta_size = aggr_sdelta->max_core_count -+ * aggr_sdelta->temp_band_count; -+ -+ if (aggr_sdelta->allow_core_count_adj -+ || aggr_sdelta->allow_temp_adj) -+ memset(aggr_sdelta->table, 0, sdelta_size -+ * sizeof(*aggr_sdelta->table)); -+ -+ if (sdelta->allow_temp_adj || sdelta->allow_core_count_adj) { -+ /* Copy new data in sdelta table */ -+ sdelta_size = sdelta->max_core_count -+ * sdelta->temp_band_count; -+ if (sdelta->table) -+ memcpy(aggr_sdelta->table, sdelta->table, -+ sdelta_size * sizeof(*sdelta->table)); -+ } -+ -+ if (sdelta->allow_boost) { -+ memcpy(aggr_sdelta->boost_table, sdelta->boost_table, -+ sdelta->temp_band_count -+ * sizeof(*sdelta->boost_table)); -+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; -+ } else if (aggr_sdelta->allow_boost) { -+ for (i = 0; i < aggr_sdelta->temp_band_count; i++) { -+ adjust_sdelta = (corner->open_loop_volt -+ - aggr_corner->open_loop_volt) -+ / step_volt; -+ aggr_sdelta->boost_table[i] += adjust_sdelta; -+ aggr_sdelta->boost_table[i] -+ = min(aggr_sdelta->boost_table[i], 0); -+ } -+ } -+ -+ aggr_corner->open_loop_volt = corner->open_loop_volt; -+ aggr_sdelta->allow_temp_adj = sdelta->allow_temp_adj; -+ aggr_sdelta->allow_core_count_adj -+ = sdelta->allow_core_count_adj; -+ aggr_sdelta->max_core_count = sdelta->max_core_count; -+ aggr_sdelta->temp_band_count = sdelta->temp_band_count; -+ } else if (aggr_corner->open_loop_volt > corner->open_loop_volt) { -+ /* -+ * Adjust the cap voltage if the open-loop requirement of new -+ * regulator is the next highest. -+ */ -+ aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, -+ (aggr_corner->open_loop_volt -+ - corner->open_loop_volt)); -+ -+ if (sdelta->allow_boost) { -+ for (i = 0; i < aggr_sdelta->temp_band_count; i++) { -+ adjust_sdelta = (aggr_corner->open_loop_volt -+ - corner->open_loop_volt) -+ / step_volt; -+ aggr_sdelta->boost_table[i] = -+ sdelta->boost_table[i] + adjust_sdelta; -+ aggr_sdelta->boost_table[i] -+ = min(aggr_sdelta->boost_table[i], 0); -+ } -+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; -+ } -+ } else { -+ /* -+ * Found another dominant regulator with same open-loop -+ * requirement. Make cap voltage to '0'. Disable core-count -+ * adjustments as we couldn't support for both regulators. -+ * Keep enable temp based adjustments if enabled for both -+ * regulators and choose mininum margin adjustment values -+ * between them. -+ */ -+ aggr_sdelta->cap_volt = 0; -+ aggr_sdelta->allow_core_count_adj = false; -+ -+ if (aggr_sdelta->allow_temp_adj -+ && sdelta->allow_temp_adj) { -+ aggr_core_count = aggr_sdelta->max_core_count - 1; -+ core_count = sdelta->max_core_count - 1; -+ temp_band_count = sdelta->temp_band_count; -+ for (j = 0; j < temp_band_count; j++) { -+ aggr_index = aggr_core_count * temp_band_count -+ + j; -+ index = core_count * temp_band_count + j; -+ aggr_sdelta->table[aggr_index] = -+ min(aggr_sdelta->table[aggr_index], -+ sdelta->table[index]); -+ } -+ } else { -+ aggr_sdelta->allow_temp_adj = false; -+ } -+ -+ if (sdelta->allow_boost) { -+ memcpy(aggr_sdelta->boost_table, sdelta->boost_table, -+ sdelta->temp_band_count -+ * sizeof(*sdelta->boost_table)); -+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; -+ } -+ } -+ -+ /* Keep non-dominant clients boost enable state */ -+ aggr_sdelta->allow_boost |= sdelta->allow_boost; -+ if (aggr_sdelta->allow_boost) -+ aggr_sdelta->allow_core_count_adj = false; -+ -+ if (aggr_sdelta->cap_volt && !(aggr_sdelta->cap_volt == INT_MAX)) { -+ core_count = aggr_sdelta->max_core_count; -+ temp_band_count = aggr_sdelta->temp_band_count; -+ /* -+ * Convert cap voltage from uV to PMIC steps and use to limit -+ * sdelta margin adjustments. -+ */ -+ cap_steps = aggr_sdelta->cap_volt / step_volt; -+ for (i = 0; i < core_count; i++) -+ for (j = 0; j < temp_band_count; j++) { -+ index = i * temp_band_count + j; -+ aggr_sdelta->table[index] = -+ min(aggr_sdelta->table[index], -+ cap_steps); -+ } -+ } -+} -+ -+/** -+ * cpr3_regulator_aggregate_corners() - aggregate two corners together -+ * @aggr_corner: Pointer to accumulated aggregated corner which -+ * is both an input and an output -+ * @corner: Pointer to the corner to be aggregated with -+ * aggr_corner -+ * @aggr_quot: Flag indicating that target quotients should be -+ * aggregated as well. -+ * @step_volt: Step size in microvolts between available set -+ * points of the VDD supply. -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_aggregate_corners(struct cpr3_corner *aggr_corner, -+ const struct cpr3_corner *corner, bool aggr_quot, -+ int step_volt) -+{ -+ int i; -+ -+ aggr_corner->ceiling_volt -+ = max(aggr_corner->ceiling_volt, corner->ceiling_volt); -+ aggr_corner->floor_volt -+ = max(aggr_corner->floor_volt, corner->floor_volt); -+ aggr_corner->last_volt -+ = max(aggr_corner->last_volt, corner->last_volt); -+ aggr_corner->system_volt -+ = max(aggr_corner->system_volt, corner->system_volt); -+ aggr_corner->mem_acc_volt -+ = max(aggr_corner->mem_acc_volt, corner->mem_acc_volt); -+ aggr_corner->irq_en |= corner->irq_en; -+ aggr_corner->use_open_loop |= corner->use_open_loop; -+ -+ if (aggr_quot) { -+ aggr_corner->ro_mask &= corner->ro_mask; -+ -+ for (i = 0; i < CPR3_RO_COUNT; i++) -+ aggr_corner->target_quot[i] -+ = max(aggr_corner->target_quot[i], -+ corner->target_quot[i]); -+ } -+ -+ if (aggr_corner->sdelta && corner->sdelta -+ && (aggr_corner->sdelta->table -+ || aggr_corner->sdelta->boost_table)) { -+ cpr3_regulator_aggregate_sdelta(aggr_corner, corner, step_volt); -+ } else { -+ aggr_corner->open_loop_volt -+ = max(aggr_corner->open_loop_volt, -+ corner->open_loop_volt); -+ } -+} -+ -+/** -+ * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller -+ * to reflect the corners used by all CPR3 regulators as well as -+ * the CPR operating mode -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * This function aggregates the CPR parameters for all CPR3 regulators -+ * associated with the VDD supply. Upon success, it sets the aggregated last -+ * known good voltage. -+ * -+ * The VDD supply voltage will not be physically configured unless this -+ * condition is met by at least one of the regulators of the controller: -+ * regulator->vreg_enabled == true && -+ * regulator->current_corner != CPR3_REGULATOR_CORNER_INVALID -+ * -+ * CPR registers for the controller and each thread are updated as long as -+ * ctrl->cpr_enabled == true. -+ * -+ * Note, CPR3 controller lock must be held by the caller. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int _cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_corner aggr_corner = {}; -+ struct cpr3_thread *thread; -+ struct cpr3_regulator *vreg; -+ struct cpr4_sdelta *sdelta; -+ bool valid = false; -+ bool thread_valid; -+ int i, j, rc, new_volt, vdd_volt, dynamic_floor_volt, last_corner_volt; -+ u32 reg_last_measurement = 0, sdelta_size; -+ int *sdelta_table, *boost_table; -+ -+ last_corner_volt = 0; -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ vdd_volt = regulator_get_voltage(ctrl->vdd_regulator); -+ if (vdd_volt < 0) { -+ cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", -+ vdd_volt); -+ return vdd_volt; -+ } -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ /* -+ * Save aggregated corner open-loop voltage which was programmed -+ * during last corner switch which is used when programming new -+ * aggregated corner open-loop voltage. -+ */ -+ last_corner_volt = ctrl->aggr_corner.open_loop_volt; -+ } -+ -+ if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop && -+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) -+ reg_last_measurement -+ = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); -+ -+ aggr_corner.sdelta = ctrl->aggr_corner.sdelta; -+ if (aggr_corner.sdelta) { -+ sdelta = aggr_corner.sdelta; -+ sdelta_table = sdelta->table; -+ if (sdelta_table) { -+ sdelta_size = sdelta->max_core_count * -+ sdelta->temp_band_count; -+ memset(sdelta_table, 0, sdelta_size -+ * sizeof(*sdelta_table)); -+ } -+ -+ boost_table = sdelta->boost_table; -+ if (boost_table) -+ memset(boost_table, 0, sdelta->temp_band_count -+ * sizeof(*boost_table)); -+ -+ memset(sdelta, 0, sizeof(*sdelta)); -+ sdelta->table = sdelta_table; -+ sdelta->cap_volt = INT_MAX; -+ sdelta->boost_table = boost_table; -+ } -+ -+ /* Aggregate the requests of all threads */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ thread = &ctrl->thread[i]; -+ thread_valid = false; -+ -+ sdelta = thread->aggr_corner.sdelta; -+ if (sdelta) { -+ sdelta_table = sdelta->table; -+ if (sdelta_table) { -+ sdelta_size = sdelta->max_core_count * -+ sdelta->temp_band_count; -+ memset(sdelta_table, 0, sdelta_size -+ * sizeof(*sdelta_table)); -+ } -+ -+ boost_table = sdelta->boost_table; -+ if (boost_table) -+ memset(boost_table, 0, sdelta->temp_band_count -+ * sizeof(*boost_table)); -+ -+ memset(sdelta, 0, sizeof(*sdelta)); -+ sdelta->table = sdelta_table; -+ sdelta->cap_volt = INT_MAX; -+ sdelta->boost_table = boost_table; -+ } -+ -+ memset(&thread->aggr_corner, 0, sizeof(thread->aggr_corner)); -+ thread->aggr_corner.sdelta = sdelta; -+ thread->aggr_corner.ro_mask = CPR3_RO_MASK; -+ -+ for (j = 0; j < thread->vreg_count; j++) { -+ vreg = &thread->vreg[j]; -+ -+ if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop) -+ cpr3_update_vreg_closed_loop_volt(vreg, -+ vdd_volt, reg_last_measurement); -+ -+ if (!vreg->vreg_enabled -+ || vreg->current_corner -+ == CPR3_REGULATOR_CORNER_INVALID) { -+ /* Cannot participate in aggregation. */ -+ vreg->aggregated = false; -+ continue; -+ } else { -+ vreg->aggregated = true; -+ thread_valid = true; -+ } -+ -+ cpr3_regulator_aggregate_corners(&thread->aggr_corner, -+ &vreg->corner[vreg->current_corner], -+ true, ctrl->step_volt); -+ } -+ -+ valid |= thread_valid; -+ -+ if (thread_valid) -+ cpr3_regulator_aggregate_corners(&aggr_corner, -+ &thread->aggr_corner, -+ false, ctrl->step_volt); -+ } -+ -+ if (valid && ctrl->cpr_allowed_hw && ctrl->cpr_allowed_sw) { -+ rc = cpr3_closed_loop_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); -+ return rc; -+ } -+ } else { -+ rc = cpr3_closed_loop_disable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); -+ return rc; -+ } -+ } -+ -+ /* No threads are enabled with a valid corner so exit. */ -+ if (!valid) -+ return 0; -+ -+ /* -+ * When using CPR hardware closed-loop, the voltage may vary anywhere -+ * between the floor and ceiling voltage without software notification. -+ * Therefore, it is required that the floor to ceiling range for the -+ * aggregated corner not intersect the APM threshold voltage. Adjust -+ * the floor to ceiling range if this requirement is violated. -+ * -+ * The following algorithm is applied in the case that -+ * floor < threshold <= ceiling: -+ * if open_loop >= threshold - adj, then floor = threshold -+ * else ceiling = threshold - step -+ * where adj = an adjustment factor to ensure sufficient voltage margin -+ * and step = VDD output step size -+ * -+ * The open-loop and last known voltages are also bounded by the new -+ * floor or ceiling value as needed. -+ */ -+ if (ctrl->use_hw_closed_loop -+ && aggr_corner.ceiling_volt >= ctrl->apm_threshold_volt -+ && aggr_corner.floor_volt < ctrl->apm_threshold_volt) { -+ -+ if (aggr_corner.open_loop_volt -+ >= ctrl->apm_threshold_volt - ctrl->apm_adj_volt) -+ aggr_corner.floor_volt = ctrl->apm_threshold_volt; -+ else -+ aggr_corner.ceiling_volt -+ = ctrl->apm_threshold_volt - ctrl->step_volt; -+ -+ aggr_corner.last_volt -+ = max(aggr_corner.last_volt, aggr_corner.floor_volt); -+ aggr_corner.last_volt -+ = min(aggr_corner.last_volt, aggr_corner.ceiling_volt); -+ aggr_corner.open_loop_volt -+ = max(aggr_corner.open_loop_volt, aggr_corner.floor_volt); -+ aggr_corner.open_loop_volt -+ = min(aggr_corner.open_loop_volt, aggr_corner.ceiling_volt); -+ } -+ -+ if (ctrl->use_hw_closed_loop -+ && aggr_corner.ceiling_volt >= ctrl->mem_acc_threshold_volt -+ && aggr_corner.floor_volt < ctrl->mem_acc_threshold_volt) { -+ aggr_corner.floor_volt = ctrl->mem_acc_threshold_volt; -+ aggr_corner.last_volt = max(aggr_corner.last_volt, -+ aggr_corner.floor_volt); -+ aggr_corner.open_loop_volt = max(aggr_corner.open_loop_volt, -+ aggr_corner.floor_volt); -+ } -+ -+ if (ctrl->use_hw_closed_loop) { -+ dynamic_floor_volt -+ = cpr3_regulator_get_dynamic_floor_volt(ctrl, -+ reg_last_measurement); -+ if (aggr_corner.floor_volt < dynamic_floor_volt) { -+ aggr_corner.floor_volt = dynamic_floor_volt; -+ aggr_corner.last_volt = max(aggr_corner.last_volt, -+ aggr_corner.floor_volt); -+ aggr_corner.open_loop_volt -+ = max(aggr_corner.open_loop_volt, -+ aggr_corner.floor_volt); -+ aggr_corner.ceiling_volt = max(aggr_corner.ceiling_volt, -+ aggr_corner.floor_volt); -+ } -+ } -+ -+ if (ctrl->cpr_enabled && ctrl->last_corner_was_closed_loop) { -+ /* -+ * Always program open-loop voltage for CPR4 controllers which -+ * support hardware closed-loop. Storing the last closed loop -+ * voltage in corner structure can still help with debugging. -+ */ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) -+ new_volt = aggr_corner.last_volt; -+ else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 -+ && ctrl->supports_hw_closed_loop) -+ new_volt = aggr_corner.open_loop_volt; -+ else -+ new_volt = min(aggr_corner.last_volt + -+ cpr3_regulator_max_sdelta_diff(aggr_corner.sdelta, -+ ctrl->step_volt), -+ aggr_corner.ceiling_volt); -+ -+ aggr_corner.last_volt = new_volt; -+ } else { -+ new_volt = aggr_corner.open_loop_volt; -+ aggr_corner.last_volt = aggr_corner.open_loop_volt; -+ } -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 -+ && ctrl->supports_hw_closed_loop) { -+ /* -+ * Store last aggregated corner open-loop voltage in vdd_volt -+ * which is used when programming current aggregated corner -+ * required voltage. -+ */ -+ vdd_volt = last_corner_volt; -+ } -+ -+ cpr3_debug(ctrl, "setting new voltage=%d uV\n", new_volt); -+ rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, -+ vdd_volt, &aggr_corner); -+ if (rc) { -+ cpr3_err(ctrl, "vdd voltage scaling failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ /* Only update registers if CPR is enabled. */ -+ if (ctrl->cpr_enabled) { -+ if (ctrl->use_hw_closed_loop) { -+ /* Hardware closed-loop */ -+ -+ /* Set ceiling and floor limits in hardware */ -+ rc = regulator_set_voltage(ctrl->vdd_limit_regulator, -+ aggr_corner.floor_volt, -+ aggr_corner.ceiling_volt); -+ if (rc) { -+ cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } else { -+ /* Software closed-loop */ -+ -+ /* -+ * Disable UP or DOWN interrupts when at ceiling or -+ * floor respectively. -+ */ -+ if (new_volt == aggr_corner.floor_volt) -+ aggr_corner.irq_en &= ~CPR3_IRQ_DOWN; -+ if (new_volt == aggr_corner.ceiling_volt) -+ aggr_corner.irq_en &= ~CPR3_IRQ_UP; -+ -+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, -+ CPR3_IRQ_UP | CPR3_IRQ_DOWN); -+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, aggr_corner.irq_en); -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ cpr3_regulator_set_target_quot(&ctrl->thread[i]); -+ -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ -+ if (vreg->vreg_enabled) -+ vreg->last_closed_loop_corner -+ = vreg->current_corner; -+ } -+ } -+ -+ if (ctrl->proc_clock_throttle) { -+ if (aggr_corner.ceiling_volt > aggr_corner.floor_volt -+ && (ctrl->use_hw_closed_loop -+ || new_volt < aggr_corner.ceiling_volt)) -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ ctrl->proc_clock_throttle); -+ else -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ CPR3_PD_THROTTLE_DISABLE); -+ } -+ -+ /* -+ * Ensure that all CPR register writes complete before -+ * re-enabling CPR loop operation. -+ */ -+ wmb(); -+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 -+ && ctrl->vdd_limit_regulator) { -+ /* Set ceiling and floor limits in hardware */ -+ rc = regulator_set_voltage(ctrl->vdd_limit_regulator, -+ aggr_corner.floor_volt, -+ aggr_corner.ceiling_volt); -+ if (rc) { -+ cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ ctrl->aggr_corner = aggr_corner; -+ -+ if (ctrl->allow_core_count_adj || ctrl->allow_temp_adj -+ || ctrl->allow_boost) { -+ rc = cpr3_controller_program_sdelta(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to program sdelta, rc=%d\n", rc); -+ return rc; -+ } -+ } -+ -+ /* -+ * Only enable the CPR controller if it is possible to set more than -+ * one vdd-supply voltage. -+ */ -+ if (aggr_corner.ceiling_volt > aggr_corner.floor_volt && -+ !aggr_corner.use_open_loop) -+ cpr3_ctrl_loop_enable(ctrl); -+ -+ ctrl->last_corner_was_closed_loop = ctrl->cpr_enabled; -+ cpr3_debug(ctrl, "CPR configuration updated\n"); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_wait_for_idle() - wait for the CPR controller to no longer be -+ * busy -+ * @ctrl: Pointer to the CPR3 controller -+ * @max_wait_ns: Max wait time in nanoseconds -+ * -+ * Return: 0 on success or -ETIMEDOUT if the controller was still busy after -+ * the maximum delay time -+ */ -+static int cpr3_regulator_wait_for_idle(struct cpr3_controller *ctrl, -+ s64 max_wait_ns) -+{ -+ ktime_t start, end; -+ s64 time_ns; -+ u32 reg; -+ -+ /* -+ * Ensure that all previous CPR register writes have completed before -+ * checking the status register. -+ */ -+ mb(); -+ -+ start = ktime_get(); -+ do { -+ end = ktime_get(); -+ time_ns = ktime_to_ns(ktime_sub(end, start)); -+ if (time_ns > max_wait_ns) { -+ cpr3_err(ctrl, "CPR controller still busy after %lld us\n", -+ div_s64(time_ns, 1000)); -+ return -ETIMEDOUT; -+ } -+ usleep_range(50, 100); -+ reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); -+ } while (reg & CPR3_CPR_STATUS_BUSY_MASK); -+ -+ return 0; -+} -+ -+/** -+ * cmp_int() - int comparison function to be passed into the sort() function -+ * which leads to ascending sorting -+ * @a: First int value -+ * @b: Second int value -+ * -+ * Return: >0 if a > b, 0 if a == b, <0 if a < b -+ */ -+static int cmp_int(const void *a, const void *b) -+{ -+ return *(int *)a - *(int *)b; -+} -+ -+/** -+ * cpr3_regulator_measure_aging() - measure the quotient difference for the -+ * specified CPR aging sensor -+ * @ctrl: Pointer to the CPR3 controller -+ * @aging_sensor: Aging sensor to measure -+ * -+ * Note that vdd-supply must be configured to the aging reference voltage before -+ * calling this function. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_measure_aging(struct cpr3_controller *ctrl, -+ struct cpr3_aging_sensor_info *aging_sensor) -+{ -+ u32 mask, reg, result, quot_min, quot_max, sel_min, sel_max; -+ u32 quot_min_scaled, quot_max_scaled; -+ u32 gcnt, gcnt_ref, gcnt0_restore, gcnt1_restore, irq_restore; -+ u32 ro_mask_restore, cont_dly_restore, up_down_dly_restore = 0; -+ int quot_delta, quot_delta_scaled, quot_delta_scaled_sum; -+ int *quot_delta_results; -+ int rc, rc2, i, aging_measurement_count, filtered_count; -+ bool is_aging_measurement; -+ -+ quot_delta_results = kcalloc(CPR3_AGING_MEASUREMENT_ITERATIONS, -+ sizeof(*quot_delta_results), GFP_KERNEL); -+ if (!quot_delta_results) -+ return -ENOMEM; -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ kfree(quot_delta_results); -+ return rc; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ /* Enable up, down, and mid CPR interrupts */ -+ irq_restore = cpr3_read(ctrl, CPR3_REG_IRQ_EN); -+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, -+ CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); -+ -+ /* Ensure that the aging sensor is assigned to CPR thread 0 */ -+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), 0); -+ -+ /* Switch from HW to SW closed-loop if necessary */ -+ if (ctrl->supports_hw_closed_loop) { -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); -+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, -+ CPR3_HW_CLOSED_LOOP_DISABLE); -+ } -+ } -+ -+ /* Configure the GCNT for RO0 and RO1 that are used for aging */ -+ gcnt0_restore = cpr3_read(ctrl, CPR3_REG_GCNT(0)); -+ gcnt1_restore = cpr3_read(ctrl, CPR3_REG_GCNT(1)); -+ gcnt_ref = cpr3_regulator_get_gcnt(ctrl); -+ gcnt = gcnt_ref * 3 / 2; -+ cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt); -+ cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt); -+ -+ /* Unmask all RO's */ -+ ro_mask_restore = cpr3_read(ctrl, CPR3_REG_RO_MASK(0)); -+ cpr3_write(ctrl, CPR3_REG_RO_MASK(0), 0); -+ -+ /* -+ * Mask all sensors except for the one to measure and bypass all -+ * sensors in collapsible domains. -+ */ -+ for (i = 0; i <= ctrl->sensor_count / 32; i++) { -+ mask = GENMASK(min(31, ctrl->sensor_count - i * 32), 0); -+ if (aging_sensor->sensor_id / 32 >= i -+ && aging_sensor->sensor_id / 32 < (i + 1)) -+ mask &= ~BIT(aging_sensor->sensor_id % 32); -+ cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), mask); -+ cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), -+ aging_sensor->bypass_mask[i]); -+ } -+ -+ /* Set CPR loop delays to 0 us */ -+ if (ctrl->supports_hw_closed_loop -+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cont_dly_restore = cpr3_read(ctrl, CPR3_REG_CPR_TIMER_MID_CONT); -+ up_down_dly_restore = cpr3_read(ctrl, -+ CPR3_REG_CPR_TIMER_UP_DN_CONT); -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, 0); -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, 0); -+ } else { -+ cont_dly_restore = cpr3_read(ctrl, -+ CPR3_REG_CPR_TIMER_AUTO_CONT); -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, 0); -+ } -+ -+ /* Set count mode to all-at-once min with no repeat */ -+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, -+ CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, -+ CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN -+ << CPR3_CPR_CTL_COUNT_MODE_SHIFT); -+ -+ cpr3_ctrl_loop_enable(ctrl); -+ -+ rc = cpr3_regulator_wait_for_idle(ctrl, -+ CPR3_AGING_MEASUREMENT_TIMEOUT_NS); -+ if (rc) -+ goto cleanup; -+ -+ /* Set count mode to all-at-once aging */ -+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, CPR3_CPR_CTL_COUNT_MODE_MASK, -+ CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE -+ << CPR3_CPR_CTL_COUNT_MODE_SHIFT); -+ -+ aging_measurement_count = 0; -+ for (i = 0; i < CPR3_AGING_MEASUREMENT_ITERATIONS; i++) { -+ /* Send CONT_NACK */ -+ cpr3_write(ctrl, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_NACK); -+ -+ rc = cpr3_regulator_wait_for_idle(ctrl, -+ CPR3_AGING_MEASUREMENT_TIMEOUT_NS); -+ if (rc) -+ goto cleanup; -+ -+ /* Check for PAGE_IS_AGE flag in status register */ -+ reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); -+ is_aging_measurement -+ = reg & CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK; -+ -+ /* Read CPR measurement results */ -+ result = cpr3_read(ctrl, CPR3_REG_RESULT1(0)); -+ quot_min = (result & CPR3_RESULT1_QUOT_MIN_MASK) -+ >> CPR3_RESULT1_QUOT_MIN_SHIFT; -+ quot_max = (result & CPR3_RESULT1_QUOT_MAX_MASK) -+ >> CPR3_RESULT1_QUOT_MAX_SHIFT; -+ sel_min = (result & CPR3_RESULT1_RO_MIN_MASK) -+ >> CPR3_RESULT1_RO_MIN_SHIFT; -+ sel_max = (result & CPR3_RESULT1_RO_MAX_MASK) -+ >> CPR3_RESULT1_RO_MAX_SHIFT; -+ -+ /* -+ * Scale the quotients so that they are equivalent to the fused -+ * values. This accounts for the difference in measurement -+ * interval times. -+ */ -+ quot_min_scaled = quot_min * (gcnt_ref + 1) / (gcnt + 1); -+ quot_max_scaled = quot_max * (gcnt_ref + 1) / (gcnt + 1); -+ -+ if (sel_max == 1) { -+ quot_delta = quot_max - quot_min; -+ quot_delta_scaled = quot_max_scaled - quot_min_scaled; -+ } else { -+ quot_delta = quot_min - quot_max; -+ quot_delta_scaled = quot_min_scaled - quot_max_scaled; -+ } -+ -+ if (is_aging_measurement) -+ quot_delta_results[aging_measurement_count++] -+ = quot_delta_scaled; -+ -+ cpr3_debug(ctrl, "aging results: page_is_age=%u, sel_min=%u, sel_max=%u, quot_min=%u, quot_max=%u, quot_delta=%d, quot_min_scaled=%u, quot_max_scaled=%u, quot_delta_scaled=%d\n", -+ is_aging_measurement, sel_min, sel_max, quot_min, -+ quot_max, quot_delta, quot_min_scaled, quot_max_scaled, -+ quot_delta_scaled); -+ } -+ -+ filtered_count -+ = aging_measurement_count - CPR3_AGING_MEASUREMENT_FILTER * 2; -+ if (filtered_count > 0) { -+ sort(quot_delta_results, aging_measurement_count, -+ sizeof(*quot_delta_results), cmp_int, NULL); -+ -+ quot_delta_scaled_sum = 0; -+ for (i = 0; i < filtered_count; i++) -+ quot_delta_scaled_sum -+ += quot_delta_results[i -+ + CPR3_AGING_MEASUREMENT_FILTER]; -+ -+ aging_sensor->measured_quot_diff -+ = quot_delta_scaled_sum / filtered_count; -+ cpr3_info(ctrl, "average quotient delta=%d (count=%d)\n", -+ aging_sensor->measured_quot_diff, -+ filtered_count); -+ } else { -+ cpr3_err(ctrl, "%d aging measurements completed after %d iterations\n", -+ aging_measurement_count, -+ CPR3_AGING_MEASUREMENT_ITERATIONS); -+ rc = -EBUSY; -+ } -+ -+cleanup: -+ kfree(quot_delta_results); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc2 = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc2) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc2); -+ rc = rc2; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_restore); -+ -+ cpr3_write(ctrl, CPR3_REG_RO_MASK(0), ro_mask_restore); -+ -+ cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt0_restore); -+ cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt1_restore); -+ -+ if (ctrl->supports_hw_closed_loop -+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly_restore); -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, -+ up_down_dly_restore); -+ } else { -+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, -+ cont_dly_restore); -+ } -+ -+ for (i = 0; i <= ctrl->sensor_count / 32; i++) { -+ cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), 0); -+ cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), 0); -+ } -+ -+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, -+ CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, -+ (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) -+ | (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT)); -+ -+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), -+ ctrl->sensor_owner[aging_sensor->sensor_id]); -+ -+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, -+ CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); -+ -+ if (ctrl->supports_hw_closed_loop) { -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, -+ ctrl->use_hw_closed_loop -+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE -+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); -+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, -+ ctrl->use_hw_closed_loop -+ ? CPR3_HW_CLOSED_LOOP_ENABLE -+ : CPR3_HW_CLOSED_LOOP_DISABLE); -+ } -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_regulator_readjust_volt_and_quot() - readjust the target quotients as -+ * well as the floor, ceiling, and open-loop voltages for the -+ * regulator by removing the old adjustment and adding the new one -+ * @vreg: Pointer to the CPR3 regulator -+ * @old_adjust_volt: Old aging adjustment voltage in microvolts -+ * @new_adjust_volt: New aging adjustment voltage in microvolts -+ * -+ * Also reset the cached closed loop voltage (last_volt) to equal the open-loop -+ * voltage for each corner. -+ * -+ * Return: None -+ */ -+static void cpr3_regulator_readjust_volt_and_quot(struct cpr3_regulator *vreg, -+ int old_adjust_volt, int new_adjust_volt) -+{ -+ unsigned long long temp; -+ int i, j, old_volt, new_volt, rounded_volt; -+ -+ if (!vreg->aging_allowed) -+ return; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ temp = (unsigned long long)old_adjust_volt -+ * (unsigned long long)vreg->corner[i].aging_derate; -+ do_div(temp, 1000); -+ old_volt = temp; -+ -+ temp = (unsigned long long)new_adjust_volt -+ * (unsigned long long)vreg->corner[i].aging_derate; -+ do_div(temp, 1000); -+ new_volt = temp; -+ -+ old_volt = min(vreg->aging_max_adjust_volt, old_volt); -+ new_volt = min(vreg->aging_max_adjust_volt, new_volt); -+ -+ for (j = 0; j < CPR3_RO_COUNT; j++) { -+ if (vreg->corner[i].target_quot[j] != 0) { -+ vreg->corner[i].target_quot[j] -+ += cpr3_quot_adjustment( -+ vreg->corner[i].ro_scale[j], -+ new_volt) -+ - cpr3_quot_adjustment( -+ vreg->corner[i].ro_scale[j], -+ old_volt); -+ } -+ } -+ -+ rounded_volt = CPR3_ROUND(new_volt, -+ vreg->thread->ctrl->step_volt); -+ -+ if (!vreg->aging_allow_open_loop_adj) -+ rounded_volt = 0; -+ -+ vreg->corner[i].ceiling_volt -+ = vreg->corner[i].unaged_ceiling_volt + rounded_volt; -+ vreg->corner[i].ceiling_volt = min(vreg->corner[i].ceiling_volt, -+ vreg->corner[i].abs_ceiling_volt); -+ vreg->corner[i].floor_volt -+ = vreg->corner[i].unaged_floor_volt + rounded_volt; -+ vreg->corner[i].floor_volt = min(vreg->corner[i].floor_volt, -+ vreg->corner[i].ceiling_volt); -+ vreg->corner[i].open_loop_volt -+ = vreg->corner[i].unaged_open_loop_volt + rounded_volt; -+ vreg->corner[i].open_loop_volt -+ = min(vreg->corner[i].open_loop_volt, -+ vreg->corner[i].ceiling_volt); -+ -+ vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; -+ -+ cpr3_debug(vreg, "corner %d: applying %d uV closed-loop and %d uV open-loop voltage margin adjustment\n", -+ i, new_volt, rounded_volt); -+ } -+} -+ -+/** -+ * cpr3_regulator_set_aging_ref_adjustment() - adjust target quotients for the -+ * regulators managed by this CPR controller to account for aging -+ * @ctrl: Pointer to the CPR3 controller -+ * @ref_adjust_volt: New aging reference adjustment voltage in microvolts to -+ * apply to all regulators managed by this CPR controller -+ * -+ * The existing aging adjustment as defined by ctrl->aging_ref_adjust_volt is -+ * first removed and then the adjustment is applied. Lastly, the value of -+ * ctrl->aging_ref_adjust_volt is updated to ref_adjust_volt. -+ */ -+static void cpr3_regulator_set_aging_ref_adjustment( -+ struct cpr3_controller *ctrl, int ref_adjust_volt) -+{ -+ struct cpr3_regulator *vreg; -+ int i, j; -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ cpr3_regulator_readjust_volt_and_quot(vreg, -+ ctrl->aging_ref_adjust_volt, ref_adjust_volt); -+ } -+ } -+ -+ ctrl->aging_ref_adjust_volt = ref_adjust_volt; -+} -+ -+/** -+ * cpr3_regulator_aging_adjust() - adjust the target quotients for regulators -+ * based on the output of CPR aging sensors -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_aging_adjust(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_regulator *vreg; -+ struct cpr3_corner restore_aging_corner; -+ struct cpr3_corner *corner; -+ int *restore_current_corner; -+ bool *restore_vreg_enabled; -+ int i, j, id, rc, rc2, vreg_count, aging_volt, max_aging_volt = 0; -+ u32 reg; -+ -+ if (!ctrl->aging_required || !ctrl->cpr_enabled -+ || ctrl->aggr_corner.ceiling_volt == 0 -+ || ctrl->aggr_corner.ceiling_volt > ctrl->aging_ref_volt) -+ return 0; -+ -+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ vreg_count++; -+ -+ if (vreg->aging_allowed && vreg->vreg_enabled -+ && vreg->current_corner > vreg->aging_corner) -+ return 0; -+ } -+ } -+ -+ /* Verify that none of the aging sensors are currently masked. */ -+ for (i = 0; i < ctrl->aging_sensor_count; i++) { -+ id = ctrl->aging_sensor[i].sensor_id; -+ reg = cpr3_read(ctrl, CPR3_REG_SENSOR_MASK_READ(id)); -+ if (reg & BIT(id % 32)) -+ return 0; -+ } -+ -+ /* -+ * Verify that the aging possible register (if specified) has an -+ * acceptable value. -+ */ -+ if (ctrl->aging_possible_reg) { -+ reg = readl_relaxed(ctrl->aging_possible_reg); -+ reg &= ctrl->aging_possible_mask; -+ if (reg != ctrl->aging_possible_val) -+ return 0; -+ } -+ -+ restore_current_corner = kcalloc(vreg_count, -+ sizeof(*restore_current_corner), GFP_KERNEL); -+ restore_vreg_enabled = kcalloc(vreg_count, -+ sizeof(*restore_vreg_enabled), GFP_KERNEL); -+ if (!restore_current_corner || !restore_vreg_enabled) { -+ kfree(restore_current_corner); -+ kfree(restore_vreg_enabled); -+ return -ENOMEM; -+ } -+ -+ /* Force all regulators to the aging corner */ -+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ -+ restore_current_corner[vreg_count] -+ = vreg->current_corner; -+ restore_vreg_enabled[vreg_count] -+ = vreg->vreg_enabled; -+ -+ vreg->current_corner = vreg->aging_corner; -+ vreg->vreg_enabled = true; -+ } -+ } -+ -+ /* Force one of the regulators to require the aging reference voltage */ -+ vreg = &ctrl->thread[0].vreg[0]; -+ corner = &vreg->corner[vreg->current_corner]; -+ restore_aging_corner = *corner; -+ corner->ceiling_volt = ctrl->aging_ref_volt; -+ corner->floor_volt = ctrl->aging_ref_volt; -+ corner->open_loop_volt = ctrl->aging_ref_volt; -+ corner->last_volt = ctrl->aging_ref_volt; -+ -+ /* Skip last_volt caching */ -+ ctrl->last_corner_was_closed_loop = false; -+ -+ /* Set the vdd supply voltage to the aging reference voltage */ -+ rc = _cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "unable to force vdd-supply to the aging reference voltage=%d uV, rc=%d\n", -+ ctrl->aging_ref_volt, rc); -+ goto cleanup; -+ } -+ -+ if (ctrl->aging_vdd_mode) { -+ rc = regulator_set_mode(ctrl->vdd_regulator, -+ ctrl->aging_vdd_mode); -+ if (rc) { -+ cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", -+ ctrl->aging_vdd_mode, rc); -+ goto cleanup; -+ } -+ } -+ -+ /* Perform aging measurement on all aging sensors */ -+ for (i = 0; i < ctrl->aging_sensor_count; i++) { -+ for (j = 0; j < CPR3_AGING_RETRY_COUNT; j++) { -+ rc = cpr3_regulator_measure_aging(ctrl, -+ &ctrl->aging_sensor[i]); -+ if (!rc) -+ break; -+ } -+ -+ if (!rc) { -+ aging_volt = -+ cpr3_voltage_adjustment( -+ ctrl->aging_sensor[i].ro_scale, -+ ctrl->aging_sensor[i].measured_quot_diff -+ - ctrl->aging_sensor[i].init_quot_diff); -+ max_aging_volt = max(max_aging_volt, aging_volt); -+ } else { -+ cpr3_err(ctrl, "CPR aging measurement failed after %d tries, rc=%d\n", -+ j, rc); -+ ctrl->aging_failed = true; -+ ctrl->aging_required = false; -+ goto cleanup; -+ } -+ } -+ -+cleanup: -+ vreg = &ctrl->thread[0].vreg[0]; -+ vreg->corner[vreg->current_corner] = restore_aging_corner; -+ -+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ vreg->current_corner -+ = restore_current_corner[vreg_count]; -+ vreg->vreg_enabled = restore_vreg_enabled[vreg_count]; -+ } -+ } -+ -+ kfree(restore_current_corner); -+ kfree(restore_vreg_enabled); -+ -+ /* Adjust the CPR target quotients according to the aging measurement */ -+ if (!rc) { -+ cpr3_regulator_set_aging_ref_adjustment(ctrl, max_aging_volt); -+ -+ cpr3_info(ctrl, "aging measurement successful; aging reference adjustment voltage=%d uV\n", -+ ctrl->aging_ref_adjust_volt); -+ ctrl->aging_succeeded = true; -+ ctrl->aging_required = false; -+ } -+ -+ if (ctrl->aging_complete_vdd_mode) { -+ rc = regulator_set_mode(ctrl->vdd_regulator, -+ ctrl->aging_complete_vdd_mode); -+ if (rc) -+ cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", -+ ctrl->aging_complete_vdd_mode, rc); -+ } -+ -+ /* Skip last_volt caching */ -+ ctrl->last_corner_was_closed_loop = false; -+ -+ /* -+ * Restore vdd-supply to the voltage before the aging measurement and -+ * restore the CPR3 controller hardware state. -+ */ -+ rc2 = _cpr3_regulator_update_ctrl_state(ctrl); -+ -+ /* Stop last_volt caching on for the next request */ -+ ctrl->last_corner_was_closed_loop = false; -+ -+ return rc ? rc : rc2; -+} -+ -+/** -+ * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller -+ * to reflect the corners used by all CPR3 regulators as well as -+ * the CPR operating mode and perform aging adjustments if needed -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Note, CPR3 controller lock must be held by the caller. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = _cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) -+ return rc; -+ -+ return cpr3_regulator_aging_adjust(ctrl); -+} -+ -+/** -+ * cpr3_regulator_set_voltage() - set the voltage corner for the CPR3 regulator -+ * associated with the regulator device -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * @corner: New voltage corner to set (offset by CPR3_CORNER_OFFSET) -+ * @corner_max: Maximum voltage corner allowed (offset by -+ * CPR3_CORNER_OFFSET) -+ * @selector: Pointer which is filled with the selector value for the -+ * corner -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. The VDD voltage will not be -+ * physically configured until both this function and cpr3_regulator_enable() -+ * are called. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_set_voltage(struct regulator_dev *rdev, -+ int corner, int corner_max, unsigned *selector) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ int rc = 0; -+ int last_corner; -+ -+ corner -= CPR3_CORNER_OFFSET; -+ corner_max -= CPR3_CORNER_OFFSET; -+ *selector = corner; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (!vreg->vreg_enabled) { -+ vreg->current_corner = corner; -+ cpr3_debug(vreg, "stored corner=%d\n", corner); -+ goto done; -+ } else if (vreg->current_corner == corner) { -+ goto done; -+ } -+ -+ last_corner = vreg->current_corner; -+ vreg->current_corner = corner; -+ -+ if (vreg->cpr4_regulator_data != NULL) -+ if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL) -+ vreg->cpr4_regulator_data->mem_acc_funcs->set_mem_acc(rdev); -+ -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); -+ vreg->current_corner = last_corner; -+ } -+ -+ if (vreg->cpr4_regulator_data != NULL) -+ if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL) -+ vreg->cpr4_regulator_data->mem_acc_funcs->clear_mem_acc(rdev); -+ -+ cpr3_debug(vreg, "set corner=%d\n", corner); -+done: -+ mutex_unlock(&ctrl->lock); -+ -+ return rc; -+} -+ -+/** -+ * cpr3_handle_temp_open_loop_adjustment() - voltage based cold temperature -+ * -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * @is_cold: Flag to denote enter/exit cold condition -+ * -+ * This function is adjusts voltage margin based on cold condition -+ * -+ * Return: 0 = success -+ */ -+ -+int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, -+ bool is_cold) -+{ -+ int i ,j, k, rc; -+ struct cpr3_regulator *vreg; -+ -+ mutex_lock(&ctrl->lock); -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ for (k = 0; k < vreg->corner_count; k++) { -+ vreg->corner[k].open_loop_volt = is_cold ? -+ vreg->corner[k].cold_temp_open_loop_volt : -+ vreg->corner[k].normal_temp_open_loop_volt; -+ } -+ } -+ } -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ mutex_unlock(&ctrl->lock); -+ -+ return rc; -+} -+ -+/** -+ * cpr3_regulator_get_voltage() - get the voltage corner for the CPR3 regulator -+ * associated with the regulator device -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. -+ * -+ * Return: voltage corner value offset by CPR3_CORNER_OFFSET -+ */ -+static int cpr3_regulator_get_voltage(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ -+ if (vreg->current_corner == CPR3_REGULATOR_CORNER_INVALID) -+ return CPR3_CORNER_OFFSET; -+ else -+ return vreg->current_corner + CPR3_CORNER_OFFSET; -+} -+ -+/** -+ * cpr3_regulator_list_voltage() - return the voltage corner mapped to the -+ * specified selector -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * @selector: Regulator selector -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. -+ * -+ * Return: voltage corner value offset by CPR3_CORNER_OFFSET -+ */ -+static int cpr3_regulator_list_voltage(struct regulator_dev *rdev, -+ unsigned selector) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ -+ if (selector < vreg->corner_count) -+ return selector + CPR3_CORNER_OFFSET; -+ else -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_is_enabled() - return the enable state of the CPR3 regulator -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. -+ * -+ * Return: true if regulator is enabled, false if regulator is disabled -+ */ -+static int cpr3_regulator_is_enabled(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ -+ return vreg->vreg_enabled; -+} -+ -+/** -+ * cpr3_regulator_enable() - enable the CPR3 regulator -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_enable(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ int rc = 0; -+ -+ if (vreg->vreg_enabled == true) -+ return 0; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (ctrl->system_regulator) { -+ rc = regulator_enable(ctrl->system_regulator); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_enable(system) failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ rc = regulator_enable(ctrl->vdd_regulator); -+ if (rc) { -+ cpr3_err(vreg, "regulator_enable(vdd) failed, rc=%d\n", rc); -+ goto done; -+ } -+ -+ vreg->vreg_enabled = true; -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); -+ regulator_disable(ctrl->vdd_regulator); -+ vreg->vreg_enabled = false; -+ goto done; -+ } -+ -+ cpr3_debug(vreg, "Enabled\n"); -+done: -+ mutex_unlock(&ctrl->lock); -+ -+ return rc; -+} -+ -+/** -+ * cpr3_regulator_disable() - disable the CPR3 regulator -+ * @rdev: Regulator device pointer for the cpr3-regulator -+ * -+ * This function is passed as a callback function into the regulator ops that -+ * are registered for each cpr3-regulator device. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_disable(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ int rc, rc2; -+ -+ if (vreg->vreg_enabled == false) -+ return 0; -+ -+ mutex_lock(&ctrl->lock); -+ rc = regulator_disable(ctrl->vdd_regulator); -+ if (rc) { -+ cpr3_err(vreg, "regulator_disable(vdd) failed, rc=%d\n", rc); -+ goto done; -+ } -+ -+ vreg->vreg_enabled = false; -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); -+ rc2 = regulator_enable(ctrl->vdd_regulator); -+ vreg->vreg_enabled = true; -+ goto done; -+ } -+ -+ if (ctrl->system_regulator) { -+ rc = regulator_disable(ctrl->system_regulator); -+ if (rc) { -+ cpr3_err(ctrl, "regulator_disable(system) failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ cpr3_debug(vreg, "Disabled\n"); -+done: -+ mutex_unlock(&ctrl->lock); -+ -+ return rc; -+} -+ -+static struct regulator_ops cpr3_regulator_ops = { -+ .enable = cpr3_regulator_enable, -+ .disable = cpr3_regulator_disable, -+ .is_enabled = cpr3_regulator_is_enabled, -+ .set_voltage = cpr3_regulator_set_voltage, -+ .get_voltage = cpr3_regulator_get_voltage, -+ .list_voltage = cpr3_regulator_list_voltage, -+}; -+ -+/** -+ * cpr3_print_result() - print CPR measurement results to the kernel log for -+ * debugging purposes -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: None -+ */ -+static void cpr3_print_result(struct cpr3_thread *thread) -+{ -+ struct cpr3_controller *ctrl = thread->ctrl; -+ u32 result[3], busy, step_dn, step_up, error_steps, error, negative; -+ u32 quot_min, quot_max, ro_min, ro_max, step_quot_min, step_quot_max; -+ u32 sensor_min, sensor_max; -+ char *sign; -+ -+ result[0] = cpr3_read(ctrl, CPR3_REG_RESULT0(thread->thread_id)); -+ result[1] = cpr3_read(ctrl, CPR3_REG_RESULT1(thread->thread_id)); -+ result[2] = cpr3_read(ctrl, CPR3_REG_RESULT2(thread->thread_id)); -+ -+ busy = !!(result[0] & CPR3_RESULT0_BUSY_MASK); -+ step_dn = !!(result[0] & CPR3_RESULT0_STEP_DN_MASK); -+ step_up = !!(result[0] & CPR3_RESULT0_STEP_UP_MASK); -+ error_steps = (result[0] & CPR3_RESULT0_ERROR_STEPS_MASK) -+ >> CPR3_RESULT0_ERROR_STEPS_SHIFT; -+ error = (result[0] & CPR3_RESULT0_ERROR_MASK) -+ >> CPR3_RESULT0_ERROR_SHIFT; -+ negative = !!(result[0] & CPR3_RESULT0_NEGATIVE_MASK); -+ -+ quot_min = (result[1] & CPR3_RESULT1_QUOT_MIN_MASK) -+ >> CPR3_RESULT1_QUOT_MIN_SHIFT; -+ quot_max = (result[1] & CPR3_RESULT1_QUOT_MAX_MASK) -+ >> CPR3_RESULT1_QUOT_MAX_SHIFT; -+ ro_min = (result[1] & CPR3_RESULT1_RO_MIN_MASK) -+ >> CPR3_RESULT1_RO_MIN_SHIFT; -+ ro_max = (result[1] & CPR3_RESULT1_RO_MAX_MASK) -+ >> CPR3_RESULT1_RO_MAX_SHIFT; -+ -+ step_quot_min = (result[2] & CPR3_RESULT2_STEP_QUOT_MIN_MASK) -+ >> CPR3_RESULT2_STEP_QUOT_MIN_SHIFT; -+ step_quot_max = (result[2] & CPR3_RESULT2_STEP_QUOT_MAX_MASK) -+ >> CPR3_RESULT2_STEP_QUOT_MAX_SHIFT; -+ sensor_min = (result[2] & CPR3_RESULT2_SENSOR_MIN_MASK) -+ >> CPR3_RESULT2_SENSOR_MIN_SHIFT; -+ sensor_max = (result[2] & CPR3_RESULT2_SENSOR_MAX_MASK) -+ >> CPR3_RESULT2_SENSOR_MAX_SHIFT; -+ -+ sign = negative ? "-" : ""; -+ cpr3_debug(ctrl, "thread %u: busy=%u, step_dn=%u, step_up=%u, error_steps=%s%u, error=%s%u\n", -+ thread->thread_id, busy, step_dn, step_up, sign, error_steps, -+ sign, error); -+ cpr3_debug(ctrl, "thread %u: quot_min=%u, quot_max=%u, ro_min=%u, ro_max=%u\n", -+ thread->thread_id, quot_min, quot_max, ro_min, ro_max); -+ cpr3_debug(ctrl, "thread %u: step_quot_min=%u, step_quot_max=%u, sensor_min=%u, sensor_max=%u\n", -+ thread->thread_id, step_quot_min, step_quot_max, sensor_min, -+ sensor_max); -+} -+ -+/** -+ * cpr3_thread_busy() - returns if the specified CPR3 thread is busy taking -+ * a measurement -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: CPR3 busy status -+ */ -+static bool cpr3_thread_busy(struct cpr3_thread *thread) -+{ -+ u32 result; -+ -+ result = cpr3_read(thread->ctrl, CPR3_REG_RESULT0(thread->thread_id)); -+ -+ return !!(result & CPR3_RESULT0_BUSY_MASK); -+} -+ -+/** -+ * cpr3_irq_handler() - CPR interrupt handler callback function used for -+ * software closed-loop operation -+ * @irq: CPR interrupt number -+ * @data: Private data corresponding to the CPR3 controller -+ * pointer -+ * -+ * This function increases or decreases the vdd supply voltage based upon the -+ * CPR controller recommendation. -+ * -+ * Return: IRQ_HANDLED -+ */ -+static irqreturn_t cpr3_irq_handler(int irq, void *data) -+{ -+ struct cpr3_controller *ctrl = data; -+ struct cpr3_corner *aggr = &ctrl->aggr_corner; -+ u32 cont = CPR3_CONT_CMD_NACK; -+ u32 reg_last_measurement = 0; -+ struct cpr3_regulator *vreg; -+ struct cpr3_corner *corner; -+ unsigned long flags; -+ int i, j, new_volt, last_volt, dynamic_floor_volt, rc; -+ u32 irq_en, status, cpr_status, ctl; -+ bool up, down; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (!ctrl->cpr_enabled) { -+ cpr3_debug(ctrl, "CPR interrupt received but CPR is disabled\n"); -+ mutex_unlock(&ctrl->lock); -+ return IRQ_HANDLED; -+ } else if (ctrl->use_hw_closed_loop) { -+ cpr3_debug(ctrl, "CPR interrupt received but CPR is using HW closed-loop\n"); -+ goto done; -+ } -+ -+ /* -+ * CPR IRQ status checking and CPR controller disabling must happen -+ * atomically and without invening delay in order to avoid an interrupt -+ * storm caused by the handler racing with the CPR controller. -+ */ -+ local_irq_save(flags); -+ preempt_disable(); -+ -+ status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); -+ up = status & CPR3_IRQ_UP; -+ down = status & CPR3_IRQ_DOWN; -+ -+ if (!up && !down) { -+ /* -+ * Toggle the CPR controller off and then back on since the -+ * hardware and software states are out of sync. This condition -+ * occurs after an aging measurement completes as the CPR IRQ -+ * physically triggers during the aging measurement but the -+ * handler is stuck waiting on the mutex lock. -+ */ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ local_irq_restore(flags); -+ preempt_enable(); -+ -+ /* Wait for the loop disable write to complete */ -+ mb(); -+ -+ /* Wait for BUSY=1 and LOOP_EN=0 in CPR controller registers. */ -+ for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { -+ cpr_status = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); -+ ctl = cpr3_read(ctrl, CPR3_REG_CPR_CTL); -+ if (cpr_status & CPR3_CPR_STATUS_BUSY_MASK -+ && (ctl & CPR3_CPR_CTL_LOOP_EN_MASK) -+ == CPR3_CPR_CTL_LOOP_DISABLE) -+ break; -+ udelay(10); -+ } -+ if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) -+ cpr3_debug(ctrl, "CPR controller not disabled after %d us\n", -+ CPR3_REGISTER_WRITE_DELAY_US); -+ -+ /* Clear interrupt status */ -+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, -+ CPR3_IRQ_UP | CPR3_IRQ_DOWN); -+ -+ /* Wait for the interrupt clearing write to complete */ -+ mb(); -+ -+ /* Wait for IRQ_STATUS register to be cleared. */ -+ for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { -+ status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); -+ if (!(status & (CPR3_IRQ_UP | CPR3_IRQ_DOWN))) -+ break; -+ udelay(10); -+ } -+ if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) -+ cpr3_debug(ctrl, "CPR interrupts not cleared after %d us\n", -+ CPR3_REGISTER_WRITE_DELAY_US); -+ -+ cpr3_ctrl_loop_enable(ctrl); -+ -+ cpr3_debug(ctrl, "CPR interrupt received but no up or down status bit is set\n"); -+ -+ mutex_unlock(&ctrl->lock); -+ return IRQ_HANDLED; -+ } else if (up && down) { -+ cpr3_debug(ctrl, "both up and down status bits set\n"); -+ /* The up flag takes precedence over the down flag. */ -+ down = false; -+ } -+ -+ if (ctrl->supports_hw_closed_loop) -+ reg_last_measurement -+ = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); -+ dynamic_floor_volt = cpr3_regulator_get_dynamic_floor_volt(ctrl, -+ reg_last_measurement); -+ -+ local_irq_restore(flags); -+ preempt_enable(); -+ -+ irq_en = aggr->irq_en; -+ last_volt = aggr->last_volt; -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ if (cpr3_thread_busy(&ctrl->thread[i])) { -+ cpr3_debug(ctrl, "CPR thread %u busy when it should be waiting for SW cont\n", -+ ctrl->thread[i].thread_id); -+ goto done; -+ } -+ } -+ -+ new_volt = up ? last_volt + ctrl->step_volt -+ : last_volt - ctrl->step_volt; -+ -+ /* Re-enable UP/DOWN interrupt when its opposite is received. */ -+ irq_en |= up ? CPR3_IRQ_DOWN : CPR3_IRQ_UP; -+ -+ if (new_volt > aggr->ceiling_volt) { -+ new_volt = aggr->ceiling_volt; -+ irq_en &= ~CPR3_IRQ_UP; -+ cpr3_debug(ctrl, "limiting to ceiling=%d uV\n", -+ aggr->ceiling_volt); -+ } else if (new_volt < aggr->floor_volt) { -+ new_volt = aggr->floor_volt; -+ irq_en &= ~CPR3_IRQ_DOWN; -+ cpr3_debug(ctrl, "limiting to floor=%d uV\n", aggr->floor_volt); -+ } -+ -+ if (down && new_volt < dynamic_floor_volt) { -+ /* -+ * The vdd-supply voltage should not be decreased below the -+ * dynamic floor voltage. However, it is not necessary (and -+ * counter productive) to force the voltage up to this level -+ * if it happened to be below it since the closed-loop voltage -+ * must have gotten there in a safe manner while the power -+ * domains for the CPR3 regulator imposing the dynamic floor -+ * were not bypassed. -+ */ -+ new_volt = last_volt; -+ irq_en &= ~CPR3_IRQ_DOWN; -+ cpr3_debug(ctrl, "limiting to dynamic floor=%d uV\n", -+ dynamic_floor_volt); -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) -+ cpr3_print_result(&ctrl->thread[i]); -+ -+ cpr3_debug(ctrl, "%s: new_volt=%d uV, last_volt=%d uV\n", -+ up ? "UP" : "DN", new_volt, last_volt); -+ -+ if (ctrl->proc_clock_throttle && last_volt == aggr->ceiling_volt -+ && new_volt < last_volt) -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ ctrl->proc_clock_throttle); -+ -+ if (new_volt != last_volt) { -+ rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, -+ last_volt, -+ aggr); -+ if (rc) { -+ cpr3_err(ctrl, "scale_vdd() failed to set vdd=%d uV, rc=%d\n", -+ new_volt, rc); -+ goto done; -+ } -+ cont = CPR3_CONT_CMD_ACK; -+ -+ /* -+ * Update the closed-loop voltage for all regulators managed -+ * by this CPR controller. -+ */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ cpr3_update_vreg_closed_loop_volt(vreg, -+ new_volt, reg_last_measurement); -+ } -+ } -+ } -+ -+ if (ctrl->proc_clock_throttle && new_volt == aggr->ceiling_volt) -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ CPR3_PD_THROTTLE_DISABLE); -+ -+ corner = &ctrl->thread[0].vreg[0].corner[ -+ ctrl->thread[0].vreg[0].current_corner]; -+ -+ if (irq_en != aggr->irq_en) { -+ aggr->irq_en = irq_en; -+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_en); -+ } -+ -+ aggr->last_volt = new_volt; -+ -+done: -+ /* Clear interrupt status */ -+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, CPR3_IRQ_UP | CPR3_IRQ_DOWN); -+ -+ /* ACK or NACK the CPR controller */ -+ cpr3_write(ctrl, CPR3_REG_CONT_CMD, cont); -+ -+ mutex_unlock(&ctrl->lock); -+ return IRQ_HANDLED; -+} -+ -+/** -+ * cpr3_ceiling_irq_handler() - CPR ceiling reached interrupt handler callback -+ * function used for hardware closed-loop operation -+ * @irq: CPR ceiling interrupt number -+ * @data: Private data corresponding to the CPR3 controller -+ * pointer -+ * -+ * This function disables processor clock throttling and closed-loop operation -+ * when the ceiling voltage is reached. -+ * -+ * Return: IRQ_HANDLED -+ */ -+static irqreturn_t cpr3_ceiling_irq_handler(int irq, void *data) -+{ -+ struct cpr3_controller *ctrl = data; -+ int volt; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (!ctrl->cpr_enabled) { -+ cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is disabled\n"); -+ goto done; -+ } else if (!ctrl->use_hw_closed_loop) { -+ cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is using SW closed-loop\n"); -+ goto done; -+ } -+ -+ volt = regulator_get_voltage(ctrl->vdd_regulator); -+ if (volt < 0) { -+ cpr3_err(ctrl, "could not get vdd voltage, rc=%d\n", volt); -+ goto done; -+ } else if (volt != ctrl->aggr_corner.ceiling_volt) { -+ cpr3_debug(ctrl, "CPR ceiling interrupt received but vdd voltage: %d uV != ceiling voltage: %d uV\n", -+ volt, ctrl->aggr_corner.ceiling_volt); -+ goto done; -+ } -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ /* -+ * Since the ceiling voltage has been reached, disable processor -+ * clock throttling as well as CPR closed-loop operation. -+ */ -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ CPR3_PD_THROTTLE_DISABLE); -+ cpr3_ctrl_loop_disable(ctrl); -+ cpr3_debug(ctrl, "CPR closed-loop and throttling disabled\n"); -+ } -+ -+done: -+ mutex_unlock(&ctrl->lock); -+ return IRQ_HANDLED; -+} -+ -+/** -+ * cpr3_regulator_vreg_register() - register a regulator device for a CPR3 -+ * regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function initializes all regulator framework related structures and then -+ * calls regulator_register() for the CPR3 regulator. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_vreg_register(struct cpr3_regulator *vreg) -+{ -+ struct regulator_config config = {}; -+ struct regulator_desc *rdesc; -+ struct regulator_init_data *init_data; -+ int rc; -+ -+ init_data = of_get_regulator_init_data(vreg->thread->ctrl->dev, -+ vreg->of_node, &vreg->rdesc); -+ if (!init_data) { -+ cpr3_err(vreg, "regulator init data is missing\n"); -+ return -EINVAL; -+ } -+ -+ init_data->constraints.input_uV = init_data->constraints.max_uV; -+ rdesc = &vreg->rdesc; -+ init_data->constraints.valid_ops_mask |= -+ REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS; -+ rdesc->ops = &cpr3_regulator_ops; -+ -+ rdesc->n_voltages = vreg->corner_count; -+ rdesc->name = init_data->constraints.name; -+ rdesc->owner = THIS_MODULE; -+ rdesc->type = REGULATOR_VOLTAGE; -+ -+ config.dev = vreg->thread->ctrl->dev; -+ config.driver_data = vreg; -+ config.init_data = init_data; -+ config.of_node = vreg->of_node; -+ -+ vreg->rdev = regulator_register(rdesc, &config); -+ if (IS_ERR(vreg->rdev)) { -+ rc = PTR_ERR(vreg->rdev); -+ cpr3_err(vreg, "regulator_register failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ return 0; -+} -+ -+static int debugfs_int_set(void *data, u64 val) -+{ -+ *(int *)data = val; -+ return 0; -+} -+ -+static int debugfs_int_get(void *data, u64 *val) -+{ -+ *val = *(int *)data; -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(fops_int, debugfs_int_get, debugfs_int_set, "%lld\n"); -+DEFINE_SIMPLE_ATTRIBUTE(fops_int_ro, debugfs_int_get, NULL, "%lld\n"); -+DEFINE_SIMPLE_ATTRIBUTE(fops_int_wo, NULL, debugfs_int_set, "%lld\n"); -+ -+/** -+ * debugfs_create_int - create a debugfs file that is used to read and write a -+ * signed int value -+ * @name: Pointer to a string containing the name of the file to -+ * create -+ * @mode: The permissions that the file should have -+ * @parent: Pointer to the parent dentry for this file. This should -+ * be a directory dentry if set. If this parameter is -+ * %NULL, then the file will be created in the root of the -+ * debugfs filesystem. -+ * @value: Pointer to the variable that the file should read to and -+ * write from -+ * -+ * This function creates a file in debugfs with the given name that -+ * contains the value of the variable @value. If the @mode variable is so -+ * set, it can be read from, and written to. -+ * -+ * This function will return a pointer to a dentry if it succeeds. This -+ * pointer must be passed to the debugfs_remove() function when the file is -+ * to be removed. If an error occurs, %NULL will be returned. -+ */ -+static struct dentry *debugfs_create_int(const char *name, umode_t mode, -+ struct dentry *parent, int *value) -+{ -+ /* if there are no write bits set, make read only */ -+ if (!(mode & S_IWUGO)) -+ return debugfs_create_file(name, mode, parent, value, -+ &fops_int_ro); -+ /* if there are no read bits set, make write only */ -+ if (!(mode & S_IRUGO)) -+ return debugfs_create_file(name, mode, parent, value, -+ &fops_int_wo); -+ -+ return debugfs_create_file(name, mode, parent, value, &fops_int); -+} -+ -+static int debugfs_bool_get(void *data, u64 *val) -+{ -+ *val = *(bool *)data; -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(fops_bool_ro, debugfs_bool_get, NULL, "%lld\n"); -+ -+/** -+ * struct cpr3_debug_corner_info - data structure used by the -+ * cpr3_debugfs_create_corner_int function -+ * @vreg: Pointer to the CPR3 regulator -+ * @index: Pointer to the corner array index -+ * @member_offset: Offset in bytes from the beginning of struct cpr3_corner -+ * to the beginning of the value to be read from -+ * @corner: Pointer to the CPR3 corner array -+ */ -+struct cpr3_debug_corner_info { -+ struct cpr3_regulator *vreg; -+ int *index; -+ size_t member_offset; -+ struct cpr3_corner *corner; -+}; -+ -+static int cpr3_debug_corner_int_get(void *data, u64 *val) -+{ -+ struct cpr3_debug_corner_info *info = data; -+ struct cpr3_controller *ctrl = info->vreg->thread->ctrl; -+ int i; -+ -+ mutex_lock(&ctrl->lock); -+ -+ i = *info->index; -+ if (i < 0) -+ i = 0; -+ -+ *val = *(int *)((char *)&info->vreg->corner[i] + info->member_offset); -+ -+ mutex_unlock(&ctrl->lock); -+ -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_int_fops, cpr3_debug_corner_int_get, -+ NULL, "%lld\n"); -+ -+/** -+ * cpr3_debugfs_create_corner_int - create a debugfs file that is used to read -+ * a signed int value out of a CPR3 regulator's corner array -+ * @vreg: Pointer to the CPR3 regulator -+ * @name: Pointer to a string containing the name of the file to -+ * create -+ * @mode: The permissions that the file should have -+ * @parent: Pointer to the parent dentry for this file. This should -+ * be a directory dentry if set. If this parameter is -+ * %NULL, then the file will be created in the root of the -+ * debugfs filesystem. -+ * @index: Pointer to the corner array index -+ * @member_offset: Offset in bytes from the beginning of struct cpr3_corner -+ * to the beginning of the value to be read from -+ * -+ * This function creates a file in debugfs with the given name that -+ * contains the value of the int type variable vreg->corner[index].member -+ * where member_offset == offsetof(struct cpr3_corner, member). -+ */ -+static struct dentry *cpr3_debugfs_create_corner_int( -+ struct cpr3_regulator *vreg, const char *name, umode_t mode, -+ struct dentry *parent, int *index, size_t member_offset) -+{ -+ struct cpr3_debug_corner_info *info; -+ -+ info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return NULL; -+ -+ info->vreg = vreg; -+ info->index = index; -+ info->member_offset = member_offset; -+ -+ return debugfs_create_file(name, mode, parent, info, -+ &cpr3_debug_corner_int_fops); -+} -+ -+static int cpr3_debug_quot_open(struct inode *inode, struct file *file) -+{ -+ struct cpr3_debug_corner_info *info = inode->i_private; -+ struct cpr3_thread *thread = info->vreg->thread; -+ int size, i, pos; -+ u32 *quot; -+ char *buf; -+ -+ /* -+ * Max size: -+ * - 10 digits + ' ' or '\n' = 11 bytes per number -+ * - terminating '\0' -+ */ -+ size = CPR3_RO_COUNT * 11; -+ buf = kzalloc(size + 1, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ file->private_data = buf; -+ -+ mutex_lock(&thread->ctrl->lock); -+ -+ quot = info->corner[*info->index].target_quot; -+ -+ for (i = 0, pos = 0; i < CPR3_RO_COUNT; i++) -+ pos += scnprintf(buf + pos, size - pos, "%u%c", -+ quot[i], i < CPR3_RO_COUNT - 1 ? ' ' : '\n'); -+ -+ mutex_unlock(&thread->ctrl->lock); -+ -+ return nonseekable_open(inode, file); -+} -+ -+static ssize_t cpr3_debug_quot_read(struct file *file, char __user *buf, -+ size_t len, loff_t *ppos) -+{ -+ return simple_read_from_buffer(buf, len, ppos, file->private_data, -+ strlen(file->private_data)); -+} -+ -+static int cpr3_debug_quot_release(struct inode *inode, struct file *file) -+{ -+ kfree(file->private_data); -+ -+ return 0; -+} -+ -+static const struct file_operations cpr3_debug_quot_fops = { -+ .owner = THIS_MODULE, -+ .open = cpr3_debug_quot_open, -+ .release = cpr3_debug_quot_release, -+ .read = cpr3_debug_quot_read, -+ .llseek = no_llseek, -+}; -+ -+/** -+ * cpr3_regulator_debugfs_corner_add() - add debugfs files to expose -+ * configuration data for the CPR corner -+ * @vreg: Pointer to the CPR3 regulator -+ * @corner_dir: Pointer to the parent corner dentry for the new files -+ * @index: Pointer to the corner array index -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_debugfs_corner_add(struct cpr3_regulator *vreg, -+ struct dentry *corner_dir, int *index) -+{ -+ struct cpr3_debug_corner_info *info; -+ struct dentry *temp; -+ -+ temp = cpr3_debugfs_create_corner_int(vreg, "floor_volt", S_IRUGO, -+ corner_dir, index, offsetof(struct cpr3_corner, floor_volt)); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "floor_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = cpr3_debugfs_create_corner_int(vreg, "ceiling_volt", S_IRUGO, -+ corner_dir, index, offsetof(struct cpr3_corner, ceiling_volt)); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "ceiling_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = cpr3_debugfs_create_corner_int(vreg, "open_loop_volt", S_IRUGO, -+ corner_dir, index, -+ offsetof(struct cpr3_corner, open_loop_volt)); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "open_loop_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = cpr3_debugfs_create_corner_int(vreg, "last_volt", S_IRUGO, -+ corner_dir, index, offsetof(struct cpr3_corner, last_volt)); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "last_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return; -+ -+ info->vreg = vreg; -+ info->index = index; -+ info->corner = vreg->corner; -+ -+ temp = debugfs_create_file("target_quots", S_IRUGO, corner_dir, -+ info, &cpr3_debug_quot_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "target_quots debugfs file creation failed\n"); -+ return; -+ } -+} -+ -+/** -+ * cpr3_debug_corner_index_set() - debugfs callback used to change the -+ * value of the CPR3 regulator debug_corner index -+ * @data: Pointer to private data which is equal to the CPR3 -+ * regulator pointer -+ * @val: New value for debug_corner -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_corner_index_set(void *data, u64 val) -+{ -+ struct cpr3_regulator *vreg = data; -+ -+ if (val < CPR3_CORNER_OFFSET || val > vreg->corner_count) { -+ cpr3_err(vreg, "invalid corner index %llu; allowed values: %d-%d\n", -+ val, CPR3_CORNER_OFFSET, vreg->corner_count); -+ return -EINVAL; -+ } -+ -+ mutex_lock(&vreg->thread->ctrl->lock); -+ vreg->debug_corner = val - CPR3_CORNER_OFFSET; -+ mutex_unlock(&vreg->thread->ctrl->lock); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_debug_corner_index_get() - debugfs callback used to retrieve -+ * the value of the CPR3 regulator debug_corner index -+ * @data: Pointer to private data which is equal to the CPR3 -+ * regulator pointer -+ * @val: Output parameter written with the value of -+ * debug_corner -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_corner_index_get(void *data, u64 *val) -+{ -+ struct cpr3_regulator *vreg = data; -+ -+ *val = vreg->debug_corner + CPR3_CORNER_OFFSET; -+ -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_index_fops, -+ cpr3_debug_corner_index_get, -+ cpr3_debug_corner_index_set, -+ "%llu\n"); -+ -+/** -+ * cpr3_debug_current_corner_index_get() - debugfs callback used to retrieve -+ * the value of the CPR3 regulator current_corner index -+ * @data: Pointer to private data which is equal to the CPR3 -+ * regulator pointer -+ * @val: Output parameter written with the value of -+ * current_corner -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_current_corner_index_get(void *data, u64 *val) -+{ -+ struct cpr3_regulator *vreg = data; -+ -+ *val = vreg->current_corner + CPR3_CORNER_OFFSET; -+ -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_current_corner_index_fops, -+ cpr3_debug_current_corner_index_get, -+ NULL, "%llu\n"); -+ -+/** -+ * cpr3_regulator_debugfs_vreg_add() - add debugfs files to expose configuration -+ * data for the CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * @thread_dir CPR3 thread debugfs directory handle -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_debugfs_vreg_add(struct cpr3_regulator *vreg, -+ struct dentry *thread_dir) -+{ -+ struct dentry *temp, *corner_dir, *vreg_dir; -+ -+ vreg_dir = debugfs_create_dir(vreg->name, thread_dir); -+ if (IS_ERR_OR_NULL(vreg_dir)) { -+ cpr3_err(vreg, "%s debugfs directory creation failed\n", -+ vreg->name); -+ return; -+ } -+ -+ temp = debugfs_create_int("speed_bin_fuse", S_IRUGO, vreg_dir, -+ &vreg->speed_bin_fuse); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "speed_bin_fuse debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("cpr_rev_fuse", S_IRUGO, vreg_dir, -+ &vreg->cpr_rev_fuse); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "cpr_rev_fuse debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("fuse_combo", S_IRUGO, vreg_dir, -+ &vreg->fuse_combo); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "fuse_combo debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("corner_count", S_IRUGO, vreg_dir, -+ &vreg->corner_count); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "corner_count debugfs file creation failed\n"); -+ return; -+ } -+ -+ corner_dir = debugfs_create_dir("corner", vreg_dir); -+ if (IS_ERR_OR_NULL(corner_dir)) { -+ cpr3_err(vreg, "corner debugfs directory creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("index", S_IRUGO | S_IWUSR, corner_dir, -+ vreg, &cpr3_debug_corner_index_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "index debugfs file creation failed\n"); -+ return; -+ } -+ -+ cpr3_regulator_debugfs_corner_add(vreg, corner_dir, -+ &vreg->debug_corner); -+ -+ corner_dir = debugfs_create_dir("current_corner", vreg_dir); -+ if (IS_ERR_OR_NULL(corner_dir)) { -+ cpr3_err(vreg, "current_corner debugfs directory creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("index", S_IRUGO, corner_dir, -+ vreg, &cpr3_debug_current_corner_index_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(vreg, "index debugfs file creation failed\n"); -+ return; -+ } -+ -+ cpr3_regulator_debugfs_corner_add(vreg, corner_dir, -+ &vreg->current_corner); -+} -+ -+/** -+ * cpr3_regulator_debugfs_thread_add() - add debugfs files to expose -+ * configuration data for the CPR thread -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_debugfs_thread_add(struct cpr3_thread *thread) -+{ -+ struct cpr3_controller *ctrl = thread->ctrl; -+ struct dentry *aggr_dir, *temp, *thread_dir; -+ struct cpr3_debug_corner_info *info; -+ char buf[20]; -+ int *index; -+ int i; -+ -+ scnprintf(buf, sizeof(buf), "thread%u", thread->thread_id); -+ thread_dir = debugfs_create_dir(buf, thread->ctrl->debugfs); -+ if (IS_ERR_OR_NULL(thread_dir)) { -+ cpr3_err(ctrl, "thread %u %s debugfs directory creation failed\n", -+ thread->thread_id, buf); -+ return; -+ } -+ -+ aggr_dir = debugfs_create_dir("max_aggregated_params", thread_dir); -+ if (IS_ERR_OR_NULL(aggr_dir)) { -+ cpr3_err(ctrl, "thread %u max_aggregated_params debugfs directory creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir, -+ &thread->aggr_corner.floor_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread %u aggr floor_volt debugfs file creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir, -+ &thread->aggr_corner.ceiling_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread %u aggr ceiling_volt debugfs file creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir, -+ &thread->aggr_corner.open_loop_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread %u aggr open_loop_volt debugfs file creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir, -+ &thread->aggr_corner.last_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread %u aggr last_volt debugfs file creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ info = devm_kzalloc(thread->ctrl->dev, sizeof(*info), GFP_KERNEL); -+ index = devm_kzalloc(thread->ctrl->dev, sizeof(*index), GFP_KERNEL); -+ if (!info || !index) -+ return; -+ *index = 0; -+ info->vreg = &thread->vreg[0]; -+ info->index = index; -+ info->corner = &thread->aggr_corner; -+ -+ temp = debugfs_create_file("target_quots", S_IRUGO, aggr_dir, -+ info, &cpr3_debug_quot_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread %u target_quots debugfs file creation failed\n", -+ thread->thread_id); -+ return; -+ } -+ -+ for (i = 0; i < thread->vreg_count; i++) -+ cpr3_regulator_debugfs_vreg_add(&thread->vreg[i], thread_dir); -+} -+ -+/** -+ * cpr3_debug_closed_loop_enable_set() - debugfs callback used to change the -+ * value of the CPR controller cpr_allowed_sw flag which enables or -+ * disables closed-loop operation -+ * @data: Pointer to private data which is equal to the CPR -+ * controller pointer -+ * @val: New value for cpr_allowed_sw -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_closed_loop_enable_set(void *data, u64 val) -+{ -+ struct cpr3_controller *ctrl = data; -+ bool enable = !!val; -+ int rc; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (ctrl->cpr_allowed_sw == enable) -+ goto done; -+ -+ if (enable && !ctrl->cpr_allowed_hw) { -+ cpr3_err(ctrl, "CPR closed-loop operation is not allowed\n"); -+ goto done; -+ } -+ -+ ctrl->cpr_allowed_sw = enable; -+ -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not change CPR enable state=%u, rc=%d\n", -+ enable, rc); -+ goto done; -+ } -+ -+ if (ctrl->proc_clock_throttle && !ctrl->cpr_enabled) { -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ ctrl->cpr_enabled = true; -+ -+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, -+ CPR3_PD_THROTTLE_DISABLE); -+ -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ } -+ -+ cpr3_debug(ctrl, "closed-loop=%s\n", enable ? "enabled" : "disabled"); -+done: -+ mutex_unlock(&ctrl->lock); -+ return 0; -+} -+ -+/** -+ * cpr3_debug_closed_loop_enable_get() - debugfs callback used to retrieve -+ * the value of the CPR controller cpr_allowed_sw flag which -+ * indicates if closed-loop operation is enabled -+ * @data: Pointer to private data which is equal to the CPR -+ * controller pointer -+ * @val: Output parameter written with the value of -+ * cpr_allowed_sw -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_closed_loop_enable_get(void *data, u64 *val) -+{ -+ struct cpr3_controller *ctrl = data; -+ -+ *val = ctrl->cpr_allowed_sw; -+ -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_closed_loop_enable_fops, -+ cpr3_debug_closed_loop_enable_get, -+ cpr3_debug_closed_loop_enable_set, -+ "%llu\n"); -+ -+/** -+ * cpr3_debug_hw_closed_loop_enable_set() - debugfs callback used to change the -+ * value of the CPR controller use_hw_closed_loop flag which -+ * switches between software closed-loop and hardware closed-loop -+ * operation for CPR3 and CPR4 controllers and between open-loop -+ * and full hardware closed-loop operation for CPRh controllers. -+ * @data: Pointer to private data which is equal to the CPR -+ * controller pointer -+ * @val: New value for use_hw_closed_loop -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_hw_closed_loop_enable_set(void *data, u64 val) -+{ -+ struct cpr3_controller *ctrl = data; -+ bool use_hw_closed_loop = !!val; -+ struct cpr3_regulator *vreg; -+ bool cpr_enabled; -+ int i, j, k, rc; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (ctrl->use_hw_closed_loop == use_hw_closed_loop) -+ goto done; -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ ctrl->use_hw_closed_loop = use_hw_closed_loop; -+ -+ cpr_enabled = ctrl->cpr_enabled; -+ -+ /* Ensure that CPR clocks are enabled before writing to registers. */ -+ if (!cpr_enabled) { -+ rc = cpr3_clock_enable(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); -+ goto done; -+ } -+ ctrl->cpr_enabled = true; -+ } -+ -+ if (ctrl->use_hw_closed_loop) -+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, 0); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, -+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, -+ ctrl->use_hw_closed_loop -+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE -+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); -+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, -+ ctrl->use_hw_closed_loop -+ ? CPR3_HW_CLOSED_LOOP_ENABLE -+ : CPR3_HW_CLOSED_LOOP_DISABLE); -+ } -+ -+ /* Turn off CPR clocks if they were off before this function call. */ -+ if (!cpr_enabled) { -+ cpr3_clock_disable(ctrl); -+ ctrl->cpr_enabled = false; -+ } -+ -+ if (ctrl->use_hw_closed_loop && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ rc = regulator_enable(ctrl->vdd_limit_regulator); -+ if (rc) { -+ cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } else if (!ctrl->use_hw_closed_loop -+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ rc = regulator_disable(ctrl->vdd_limit_regulator); -+ if (rc) { -+ cpr3_err(ctrl, "CPR limit regulator disable failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ /* -+ * Due to APM and mem-acc floor restriction constraints, -+ * the closed-loop voltage may be different when using -+ * software closed-loop vs hardware closed-loop. Therefore, -+ * reset the cached closed-loop voltage for all corners to the -+ * corresponding open-loop voltage when switching between -+ * SW and HW closed-loop mode. -+ */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ for (k = 0; k < vreg->corner_count; k++) -+ vreg->corner[k].last_volt -+ = vreg->corner[k].open_loop_volt; -+ } -+ } -+ -+ /* Skip last_volt caching */ -+ ctrl->last_corner_was_closed_loop = false; -+ -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not change CPR HW closed-loop enable state=%u, rc=%d\n", -+ use_hw_closed_loop, rc); -+ goto done; -+ } -+ -+ cpr3_debug(ctrl, "CPR mode=%s\n", -+ use_hw_closed_loop ? -+ "HW closed-loop" : "SW closed-loop"); -+done: -+ mutex_unlock(&ctrl->lock); -+ return 0; -+} -+ -+/** -+ * cpr3_debug_hw_closed_loop_enable_get() - debugfs callback used to retrieve -+ * the value of the CPR controller use_hw_closed_loop flag which -+ * indicates if hardware closed-loop operation is being used in -+ * place of software closed-loop operation -+ * @data: Pointer to private data which is equal to the CPR -+ * controller pointer -+ * @val: Output parameter written with the value of -+ * use_hw_closed_loop -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_hw_closed_loop_enable_get(void *data, u64 *val) -+{ -+ struct cpr3_controller *ctrl = data; -+ -+ *val = ctrl->use_hw_closed_loop; -+ -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_hw_closed_loop_enable_fops, -+ cpr3_debug_hw_closed_loop_enable_get, -+ cpr3_debug_hw_closed_loop_enable_set, -+ "%llu\n"); -+ -+/** -+ * cpr3_debug_trigger_aging_measurement_set() - debugfs callback used to trigger -+ * another CPR measurement -+ * @data: Pointer to private data which is equal to the CPR -+ * controller pointer -+ * @val: Unused -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_debug_trigger_aging_measurement_set(void *data, u64 val) -+{ -+ struct cpr3_controller *ctrl = data; -+ int rc; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); -+ ctrl->aging_required = true; -+ ctrl->aging_succeeded = false; -+ ctrl->aging_failed = false; -+ -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not update the CPR controller state, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+done: -+ mutex_unlock(&ctrl->lock); -+ return 0; -+} -+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_trigger_aging_measurement_fops, -+ NULL, -+ cpr3_debug_trigger_aging_measurement_set, -+ "%llu\n"); -+ -+/** -+ * cpr3_regulator_debugfs_ctrl_add() - add debugfs files to expose configuration -+ * data for the CPR controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_debugfs_ctrl_add(struct cpr3_controller *ctrl) -+{ -+ struct dentry *temp, *aggr_dir; -+ int i; -+ -+ /* Add cpr3-regulator base directory if it isn't present already. */ -+ if (cpr3_debugfs_base == NULL) { -+ cpr3_debugfs_base = debugfs_create_dir("cpr3-regulator", NULL); -+ if (IS_ERR_OR_NULL(cpr3_debugfs_base)) { -+ cpr3_err(ctrl, "cpr3-regulator debugfs base directory creation failed\n"); -+ cpr3_debugfs_base = NULL; -+ return; -+ } -+ } -+ -+ ctrl->debugfs = debugfs_create_dir(ctrl->name, cpr3_debugfs_base); -+ if (IS_ERR_OR_NULL(ctrl->debugfs)) { -+ cpr3_err(ctrl, "cpr3-regulator controller debugfs directory creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("cpr_closed_loop_enable", S_IRUGO | S_IWUSR, -+ ctrl->debugfs, ctrl, -+ &cpr3_debug_closed_loop_enable_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "cpr_closed_loop_enable debugfs file creation failed\n"); -+ return; -+ } -+ -+ if (ctrl->supports_hw_closed_loop) { -+ temp = debugfs_create_file("use_hw_closed_loop", -+ S_IRUGO | S_IWUSR, ctrl->debugfs, ctrl, -+ &cpr3_debug_hw_closed_loop_enable_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "use_hw_closed_loop debugfs file creation failed\n"); -+ return; -+ } -+ } -+ -+ temp = debugfs_create_int("thread_count", S_IRUGO, ctrl->debugfs, -+ &ctrl->thread_count); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "thread_count debugfs file creation failed\n"); -+ return; -+ } -+ -+ if (ctrl->apm) { -+ temp = debugfs_create_int("apm_threshold_volt", S_IRUGO, -+ ctrl->debugfs, &ctrl->apm_threshold_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "apm_threshold_volt debugfs file creation failed\n"); -+ return; -+ } -+ } -+ -+ if (ctrl->aging_required || ctrl->aging_succeeded -+ || ctrl->aging_failed) { -+ temp = debugfs_create_int("aging_adj_volt", S_IRUGO, -+ ctrl->debugfs, &ctrl->aging_ref_adjust_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aging_adj_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("aging_succeeded", S_IRUGO, -+ ctrl->debugfs, &ctrl->aging_succeeded, &fops_bool_ro); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aging_succeeded debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("aging_failed", S_IRUGO, -+ ctrl->debugfs, &ctrl->aging_failed, &fops_bool_ro); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aging_failed debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_file("aging_trigger", S_IWUSR, -+ ctrl->debugfs, ctrl, -+ &cpr3_debug_trigger_aging_measurement_fops); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aging_trigger debugfs file creation failed\n"); -+ return; -+ } -+ } -+ -+ aggr_dir = debugfs_create_dir("max_aggregated_voltages", ctrl->debugfs); -+ if (IS_ERR_OR_NULL(aggr_dir)) { -+ cpr3_err(ctrl, "max_aggregated_voltages debugfs directory creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir, -+ &ctrl->aggr_corner.floor_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aggr floor_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir, -+ &ctrl->aggr_corner.ceiling_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aggr ceiling_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir, -+ &ctrl->aggr_corner.open_loop_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aggr open_loop_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir, -+ &ctrl->aggr_corner.last_volt); -+ if (IS_ERR_OR_NULL(temp)) { -+ cpr3_err(ctrl, "aggr last_volt debugfs file creation failed\n"); -+ return; -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) -+ cpr3_regulator_debugfs_thread_add(&ctrl->thread[i]); -+} -+ -+/** -+ * cpr3_regulator_debugfs_ctrl_remove() - remove debugfs files for the CPR -+ * controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Note, this function must be called after the controller has been removed from -+ * cpr3_controller_list and while the cpr3_controller_list_mutex lock is held. -+ * -+ * Return: none -+ */ -+static void cpr3_regulator_debugfs_ctrl_remove(struct cpr3_controller *ctrl) -+{ -+ if (list_empty(&cpr3_controller_list)) { -+ debugfs_remove_recursive(cpr3_debugfs_base); -+ cpr3_debugfs_base = NULL; -+ } else { -+ debugfs_remove_recursive(ctrl->debugfs); -+ } -+} -+ -+/** -+ * cpr3_regulator_init_ctrl_data() - performs initialization of CPR controller -+ * elements -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_init_ctrl_data(struct cpr3_controller *ctrl) -+{ -+ /* Read the initial vdd voltage from hardware. */ -+ ctrl->aggr_corner.last_volt -+ = regulator_get_voltage(ctrl->vdd_regulator); -+ if (ctrl->aggr_corner.last_volt < 0) { -+ cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", -+ ctrl->aggr_corner.last_volt); -+ return ctrl->aggr_corner.last_volt; -+ } -+ ctrl->aggr_corner.open_loop_volt = ctrl->aggr_corner.last_volt; -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_init_vreg_data() - performs initialization of common CPR3 -+ * regulator elements and validate aging configurations -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_init_vreg_data(struct cpr3_regulator *vreg) -+{ -+ int i, j; -+ bool init_aging; -+ -+ vreg->current_corner = CPR3_REGULATOR_CORNER_INVALID; -+ vreg->last_closed_loop_corner = CPR3_REGULATOR_CORNER_INVALID; -+ -+ init_aging = vreg->aging_allowed && vreg->thread->ctrl->aging_required; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; -+ vreg->corner[i].irq_en = CPR3_IRQ_UP | CPR3_IRQ_DOWN; -+ -+ vreg->corner[i].ro_mask = 0; -+ for (j = 0; j < CPR3_RO_COUNT; j++) { -+ if (vreg->corner[i].target_quot[j] == 0) -+ vreg->corner[i].ro_mask |= BIT(j); -+ } -+ -+ if (init_aging) { -+ vreg->corner[i].unaged_floor_volt -+ = vreg->corner[i].floor_volt; -+ vreg->corner[i].unaged_ceiling_volt -+ = vreg->corner[i].ceiling_volt; -+ vreg->corner[i].unaged_open_loop_volt -+ = vreg->corner[i].open_loop_volt; -+ } -+ -+ if (vreg->aging_allowed) { -+ if (vreg->corner[i].unaged_floor_volt <= 0) { -+ cpr3_err(vreg, "invalid unaged_floor_volt[%d] = %d\n", -+ i, vreg->corner[i].unaged_floor_volt); -+ return -EINVAL; -+ } -+ if (vreg->corner[i].unaged_ceiling_volt <= 0) { -+ cpr3_err(vreg, "invalid unaged_ceiling_volt[%d] = %d\n", -+ i, vreg->corner[i].unaged_ceiling_volt); -+ return -EINVAL; -+ } -+ if (vreg->corner[i].unaged_open_loop_volt <= 0) { -+ cpr3_err(vreg, "invalid unaged_open_loop_volt[%d] = %d\n", -+ i, vreg->corner[i].unaged_open_loop_volt); -+ return -EINVAL; -+ } -+ } -+ } -+ -+ if (vreg->aging_allowed && vreg->corner[vreg->aging_corner].ceiling_volt -+ > vreg->thread->ctrl->aging_ref_volt) { -+ cpr3_err(vreg, "aging corner %d ceiling voltage = %d > aging ref voltage = %d uV\n", -+ vreg->aging_corner, -+ vreg->corner[vreg->aging_corner].ceiling_volt, -+ vreg->thread->ctrl->aging_ref_volt); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_suspend() - perform common required CPR3 power down steps -+ * before the system enters suspend -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_regulator_suspend(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ mutex_lock(&ctrl->lock); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ mutex_unlock(&ctrl->lock); -+ return rc; -+ } -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ rc = cpr3_closed_loop_disable(ctrl); -+ if (rc) -+ cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); -+ -+ ctrl->cpr_suspended = true; -+ -+ mutex_unlock(&ctrl->lock); -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_resume() - perform common required CPR3 power up steps after -+ * the system resumes from suspend -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_regulator_resume(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ mutex_lock(&ctrl->lock); -+ -+ ctrl->cpr_suspended = false; -+ rc = cpr3_regulator_update_ctrl_state(ctrl); -+ if (rc) -+ cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); -+ -+ mutex_unlock(&ctrl->lock); -+ return 0; -+} -+ -+/** -+ * cpr3_regulator_validate_controller() - verify the data passed in via the -+ * cpr3_controller data structure -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_regulator_validate_controller(struct cpr3_controller *ctrl) -+{ -+ struct cpr3_thread *thread; -+ struct cpr3_regulator *vreg; -+ int i, j, allow_boost_vreg_count = 0; -+ -+ if (!ctrl->vdd_regulator) { -+ cpr3_err(ctrl, "vdd regulator missing\n"); -+ return -EINVAL; -+ } else if (ctrl->sensor_count <= 0 -+ || ctrl->sensor_count > CPR3_MAX_SENSOR_COUNT) { -+ cpr3_err(ctrl, "invalid CPR sensor count=%d\n", -+ ctrl->sensor_count); -+ return -EINVAL; -+ } else if (!ctrl->sensor_owner) { -+ cpr3_err(ctrl, "CPR sensor ownership table missing\n"); -+ return -EINVAL; -+ } -+ -+ if (ctrl->aging_required) { -+ for (i = 0; i < ctrl->aging_sensor_count; i++) { -+ if (ctrl->aging_sensor[i].sensor_id -+ >= ctrl->sensor_count) { -+ cpr3_err(ctrl, "aging_sensor[%d] id=%u is not in the value range 0-%d", -+ i, ctrl->aging_sensor[i].sensor_id, -+ ctrl->sensor_count - 1); -+ return -EINVAL; -+ } -+ } -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ thread = &ctrl->thread[i]; -+ for (j = 0; j < thread->vreg_count; j++) { -+ vreg = &thread->vreg[j]; -+ if (vreg->allow_boost) -+ allow_boost_vreg_count++; -+ } -+ } -+ -+ if (allow_boost_vreg_count > 1) { -+ /* -+ * Boost feature is not allowed to be used for more -+ * than one CPR3 regulator of a CPR3 controller. -+ */ -+ cpr3_err(ctrl, "Boost feature is enabled for more than one regulator\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_panic_callback() - panic notification callback function. This function -+ * is invoked when a kernel panic occurs. -+ * @nfb: Notifier block pointer of CPR3 controller -+ * @event: Value passed unmodified to notifier function -+ * @data: Pointer passed unmodified to notifier function -+ * -+ * Return: NOTIFY_OK -+ */ -+static int cpr3_panic_callback(struct notifier_block *nfb, -+ unsigned long event, void *data) -+{ -+ struct cpr3_controller *ctrl = container_of(nfb, -+ struct cpr3_controller, panic_notifier); -+ struct cpr3_panic_regs_info *regs_info = ctrl->panic_regs_info; -+ struct cpr3_reg_info *reg; -+ int i = 0; -+ -+ for (i = 0; i < regs_info->reg_count; i++) { -+ reg = &(regs_info->regs[i]); -+ reg->value = readl_relaxed(reg->virt_addr); -+ pr_err("%s[0x%08x] = 0x%08x\n", reg->name, reg->addr, -+ reg->value); -+ } -+ /* -+ * Barrier to ensure that the information has been updated in the -+ * structure. -+ */ -+ mb(); -+ -+ return NOTIFY_OK; -+} -+ -+/** -+ * cpr3_regulator_register() - register the regulators for a CPR3 controller and -+ * perform CPR hardware initialization -+ * @pdev: Platform device pointer for the CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ int i, j, rc; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "%s: Device tree node is missing\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (!ctrl || !ctrl->name) { -+ dev_err(dev, "%s: CPR controller data is missing\n", __func__); -+ return -EINVAL; -+ } -+ -+ rc = cpr3_regulator_validate_controller(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "controller validation failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ mutex_init(&ctrl->lock); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpr_ctrl"); -+ if (!res || !res->start) { -+ cpr3_err(ctrl, "CPR controller address is missing\n"); -+ return -ENXIO; -+ } -+ ctrl->cpr_ctrl_base = devm_ioremap(dev, res->start, resource_size(res)); -+ -+ if (ctrl->aging_possible_mask) { -+ /* -+ * Aging possible register address is required if an aging -+ * possible mask has been specified. -+ */ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "aging_allowed"); -+ if (!res || !res->start) { -+ cpr3_err(ctrl, "CPR aging allowed address is missing\n"); -+ return -ENXIO; -+ } -+ ctrl->aging_possible_reg = devm_ioremap(dev, res->start, -+ resource_size(res)); -+ } -+ -+ ctrl->irq = platform_get_irq_byname(pdev, "cpr"); -+ if (ctrl->irq < 0) { -+ cpr3_err(ctrl, "missing CPR interrupt\n"); -+ return ctrl->irq; -+ } -+ -+ if (ctrl->supports_hw_closed_loop) { -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ ctrl->ceiling_irq = platform_get_irq_byname(pdev, -+ "ceiling"); -+ if (ctrl->ceiling_irq < 0) { -+ cpr3_err(ctrl, "missing ceiling interrupt\n"); -+ return ctrl->ceiling_irq; -+ } -+ } -+ } -+ -+ rc = cpr3_regulator_init_ctrl_data(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ rc = cpr3_regulator_init_vreg_data( -+ &ctrl->thread[i].vreg[j]); -+ if (rc) -+ return rc; -+ cpr3_print_quots(&ctrl->thread[i].vreg[j]); -+ } -+ } -+ -+ /* -+ * Add the maximum possible aging voltage margin until it is possible -+ * to perform an aging measurement. -+ */ -+ if (ctrl->aging_required) -+ cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); -+ -+ rc = cpr3_regulator_init_ctrl(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "CPR controller initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ /* Register regulator devices for all threads. */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ rc = cpr3_regulator_vreg_register( -+ &ctrl->thread[i].vreg[j]); -+ if (rc) { -+ cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n", -+ rc); -+ goto free_regulators; -+ } -+ } -+ } -+ -+ rc = devm_request_threaded_irq(dev, ctrl->irq, NULL, -+ cpr3_irq_handler, -+ IRQF_ONESHOT | -+ IRQF_TRIGGER_RISING, -+ "cpr3", ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not request IRQ %d, rc=%d\n", -+ ctrl->irq, rc); -+ goto free_regulators; -+ } -+ -+ if (ctrl->supports_hw_closed_loop && -+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { -+ rc = devm_request_threaded_irq(dev, ctrl->ceiling_irq, NULL, -+ cpr3_ceiling_irq_handler, -+ IRQF_ONESHOT | IRQF_TRIGGER_RISING, -+ "cpr3_ceiling", ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "could not request ceiling IRQ %d, rc=%d\n", -+ ctrl->ceiling_irq, rc); -+ goto free_regulators; -+ } -+ } -+ -+ mutex_lock(&cpr3_controller_list_mutex); -+ cpr3_regulator_debugfs_ctrl_add(ctrl); -+ list_add(&ctrl->list, &cpr3_controller_list); -+ mutex_unlock(&cpr3_controller_list_mutex); -+ -+ if (ctrl->panic_regs_info) { -+ /* Register panic notification call back */ -+ ctrl->panic_notifier.notifier_call = cpr3_panic_callback; -+ atomic_notifier_chain_register(&panic_notifier_list, -+ &ctrl->panic_notifier); -+ } -+ -+ return 0; -+ -+free_regulators: -+ for (i = 0; i < ctrl->thread_count; i++) -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) -+ if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev)) -+ regulator_unregister( -+ ctrl->thread[i].vreg[j].rdev); -+ return rc; -+} -+ -+/** -+ * cpr3_open_loop_regulator_register() - register the regulators for a CPR3 -+ * controller which will always work in Open loop and -+ * won't support close loop. -+ * @pdev: Platform device pointer for the CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_open_loop_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl) -+{ -+ struct device *dev = &pdev->dev; -+ struct cpr3_regulator *vreg; -+ int i, j, rc; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "%s: Device tree node is missing\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (!ctrl || !ctrl->name) { -+ dev_err(dev, "%s: CPR controller data is missing\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (!ctrl->vdd_regulator) { -+ cpr3_err(ctrl, "vdd regulator missing\n"); -+ return -EINVAL; -+ } -+ -+ mutex_init(&ctrl->lock); -+ -+ rc = cpr3_regulator_init_ctrl_data(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ vreg = &ctrl->thread[i].vreg[j]; -+ vreg->corner[i].last_volt = -+ vreg->corner[i].open_loop_volt; -+ } -+ } -+ -+ /* Register regulator devices for all threads. */ -+ for (i = 0; i < ctrl->thread_count; i++) { -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) { -+ rc = cpr3_regulator_vreg_register( -+ &ctrl->thread[i].vreg[j]); -+ if (rc) { -+ cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n", -+ rc); -+ goto free_regulators; -+ } -+ } -+ } -+ -+ mutex_lock(&cpr3_controller_list_mutex); -+ list_add(&ctrl->list, &cpr3_controller_list); -+ mutex_unlock(&cpr3_controller_list_mutex); -+ -+ return 0; -+ -+free_regulators: -+ for (i = 0; i < ctrl->thread_count; i++) -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) -+ if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev)) -+ regulator_unregister( -+ ctrl->thread[i].vreg[j].rdev); -+ return rc; -+} -+ -+/** -+ * cpr3_regulator_unregister() - unregister the regulators for a CPR3 controller -+ * and perform CPR hardware shutdown -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_regulator_unregister(struct cpr3_controller *ctrl) -+{ -+ int i, j, rc = 0; -+ -+ mutex_lock(&cpr3_controller_list_mutex); -+ list_del(&ctrl->list); -+ cpr3_regulator_debugfs_ctrl_remove(ctrl); -+ mutex_unlock(&cpr3_controller_list_mutex); -+ -+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { -+ rc = cpr3_ctrl_clear_cpr4_config(ctrl); -+ if (rc) -+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", -+ rc); -+ } -+ -+ cpr3_ctrl_loop_disable(ctrl); -+ -+ cpr3_closed_loop_disable(ctrl); -+ -+ if (ctrl->vdd_limit_regulator) { -+ regulator_disable(ctrl->vdd_limit_regulator); -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) -+ regulator_unregister(ctrl->thread[i].vreg[j].rdev); -+ -+ if (ctrl->panic_notifier.notifier_call) -+ atomic_notifier_chain_unregister(&panic_notifier_list, -+ &ctrl->panic_notifier); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_open_loop_regulator_unregister() - unregister the regulators for a CPR3 -+ * open loop controller and perform CPR hardware shutdown -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl) -+{ -+ int i, j; -+ -+ mutex_lock(&cpr3_controller_list_mutex); -+ list_del(&ctrl->list); -+ mutex_unlock(&cpr3_controller_list_mutex); -+ -+ if (ctrl->vdd_limit_regulator) { -+ regulator_disable(ctrl->vdd_limit_regulator); -+ } -+ -+ for (i = 0; i < ctrl->thread_count; i++) -+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) -+ regulator_unregister(ctrl->thread[i].vreg[j].rdev); -+ -+ if (ctrl->panic_notifier.notifier_call) -+ atomic_notifier_chain_unregister(&panic_notifier_list, -+ &ctrl->panic_notifier); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/regulator/cpr3-regulator.h -@@ -0,0 +1,1211 @@ -+/* -+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __REGULATOR_CPR3_REGULATOR_H__ -+#define __REGULATOR_CPR3_REGULATOR_H__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct cpr3_controller; -+struct cpr3_thread; -+ -+/** -+ * struct cpr3_fuse_param - defines one contiguous segment of a fuse parameter -+ * that is contained within a given row. -+ * @row: Fuse row number -+ * @bit_start: The first bit within the row of the fuse parameter segment -+ * @bit_end: The last bit within the row of the fuse parameter segment -+ * -+ * Each fuse row is 64 bits in length. bit_start and bit_end may take values -+ * from 0 to 63. bit_start must be less than or equal to bit_end. -+ */ -+struct cpr3_fuse_param { -+ unsigned row; -+ unsigned bit_start; -+ unsigned bit_end; -+}; -+ -+/* Each CPR3 sensor has 16 ring oscillators */ -+#define CPR3_RO_COUNT 16 -+ -+/* The maximum number of sensors that can be present on a single CPR loop. */ -+#define CPR3_MAX_SENSOR_COUNT 256 -+ -+/* This constant is used when allocating array printing buffers. */ -+#define MAX_CHARS_PER_INT 10 -+ -+/** -+ * struct cpr4_sdelta - CPR4 controller specific data structure for the sdelta -+ * adjustment table which is used to adjust the VDD supply -+ * voltage automatically based upon the temperature and/or -+ * the number of online CPU cores. -+ * @allow_core_count_adj: Core count adjustments are allowed. -+ * @allow_temp_adj: Temperature based adjustments are allowed. -+ * @max_core_count: Maximum number of cores considered for core count -+ * adjustment logic. -+ * @temp_band_count: Number of temperature bands considered for temperature -+ * based adjustment logic. -+ * @cap_volt: CAP in uV to apply to SDELTA margins with multiple -+ * cpr3-regulators defined for single controller. -+ * @table: SDELTA table with per-online-core and temperature based -+ * adjustments of size (max_core_count * temp_band_count) -+ * Outer: core count -+ * Inner: temperature band -+ * Each element has units of VDD supply steps. Positive -+ * values correspond to a reduction in voltage and negative -+ * value correspond to an increase (this follows the SDELTA -+ * register semantics). -+ * @allow_boost: Voltage boost allowed. -+ * @boost_num_cores: The number of online cores at which the boost voltage -+ * adjustments will be applied -+ * @boost_table: SDELTA table with boost voltage adjustments of size -+ * temp_band_count. Each element has units of VDD supply -+ * steps. Positive values correspond to a reduction in -+ * voltage and negative value correspond to an increase -+ * (this follows the SDELTA register semantics). -+ */ -+struct cpr4_sdelta { -+ bool allow_core_count_adj; -+ bool allow_temp_adj; -+ int max_core_count; -+ int temp_band_count; -+ int cap_volt; -+ int *table; -+ bool allow_boost; -+ int boost_num_cores; -+ int *boost_table; -+}; -+ -+/** -+ * struct cpr3_corner - CPR3 virtual voltage corner data structure -+ * @floor_volt: CPR closed-loop floor voltage in microvolts -+ * @ceiling_volt: CPR closed-loop ceiling voltage in microvolts -+ * @open_loop_volt: CPR open-loop voltage (i.e. initial voltage) in -+ * microvolts -+ * @last_volt: Last known settled CPR closed-loop voltage which is used -+ * when switching to a new corner -+ * @abs_ceiling_volt: The absolute CPR closed-loop ceiling voltage in -+ * microvolts. This is used to limit the ceiling_volt -+ * value when it is increased as a result of aging -+ * adjustment. -+ * @unaged_floor_volt: The CPR closed-loop floor voltage in microvolts before -+ * any aging adjustment is performed -+ * @unaged_ceiling_volt: The CPR closed-loop ceiling voltage in microvolts -+ * before any aging adjustment is performed -+ * @unaged_open_loop_volt: The CPR open-loop voltage (i.e. initial voltage) in -+ * microvolts before any aging adjusment is performed -+ * @system_volt: The system-supply voltage in microvolts or corners or -+ * levels -+ * @mem_acc_volt: The mem-acc-supply voltage in corners -+ * @proc_freq: Processor frequency in Hertz. For CPR rev. 3 and 4 -+ * conrollers, this field is only used by platform specific -+ * CPR3 driver for interpolation. For CPRh-compliant -+ * controllers, this frequency is also utilized by the -+ * clock driver to determine the corner to CPU clock -+ * frequency mappings. -+ * @cpr_fuse_corner: Fused corner index associated with this virtual corner -+ * (only used by platform specific CPR3 driver for -+ * mapping purposes) -+ * @target_quot: Array of target quotient values to use for each ring -+ * oscillator (RO) for this corner. A value of 0 should be -+ * specified as the target quotient for each RO that is -+ * unused by this corner. -+ * @ro_scale: Array of CPR ring oscillator (RO) scaling factors. The -+ * scaling factor for each RO is defined from RO0 to RO15 -+ * with units of QUOT/V. A value of 0 may be specified for -+ * an RO that is unused. -+ * @ro_mask: Bitmap where each of the 16 LSBs indicate if the -+ * corresponding ROs should be masked for this corner -+ * @irq_en: Bitmap of the CPR interrupts to enable for this corner -+ * @aging_derate: The amount to derate the aging voltage adjustment -+ * determined for the reference corner in units of uV/mV. -+ * E.g. a value of 900 would imply that the adjustment for -+ * this corner should be 90% (900/1000) of that for the -+ * reference corner. -+ * @use_open_loop: Boolean indicating that open-loop (i.e CPR disabled) as -+ * opposed to closed-loop operation must be used for this -+ * corner on CPRh controllers. -+ * @sdelta: The CPR4 controller specific data for this corner. This -+ * field is applicable for CPR4 controllers. -+ * -+ * The value of last_volt is initialized inside of the cpr3_regulator_register() -+ * call with the open_loop_volt value. It can later be updated to the settled -+ * VDD supply voltage. The values for unaged_floor_volt, unaged_ceiling_volt, -+ * and unaged_open_loop_volt are initialized inside of cpr3_regulator_register() -+ * if ctrl->aging_required == true. These three values must be pre-initialized -+ * if cpr3_regulator_register() is called with ctrl->aging_required == false and -+ * ctrl->aging_succeeded == true. -+ * -+ * The values of ro_mask and irq_en are initialized inside of the -+ * cpr3_regulator_register() call. -+ */ -+struct cpr3_corner { -+ int floor_volt; -+ int ceiling_volt; -+ int cold_temp_open_loop_volt; -+ int normal_temp_open_loop_volt; -+ int open_loop_volt; -+ int last_volt; -+ int abs_ceiling_volt; -+ int unaged_floor_volt; -+ int unaged_ceiling_volt; -+ int unaged_open_loop_volt; -+ int system_volt; -+ int mem_acc_volt; -+ u32 proc_freq; -+ int cpr_fuse_corner; -+ u32 target_quot[CPR3_RO_COUNT]; -+ u32 ro_scale[CPR3_RO_COUNT]; -+ u32 ro_mask; -+ u32 irq_en; -+ int aging_derate; -+ bool use_open_loop; -+ struct cpr4_sdelta *sdelta; -+}; -+ -+/** -+ * struct cprh_corner_band - CPRh controller specific data structure which -+ * encapsulates the range of corners and the SDELTA -+ * adjustment table to be applied to the corners within -+ * the min and max bounds of the corner band. -+ * @corner: Corner number which defines the corner band boundary -+ * @sdelta: The SDELTA adjustment table which contains core-count -+ * and temp based margin adjustments that are applicable -+ * to the corner band. -+ */ -+struct cprh_corner_band { -+ int corner; -+ struct cpr4_sdelta *sdelta; -+}; -+ -+/** -+ * struct cpr3_fuse_parameters - CPR4 fuse specific data structure which has -+ * the required fuse parameters need for Close Loop CPR -+ * @(*apss_ro_sel_param)[2]: Pointer to RO select fuse details -+ * @(*apss_init_voltage_param)[2]: Pointer to Target voltage fuse details -+ * @(*apss_target_quot_param)[2]: Pointer to Target quot fuse details -+ * @(*apss_quot_offset_param)[2]: Pointer to quot offset fuse details -+ * @cpr_fusing_rev_param: Pointer to CPR revision fuse details -+ * @apss_speed_bin_param: Pointer to Speed bin fuse details -+ * @cpr_boost_fuse_cfg_param: Pointer to Boost fuse cfg details -+ * @apss_boost_fuse_volt_param: Pointer to Boost fuse volt details -+ * @misc_fuse_volt_adj_param: Pointer to Misc fuse volt fuse details -+ */ -+struct cpr3_fuse_parameters { -+ struct cpr3_fuse_param (*apss_ro_sel_param)[2]; -+ struct cpr3_fuse_param (*apss_init_voltage_param)[2]; -+ struct cpr3_fuse_param (*apss_target_quot_param)[2]; -+ struct cpr3_fuse_param (*apss_quot_offset_param)[2]; -+ struct cpr3_fuse_param *cpr_fusing_rev_param; -+ struct cpr3_fuse_param *apss_speed_bin_param; -+ struct cpr3_fuse_param *cpr_boost_fuse_cfg_param; -+ struct cpr3_fuse_param *apss_boost_fuse_volt_param; -+ struct cpr3_fuse_param *misc_fuse_volt_adj_param; -+}; -+ -+struct cpr4_mem_acc_func { -+ void (*set_mem_acc)(struct regulator_dev *); -+ void (*clear_mem_acc)(struct regulator_dev *); -+}; -+ -+/** -+ * struct cpr4_reg_data - CPR4 regulator specific data structure which is -+ * target specific -+ * @cpr_valid_fuse_count: Number of valid fuse corners -+ * @fuse_ref_volt: Pointer to fuse reference voltage -+ * @fuse_step_volt: CPR step voltage available in fuse -+ * @cpr_clk_rate: CPR clock rate -+ * @boost_fuse_ref_volt: Boost fuse reference voltage -+ * @boost_ceiling_volt: Boost ceiling voltage -+ * @boost_floor_volt: Boost floor voltage -+ * @cpr3_fuse_params: Pointer to CPR fuse parameters -+ * @mem_acc_funcs: Pointer to MEM ACC set/clear functions -+ **/ -+struct cpr4_reg_data { -+ u32 cpr_valid_fuse_count; -+ int *fuse_ref_volt; -+ u32 fuse_step_volt; -+ u32 cpr_clk_rate; -+ int boost_fuse_ref_volt; -+ int boost_ceiling_volt; -+ int boost_floor_volt; -+ struct cpr3_fuse_parameters *cpr3_fuse_params; -+ struct cpr4_mem_acc_func *mem_acc_funcs; -+}; -+/** -+ * struct cpr3_reg_data - CPR3 regulator specific data structure which is -+ * target specific -+ * @cpr_valid_fuse_count: Number of valid fuse corners -+ * @(*init_voltage_param)[2]: Pointer to Target voltage fuse details -+ * @fuse_ref_volt: Pointer to fuse reference voltage -+ * @fuse_step_volt: CPR step voltage available in fuse -+ * @cpr_clk_rate: CPR clock rate -+ * @cpr3_fuse_params: Pointer to CPR fuse parameters -+ **/ -+struct cpr3_reg_data { -+ u32 cpr_valid_fuse_count; -+ struct cpr3_fuse_param (*init_voltage_param)[2]; -+ int *fuse_ref_volt; -+ u32 fuse_step_volt; -+ u32 cpr_clk_rate; -+}; -+ -+/** -+ * struct cpr3_regulator - CPR3 logical regulator instance associated with a -+ * given CPR3 hardware thread -+ * @of_node: Device node associated with the device tree child node -+ * of this CPR3 regulator -+ * @thread: Pointer to the CPR3 thread which manages this CPR3 -+ * regulator -+ * @name: Unique name for this CPR3 regulator which is filled -+ * using the device tree regulator-name property -+ * @rdesc: Regulator description for this CPR3 regulator -+ * @rdev: Regulator device pointer for the regulator registered -+ * for this CPR3 regulator -+ * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used -+ * to manage memory circuitry settings based upon CPR3 -+ * regulator output voltage. -+ * @corner: Array of all corners supported by this CPR3 regulator -+ * @corner_count: The number of elements in the corner array -+ * @corner_band: Array of all corner bands supported by CPRh compatible -+ * controllers -+ * @cpr4_regulator_data Target specific cpr4 regulator data -+ * @cpr3_regulator_data Target specific cpr3 regulator data -+ * @corner_band_count: The number of elements in the corner band array -+ * @platform_fuses: Pointer to platform specific CPR fuse data (only used by -+ * platform specific CPR3 driver) -+ * @speed_bin_fuse: Value read from the speed bin fuse parameter -+ * @speed_bins_supported: The number of speed bins supported by the device tree -+ * configuration for this CPR3 regulator -+ * @cpr_rev_fuse: Value read from the CPR fusing revision fuse parameter -+ * @fuse_combo: Platform specific enum value identifying the specific -+ * combination of fuse values found on a given chip -+ * @fuse_combos_supported: The number of fuse combinations supported by the -+ * device tree configuration for this CPR3 regulator -+ * @fuse_corner_count: Number of corners defined by fuse parameters -+ * @fuse_corner_map: Array of length fuse_corner_count which specifies the -+ * highest corner associated with each fuse corner. Note -+ * that each element must correspond to a valid corner -+ * and that element values must be strictly increasing. -+ * Also, it is acceptable for the lowest fuse corner to map -+ * to a corner other than the lowest. Likewise, it is -+ * acceptable for the highest fuse corner to map to a -+ * corner other than the highest. -+ * @fuse_combo_corner_sum: The sum of the corner counts across all fuse combos -+ * @fuse_combo_offset: The device tree property array offset for the selected -+ * fuse combo -+ * @speed_bin_corner_sum: The sum of the corner counts across all speed bins -+ * This may be specified as 0 if per speed bin parsing -+ * support is not required. -+ * @speed_bin_offset: The device tree property array offset for the selected -+ * speed bin -+ * @fuse_combo_corner_band_sum: The sum of the corner band counts across all -+ * fuse combos -+ * @fuse_combo_corner_band_offset: The device tree property array offset for -+ * the corner band count corresponding to the selected -+ * fuse combo -+ * @speed_bin_corner_band_sum: The sum of the corner band counts across all -+ * speed bins. This may be specified as 0 if per speed bin -+ * parsing support is not required -+ * @speed_bin_corner_band_offset: The device tree property array offset for the -+ * corner band count corresponding to the selected speed -+ * bin -+ * @pd_bypass_mask: Bit mask of power domains associated with this CPR3 -+ * regulator -+ * @dynamic_floor_corner: Index identifying the voltage corner for the CPR3 -+ * regulator whose last_volt value should be used as the -+ * global CPR floor voltage if all of the power domains -+ * associated with this CPR3 regulator are bypassed -+ * @uses_dynamic_floor: Boolean flag indicating that dynamic_floor_corner should -+ * be utilized for the CPR3 regulator -+ * @current_corner: Index identifying the currently selected voltage corner -+ * for the CPR3 regulator or less than 0 if no corner has -+ * been requested -+ * @last_closed_loop_corner: Index identifying the last voltage corner for the -+ * CPR3 regulator which was configured when operating in -+ * CPR closed-loop mode or less than 0 if no corner has -+ * been requested. CPR registers are only written to when -+ * using closed-loop mode. -+ * @aggregated: Boolean flag indicating that this CPR3 regulator -+ * participated in the last aggregation event -+ * @debug_corner: Index identifying voltage corner used for displaying -+ * corner configuration values in debugfs -+ * @vreg_enabled: Boolean defining the enable state of the CPR3 -+ * regulator's regulator within the regulator framework. -+ * @aging_allowed: Boolean defining if CPR aging adjustments are allowed -+ * for this CPR3 regulator given the fuse combo of the -+ * device -+ * @aging_allow_open_loop_adj: Boolean defining if the open-loop voltage of each -+ * corner of this regulator should be adjusted as a result -+ * of an aging measurement. This flag can be set to false -+ * when the open-loop voltage adjustments have been -+ * specified such that they include the maximum possible -+ * aging adjustment. This flag is only used if -+ * aging_allowed == true. -+ * @aging_corner: The corner that should be configured for this regulator -+ * when an aging measurement is performed. -+ * @aging_max_adjust_volt: The maximum aging voltage margin in microvolts that -+ * may be added to the target quotients of this regulator. -+ * A value of 0 may be specified if this regulator does not -+ * require any aging adjustment. -+ * @allow_core_count_adj: Core count adjustments are allowed for this regulator. -+ * @allow_temp_adj: Temperature based adjustments are allowed for this -+ * regulator. -+ * @max_core_count: Maximum number of cores considered for core count -+ * adjustment logic. -+ * @allow_boost: Voltage boost allowed for this regulator. -+ * -+ * This structure contains both configuration and runtime state data. The -+ * elements current_corner, last_closed_loop_corner, aggregated, debug_corner, -+ * and vreg_enabled are state variables. -+ */ -+struct cpr3_regulator { -+ struct device_node *of_node; -+ struct cpr3_thread *thread; -+ const char *name; -+ struct regulator_desc rdesc; -+ struct regulator_dev *rdev; -+ struct regulator *mem_acc_regulator; -+ struct cpr3_corner *corner; -+ int corner_count; -+ struct cprh_corner_band *corner_band; -+ struct cpr4_reg_data *cpr4_regulator_data; -+ struct cpr3_reg_data *cpr3_regulator_data; -+ u32 corner_band_count; -+ -+ void *platform_fuses; -+ int speed_bin_fuse; -+ int speed_bins_supported; -+ int cpr_rev_fuse; -+ int part_type; -+ int part_type_supported; -+ int fuse_combo; -+ int fuse_combos_supported; -+ int fuse_corner_count; -+ int *fuse_corner_map; -+ int fuse_combo_corner_sum; -+ int fuse_combo_offset; -+ int speed_bin_corner_sum; -+ int speed_bin_offset; -+ int fuse_combo_corner_band_sum; -+ int fuse_combo_corner_band_offset; -+ int speed_bin_corner_band_sum; -+ int speed_bin_corner_band_offset; -+ u32 pd_bypass_mask; -+ int dynamic_floor_corner; -+ bool uses_dynamic_floor; -+ -+ int current_corner; -+ int last_closed_loop_corner; -+ bool aggregated; -+ int debug_corner; -+ bool vreg_enabled; -+ -+ bool aging_allowed; -+ bool aging_allow_open_loop_adj; -+ int aging_corner; -+ int aging_max_adjust_volt; -+ -+ bool allow_core_count_adj; -+ bool allow_temp_adj; -+ int max_core_count; -+ bool allow_boost; -+}; -+ -+/** -+ * struct cpr3_thread - CPR3 hardware thread data structure -+ * @thread_id: Hardware thread ID -+ * @of_node: Device node associated with the device tree child node -+ * of this CPR3 thread -+ * @ctrl: Pointer to the CPR3 controller which manages this thread -+ * @vreg: Array of CPR3 regulators handled by the CPR3 thread -+ * @vreg_count: Number of elements in the vreg array -+ * @aggr_corner: CPR corner containing the in process aggregated voltage -+ * and target quotient configurations which will be applied -+ * @last_closed_loop_aggr_corner: CPR corner containing the most recent -+ * configurations which were written into hardware -+ * registers when operating in closed loop mode (i.e. with -+ * CPR enabled) -+ * @consecutive_up: The number of consecutive CPR step up events needed to -+ * to trigger an up interrupt -+ * @consecutive_down: The number of consecutive CPR step down events needed to -+ * to trigger a down interrupt -+ * @up_threshold: The number CPR error steps required to generate an up -+ * event -+ * @down_threshold: The number CPR error steps required to generate a down -+ * event -+ * -+ * This structure contains both configuration and runtime state data. The -+ * elements aggr_corner and last_closed_loop_aggr_corner are state variables. -+ */ -+struct cpr3_thread { -+ u32 thread_id; -+ struct device_node *of_node; -+ struct cpr3_controller *ctrl; -+ struct cpr3_regulator *vreg; -+ int vreg_count; -+ struct cpr3_corner aggr_corner; -+ struct cpr3_corner last_closed_loop_aggr_corner; -+ -+ u32 consecutive_up; -+ u32 consecutive_down; -+ u32 up_threshold; -+ u32 down_threshold; -+}; -+ -+/* Per CPR controller data */ -+/** -+ * enum cpr3_mem_acc_corners - Constants which define the number of mem-acc -+ * regulator corners available in the mem-acc corner map array. -+ * %CPR3_MEM_ACC_LOW_CORNER: Index in mem-acc corner map array mapping to the -+ * mem-acc regulator corner -+ * to be used for low voltage vdd supply -+ * %CPR3_MEM_ACC_HIGH_CORNER: Index in mem-acc corner map array mapping to the -+ * mem-acc regulator corner to be used for high -+ * voltage vdd supply -+ * %CPR3_MEM_ACC_CORNERS: Number of elements in the mem-acc corner map -+ * array -+ */ -+enum cpr3_mem_acc_corners { -+ CPR3_MEM_ACC_LOW_CORNER = 0, -+ CPR3_MEM_ACC_HIGH_CORNER = 1, -+ CPR3_MEM_ACC_CORNERS = 2, -+}; -+ -+/** -+ * enum cpr3_count_mode - CPR3 controller count mode which defines the -+ * method that CPR sensor data is acquired -+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_MIN: Capture all CPR sensor readings -+ * simultaneously and report the minimum -+ * value seen in successive measurements -+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_MAX: Capture all CPR sensor readings -+ * simultaneously and report the maximum -+ * value seen in successive measurements -+ * %CPR3_COUNT_MODE_STAGGERED: Read one sensor at a time in a -+ * sequential fashion -+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_AGE: Capture all CPR aging sensor readings -+ * simultaneously. -+ */ -+enum cpr3_count_mode { -+ CPR3_COUNT_MODE_ALL_AT_ONCE_MIN = 0, -+ CPR3_COUNT_MODE_ALL_AT_ONCE_MAX = 1, -+ CPR3_COUNT_MODE_STAGGERED = 2, -+ CPR3_COUNT_MODE_ALL_AT_ONCE_AGE = 3, -+}; -+ -+/** -+ * enum cpr_controller_type - supported CPR controller hardware types -+ * %CPR_CTRL_TYPE_CPR3: HW has CPR3 controller -+ * %CPR_CTRL_TYPE_CPR4: HW has CPR4 controller -+ */ -+enum cpr_controller_type { -+ CPR_CTRL_TYPE_CPR3, -+ CPR_CTRL_TYPE_CPR4, -+}; -+ -+/** -+ * cpr_setting - supported CPR global settings -+ * %CPR_DEFAULT: default mode from dts will be used -+ * %CPR_DISABLED: ceiling voltage will be used for all the corners -+ * %CPR_OPEN_LOOP_EN: CPR will work in OL -+ * %CPR_CLOSED_LOOP_EN: CPR will work in CL, if supported -+ */ -+enum cpr_setting { -+ CPR_DEFAULT = 0, -+ CPR_DISABLED = 1, -+ CPR_OPEN_LOOP_EN = 2, -+ CPR_CLOSED_LOOP_EN = 3, -+}; -+ -+/** -+ * struct cpr3_aging_sensor_info - CPR3 aging sensor information -+ * @sensor_id The index of the CPR3 sensor to be used in the aging -+ * measurement. -+ * @ro_scale The CPR ring oscillator (RO) scaling factor for the -+ * aging sensor with units of QUOT/V. -+ * @init_quot_diff: The fused quotient difference between aged and un-aged -+ * paths that was measured at manufacturing time. -+ * @measured_quot_diff: The quotient difference measured at runtime. -+ * @bypass_mask: Bit mask of the CPR sensors that must be bypassed during -+ * the aging measurement for this sensor -+ * -+ * This structure contains both configuration and runtime state data. The -+ * element measured_quot_diff is a state variable. -+ */ -+struct cpr3_aging_sensor_info { -+ u32 sensor_id; -+ u32 ro_scale; -+ int init_quot_diff; -+ int measured_quot_diff; -+ u32 bypass_mask[CPR3_MAX_SENSOR_COUNT / 32]; -+}; -+ -+/** -+ * struct cpr3_reg_info - Register information data structure -+ * @name: Register name -+ * @addr: Register physical address -+ * @value: Register content -+ * @virt_addr: Register virtual address -+ * -+ * This data structure is used to dump some critical register contents -+ * when the device crashes due to a kernel panic. -+ */ -+struct cpr3_reg_info { -+ const char *name; -+ u32 addr; -+ u32 value; -+ void __iomem *virt_addr; -+}; -+ -+/** -+ * struct cpr3_panic_regs_info - Data structure to dump critical register -+ * contents. -+ * @reg_count: Number of elements in the regs array -+ * @regs: Array of critical registers information -+ * -+ * This data structure is used to dump critical register contents when -+ * the device crashes due to a kernel panic. -+ */ -+struct cpr3_panic_regs_info { -+ int reg_count; -+ struct cpr3_reg_info *regs; -+}; -+ -+/** -+ * struct cpr3_controller - CPR3 controller data structure -+ * @dev: Device pointer for the CPR3 controller device -+ * @name: Unique name for the CPR3 controller -+ * @ctrl_id: Controller ID corresponding to the VDD supply number -+ * that this CPR3 controller manages. -+ * @cpr_ctrl_base: Virtual address of the CPR3 controller base register -+ * @fuse_base: Virtual address of fuse row 0 -+ * @aging_possible_reg: Virtual address of an optional platform-specific -+ * register that must be ready to determine if it is -+ * possible to perform an aging measurement. -+ * @list: list head used in a global cpr3-regulator list so that -+ * cpr3-regulator structs can be found easily in RAM dumps -+ * @thread: Array of CPR3 threads managed by the CPR3 controller -+ * @thread_count: Number of elements in the thread array -+ * @sensor_owner: Array of thread IDs indicating which thread owns a given -+ * CPR sensor -+ * @sensor_count: The number of CPR sensors found on the CPR loop managed -+ * by this CPR controller. Must be equal to the number of -+ * elements in the sensor_owner array -+ * @soc_revision: Revision number of the SoC. This may be unused by -+ * platforms that do not have different behavior for -+ * different SoC revisions. -+ * @lock: Mutex lock used to ensure mutual exclusion between -+ * all of the threads associated with the controller -+ * @vdd_regulator: Pointer to the VDD supply regulator which this CPR3 -+ * controller manages -+ * @system_regulator: Pointer to the optional system-supply regulator upon -+ * which the VDD supply regulator depends. -+ * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used -+ * to manage memory circuitry settings based upon the -+ * VDD supply output voltage. -+ * @vdd_limit_regulator: Pointer to the VDD supply limit regulator which is used -+ * for hardware closed-loop in order specify ceiling and -+ * floor voltage limits (platform specific) -+ * @system_supply_max_volt: Voltage in microvolts which corresponds to the -+ * absolute ceiling voltage of the system-supply -+ * @mem_acc_threshold_volt: mem-acc threshold voltage in microvolts -+ * @mem_acc_corner_map: mem-acc regulator corners mapping to low and high -+ * voltage mem-acc settings for the memories powered by -+ * this CPR3 controller and its associated CPR3 regulators -+ * @mem_acc_crossover_volt: Voltage in microvolts corresponding to the voltage -+ * that the VDD supply must be set to while a MEM ACC -+ * switch is in progress. This element must be initialized -+ * for CPRh controllers when a MEM ACC threshold voltage is -+ * defined. -+ * @core_clk: Pointer to the CPR3 controller core clock -+ * @iface_clk: Pointer to the CPR3 interface clock (platform specific) -+ * @bus_clk: Pointer to the CPR3 bus clock (platform specific) -+ * @irq: CPR interrupt number -+ * @irq_affinity_mask: The cpumask for the CPUs which the CPR interrupt should -+ * have affinity for -+ * @cpu_hotplug_notifier: CPU hotplug notifier used to reset IRQ affinity when a -+ * CPU is brought back online -+ * @ceiling_irq: Interrupt number for the interrupt that is triggered -+ * when hardware closed-loop attempts to exceed the ceiling -+ * voltage -+ * @apm: Handle to the array power mux (APM) -+ * @apm_threshold_volt: Voltage in microvolts which defines the threshold -+ * voltage to determine the APM supply selection for -+ * each corner -+ * @apm_crossover_volt: Voltage in microvolts corresponding to the voltage that -+ * the VDD supply must be set to while an APM switch is in -+ * progress. This element must be initialized for CPRh -+ * controllers when an APM threshold voltage is defined -+ * @apm_adj_volt: Minimum difference between APM threshold voltage and -+ * open-loop voltage which allows the APM threshold voltage -+ * to be used as a ceiling -+ * @apm_high_supply: APM supply to configure if VDD voltage is greater than -+ * or equal to the APM threshold voltage -+ * @apm_low_supply: APM supply to configure if the VDD voltage is less than -+ * the APM threshold voltage -+ * @base_volt: Minimum voltage in microvolts supported by the VDD -+ * supply managed by this CPR controller -+ * @corner_switch_delay_time: The delay time in nanoseconds used by the CPR -+ * controller to wait for voltage settling before -+ * acknowledging the OSM block after corner changes -+ * @cpr_clock_rate: CPR reference clock frequency in Hz. -+ * @sensor_time: The time in nanoseconds that each sensor takes to -+ * perform a measurement. -+ * @loop_time: The time in nanoseconds between consecutive CPR -+ * measurements. -+ * @up_down_delay_time: The time to delay in nanoseconds between consecutive CPR -+ * measurements when the last measurement recommended -+ * increasing or decreasing the vdd-supply voltage. -+ * (platform specific) -+ * @idle_clocks: Number of CPR reference clock ticks that the CPR -+ * controller waits in transitional states. -+ * @step_quot_init_min: The default minimum CPR step quotient value. The step -+ * quotient is the number of additional ring oscillator -+ * ticks observed when increasing one step in vdd-supply -+ * output voltage. -+ * @step_quot_init_max: The default maximum CPR step quotient value. -+ * @step_volt: Step size in microvolts between available set points -+ * of the VDD supply -+ * @down_error_step_limit: CPR4 hardware closed-loop down error step limit which -+ * defines the maximum number of VDD supply regulator steps -+ * that the voltage may be reduced as the result of a -+ * single CPR measurement. -+ * @up_error_step_limit: CPR4 hardware closed-loop up error step limit which -+ * defines the maximum number of VDD supply regulator steps -+ * that the voltage may be increased as the result of a -+ * single CPR measurement. -+ * @count_mode: CPR controller count mode -+ * @count_repeat: Number of times to perform consecutive sensor -+ * measurements when using all-at-once count modes. -+ * @proc_clock_throttle: Defines the processor clock frequency throttling -+ * register value to use. This can be used to reduce the -+ * clock frequency when a power domain exits a low power -+ * mode until CPR settles at a new voltage. -+ * (platform specific) -+ * @cpr_allowed_hw: Boolean which indicates if closed-loop CPR operation is -+ * permitted for a given chip based upon hardware fuse -+ * values -+ * @cpr_allowed_sw: Boolean which indicates if closed-loop CPR operation is -+ * permitted based upon software policies -+ * @supports_hw_closed_loop: Boolean which indicates if this CPR3/4 controller -+ * physically supports hardware closed-loop CPR operation -+ * @use_hw_closed_loop: Boolean which indicates that this controller will be -+ * using hardware closed-loop operation in place of -+ * software closed-loop operation. -+ * @ctrl_type: CPR controller type -+ * @saw_use_unit_mV: Boolean which indicates the unit used in SAW PVC -+ * interface is mV. -+ * @aggr_corner: CPR corner containing the most recently aggregated -+ * voltage configurations which are being used currently -+ * @cpr_enabled: Boolean which indicates that the CPR controller is -+ * enabled and operating in closed-loop mode. CPR clocks -+ * have been prepared and enabled whenever this flag is -+ * true. -+ * @last_corner_was_closed_loop: Boolean indicating if the last known corners -+ * were updated during closed loop operation. -+ * @cpr_suspended: Boolean which indicates that CPR has been temporarily -+ * disabled while enterring system suspend. -+ * @debugfs: Pointer to the debugfs directory of this CPR3 controller -+ * @aging_ref_volt: Reference voltage in microvolts to configure when -+ * performing CPR aging measurements. -+ * @aging_vdd_mode: vdd-supply regulator mode to configure before performing -+ * a CPR aging measurement. It should be one of -+ * REGULATOR_MODE_*. -+ * @aging_complete_vdd_mode: vdd-supply regulator mode to configure after -+ * performing a CPR aging measurement. It should be one of -+ * REGULATOR_MODE_*. -+ * @aging_ref_adjust_volt: The reference aging voltage margin in microvolts that -+ * should be added to the target quotients of the -+ * regulators managed by this controller after derating. -+ * @aging_required: Flag which indicates that a CPR aging measurement still -+ * needs to be performed for this CPR3 controller. -+ * @aging_succeeded: Flag which indicates that a CPR aging measurement has -+ * completed successfully. -+ * @aging_failed: Flag which indicates that a CPR aging measurement has -+ * failed to complete successfully. -+ * @aging_sensor: Array of CPR3 aging sensors which are used to perform -+ * aging measurements at a runtime. -+ * @aging_sensor_count: Number of elements in the aging_sensor array -+ * @aging_possible_mask: Optional bitmask used to mask off the -+ * aging_possible_reg register. -+ * @aging_possible_val: Optional value that the masked aging_possible_reg -+ * register must have in order for a CPR aging measurement -+ * to be possible. -+ * @step_quot_fixed: Fixed step quotient value used for target quotient -+ * adjustment if use_dynamic_step_quot is not set. -+ * This parameter is only relevant for CPR4 controllers -+ * when using the per-online-core or per-temperature -+ * adjustments. -+ * @initial_temp_band: Temperature band used for calculation of base-line -+ * target quotients (fused). -+ * @use_dynamic_step_quot: Boolean value which indicates that margin adjustment -+ * of target quotient will be based on the step quotient -+ * calculated dynamically in hardware for each RO. -+ * @allow_core_count_adj: Core count adjustments are allowed for this controller -+ * @allow_temp_adj: Temperature based adjustments are allowed for -+ * this controller -+ * @allow_boost: Voltage boost allowed for this controller. -+ * @temp_band_count: Number of temperature bands used for temperature based -+ * adjustment logic -+ * @temp_points: Array of temperature points in decidegrees Celsius used -+ * to specify the ranges for selected temperature bands. -+ * The array must have (temp_band_count - 1) elements -+ * allocated. -+ * @temp_sensor_id_start: Start ID of temperature sensors used for temperature -+ * based adjustments. -+ * @temp_sensor_id_end: End ID of temperature sensors used for temperature -+ * based adjustments. -+ * @voltage_settling_time: The time in nanoseconds that it takes for the -+ * VDD supply voltage to settle after being increased or -+ * decreased by step_volt microvolts which is used when -+ * SDELTA voltage margin adjustments are applied. -+ * @cpr_global_setting: Global setting for this CPR controller -+ * @panic_regs_info: Array of panic registers information which provides the -+ * list of registers to dump when the device crashes. -+ * @panic_notifier: Notifier block registered to global panic notifier list. -+ * -+ * This structure contains both configuration and runtime state data. The -+ * elements cpr_allowed_sw, use_hw_closed_loop, aggr_corner, cpr_enabled, -+ * last_corner_was_closed_loop, cpr_suspended, aging_ref_adjust_volt, -+ * aging_required, aging_succeeded, and aging_failed are state variables. -+ * -+ * The apm* elements do not need to be initialized if the VDD supply managed by -+ * the CPR3 controller does not utilize an APM. -+ * -+ * The elements step_quot_fixed, initial_temp_band, allow_core_count_adj, -+ * allow_temp_adj and temp* need to be initialized for CPR4 controllers which -+ * are using per-online-core or per-temperature adjustments. -+ */ -+struct cpr3_controller { -+ struct device *dev; -+ const char *name; -+ int ctrl_id; -+ void __iomem *cpr_ctrl_base; -+ void __iomem *fuse_base; -+ void __iomem *aging_possible_reg; -+ struct list_head list; -+ struct cpr3_thread *thread; -+ int thread_count; -+ u8 *sensor_owner; -+ int sensor_count; -+ int soc_revision; -+ struct mutex lock; -+ struct regulator *vdd_regulator; -+ struct regulator *system_regulator; -+ struct regulator *mem_acc_regulator; -+ struct regulator *vdd_limit_regulator; -+ int system_supply_max_volt; -+ int mem_acc_threshold_volt; -+ int mem_acc_corner_map[CPR3_MEM_ACC_CORNERS]; -+ int mem_acc_crossover_volt; -+ struct clk *core_clk; -+ struct clk *iface_clk; -+ struct clk *bus_clk; -+ int irq; -+ struct cpumask irq_affinity_mask; -+ struct notifier_block cpu_hotplug_notifier; -+ int ceiling_irq; -+ struct msm_apm_ctrl_dev *apm; -+ int apm_threshold_volt; -+ int apm_crossover_volt; -+ int apm_adj_volt; -+ enum msm_apm_supply apm_high_supply; -+ enum msm_apm_supply apm_low_supply; -+ int base_volt; -+ u32 corner_switch_delay_time; -+ u32 cpr_clock_rate; -+ u32 sensor_time; -+ u32 loop_time; -+ u32 up_down_delay_time; -+ u32 idle_clocks; -+ u32 step_quot_init_min; -+ u32 step_quot_init_max; -+ int step_volt; -+ u32 down_error_step_limit; -+ u32 up_error_step_limit; -+ enum cpr3_count_mode count_mode; -+ u32 count_repeat; -+ u32 proc_clock_throttle; -+ bool cpr_allowed_hw; -+ bool cpr_allowed_sw; -+ bool supports_hw_closed_loop; -+ bool use_hw_closed_loop; -+ enum cpr_controller_type ctrl_type; -+ bool saw_use_unit_mV; -+ struct cpr3_corner aggr_corner; -+ bool cpr_enabled; -+ bool last_corner_was_closed_loop; -+ bool cpr_suspended; -+ struct dentry *debugfs; -+ -+ int aging_ref_volt; -+ unsigned int aging_vdd_mode; -+ unsigned int aging_complete_vdd_mode; -+ int aging_ref_adjust_volt; -+ bool aging_required; -+ bool aging_succeeded; -+ bool aging_failed; -+ struct cpr3_aging_sensor_info *aging_sensor; -+ int aging_sensor_count; -+ u32 cur_sensor_state; -+ u32 aging_possible_mask; -+ u32 aging_possible_val; -+ -+ u32 step_quot_fixed; -+ u32 initial_temp_band; -+ bool use_dynamic_step_quot; -+ bool allow_core_count_adj; -+ bool allow_temp_adj; -+ bool allow_boost; -+ int temp_band_count; -+ int *temp_points; -+ u32 temp_sensor_id_start; -+ u32 temp_sensor_id_end; -+ u32 voltage_settling_time; -+ enum cpr_setting cpr_global_setting; -+ struct cpr3_panic_regs_info *panic_regs_info; -+ struct notifier_block panic_notifier; -+}; -+ -+/* Used for rounding voltages to the closest physically available set point. */ -+#define CPR3_ROUND(n, d) (DIV_ROUND_UP(n, d) * (d)) -+ -+#define cpr3_err(cpr3_thread, message, ...) \ -+ pr_err("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) -+#define cpr3_info(cpr3_thread, message, ...) \ -+ pr_info("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) -+#define cpr3_debug(cpr3_thread, message, ...) \ -+ pr_debug("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__) -+ -+/* -+ * Offset subtracted from voltage corner values passed in from the regulator -+ * framework in order to get internal voltage corner values. This is needed -+ * since the regulator framework treats 0 as an error value at regulator -+ * registration time. -+ */ -+#define CPR3_CORNER_OFFSET 1 -+ -+#ifdef CONFIG_REGULATOR_CPR3 -+ -+int cpr3_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl); -+int cpr3_open_loop_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl); -+int cpr3_regulator_unregister(struct cpr3_controller *ctrl); -+int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl); -+int cpr3_regulator_suspend(struct cpr3_controller *ctrl); -+int cpr3_regulator_resume(struct cpr3_controller *ctrl); -+ -+int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id, -+ u32 max_thread_id); -+int cpr3_map_fuse_base(struct cpr3_controller *ctrl, -+ struct platform_device *pdev); -+int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, -+ struct platform_device *pdev, u8 start, u8 end); -+int cpr3_read_fuse_param(void __iomem *fuse_base_addr, -+ const struct cpr3_fuse_param *param, u64 *param_value); -+int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse, -+ int fuse_len); -+u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x); -+int cpr3_parse_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out); -+int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out); -+int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out); -+int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg); -+int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname, -+ u32 *out_value, u32 value_min, u32 value_max); -+int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname, -+ u32 *out_value, u32 value_min, u32 value_max); -+int cpr3_parse_common_thread_data(struct cpr3_thread *thread); -+int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl); -+int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl); -+int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg); -+void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg); -+int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg); -+void cpr3_print_quots(struct cpr3_regulator *vreg); -+int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt); -+int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, -+ int *fuse_volt); -+int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg, -+ int *fuse_volt); -+int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg); -+int cpr3_quot_adjustment(int ro_scale, int volt_adjust); -+int cpr3_voltage_adjustment(int ro_scale, int quot_adjust); -+int cpr3_parse_closed_loop_voltage_adjustments(struct cpr3_regulator *vreg, -+ u64 *ro_sel, int *volt_adjust, -+ int *volt_adjust_fuse, int *ro_scale); -+int cpr4_parse_core_count_temp_voltage_adj(struct cpr3_regulator *vreg, -+ bool use_corner_band); -+int cpr3_apm_init(struct cpr3_controller *ctrl); -+int cpr3_mem_acc_init(struct cpr3_regulator *vreg); -+void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg); -+void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg); -+int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, -+ int *fuse_volt_adjust); -+int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, -+ bool is_cold); -+int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp); -+bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg); -+ -+#else -+ -+static inline int cpr3_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl) -+{ -+ return -ENXIO; -+} -+ -+static inline int -+cpr3_open_loop_regulator_register(struct platform_device *pdev, -+ struct cpr3_controller *ctrl); -+{ -+ return -ENXIO; -+} -+ -+static inline int cpr3_regulator_unregister(struct cpr3_controller *ctrl) -+{ -+ return -ENXIO; -+} -+ -+static inline int -+cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl) -+{ -+ return -ENXIO; -+} -+ -+static inline int cpr3_regulator_suspend(struct cpr3_controller *ctrl) -+{ -+ return -ENXIO; -+} -+ -+static inline int cpr3_regulator_resume(struct cpr3_controller *ctrl) -+{ -+ return -ENXIO; -+} -+ -+static inline int cpr3_get_thread_name(struct cpr3_thread *thread, -+ struct device_node *thread_node) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_allocate_threads(struct cpr3_controller *ctrl, -+ u32 min_thread_id, u32 max_thread_id) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_map_fuse_base(struct cpr3_controller *ctrl, -+ struct platform_device *pdev) -+{ -+ return -ENXIO; -+} -+ -+static inline int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, -+ struct platform_device *pdev, u8 start, u8 end) -+{ -+ return 0; -+} -+ -+static inline int cpr3_read_fuse_param(void __iomem *fuse_base_addr, -+ const struct cpr3_fuse_param *param, u64 *param_value) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_convert_open_loop_voltage_fuse(int ref_volt, -+ int step_volt, u32 fuse, int fuse_len) -+{ -+ return -EPERM; -+} -+ -+static inline u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x) -+{ -+ return 0; -+} -+ -+static inline int cpr3_parse_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_corner_band_array_property( -+ struct cpr3_regulator *vreg, const char *prop_name, -+ int tuple_size, u32 *out) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_thread_u32(struct cpr3_thread *thread, -+ const char *propname, u32 *out_value, u32 value_min, -+ u32 value_max) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, -+ const char *propname, u32 *out_value, u32 value_min, -+ u32 value_max) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_common_thread_data(struct cpr3_thread *thread) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl) -+{ -+ return -EPERM; -+} -+ -+static inline int -+cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg) -+{ -+ return -EPERM; -+} -+ -+static inline void cpr3_open_loop_voltage_as_ceiling( -+ struct cpr3_regulator *vreg) -+{ -+ return; -+} -+ -+static inline int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg) -+{ -+ return -EPERM; -+} -+ -+static inline void cpr3_print_quots(struct cpr3_regulator *vreg) -+{ -+ return; -+} -+ -+static inline int -+cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt) -+{ -+ return -EPERM; -+} -+ -+static inline int -+cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, -+ int *fuse_volt) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_adjust_fused_open_loop_voltages( -+ struct cpr3_regulator *vreg, int *fuse_volt) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg) -+{ -+ return -EPERM; -+} -+ -+static inline int cpr3_quot_adjustment(int ro_scale, int volt_adjust) -+{ -+ return 0; -+} -+ -+static inline int cpr3_voltage_adjustment(int ro_scale, int quot_adjust) -+{ -+ return 0; -+} -+ -+static inline int cpr3_parse_closed_loop_voltage_adjustments( -+ struct cpr3_regulator *vreg, u64 *ro_sel, -+ int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) -+{ -+ return 0; -+} -+ -+static inline int cpr4_parse_core_count_temp_voltage_adj( -+ struct cpr3_regulator *vreg, bool use_corner_band) -+{ -+ return 0; -+} -+ -+static inline int cpr3_apm_init(struct cpr3_controller *ctrl) -+{ -+ return 0; -+} -+ -+static inline int cpr3_mem_acc_init(struct cpr3_regulator *vreg) -+{ -+ return 0; -+} -+ -+static inline void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg) -+{ -+} -+ -+static inline void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg) -+{ -+} -+ -+static inline int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, -+ int *fuse_volt_adjust) -+{ -+ return 0; -+} -+ -+static inline int -+cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl, -+ bool is_cold) -+{ -+ return 0; -+} -+ -+static inline bool -+cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg) -+{ -+ return false; -+} -+ -+static inline int -+cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp) -+{ -+ return 0; -+} -+#endif /* CONFIG_REGULATOR_CPR3 */ -+ -+#endif /* __REGULATOR_CPR_REGULATOR_H__ */ ---- /dev/null -+++ b/drivers/regulator/cpr3-util.c -@@ -0,0 +1,2750 @@ -+/* -+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+/* -+ * This file contains utility functions to be used by platform specific CPR3 -+ * regulator drivers. -+ */ -+ -+#define pr_fmt(fmt) "%s: " fmt, __func__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "cpr3-regulator.h" -+ -+#define BYTES_PER_FUSE_ROW 8 -+#define MAX_FUSE_ROW_BIT 63 -+ -+#define CPR3_CONSECUTIVE_UP_DOWN_MIN 0 -+#define CPR3_CONSECUTIVE_UP_DOWN_MAX 15 -+#define CPR3_UP_DOWN_THRESHOLD_MIN 0 -+#define CPR3_UP_DOWN_THRESHOLD_MAX 31 -+#define CPR3_STEP_QUOT_MIN 0 -+#define CPR3_STEP_QUOT_MAX 63 -+#define CPR3_IDLE_CLOCKS_MIN 0 -+#define CPR3_IDLE_CLOCKS_MAX 31 -+ -+/* This constant has units of uV/mV so 1000 corresponds to 100%. */ -+#define CPR3_AGING_DERATE_UNITY 1000 -+ -+/** -+ * cpr3_allocate_regulators() - allocate and initialize CPR3 regulators for a -+ * given thread based upon device tree data -+ * @thread: Pointer to the CPR3 thread -+ * -+ * This function allocates the thread->vreg array based upon the number of -+ * device tree regulator subnodes. It also initializes generic elements of each -+ * regulator struct such as name, of_node, and thread. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_allocate_regulators(struct cpr3_thread *thread) -+{ -+ struct device_node *node; -+ int i, rc; -+ -+ thread->vreg_count = 0; -+ -+ for_each_available_child_of_node(thread->of_node, node) { -+ thread->vreg_count++; -+ } -+ -+ thread->vreg = devm_kcalloc(thread->ctrl->dev, thread->vreg_count, -+ sizeof(*thread->vreg), GFP_KERNEL); -+ if (!thread->vreg) -+ return -ENOMEM; -+ -+ i = 0; -+ for_each_available_child_of_node(thread->of_node, node) { -+ thread->vreg[i].of_node = node; -+ thread->vreg[i].thread = thread; -+ -+ rc = of_property_read_string(node, "regulator-name", -+ &thread->vreg[i].name); -+ if (rc) { -+ dev_err(thread->ctrl->dev, "could not find regulator name, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ i++; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_allocate_threads() - allocate and initialize CPR3 threads for a given -+ * controller based upon device tree data -+ * @ctrl: Pointer to the CPR3 controller -+ * @min_thread_id: Minimum allowed hardware thread ID for this controller -+ * @max_thread_id: Maximum allowed hardware thread ID for this controller -+ * -+ * This function allocates the ctrl->thread array based upon the number of -+ * device tree thread subnodes. It also initializes generic elements of each -+ * thread struct such as thread_id, of_node, ctrl, and vreg array. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id, -+ u32 max_thread_id) -+{ -+ struct device *dev = ctrl->dev; -+ struct device_node *thread_node; -+ int i, j, rc; -+ -+ ctrl->thread_count = 0; -+ -+ for_each_available_child_of_node(dev->of_node, thread_node) { -+ ctrl->thread_count++; -+ } -+ -+ ctrl->thread = devm_kcalloc(dev, ctrl->thread_count, -+ sizeof(*ctrl->thread), GFP_KERNEL); -+ if (!ctrl->thread) -+ return -ENOMEM; -+ -+ i = 0; -+ for_each_available_child_of_node(dev->of_node, thread_node) { -+ ctrl->thread[i].of_node = thread_node; -+ ctrl->thread[i].ctrl = ctrl; -+ -+ rc = of_property_read_u32(thread_node, "qcom,cpr-thread-id", -+ &ctrl->thread[i].thread_id); -+ if (rc) { -+ dev_err(dev, "could not read DT property qcom,cpr-thread-id, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (ctrl->thread[i].thread_id < min_thread_id || -+ ctrl->thread[i].thread_id > max_thread_id) { -+ dev_err(dev, "invalid thread id = %u; not within [%u, %u]\n", -+ ctrl->thread[i].thread_id, min_thread_id, -+ max_thread_id); -+ return -EINVAL; -+ } -+ -+ /* Verify that the thread ID is unique for all child nodes. */ -+ for (j = 0; j < i; j++) { -+ if (ctrl->thread[j].thread_id -+ == ctrl->thread[i].thread_id) { -+ dev_err(dev, "duplicate thread id = %u found\n", -+ ctrl->thread[i].thread_id); -+ return -EINVAL; -+ } -+ } -+ -+ rc = cpr3_allocate_regulators(&ctrl->thread[i]); -+ if (rc) -+ return rc; -+ -+ i++; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_map_fuse_base() - ioremap the base address of the fuse region -+ * @ctrl: Pointer to the CPR3 controller -+ * @pdev: Platform device pointer for the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_map_fuse_base(struct cpr3_controller *ctrl, -+ struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fuse_base"); -+ if (!res || !res->start) { -+ dev_err(&pdev->dev, "fuse base address is missing\n"); -+ return -ENXIO; -+ } -+ -+ ctrl->fuse_base = devm_ioremap(&pdev->dev, res->start, -+ resource_size(res)); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_read_tcsr_setting - reads the CPR setting bits from TCSR register -+ * @ctrl: Pointer to the CPR3 controller -+ * @pdev: Platform device pointer for the CPR3 controller -+ * @start: start bit in TCSR register -+ * @end: end bit in TCSR register -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl, -+ struct platform_device *pdev, u8 start, u8 end) -+{ -+ struct resource *res; -+ void __iomem *tcsr_reg; -+ u32 val; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "cpr_tcsr_reg"); -+ if (!res || !res->start) -+ return 0; -+ -+ tcsr_reg = ioremap(res->start, resource_size(res)); -+ if (!tcsr_reg) { -+ dev_err(&pdev->dev, "tcsr ioremap failed\n"); -+ return 0; -+ } -+ -+ val = readl_relaxed(tcsr_reg); -+ val &= GENMASK(end, start); -+ val >>= start; -+ -+ switch (val) { -+ case 1: -+ ctrl->cpr_global_setting = CPR_DISABLED; -+ break; -+ case 2: -+ ctrl->cpr_global_setting = CPR_OPEN_LOOP_EN; -+ break; -+ case 3: -+ ctrl->cpr_global_setting = CPR_CLOSED_LOOP_EN; -+ break; -+ default: -+ ctrl->cpr_global_setting = CPR_DEFAULT; -+ } -+ -+ iounmap(tcsr_reg); -+ -+ return 0; -+} -+ -+/** -+ * cpr3_read_fuse_param() - reads a CPR3 fuse parameter out of eFuses -+ * @fuse_base_addr: Virtual memory address of the eFuse base address -+ * @param: Null terminated array of fuse param segments to read -+ * from -+ * @param_value: Output with value read from the eFuses -+ * -+ * This function reads from each of the parameter segments listed in the param -+ * array and concatenates their values together. Reading stops when an element -+ * is reached which has all 0 struct values. The total number of bits specified -+ * for the fuse parameter across all segments must be less than or equal to 64. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_read_fuse_param(void __iomem *fuse_base_addr, -+ const struct cpr3_fuse_param *param, u64 *param_value) -+{ -+ u64 fuse_val, val; -+ int bits; -+ int bits_total = 0; -+ -+ *param_value = 0; -+ -+ while (param->row || param->bit_start || param->bit_end) { -+ if (param->bit_start > param->bit_end -+ || param->bit_end > MAX_FUSE_ROW_BIT) { -+ pr_err("Invalid fuse parameter segment: row=%u, start=%u, end=%u\n", -+ param->row, param->bit_start, param->bit_end); -+ return -EINVAL; -+ } -+ -+ bits = param->bit_end - param->bit_start + 1; -+ if (bits_total + bits > 64) { -+ pr_err("Invalid fuse parameter segments; total bits = %d\n", -+ bits_total + bits); -+ return -EINVAL; -+ } -+ -+ fuse_val = readq_relaxed(fuse_base_addr -+ + param->row * BYTES_PER_FUSE_ROW); -+ val = (fuse_val >> param->bit_start) & ((1ULL << bits) - 1); -+ *param_value |= val << bits_total; -+ bits_total += bits; -+ -+ param++; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_convert_open_loop_voltage_fuse() - converts an open loop voltage fuse -+ * value into an absolute voltage with units of microvolts -+ * @ref_volt: Reference voltage in microvolts -+ * @step_volt: The step size in microvolts of the fuse LSB -+ * @fuse: Open loop voltage fuse value -+ * @fuse_len: The bit length of the fuse value -+ * -+ * The MSB of the fuse parameter corresponds to a sign bit. If it is set, then -+ * the lower bits correspond to the number of steps to go down from the -+ * reference voltage. If it is not set, then the lower bits correspond to the -+ * number of steps to go up from the reference voltage. -+ */ -+int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse, -+ int fuse_len) -+{ -+ int sign, steps; -+ -+ sign = (fuse & (1 << (fuse_len - 1))) ? -1 : 1; -+ steps = fuse & ((1 << (fuse_len - 1)) - 1); -+ -+ return ref_volt + sign * steps * step_volt; -+} -+ -+/** -+ * cpr3_interpolate() - performs linear interpolation -+ * @x1 Lower known x value -+ * @y1 Lower known y value -+ * @x2 Upper known x value -+ * @y2 Upper known y value -+ * @x Intermediate x value -+ * -+ * Returns y where (x, y) falls on the line between (x1, y1) and (x2, y2). -+ * It is required that x1 < x2, y1 <= y2, and x1 <= x <= x2. If these -+ * conditions are not met, then y2 will be returned. -+ */ -+u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x) -+{ -+ u64 temp; -+ -+ if (x1 >= x2 || y1 > y2 || x1 > x || x > x2) -+ return y2; -+ -+ temp = (x2 - x) * (y2 - y1); -+ do_div(temp, (u32)(x2 - x1)); -+ -+ return y2 - temp; -+} -+ -+/** -+ * cpr3_parse_array_property() - fill an array from a portion of the values -+ * specified for a device tree property -+ * @vreg: Pointer to the CPR3 regulator -+ * @prop_name: The name of the device tree property to read from -+ * @tuple_size: The number of elements in each tuple -+ * @out: Output data array which must be of size tuple_size -+ * -+ * cpr3_parse_common_corner_data() must be called for vreg before this function -+ * is called so that fuse combo and speed bin size elements are initialized. -+ * -+ * Three formats are supported for the device tree property: -+ * 1. Length == tuple_size -+ * (reading begins at index 0) -+ * 2. Length == tuple_size * vreg->fuse_combos_supported -+ * (reading begins at index tuple_size * vreg->fuse_combo) -+ * 3. Length == tuple_size * vreg->speed_bins_supported -+ * (reading begins at index tuple_size * vreg->speed_bin_fuse) -+ * -+ * All other property lengths are treated as errors. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out) -+{ -+ struct device_node *node = vreg->of_node; -+ int len = 0; -+ int i, offset, rc; -+ -+ if (!of_find_property(node, prop_name, &len)) { -+ cpr3_err(vreg, "property %s is missing\n", prop_name); -+ return -EINVAL; -+ } -+ -+ if (len == tuple_size * sizeof(u32)) { -+ offset = 0; -+ } else if (len == tuple_size * vreg->fuse_combos_supported -+ * sizeof(u32)) { -+ offset = tuple_size * vreg->fuse_combo; -+ } else if (vreg->speed_bins_supported > 0 && -+ len == tuple_size * vreg->speed_bins_supported * sizeof(u32)) { -+ offset = tuple_size * vreg->speed_bin_fuse; -+ } else { -+ if (vreg->speed_bins_supported > 0) -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", -+ prop_name, len, -+ tuple_size * sizeof(u32), -+ tuple_size * vreg->speed_bins_supported -+ * sizeof(u32), -+ tuple_size * vreg->fuse_combos_supported -+ * sizeof(u32)); -+ else -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", -+ prop_name, len, -+ tuple_size * sizeof(u32), -+ tuple_size * vreg->fuse_combos_supported -+ * sizeof(u32)); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < tuple_size; i++) { -+ rc = of_property_read_u32_index(node, prop_name, offset + i, -+ &out[i]); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_name, rc); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_parse_corner_array_property() - fill a per-corner array from a portion -+ * of the values specified for a device tree property -+ * @vreg: Pointer to the CPR3 regulator -+ * @prop_name: The name of the device tree property to read from -+ * @tuple_size: The number of elements in each per-corner tuple -+ * @out: Output data array which must be of size: -+ * tuple_size * vreg->corner_count -+ * -+ * cpr3_parse_common_corner_data() must be called for vreg before this function -+ * is called so that fuse combo and speed bin size elements are initialized. -+ * -+ * Three formats are supported for the device tree property: -+ * 1. Length == tuple_size * vreg->corner_count -+ * (reading begins at index 0) -+ * 2. Length == tuple_size * vreg->fuse_combo_corner_sum -+ * (reading begins at index tuple_size * vreg->fuse_combo_offset) -+ * 3. Length == tuple_size * vreg->speed_bin_corner_sum -+ * (reading begins at index tuple_size * vreg->speed_bin_offset) -+ * -+ * All other property lengths are treated as errors. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out) -+{ -+ struct device_node *node = vreg->of_node; -+ int len = 0; -+ int i, offset, rc; -+ -+ if (!of_find_property(node, prop_name, &len)) { -+ cpr3_err(vreg, "property %s is missing\n", prop_name); -+ return -EINVAL; -+ } -+ -+ if (len == tuple_size * vreg->corner_count * sizeof(u32)) { -+ offset = 0; -+ } else if (len == tuple_size * vreg->fuse_combo_corner_sum -+ * sizeof(u32)) { -+ offset = tuple_size * vreg->fuse_combo_offset; -+ } else if (vreg->speed_bin_corner_sum > 0 && -+ len == tuple_size * vreg->speed_bin_corner_sum * sizeof(u32)) { -+ offset = tuple_size * vreg->speed_bin_offset; -+ } else { -+ if (vreg->speed_bin_corner_sum > 0) -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", -+ prop_name, len, -+ tuple_size * vreg->corner_count * sizeof(u32), -+ tuple_size * vreg->speed_bin_corner_sum -+ * sizeof(u32), -+ tuple_size * vreg->fuse_combo_corner_sum -+ * sizeof(u32)); -+ else -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", -+ prop_name, len, -+ tuple_size * vreg->corner_count * sizeof(u32), -+ tuple_size * vreg->fuse_combo_corner_sum -+ * sizeof(u32)); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < tuple_size * vreg->corner_count; i++) { -+ rc = of_property_read_u32_index(node, prop_name, offset + i, -+ &out[i]); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_name, rc); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_parse_corner_band_array_property() - fill a per-corner band array -+ * from a portion of the values specified for a device tree -+ * property -+ * @vreg: Pointer to the CPR3 regulator -+ * @prop_name: The name of the device tree property to read from -+ * @tuple_size: The number of elements in each per-corner band tuple -+ * @out: Output data array which must be of size: -+ * tuple_size * vreg->corner_band_count -+ * -+ * cpr3_parse_common_corner_data() must be called for vreg before this function -+ * is called so that fuse combo and speed bin size elements are initialized. -+ * In addition, corner band fuse combo and speed bin sum and offset elements -+ * must be initialized prior to executing this function. -+ * -+ * Three formats are supported for the device tree property: -+ * 1. Length == tuple_size * vreg->corner_band_count -+ * (reading begins at index 0) -+ * 2. Length == tuple_size * vreg->fuse_combo_corner_band_sum -+ * (reading begins at index tuple_size * -+ * vreg->fuse_combo_corner_band_offset) -+ * 3. Length == tuple_size * vreg->speed_bin_corner_band_sum -+ * (reading begins at index tuple_size * -+ * vreg->speed_bin_corner_band_offset) -+ * -+ * All other property lengths are treated as errors. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg, -+ const char *prop_name, int tuple_size, u32 *out) -+{ -+ struct device_node *node = vreg->of_node; -+ int len = 0; -+ int i, offset, rc; -+ -+ if (!of_find_property(node, prop_name, &len)) { -+ cpr3_err(vreg, "property %s is missing\n", prop_name); -+ return -EINVAL; -+ } -+ -+ if (len == tuple_size * vreg->corner_band_count * sizeof(u32)) { -+ offset = 0; -+ } else if (len == tuple_size * vreg->fuse_combo_corner_band_sum -+ * sizeof(u32)) { -+ offset = tuple_size * vreg->fuse_combo_corner_band_offset; -+ } else if (vreg->speed_bin_corner_band_sum > 0 && -+ len == tuple_size * vreg->speed_bin_corner_band_sum * -+ sizeof(u32)) { -+ offset = tuple_size * vreg->speed_bin_corner_band_offset; -+ } else { -+ if (vreg->speed_bin_corner_band_sum > 0) -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n", -+ prop_name, len, -+ tuple_size * vreg->corner_band_count * -+ sizeof(u32), -+ tuple_size * vreg->speed_bin_corner_band_sum -+ * sizeof(u32), -+ tuple_size * vreg->fuse_combo_corner_band_sum -+ * sizeof(u32)); -+ else -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", -+ prop_name, len, -+ tuple_size * vreg->corner_band_count * -+ sizeof(u32), -+ tuple_size * vreg->fuse_combo_corner_band_sum -+ * sizeof(u32)); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < tuple_size * vreg->corner_band_count; i++) { -+ rc = of_property_read_u32_index(node, prop_name, offset + i, -+ &out[i]); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_name, rc); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_parse_common_corner_data() - parse common CPR3 properties relating to -+ * the corners supported by a CPR3 regulator from device tree -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function reads, validates, and utilizes the following device tree -+ * properties: qcom,cpr-fuse-corners, qcom,cpr-fuse-combos, qcom,cpr-speed-bins, -+ * qcom,cpr-speed-bin-corners, qcom,cpr-corners, qcom,cpr-voltage-ceiling, -+ * qcom,cpr-voltage-floor, qcom,corner-frequencies, -+ * and qcom,cpr-corner-fmax-map. -+ * -+ * It initializes these CPR3 regulator elements: corner, corner_count, -+ * fuse_combos_supported, fuse_corner_map, and speed_bins_supported. It -+ * initializes these elements for each corner: ceiling_volt, floor_volt, -+ * proc_freq, and cpr_fuse_corner. -+ * -+ * It requires that the following CPR3 regulator elements be initialized before -+ * being called: fuse_corner_count, fuse_combo, and speed_bin_fuse. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg) -+{ -+ struct device_node *node = vreg->of_node; -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ u32 max_fuse_combos, fuse_corners, aging_allowed = 0; -+ u32 max_speed_bins = 0; -+ u32 *combo_corners; -+ u32 *speed_bin_corners; -+ u32 *temp; -+ int i, j, rc; -+ -+ rc = of_property_read_u32(node, "qcom,cpr-fuse-corners", &fuse_corners); -+ if (rc) { -+ cpr3_err(vreg, "error reading property qcom,cpr-fuse-corners, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (vreg->fuse_corner_count != fuse_corners) { -+ cpr3_err(vreg, "device tree config supports %d fuse corners but the hardware has %d fuse corners\n", -+ fuse_corners, vreg->fuse_corner_count); -+ return -EINVAL; -+ } -+ -+ rc = of_property_read_u32(node, "qcom,cpr-fuse-combos", -+ &max_fuse_combos); -+ if (rc) { -+ cpr3_err(vreg, "error reading property qcom,cpr-fuse-combos, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ /* -+ * Sanity check against arbitrarily large value to avoid excessive -+ * memory allocation. -+ */ -+ if (max_fuse_combos > 100 || max_fuse_combos == 0) { -+ cpr3_err(vreg, "qcom,cpr-fuse-combos is invalid: %u\n", -+ max_fuse_combos); -+ return -EINVAL; -+ } -+ -+ if (vreg->fuse_combo >= max_fuse_combos) { -+ cpr3_err(vreg, "device tree config supports fuse combos 0-%u but the hardware has combo %d\n", -+ max_fuse_combos - 1, vreg->fuse_combo); -+ BUG_ON(1); -+ return -EINVAL; -+ } -+ -+ vreg->fuse_combos_supported = max_fuse_combos; -+ -+ of_property_read_u32(node, "qcom,cpr-speed-bins", &max_speed_bins); -+ -+ /* -+ * Sanity check against arbitrarily large value to avoid excessive -+ * memory allocation. -+ */ -+ if (max_speed_bins > 100) { -+ cpr3_err(vreg, "qcom,cpr-speed-bins is invalid: %u\n", -+ max_speed_bins); -+ return -EINVAL; -+ } -+ -+ if (max_speed_bins && vreg->speed_bin_fuse >= max_speed_bins) { -+ cpr3_err(vreg, "device tree config supports speed bins 0-%u but the hardware has speed bin %d\n", -+ max_speed_bins - 1, vreg->speed_bin_fuse); -+ BUG(); -+ return -EINVAL; -+ } -+ -+ vreg->speed_bins_supported = max_speed_bins; -+ -+ combo_corners = kcalloc(vreg->fuse_combos_supported, -+ sizeof(*combo_corners), GFP_KERNEL); -+ if (!combo_corners) -+ return -ENOMEM; -+ -+ rc = of_property_read_u32_array(node, "qcom,cpr-corners", combo_corners, -+ vreg->fuse_combos_supported); -+ if (rc == -EOVERFLOW) { -+ /* Single value case */ -+ rc = of_property_read_u32(node, "qcom,cpr-corners", -+ combo_corners); -+ for (i = 1; i < vreg->fuse_combos_supported; i++) -+ combo_corners[i] = combo_corners[0]; -+ } -+ if (rc) { -+ cpr3_err(vreg, "error reading property qcom,cpr-corners, rc=%d\n", -+ rc); -+ kfree(combo_corners); -+ return rc; -+ } -+ -+ vreg->fuse_combo_offset = 0; -+ vreg->fuse_combo_corner_sum = 0; -+ for (i = 0; i < vreg->fuse_combos_supported; i++) { -+ vreg->fuse_combo_corner_sum += combo_corners[i]; -+ if (i < vreg->fuse_combo) -+ vreg->fuse_combo_offset += combo_corners[i]; -+ } -+ -+ vreg->corner_count = combo_corners[vreg->fuse_combo]; -+ -+ kfree(combo_corners); -+ -+ vreg->speed_bin_offset = 0; -+ vreg->speed_bin_corner_sum = 0; -+ if (vreg->speed_bins_supported > 0) { -+ speed_bin_corners = kcalloc(vreg->speed_bins_supported, -+ sizeof(*speed_bin_corners), GFP_KERNEL); -+ if (!speed_bin_corners) -+ return -ENOMEM; -+ -+ rc = of_property_read_u32_array(node, -+ "qcom,cpr-speed-bin-corners", speed_bin_corners, -+ vreg->speed_bins_supported); -+ if (rc) { -+ cpr3_err(vreg, "error reading property qcom,cpr-speed-bin-corners, rc=%d\n", -+ rc); -+ kfree(speed_bin_corners); -+ return rc; -+ } -+ -+ for (i = 0; i < vreg->speed_bins_supported; i++) { -+ vreg->speed_bin_corner_sum += speed_bin_corners[i]; -+ if (i < vreg->speed_bin_fuse) -+ vreg->speed_bin_offset += speed_bin_corners[i]; -+ } -+ -+ if (speed_bin_corners[vreg->speed_bin_fuse] -+ != vreg->corner_count) { -+ cpr3_err(vreg, "qcom,cpr-corners and qcom,cpr-speed-bin-corners conflict on number of corners: %d vs %u\n", -+ vreg->corner_count, -+ speed_bin_corners[vreg->speed_bin_fuse]); -+ kfree(speed_bin_corners); -+ return -EINVAL; -+ } -+ -+ kfree(speed_bin_corners); -+ } -+ -+ vreg->corner = devm_kcalloc(ctrl->dev, vreg->corner_count, -+ sizeof(*vreg->corner), GFP_KERNEL); -+ temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL); -+ if (!vreg->corner || !temp) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-ceiling", -+ 1, temp); -+ if (rc) -+ goto free_temp; -+ for (i = 0; i < vreg->corner_count; i++) { -+ vreg->corner[i].ceiling_volt -+ = CPR3_ROUND(temp[i], ctrl->step_volt); -+ vreg->corner[i].abs_ceiling_volt = vreg->corner[i].ceiling_volt; -+ } -+ -+ rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-floor", -+ 1, temp); -+ if (rc) -+ goto free_temp; -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].floor_volt -+ = CPR3_ROUND(temp[i], ctrl->step_volt); -+ -+ /* Validate ceiling and floor values */ -+ for (i = 0; i < vreg->corner_count; i++) { -+ if (vreg->corner[i].floor_volt -+ > vreg->corner[i].ceiling_volt) { -+ cpr3_err(vreg, "CPR floor[%d]=%d > ceiling[%d]=%d uV\n", -+ i, vreg->corner[i].floor_volt, -+ i, vreg->corner[i].ceiling_volt); -+ rc = -EINVAL; -+ goto free_temp; -+ } -+ } -+ -+ /* Load optional system-supply voltages */ -+ if (of_find_property(vreg->of_node, "qcom,system-voltage", NULL)) { -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,system-voltage", 1, temp); -+ if (rc) -+ goto free_temp; -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].system_volt = temp[i]; -+ } -+ -+ rc = cpr3_parse_corner_array_property(vreg, "qcom,corner-frequencies", -+ 1, temp); -+ if (rc) -+ goto free_temp; -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].proc_freq = temp[i]; -+ -+ /* Validate frequencies */ -+ for (i = 1; i < vreg->corner_count; i++) { -+ if (vreg->corner[i].proc_freq -+ < vreg->corner[i - 1].proc_freq) { -+ cpr3_err(vreg, "invalid frequency: freq[%d]=%u < freq[%d]=%u\n", -+ i, vreg->corner[i].proc_freq, i - 1, -+ vreg->corner[i - 1].proc_freq); -+ rc = -EINVAL; -+ goto free_temp; -+ } -+ } -+ -+ vreg->fuse_corner_map = devm_kcalloc(ctrl->dev, vreg->fuse_corner_count, -+ sizeof(*vreg->fuse_corner_map), GFP_KERNEL); -+ if (!vreg->fuse_corner_map) { -+ rc = -ENOMEM; -+ goto free_temp; -+ } -+ -+ rc = cpr3_parse_array_property(vreg, "qcom,cpr-corner-fmax-map", -+ vreg->fuse_corner_count, temp); -+ if (rc) -+ goto free_temp; -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ vreg->fuse_corner_map[i] = temp[i] - CPR3_CORNER_OFFSET; -+ if (temp[i] < CPR3_CORNER_OFFSET -+ || temp[i] > vreg->corner_count + CPR3_CORNER_OFFSET) { -+ cpr3_err(vreg, "invalid corner value specified in qcom,cpr-corner-fmax-map: %u\n", -+ temp[i]); -+ rc = -EINVAL; -+ goto free_temp; -+ } else if (i > 0 && temp[i - 1] >= temp[i]) { -+ cpr3_err(vreg, "invalid corner %u less than or equal to previous corner %u\n", -+ temp[i], temp[i - 1]); -+ rc = -EINVAL; -+ goto free_temp; -+ } -+ } -+ if (temp[vreg->fuse_corner_count - 1] != vreg->corner_count) -+ cpr3_debug(vreg, "Note: highest Fmax corner %u in qcom,cpr-corner-fmax-map does not match highest supported corner %d\n", -+ temp[vreg->fuse_corner_count - 1], -+ vreg->corner_count); -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ for (j = 0; j < vreg->fuse_corner_count; j++) { -+ if (i + CPR3_CORNER_OFFSET <= temp[j]) { -+ vreg->corner[i].cpr_fuse_corner = j; -+ break; -+ } -+ } -+ if (j == vreg->fuse_corner_count) { -+ /* -+ * Handle the case where the highest fuse corner maps -+ * to a corner below the highest corner. -+ */ -+ vreg->corner[i].cpr_fuse_corner -+ = vreg->fuse_corner_count - 1; -+ } -+ } -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,allow-aging-voltage-adjustment", NULL)) { -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,allow-aging-voltage-adjustment", -+ 1, &aging_allowed); -+ if (rc) -+ goto free_temp; -+ -+ vreg->aging_allowed = aging_allowed; -+ } -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,allow-aging-open-loop-voltage-adjustment", NULL)) { -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,allow-aging-open-loop-voltage-adjustment", -+ 1, &aging_allowed); -+ if (rc) -+ goto free_temp; -+ -+ vreg->aging_allow_open_loop_adj = aging_allowed; -+ } -+ -+ if (vreg->aging_allowed) { -+ if (ctrl->aging_ref_volt <= 0) { -+ cpr3_err(ctrl, "qcom,cpr-aging-ref-voltage must be specified\n"); -+ rc = -EINVAL; -+ goto free_temp; -+ } -+ -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,cpr-aging-max-voltage-adjustment", -+ 1, &vreg->aging_max_adjust_volt); -+ if (rc) -+ goto free_temp; -+ -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,cpr-aging-ref-corner", 1, &vreg->aging_corner); -+ if (rc) { -+ goto free_temp; -+ } else if (vreg->aging_corner < CPR3_CORNER_OFFSET -+ || vreg->aging_corner > vreg->corner_count - 1 -+ + CPR3_CORNER_OFFSET) { -+ cpr3_err(vreg, "aging reference corner=%d not in range [%d, %d]\n", -+ vreg->aging_corner, CPR3_CORNER_OFFSET, -+ vreg->corner_count - 1 + CPR3_CORNER_OFFSET); -+ rc = -EINVAL; -+ goto free_temp; -+ } -+ vreg->aging_corner -= CPR3_CORNER_OFFSET; -+ -+ if (of_find_property(vreg->of_node, "qcom,cpr-aging-derate", -+ NULL)) { -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-aging-derate", 1, temp); -+ if (rc) -+ goto free_temp; -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].aging_derate = temp[i]; -+ } else { -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].aging_derate -+ = CPR3_AGING_DERATE_UNITY; -+ } -+ } -+ -+free_temp: -+ kfree(temp); -+ return rc; -+} -+ -+/** -+ * cpr3_parse_thread_u32() - parse the specified property from the CPR3 thread's -+ * device tree node and verify that it is within the allowed limits -+ * @thread: Pointer to the CPR3 thread -+ * @propname: The name of the device tree property to read -+ * @out_value: The output pointer to fill with the value read -+ * @value_min: The minimum allowed property value -+ * @value_max: The maximum allowed property value -+ * -+ * This function prints a verbose error message if the property is missing or -+ * has a value which is not within the specified range. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname, -+ u32 *out_value, u32 value_min, u32 value_max) -+{ -+ int rc; -+ -+ rc = of_property_read_u32(thread->of_node, propname, out_value); -+ if (rc) { -+ cpr3_err(thread->ctrl, "thread %u error reading property %s, rc=%d\n", -+ thread->thread_id, propname, rc); -+ return rc; -+ } -+ -+ if (*out_value < value_min || *out_value > value_max) { -+ cpr3_err(thread->ctrl, "thread %u %s=%u is invalid; allowed range: [%u, %u]\n", -+ thread->thread_id, propname, *out_value, value_min, -+ value_max); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_parse_ctrl_u32() - parse the specified property from the CPR3 -+ * controller's device tree node and verify that it is within the -+ * allowed limits -+ * @ctrl: Pointer to the CPR3 controller -+ * @propname: The name of the device tree property to read -+ * @out_value: The output pointer to fill with the value read -+ * @value_min: The minimum allowed property value -+ * @value_max: The maximum allowed property value -+ * -+ * This function prints a verbose error message if the property is missing or -+ * has a value which is not within the specified range. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname, -+ u32 *out_value, u32 value_min, u32 value_max) -+{ -+ int rc; -+ -+ rc = of_property_read_u32(ctrl->dev->of_node, propname, out_value); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property %s, rc=%d\n", -+ propname, rc); -+ return rc; -+ } -+ -+ if (*out_value < value_min || *out_value > value_max) { -+ cpr3_err(ctrl, "%s=%u is invalid; allowed range: [%u, %u]\n", -+ propname, *out_value, value_min, value_max); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_parse_common_thread_data() - parse common CPR3 thread properties from -+ * device tree -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_common_thread_data(struct cpr3_thread *thread) -+{ -+ int rc; -+ -+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-up", -+ &thread->consecutive_up, CPR3_CONSECUTIVE_UP_DOWN_MIN, -+ CPR3_CONSECUTIVE_UP_DOWN_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-down", -+ &thread->consecutive_down, CPR3_CONSECUTIVE_UP_DOWN_MIN, -+ CPR3_CONSECUTIVE_UP_DOWN_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-up-threshold", -+ &thread->up_threshold, CPR3_UP_DOWN_THRESHOLD_MIN, -+ CPR3_UP_DOWN_THRESHOLD_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-down-threshold", -+ &thread->down_threshold, CPR3_UP_DOWN_THRESHOLD_MIN, -+ CPR3_UP_DOWN_THRESHOLD_MAX); -+ if (rc) -+ return rc; -+ -+ return rc; -+} -+ -+/** -+ * cpr3_parse_irq_affinity() - parse CPR IRQ affinity information -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_parse_irq_affinity(struct cpr3_controller *ctrl) -+{ -+ struct device_node *cpu_node; -+ int i, cpu; -+ int len = 0; -+ -+ if (!of_find_property(ctrl->dev->of_node, "qcom,cpr-interrupt-affinity", -+ &len)) { -+ /* No IRQ affinity required */ -+ return 0; -+ } -+ -+ len /= sizeof(u32); -+ -+ for (i = 0; i < len; i++) { -+ cpu_node = of_parse_phandle(ctrl->dev->of_node, -+ "qcom,cpr-interrupt-affinity", i); -+ if (!cpu_node) { -+ cpr3_err(ctrl, "could not find CPU node %d\n", i); -+ return -EINVAL; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ if (of_get_cpu_node(cpu, NULL) == cpu_node) { -+ cpumask_set_cpu(cpu, &ctrl->irq_affinity_mask); -+ break; -+ } -+ } -+ of_node_put(cpu_node); -+ } -+ -+ return 0; -+} -+ -+static int cpr3_panic_notifier_init(struct cpr3_controller *ctrl) -+{ -+ struct device_node *node = ctrl->dev->of_node; -+ struct cpr3_panic_regs_info *panic_regs_info; -+ struct cpr3_reg_info *regs; -+ int i, reg_count, len, rc = 0; -+ -+ if (!of_find_property(node, "qcom,cpr-panic-reg-addr-list", &len)) { -+ /* panic register address list not specified */ -+ return rc; -+ } -+ -+ reg_count = len / sizeof(u32); -+ if (!reg_count) { -+ cpr3_err(ctrl, "qcom,cpr-panic-reg-addr-list has invalid len = %d\n", -+ len); -+ return -EINVAL; -+ } -+ -+ if (!of_find_property(node, "qcom,cpr-panic-reg-name-list", NULL)) { -+ cpr3_err(ctrl, "property qcom,cpr-panic-reg-name-list not specified\n"); -+ return -EINVAL; -+ } -+ -+ len = of_property_count_strings(node, "qcom,cpr-panic-reg-name-list"); -+ if (reg_count != len) { -+ cpr3_err(ctrl, "qcom,cpr-panic-reg-name-list should have %d strings\n", -+ reg_count); -+ return -EINVAL; -+ } -+ -+ panic_regs_info = devm_kzalloc(ctrl->dev, sizeof(*panic_regs_info), -+ GFP_KERNEL); -+ if (!panic_regs_info) -+ return -ENOMEM; -+ -+ regs = devm_kcalloc(ctrl->dev, reg_count, sizeof(*regs), GFP_KERNEL); -+ if (!regs) -+ return -ENOMEM; -+ -+ for (i = 0; i < reg_count; i++) { -+ rc = of_property_read_string_index(node, -+ "qcom,cpr-panic-reg-name-list", i, -+ &(regs[i].name)); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-name-list, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = of_property_read_u32_index(node, -+ "qcom,cpr-panic-reg-addr-list", i, -+ &(regs[i].addr)); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-addr-list, rc=%d\n", -+ rc); -+ return rc; -+ } -+ regs[i].virt_addr = devm_ioremap(ctrl->dev, regs[i].addr, 0x4); -+ if (!regs[i].virt_addr) { -+ pr_err("Unable to map panic register addr 0x%08x\n", -+ regs[i].addr); -+ return -EINVAL; -+ } -+ regs[i].value = 0xFFFFFFFF; -+ } -+ -+ panic_regs_info->reg_count = reg_count; -+ panic_regs_info->regs = regs; -+ ctrl->panic_regs_info = panic_regs_info; -+ -+ return rc; -+} -+ -+/** -+ * cpr3_parse_common_ctrl_data() - parse common CPR3 controller properties from -+ * device tree -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-sensor-time", -+ &ctrl->sensor_time, 0, UINT_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-loop-time", -+ &ctrl->loop_time, 0, UINT_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-idle-cycles", -+ &ctrl->idle_clocks, CPR3_IDLE_CLOCKS_MIN, -+ CPR3_IDLE_CLOCKS_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-min", -+ &ctrl->step_quot_init_min, CPR3_STEP_QUOT_MIN, -+ CPR3_STEP_QUOT_MAX); -+ if (rc) -+ return rc; -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-max", -+ &ctrl->step_quot_init_max, CPR3_STEP_QUOT_MIN, -+ CPR3_STEP_QUOT_MAX); -+ if (rc) -+ return rc; -+ -+ rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step", -+ &ctrl->step_volt); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n", -+ rc); -+ return rc; -+ } -+ if (ctrl->step_volt <= 0) { -+ cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n", -+ ctrl->step_volt); -+ return -EINVAL; -+ } -+ -+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-count-mode", -+ &ctrl->count_mode, CPR3_COUNT_MODE_ALL_AT_ONCE_MIN, -+ CPR3_COUNT_MODE_STAGGERED); -+ if (rc) -+ return rc; -+ -+ /* Count repeat is optional */ -+ ctrl->count_repeat = 0; -+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-count-repeat", -+ &ctrl->count_repeat); -+ -+ ctrl->cpr_allowed_sw = -+ of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-enable") || -+ ctrl->cpr_global_setting == CPR_CLOSED_LOOP_EN; -+ -+ rc = cpr3_parse_irq_affinity(ctrl); -+ if (rc) -+ return rc; -+ -+ /* Aging reference voltage is optional */ -+ ctrl->aging_ref_volt = 0; -+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-aging-ref-voltage", -+ &ctrl->aging_ref_volt); -+ -+ /* Aging possible bitmask is optional */ -+ ctrl->aging_possible_mask = 0; -+ of_property_read_u32(ctrl->dev->of_node, -+ "qcom,cpr-aging-allowed-reg-mask", -+ &ctrl->aging_possible_mask); -+ -+ if (ctrl->aging_possible_mask) { -+ /* -+ * Aging possible register value required if bitmask is -+ * specified -+ */ -+ rc = cpr3_parse_ctrl_u32(ctrl, -+ "qcom,cpr-aging-allowed-reg-value", -+ &ctrl->aging_possible_val, 0, UINT_MAX); -+ if (rc) -+ return rc; -+ } -+ -+ if (of_find_property(ctrl->dev->of_node, "clock-names", NULL)) { -+ ctrl->core_clk = devm_clk_get(ctrl->dev, "core_clk"); -+ if (IS_ERR(ctrl->core_clk)) { -+ rc = PTR_ERR(ctrl->core_clk); -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable request core clock, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ rc = cpr3_panic_notifier_init(ctrl); -+ if (rc) -+ return rc; -+ -+ if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) { -+ ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd"); -+ if (IS_ERR(ctrl->vdd_regulator)) { -+ rc = PTR_ERR(ctrl->vdd_regulator); -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } else { -+ cpr3_err(ctrl, "vdd supply is not defined\n"); -+ return -ENODEV; -+ } -+ -+ ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev, -+ "system"); -+ if (IS_ERR(ctrl->system_regulator)) { -+ rc = PTR_ERR(ctrl->system_regulator); -+ if (rc != -EPROBE_DEFER) { -+ rc = 0; -+ ctrl->system_regulator = NULL; -+ } else { -+ return rc; -+ } -+ } -+ -+ ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev, -+ "mem-acc"); -+ if (IS_ERR(ctrl->mem_acc_regulator)) { -+ rc = PTR_ERR(ctrl->mem_acc_regulator); -+ if (rc != -EPROBE_DEFER) { -+ rc = 0; -+ ctrl->mem_acc_regulator = NULL; -+ } else { -+ return rc; -+ } -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_parse_open_loop_common_ctrl_data() - parse common open loop CPR3 -+ * controller properties from device tree -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step", -+ &ctrl->step_volt); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (ctrl->step_volt <= 0) { -+ cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n", -+ ctrl->step_volt); -+ return -EINVAL; -+ } -+ -+ if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) { -+ ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd"); -+ if (IS_ERR(ctrl->vdd_regulator)) { -+ rc = PTR_ERR(ctrl->vdd_regulator); -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } else { -+ cpr3_err(ctrl, "vdd supply is not defined\n"); -+ return -ENODEV; -+ } -+ -+ ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev, -+ "system"); -+ if (IS_ERR(ctrl->system_regulator)) { -+ rc = PTR_ERR(ctrl->system_regulator); -+ if (rc != -EPROBE_DEFER) { -+ rc = 0; -+ ctrl->system_regulator = NULL; -+ } else { -+ return rc; -+ } -+ } else { -+ rc = regulator_enable(ctrl->system_regulator); -+ } -+ -+ ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev, -+ "mem-acc"); -+ if (IS_ERR(ctrl->mem_acc_regulator)) { -+ rc = PTR_ERR(ctrl->mem_acc_regulator); -+ if (rc != -EPROBE_DEFER) { -+ rc = 0; -+ ctrl->mem_acc_regulator = NULL; -+ } else { -+ return rc; -+ } -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_limit_open_loop_voltages() - modify the open-loop voltage of each corner -+ * so that it fits within the floor to ceiling -+ * voltage range of the corner -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function clips the open-loop voltage for each corner so that it is -+ * limited to the floor to ceiling range. It also rounds each open-loop voltage -+ * so that it corresponds to a set point available to the underlying regulator. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg) -+{ -+ int i, volt; -+ -+ cpr3_debug(vreg, "open-loop voltages after trimming and rounding:\n"); -+ for (i = 0; i < vreg->corner_count; i++) { -+ volt = CPR3_ROUND(vreg->corner[i].open_loop_volt, -+ vreg->thread->ctrl->step_volt); -+ if (volt < vreg->corner[i].floor_volt) -+ volt = vreg->corner[i].floor_volt; -+ else if (volt > vreg->corner[i].ceiling_volt) -+ volt = vreg->corner[i].ceiling_volt; -+ vreg->corner[i].open_loop_volt = volt; -+ cpr3_debug(vreg, "corner[%2d]: open-loop=%d uV\n", i, volt); -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr3_open_loop_voltage_as_ceiling() - configures the ceiling voltage for each -+ * corner to equal the open-loop voltage if the relevant device -+ * tree property is found for the CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function assumes that the the open-loop voltage for each corner has -+ * already been rounded to the nearest allowed set point and that it falls -+ * within the floor to ceiling range. -+ * -+ * Return: none -+ */ -+void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg) -+{ -+ int i; -+ -+ if (!of_property_read_bool(vreg->of_node, -+ "qcom,cpr-scaled-open-loop-voltage-as-ceiling")) -+ return; -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].ceiling_volt -+ = vreg->corner[i].open_loop_volt; -+} -+ -+/** -+ * cpr3_limit_floor_voltages() - raise the floor voltage of each corner so that -+ * the optional maximum floor to ceiling voltage range specified in -+ * device tree is satisfied -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function also ensures that the open-loop voltage for each corner falls -+ * within the final floor to ceiling voltage range and that floor voltages -+ * increase monotonically. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg) -+{ -+ char *prop = "qcom,cpr-floor-to-ceiling-max-range"; -+ int i, floor_new; -+ u32 *floor_range; -+ int rc = 0; -+ -+ if (!of_find_property(vreg->of_node, prop, NULL)) -+ goto enforce_monotonicity; -+ -+ floor_range = kcalloc(vreg->corner_count, sizeof(*floor_range), -+ GFP_KERNEL); -+ if (!floor_range) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_corner_array_property(vreg, prop, 1, floor_range); -+ if (rc) -+ goto free_floor_adjust; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ if ((s32)floor_range[i] >= 0) { -+ floor_new = CPR3_ROUND(vreg->corner[i].ceiling_volt -+ - floor_range[i], -+ vreg->thread->ctrl->step_volt); -+ -+ vreg->corner[i].floor_volt = max(floor_new, -+ vreg->corner[i].floor_volt); -+ if (vreg->corner[i].open_loop_volt -+ < vreg->corner[i].floor_volt) -+ vreg->corner[i].open_loop_volt -+ = vreg->corner[i].floor_volt; -+ } -+ } -+ -+free_floor_adjust: -+ kfree(floor_range); -+ -+enforce_monotonicity: -+ /* Ensure that floor voltages increase monotonically. */ -+ for (i = 1; i < vreg->corner_count; i++) { -+ if (vreg->corner[i].floor_volt -+ < vreg->corner[i - 1].floor_volt) { -+ cpr3_debug(vreg, "corner %d floor voltage=%d uV < corner %d voltage=%d uV; overriding: corner %d voltage=%d\n", -+ i, vreg->corner[i].floor_volt, -+ i - 1, vreg->corner[i - 1].floor_volt, -+ i, vreg->corner[i - 1].floor_volt); -+ vreg->corner[i].floor_volt -+ = vreg->corner[i - 1].floor_volt; -+ -+ if (vreg->corner[i].open_loop_volt -+ < vreg->corner[i].floor_volt) -+ vreg->corner[i].open_loop_volt -+ = vreg->corner[i].floor_volt; -+ if (vreg->corner[i].ceiling_volt -+ < vreg->corner[i].floor_volt) -+ vreg->corner[i].ceiling_volt -+ = vreg->corner[i].floor_volt; -+ } -+ } -+ -+ return rc; -+} -+ -+/** -+ * cpr3_print_quots() - print CPR target quotients into the kernel log for -+ * debugging purposes -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: none -+ */ -+void cpr3_print_quots(struct cpr3_regulator *vreg) -+{ -+ int i, j, pos; -+ size_t buflen; -+ char *buf; -+ -+ buflen = sizeof(*buf) * CPR3_RO_COUNT * (MAX_CHARS_PER_INT + 2); -+ buf = kzalloc(buflen, GFP_KERNEL); -+ if (!buf) -+ return; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ for (j = 0, pos = 0; j < CPR3_RO_COUNT; j++) -+ pos += scnprintf(buf + pos, buflen - pos, " %u", -+ vreg->corner[i].target_quot[j]); -+ cpr3_debug(vreg, "target quots[%2d]:%s\n", i, buf); -+ } -+ -+ kfree(buf); -+} -+ -+/** -+ * cpr3_determine_part_type() - determine the part type (SS/TT/FF). -+ * -+ * qcom,cpr-part-types prop tells the number of part types for which correction -+ * voltages are different. Another prop qcom,cpr-parts-voltage will contain the -+ * open loop fuse voltage which will be compared with this part voltage -+ * and accordingly part type will de determined. -+ * -+ * if qcom,cpr-part-types has value n, then qcom,cpr-parts-voltage will be -+ * array of n - 1 elements which will contain the voltage in increasing order. -+ * This function compares the fused volatge with all these voltage and returns -+ * the first index for which the fused volatge is greater. -+ * -+ * @vreg: Pointer to the CPR3 regulator -+ * @fuse_volt: fused open loop voltage which will be compared with -+ * qcom,cpr-parts-voltage array -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt) -+{ -+ int i, rc, len; -+ u32 volt; -+ int soc_version_major; -+ char prop_name[100]; -+ const char prop_name_def[] = "qcom,cpr-parts-voltage"; -+ const char prop_name_v2[] = "qcom,cpr-parts-voltage-v2"; -+ -+ soc_version_major = read_ipq_soc_version_major(); -+ BUG_ON(soc_version_major <= 0); -+ -+ if (of_property_read_u32(vreg->of_node, "qcom,cpr-part-types", -+ &vreg->part_type_supported)) -+ return 0; -+ -+ if (soc_version_major > 1) -+ strlcpy(prop_name, prop_name_v2, sizeof(prop_name_v2)); -+ else -+ strlcpy(prop_name, prop_name_def, sizeof(prop_name_def)); -+ -+ if (!of_find_property(vreg->of_node, prop_name, &len)) { -+ cpr3_err(vreg, "property %s is missing\n", prop_name); -+ return -EINVAL; -+ } -+ -+ if (len != (vreg->part_type_supported - 1) * sizeof(u32)) { -+ cpr3_err(vreg, "wrong len in qcom,cpr-parts-voltage\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < vreg->part_type_supported - 1; i++) { -+ rc = of_property_read_u32_index(vreg->of_node, -+ prop_name, i, &volt); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_name, rc); -+ return rc; -+ } -+ -+ if (fuse_volt < volt) -+ break; -+ } -+ -+ vreg->part_type = i; -+ return 0; -+} -+ -+int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg, -+ int *fuse_volt) -+{ -+ int i, rc, prev_volt; -+ int *volt_adjust; -+ char prop_str[75]; -+ int soc_version_major = read_ipq_soc_version_major(); -+ -+ BUG_ON(soc_version_major <= 0); -+ -+ if (vreg->part_type_supported) { -+ if (soc_version_major > 1) -+ snprintf(prop_str, sizeof(prop_str), -+ "qcom,cpr-cold-temp-voltage-adjustment-v2-%d", -+ vreg->part_type); -+ else -+ snprintf(prop_str, sizeof(prop_str), -+ "qcom,cpr-cold-temp-voltage-adjustment-%d", -+ vreg->part_type); -+ } else { -+ strlcpy(prop_str, "qcom,cpr-cold-temp-voltage-adjustment", -+ sizeof(prop_str)); -+ } -+ -+ if (!of_find_property(vreg->of_node, prop_str, NULL)) { -+ /* No adjustment required. */ -+ cpr3_info(vreg, "No cold temperature adjustment required.\n"); -+ return 0; -+ } -+ -+ volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust), -+ GFP_KERNEL); -+ if (!volt_adjust) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_array_property(vreg, prop_str, -+ vreg->fuse_corner_count, volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not load cold temp voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ if (volt_adjust[i]) { -+ prev_volt = fuse_volt[i]; -+ fuse_volt[i] += volt_adjust[i]; -+ cpr3_debug(vreg, -+ "adjusted fuse corner %d open-loop voltage: %d -> %d uV\n", -+ i, prev_volt, fuse_volt[i]); -+ } -+ } -+ -+done: -+ kfree(volt_adjust); -+ return rc; -+} -+ -+/** -+ * cpr3_can_adjust_cold_temp() - Is cold temperature adjustment available -+ * -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function checks the cold temperature threshold is available -+ * -+ * Return: true on cold temperature threshold is available, else false -+ */ -+bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg) -+{ -+ char prop_str[75]; -+ int soc_version_major = read_ipq_soc_version_major(); -+ -+ BUG_ON(soc_version_major <= 0); -+ -+ if (soc_version_major > 1) -+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2", -+ sizeof(prop_str)); -+ else -+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold", -+ sizeof(prop_str)); -+ -+ if (!of_find_property(vreg->of_node, prop_str, NULL)) { -+ /* No adjustment required. */ -+ return false; -+ } else -+ return true; -+} -+ -+/** -+ * cpr3_get_cold_temp_threshold() - get cold temperature threshold -+ * -+ * @vreg: Pointer to the CPR3 regulator -+ * @cold_temp: cold temperature read. -+ * -+ * This function reads the cold temperature threshold below which -+ * cold temperature adjustment margins will be applied. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp) -+{ -+ int rc; -+ u32 temp; -+ char req_prop_str[75], prop_str[75]; -+ int soc_version_major = read_ipq_soc_version_major(); -+ -+ BUG_ON(soc_version_major <= 0); -+ -+ if (vreg->part_type_supported) { -+ if (soc_version_major > 1) -+ snprintf(req_prop_str, sizeof(req_prop_str), -+ "qcom,cpr-cold-temp-voltage-adjustment-v2-%d", -+ vreg->part_type); -+ else -+ snprintf(req_prop_str, sizeof(req_prop_str), -+ "qcom,cpr-cold-temp-voltage-adjustment-%d", -+ vreg->part_type); -+ } else { -+ strlcpy(req_prop_str, "qcom,cpr-cold-temp-voltage-adjustment", -+ sizeof(req_prop_str)); -+ } -+ -+ if (soc_version_major > 1) -+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2", -+ sizeof(prop_str)); -+ else -+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold", -+ sizeof(prop_str)); -+ -+ if (!of_find_property(vreg->of_node, req_prop_str, NULL)) { -+ /* No adjustment required. */ -+ cpr3_info(vreg, "Cold temperature adjustment not required.\n"); -+ return 0; -+ } -+ -+ if (!of_find_property(vreg->of_node, prop_str, NULL)) { -+ /* No adjustment required. */ -+ cpr3_err(vreg, "Missing %s required for %s\n", -+ prop_str, req_prop_str); -+ return -EINVAL; -+ } -+ -+ rc = of_property_read_u32(vreg->of_node, prop_str, &temp); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_str, rc); -+ return rc; -+ } -+ -+ *cold_temp = temp; -+ return 0; -+} -+ -+/** -+ * cpr3_adjust_fused_open_loop_voltages() - adjust the fused open-loop voltages -+ * for each fuse corner according to device tree values -+ * @vreg: Pointer to the CPR3 regulator -+ * @fuse_volt: Pointer to an array of the fused open-loop voltage -+ * values -+ * -+ * Voltage values in fuse_volt are modified in place. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg, -+ int *fuse_volt) -+{ -+ int i, rc, prev_volt; -+ int *volt_adjust; -+ char prop_str[75]; -+ int soc_version_major = read_ipq_soc_version_major(); -+ -+ BUG_ON(soc_version_major <= 0); -+ -+ if (vreg->part_type_supported) { -+ if (soc_version_major > 1) -+ snprintf(prop_str, sizeof(prop_str), -+ "qcom,cpr-open-loop-voltage-fuse-adjustment-v2-%d", -+ vreg->part_type); -+ else -+ snprintf(prop_str, sizeof(prop_str), -+ "qcom,cpr-open-loop-voltage-fuse-adjustment-%d", -+ vreg->part_type); -+ } else { -+ strlcpy(prop_str, "qcom,cpr-open-loop-voltage-fuse-adjustment", -+ sizeof(prop_str)); -+ } -+ -+ if (!of_find_property(vreg->of_node, prop_str, NULL)) { -+ /* No adjustment required. */ -+ return 0; -+ } -+ -+ volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust), -+ GFP_KERNEL); -+ if (!volt_adjust) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_array_property(vreg, -+ prop_str, vreg->fuse_corner_count, volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not load open-loop fused voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ if (volt_adjust[i]) { -+ prev_volt = fuse_volt[i]; -+ fuse_volt[i] += volt_adjust[i]; -+ cpr3_debug(vreg, "adjusted fuse corner %d open-loop voltage: %d --> %d uV\n", -+ i, prev_volt, fuse_volt[i]); -+ } -+ } -+ -+done: -+ kfree(volt_adjust); -+ return rc; -+} -+ -+/** -+ * cpr3_adjust_open_loop_voltages() - adjust the open-loop voltages for each -+ * corner according to device tree values -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg) -+{ -+ int i, rc, prev_volt, min_volt; -+ int *volt_adjust, *volt_diff; -+ -+ if (!of_find_property(vreg->of_node, -+ "qcom,cpr-open-loop-voltage-adjustment", NULL)) { -+ /* No adjustment required. */ -+ return 0; -+ } -+ -+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), -+ GFP_KERNEL); -+ volt_diff = kcalloc(vreg->corner_count, sizeof(*volt_diff), GFP_KERNEL); -+ if (!volt_adjust || !volt_diff) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-open-loop-voltage-adjustment", 1, volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not load open-loop voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ if (volt_adjust[i]) { -+ prev_volt = vreg->corner[i].open_loop_volt; -+ vreg->corner[i].open_loop_volt += volt_adjust[i]; -+ cpr3_debug(vreg, "adjusted corner %d open-loop voltage: %d --> %d uV\n", -+ i, prev_volt, vreg->corner[i].open_loop_volt); -+ } -+ } -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,cpr-open-loop-voltage-min-diff", NULL)) { -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-open-loop-voltage-min-diff", 1, volt_diff); -+ if (rc) { -+ cpr3_err(vreg, "could not load minimum open-loop voltage differences, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ /* -+ * Ensure that open-loop voltages increase monotonically with respect -+ * to configurable minimum allowed differences. -+ */ -+ for (i = 1; i < vreg->corner_count; i++) { -+ min_volt = vreg->corner[i - 1].open_loop_volt + volt_diff[i]; -+ if (vreg->corner[i].open_loop_volt < min_volt) { -+ cpr3_debug(vreg, "adjusted corner %d open-loop voltage=%d uV < corner %d voltage=%d uV + min diff=%d uV; overriding: corner %d voltage=%d\n", -+ i, vreg->corner[i].open_loop_volt, -+ i - 1, vreg->corner[i - 1].open_loop_volt, -+ volt_diff[i], i, min_volt); -+ vreg->corner[i].open_loop_volt = min_volt; -+ } -+ } -+ -+done: -+ kfree(volt_diff); -+ kfree(volt_adjust); -+ return rc; -+} -+ -+/** -+ * cpr3_quot_adjustment() - returns the quotient adjustment value resulting from -+ * the specified voltage adjustment and RO scaling factor -+ * @ro_scale: The CPR ring oscillator (RO) scaling factor with units -+ * of QUOT/V -+ * @volt_adjust: The amount to adjust the voltage by in units of -+ * microvolts. This value may be positive or negative. -+ */ -+int cpr3_quot_adjustment(int ro_scale, int volt_adjust) -+{ -+ unsigned long long temp; -+ int quot_adjust; -+ int sign = 1; -+ -+ if (ro_scale < 0) { -+ sign = -sign; -+ ro_scale = -ro_scale; -+ } -+ -+ if (volt_adjust < 0) { -+ sign = -sign; -+ volt_adjust = -volt_adjust; -+ } -+ -+ temp = (unsigned long long)ro_scale * (unsigned long long)volt_adjust; -+ do_div(temp, 1000000); -+ -+ quot_adjust = temp; -+ quot_adjust *= sign; -+ -+ return quot_adjust; -+} -+ -+/** -+ * cpr3_voltage_adjustment() - returns the voltage adjustment value resulting -+ * from the specified quotient adjustment and RO scaling factor -+ * @ro_scale: The CPR ring oscillator (RO) scaling factor with units -+ * of QUOT/V -+ * @quot_adjust: The amount to adjust the quotient by in units of -+ * QUOT. This value may be positive or negative. -+ */ -+int cpr3_voltage_adjustment(int ro_scale, int quot_adjust) -+{ -+ unsigned long long temp; -+ int volt_adjust; -+ int sign = 1; -+ -+ if (ro_scale < 0) { -+ sign = -sign; -+ ro_scale = -ro_scale; -+ } -+ -+ if (quot_adjust < 0) { -+ sign = -sign; -+ quot_adjust = -quot_adjust; -+ } -+ -+ if (ro_scale == 0) -+ return 0; -+ -+ temp = (unsigned long long)quot_adjust * 1000000; -+ do_div(temp, ro_scale); -+ -+ volt_adjust = temp; -+ volt_adjust *= sign; -+ -+ return volt_adjust; -+} -+ -+/** -+ * cpr3_parse_closed_loop_voltage_adjustments() - load per-fuse-corner and -+ * per-corner closed-loop adjustment values from device tree -+ * @vreg: Pointer to the CPR3 regulator -+ * @ro_sel: Array of ring oscillator values selected for each -+ * fuse corner -+ * @volt_adjust: Pointer to array which will be filled with the -+ * per-corner closed-loop adjustment voltages -+ * @volt_adjust_fuse: Pointer to array which will be filled with the -+ * per-fuse-corner closed-loop adjustment voltages -+ * @ro_scale: Pointer to array which will be filled with the -+ * per-fuse-corner RO scaling factor values with units of -+ * QUOT/V -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_parse_closed_loop_voltage_adjustments( -+ struct cpr3_regulator *vreg, u64 *ro_sel, -+ int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) -+{ -+ int i, rc; -+ u32 *ro_all_scale; -+ -+ char volt_adj[] = "qcom,cpr-closed-loop-voltage-adjustment"; -+ char volt_fuse_adj[] = "qcom,cpr-closed-loop-voltage-fuse-adjustment"; -+ char ro_scaling[] = "qcom,cpr-ro-scaling-factor"; -+ -+ if (!of_find_property(vreg->of_node, volt_adj, NULL) -+ && !of_find_property(vreg->of_node, volt_fuse_adj, NULL) -+ && !vreg->aging_allowed) { -+ /* No adjustment required. */ -+ return 0; -+ } else if (!of_find_property(vreg->of_node, ro_scaling, NULL)) { -+ cpr3_err(vreg, "Missing %s required for closed-loop voltage adjustment.\n", -+ ro_scaling); -+ return -EINVAL; -+ } -+ -+ ro_all_scale = kcalloc(vreg->fuse_corner_count * CPR3_RO_COUNT, -+ sizeof(*ro_all_scale), GFP_KERNEL); -+ if (!ro_all_scale) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_array_property(vreg, ro_scaling, -+ vreg->fuse_corner_count * CPR3_RO_COUNT, ro_all_scale); -+ if (rc) { -+ cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) -+ ro_scale[i] = ro_all_scale[i * CPR3_RO_COUNT + ro_sel[i]]; -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ memcpy(vreg->corner[i].ro_scale, -+ &ro_all_scale[vreg->corner[i].cpr_fuse_corner * CPR3_RO_COUNT], -+ sizeof(*ro_all_scale) * CPR3_RO_COUNT); -+ -+ if (of_find_property(vreg->of_node, volt_fuse_adj, NULL)) { -+ rc = cpr3_parse_array_property(vreg, volt_fuse_adj, -+ vreg->fuse_corner_count, volt_adjust_fuse); -+ if (rc) { -+ cpr3_err(vreg, "could not load closed-loop fused voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ if (of_find_property(vreg->of_node, volt_adj, NULL)) { -+ rc = cpr3_parse_corner_array_property(vreg, volt_adj, -+ 1, volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+done: -+ kfree(ro_all_scale); -+ return rc; -+} -+ -+/** -+ * cpr3_apm_init() - initialize APM data for a CPR3 controller -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * This function loads memory array power mux (APM) data from device tree -+ * if it is present and requests a handle to the appropriate APM controller -+ * device. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_apm_init(struct cpr3_controller *ctrl) -+{ -+ struct device_node *node = ctrl->dev->of_node; -+ int rc; -+ -+ if (!of_find_property(node, "qcom,apm-ctrl", NULL)) { -+ /* No APM used */ -+ return 0; -+ } -+ -+ ctrl->apm = msm_apm_ctrl_dev_get(ctrl->dev); -+ if (IS_ERR(ctrl->apm)) { -+ rc = PTR_ERR(ctrl->apm); -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "APM get failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ rc = of_property_read_u32(node, "qcom,apm-threshold-voltage", -+ &ctrl->apm_threshold_volt); -+ if (rc) { -+ cpr3_err(ctrl, "error reading qcom,apm-threshold-voltage, rc=%d\n", -+ rc); -+ return rc; -+ } -+ ctrl->apm_threshold_volt -+ = CPR3_ROUND(ctrl->apm_threshold_volt, ctrl->step_volt); -+ -+ /* No error check since this is an optional property. */ -+ of_property_read_u32(node, "qcom,apm-hysteresis-voltage", -+ &ctrl->apm_adj_volt); -+ ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt); -+ -+ ctrl->apm_high_supply = MSM_APM_SUPPLY_APCC; -+ ctrl->apm_low_supply = MSM_APM_SUPPLY_MX; -+ -+ return 0; -+} -+ -+/** -+ * cpr3_mem_acc_init() - initialize mem-acc regulator data for -+ * a CPR3 regulator -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_mem_acc_init(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ u32 *temp; -+ int i, rc; -+ -+ if (!ctrl->mem_acc_regulator) { -+ cpr3_info(ctrl, "not using memory accelerator regulator\n"); -+ return 0; -+ } -+ -+ temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL); -+ if (!temp) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_corner_array_property(vreg, "qcom,mem-acc-voltage", -+ 1, temp); -+ if (rc) { -+ cpr3_err(ctrl, "could not load mem-acc corners, rc=%d\n", rc); -+ } else { -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].mem_acc_volt = temp[i]; -+ } -+ -+ kfree(temp); -+ return rc; -+} -+ -+/** -+ * cpr4_load_core_and_temp_adj() - parse amount of voltage adjustment for -+ * per-online-core and per-temperature voltage adjustment for a -+ * given corner or corner band from device tree. -+ * @vreg: Pointer to the CPR3 regulator -+ * @num: Corner number or corner band number -+ * @use_corner_band: Boolean indicating if the CPR3 regulator supports -+ * adjustments per corner band -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_load_core_and_temp_adj(struct cpr3_regulator *vreg, -+ int num, bool use_corner_band) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct cpr4_sdelta *sdelta; -+ int sdelta_size, i, j, pos, rc = 0; -+ char str[75]; -+ size_t buflen; -+ char *buf; -+ -+ sdelta = use_corner_band ? vreg->corner_band[num].sdelta : -+ vreg->corner[num].sdelta; -+ -+ if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj) { -+ /* corner doesn't need sdelta table */ -+ sdelta->max_core_count = 0; -+ sdelta->temp_band_count = 0; -+ return rc; -+ } -+ -+ sdelta_size = sdelta->max_core_count * sdelta->temp_band_count; -+ if (use_corner_band) -+ snprintf(str, sizeof(str), -+ "corner_band=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n", -+ num, sdelta->max_core_count, -+ sdelta->temp_band_count, sdelta_size); -+ else -+ snprintf(str, sizeof(str), -+ "corner=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n", -+ num, sdelta->max_core_count, -+ sdelta->temp_band_count, sdelta_size); -+ -+ cpr3_debug(vreg, "%s", str); -+ -+ sdelta->table = devm_kcalloc(ctrl->dev, sdelta_size, -+ sizeof(*sdelta->table), GFP_KERNEL); -+ if (!sdelta->table) -+ return -ENOMEM; -+ -+ if (use_corner_band) -+ snprintf(str, sizeof(str), -+ "qcom,cpr-corner-band%d-temp-core-voltage-adjustment", -+ num + CPR3_CORNER_OFFSET); -+ else -+ snprintf(str, sizeof(str), -+ "qcom,cpr-corner%d-temp-core-voltage-adjustment", -+ num + CPR3_CORNER_OFFSET); -+ -+ rc = cpr3_parse_array_property(vreg, str, sdelta_size, -+ sdelta->table); -+ if (rc) { -+ cpr3_err(vreg, "could not load %s, rc=%d\n", str, rc); -+ return rc; -+ } -+ -+ /* -+ * Convert sdelta margins from uV to PMIC steps and apply negation to -+ * follow the SDELTA register semantics. -+ */ -+ for (i = 0; i < sdelta_size; i++) -+ sdelta->table[i] = -(sdelta->table[i] / ctrl->step_volt); -+ -+ buflen = sizeof(*buf) * sdelta_size * (MAX_CHARS_PER_INT + 2); -+ buf = kzalloc(buflen, GFP_KERNEL); -+ if (!buf) -+ return rc; -+ -+ for (i = 0; i < sdelta->max_core_count; i++) { -+ for (j = 0, pos = 0; j < sdelta->temp_band_count; j++) -+ pos += scnprintf(buf + pos, buflen - pos, " %u", -+ sdelta->table[i * sdelta->temp_band_count + j]); -+ cpr3_debug(vreg, "sdelta[%d]:%s\n", i, buf); -+ } -+ -+ kfree(buf); -+ return rc; -+} -+ -+/** -+ * cpr4_parse_core_count_temp_voltage_adj() - parse configuration data for -+ * per-online-core and per-temperature voltage adjustment for -+ * a CPR3 regulator from device tree. -+ * @vreg: Pointer to the CPR3 regulator -+ * @use_corner_band: Boolean indicating if the CPR3 regulator supports -+ * adjustments per corner band -+ * -+ * This function supports parsing of per-online-core and per-temperature -+ * adjustments per corner or per corner band. CPR controllers which support -+ * corner bands apply the same adjustments to all corners within a corner band. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr4_parse_core_count_temp_voltage_adj( -+ struct cpr3_regulator *vreg, bool use_corner_band) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct device_node *node = vreg->of_node; -+ struct cpr3_corner *corner; -+ struct cpr4_sdelta *sdelta; -+ int i, sdelta_table_count, rc = 0; -+ int *allow_core_count_adj = NULL, *allow_temp_adj = NULL; -+ char prop_str[75]; -+ -+ if (of_find_property(node, use_corner_band ? -+ "qcom,corner-band-allow-temp-adjustment" -+ : "qcom,corner-allow-temp-adjustment", NULL)) { -+ if (!ctrl->allow_temp_adj) { -+ cpr3_err(ctrl, "Temperature adjustment configurations missing\n"); -+ return -EINVAL; -+ } -+ -+ vreg->allow_temp_adj = true; -+ } -+ -+ if (of_find_property(node, use_corner_band ? -+ "qcom,corner-band-allow-core-count-adjustment" -+ : "qcom,corner-allow-core-count-adjustment", -+ NULL)) { -+ rc = of_property_read_u32(node, "qcom,max-core-count", -+ &vreg->max_core_count); -+ if (rc) { -+ cpr3_err(vreg, "error reading qcom,max-core-count, rc=%d\n", -+ rc); -+ return -EINVAL; -+ } -+ -+ vreg->allow_core_count_adj = true; -+ ctrl->allow_core_count_adj = true; -+ } -+ -+ if (!vreg->allow_temp_adj && !vreg->allow_core_count_adj) { -+ /* -+ * Both per-online-core and temperature based adjustments are -+ * disabled for this regulator. -+ */ -+ return 0; -+ } else if (!vreg->allow_core_count_adj) { -+ /* -+ * Only per-temperature voltage adjusments are allowed. -+ * Keep max core count value as 1 to allocate SDELTA. -+ */ -+ vreg->max_core_count = 1; -+ } -+ -+ if (vreg->allow_core_count_adj) { -+ allow_core_count_adj = kcalloc(vreg->corner_count, -+ sizeof(*allow_core_count_adj), -+ GFP_KERNEL); -+ if (!allow_core_count_adj) -+ return -ENOMEM; -+ -+ snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ? -+ "qcom,corner-band-allow-core-count-adjustment" : -+ "qcom,corner-allow-core-count-adjustment"); -+ -+ rc = use_corner_band ? -+ cpr3_parse_corner_band_array_property(vreg, prop_str, -+ 1, allow_core_count_adj) : -+ cpr3_parse_corner_array_property(vreg, prop_str, -+ 1, allow_core_count_adj); -+ if (rc) { -+ cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str, -+ rc); -+ goto done; -+ } -+ } -+ -+ if (vreg->allow_temp_adj) { -+ allow_temp_adj = kcalloc(vreg->corner_count, -+ sizeof(*allow_temp_adj), GFP_KERNEL); -+ if (!allow_temp_adj) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ? -+ "qcom,corner-band-allow-temp-adjustment" : -+ "qcom,corner-allow-temp-adjustment"); -+ -+ rc = use_corner_band ? -+ cpr3_parse_corner_band_array_property(vreg, prop_str, -+ 1, allow_temp_adj) : -+ cpr3_parse_corner_array_property(vreg, prop_str, -+ 1, allow_temp_adj); -+ if (rc) { -+ cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str, -+ rc); -+ goto done; -+ } -+ } -+ -+ sdelta_table_count = use_corner_band ? vreg->corner_band_count : -+ vreg->corner_count; -+ -+ for (i = 0; i < sdelta_table_count; i++) { -+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*corner->sdelta), -+ GFP_KERNEL); -+ if (!sdelta) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ if (allow_core_count_adj) -+ sdelta->allow_core_count_adj = allow_core_count_adj[i]; -+ if (allow_temp_adj) -+ sdelta->allow_temp_adj = allow_temp_adj[i]; -+ sdelta->max_core_count = vreg->max_core_count; -+ sdelta->temp_band_count = ctrl->temp_band_count; -+ -+ if (use_corner_band) -+ vreg->corner_band[i].sdelta = sdelta; -+ else -+ vreg->corner[i].sdelta = sdelta; -+ -+ rc = cpr4_load_core_and_temp_adj(vreg, i, use_corner_band); -+ if (rc) { -+ cpr3_err(vreg, "corner/band %d core and temp adjustment loading failed, rc=%d\n", -+ i, rc); -+ goto done; -+ } -+ } -+ -+done: -+ kfree(allow_core_count_adj); -+ kfree(allow_temp_adj); -+ -+ return rc; -+} -+ -+/** -+ * cprh_adjust_voltages_for_apm() - adjust per-corner floor and ceiling voltages -+ * so that they do not overlap the APM threshold voltage. -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * The memory array power mux (APM) must be configured for a specific supply -+ * based upon where the VDD voltage lies with respect to the APM threshold -+ * voltage. When using CPR hardware closed-loop, the voltage may vary anywhere -+ * between the floor and ceiling voltage without software notification. -+ * Therefore, it is required that the floor to ceiling range for every corner -+ * not intersect the APM threshold voltage. This function adjusts the floor to -+ * ceiling range for each corner which violates this requirement. -+ * -+ * The following algorithm is applied: -+ * if floor < threshold <= ceiling: -+ * if open_loop >= threshold, then floor = threshold - adj -+ * else ceiling = threshold - step -+ * where: -+ * adj = APM hysteresis voltage established to minimize the number of -+ * corners with artificially increased floor voltages -+ * step = voltage in microvolts of a single step of the VDD supply -+ * -+ * The open-loop voltage is also bounded by the new floor or ceiling value as -+ * needed. -+ * -+ * Return: none -+ */ -+void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct cpr3_corner *corner; -+ int i, adj, threshold, prev_ceiling, prev_floor, prev_open_loop; -+ -+ if (!ctrl->apm_threshold_volt) { -+ /* APM not being used. */ -+ return; -+ } -+ -+ ctrl->apm_threshold_volt = CPR3_ROUND(ctrl->apm_threshold_volt, -+ ctrl->step_volt); -+ ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt); -+ -+ threshold = ctrl->apm_threshold_volt; -+ adj = ctrl->apm_adj_volt; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ corner = &vreg->corner[i]; -+ -+ if (threshold <= corner->floor_volt -+ || threshold > corner->ceiling_volt) -+ continue; -+ -+ prev_floor = corner->floor_volt; -+ prev_ceiling = corner->ceiling_volt; -+ prev_open_loop = corner->open_loop_volt; -+ -+ if (corner->open_loop_volt >= threshold) { -+ corner->floor_volt = max(corner->floor_volt, -+ threshold - adj); -+ if (corner->open_loop_volt < corner->floor_volt) -+ corner->open_loop_volt = corner->floor_volt; -+ } else { -+ corner->ceiling_volt = threshold - ctrl->step_volt; -+ } -+ -+ if (corner->floor_volt != prev_floor -+ || corner->ceiling_volt != prev_ceiling -+ || corner->open_loop_volt != prev_open_loop) -+ cpr3_debug(vreg, "APM threshold=%d, APM adj=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n", -+ threshold, adj, i, prev_floor, prev_ceiling, -+ prev_open_loop, corner->floor_volt, -+ corner->ceiling_volt, corner->open_loop_volt); -+ } -+} -+ -+/** -+ * cprh_adjust_voltages_for_mem_acc() - adjust per-corner floor and ceiling -+ * voltages so that they do not intersect the MEM ACC threshold -+ * voltage -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * The following algorithm is applied: -+ * if floor < threshold <= ceiling: -+ * if open_loop >= threshold, then floor = threshold -+ * else ceiling = threshold - step -+ * where: -+ * step = voltage in microvolts of a single step of the VDD supply -+ * -+ * The open-loop voltage is also bounded by the new floor or ceiling value as -+ * needed. -+ * -+ * Return: none -+ */ -+void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct cpr3_corner *corner; -+ int i, threshold, prev_ceiling, prev_floor, prev_open_loop; -+ -+ if (!ctrl->mem_acc_threshold_volt) { -+ /* MEM ACC not being used. */ -+ return; -+ } -+ -+ ctrl->mem_acc_threshold_volt = CPR3_ROUND(ctrl->mem_acc_threshold_volt, -+ ctrl->step_volt); -+ -+ threshold = ctrl->mem_acc_threshold_volt; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ corner = &vreg->corner[i]; -+ -+ if (threshold <= corner->floor_volt -+ || threshold > corner->ceiling_volt) -+ continue; -+ -+ prev_floor = corner->floor_volt; -+ prev_ceiling = corner->ceiling_volt; -+ prev_open_loop = corner->open_loop_volt; -+ -+ if (corner->open_loop_volt >= threshold) { -+ corner->floor_volt = max(corner->floor_volt, threshold); -+ if (corner->open_loop_volt < corner->floor_volt) -+ corner->open_loop_volt = corner->floor_volt; -+ } else { -+ corner->ceiling_volt = threshold - ctrl->step_volt; -+ } -+ -+ if (corner->floor_volt != prev_floor -+ || corner->ceiling_volt != prev_ceiling -+ || corner->open_loop_volt != prev_open_loop) -+ cpr3_debug(vreg, "MEM ACC threshold=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n", -+ threshold, i, prev_floor, prev_ceiling, -+ prev_open_loop, corner->floor_volt, -+ corner->ceiling_volt, corner->open_loop_volt); -+ } -+} -+ -+/** -+ * cpr3_apply_closed_loop_offset_voltages() - modify the closed-loop voltage -+ * adjustments by the amounts that are needed for this -+ * fuse combo -+ * @vreg: Pointer to the CPR3 regulator -+ * @volt_adjust: Array of closed-loop voltage adjustment values of length -+ * vreg->corner_count which is further adjusted based upon -+ * offset voltage fuse values. -+ * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length -+ * vreg->fuse_corner_count. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr3_apply_closed_loop_offset_voltages(struct cpr3_regulator *vreg, -+ int *volt_adjust, int *fuse_volt_adjust) -+{ -+ u32 *corner_map; -+ int rc = 0, i; -+ -+ if (!of_find_property(vreg->of_node, -+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL)) { -+ /* No closed-loop offset required. */ -+ return 0; -+ } -+ -+ corner_map = kcalloc(vreg->corner_count, sizeof(*corner_map), -+ GFP_KERNEL); -+ if (!corner_map) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map", -+ 1, corner_map); -+ if (rc) -+ goto done; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ if (corner_map[i] == 0) { -+ continue; -+ } else if (corner_map[i] > vreg->fuse_corner_count) { -+ cpr3_err(vreg, "corner %d mapped to invalid fuse corner: %u\n", -+ i, corner_map[i]); -+ rc = -EINVAL; -+ goto done; -+ } -+ -+ volt_adjust[i] += fuse_volt_adjust[corner_map[i] - 1]; -+ } -+ -+done: -+ kfree(corner_map); -+ return rc; -+} -+ -+/** -+ * cpr3_enforce_inc_quotient_monotonicity() - Ensure that target quotients -+ * increase monotonically from lower to higher corners -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static void cpr3_enforce_inc_quotient_monotonicity(struct cpr3_regulator *vreg) -+{ -+ int i, j; -+ -+ for (i = 1; i < vreg->corner_count; i++) { -+ for (j = 0; j < CPR3_RO_COUNT; j++) { -+ if (vreg->corner[i].target_quot[j] -+ && vreg->corner[i].target_quot[j] -+ < vreg->corner[i - 1].target_quot[j]) { -+ cpr3_debug(vreg, "corner %d RO%u target quot=%u < corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", -+ i, j, -+ vreg->corner[i].target_quot[j], -+ i - 1, j, -+ vreg->corner[i - 1].target_quot[j], -+ i, j, -+ vreg->corner[i - 1].target_quot[j]); -+ vreg->corner[i].target_quot[j] -+ = vreg->corner[i - 1].target_quot[j]; -+ } -+ } -+ } -+} -+ -+/** -+ * cpr3_enforce_dec_quotient_monotonicity() - Ensure that target quotients -+ * decrease monotonically from higher to lower corners -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static void cpr3_enforce_dec_quotient_monotonicity(struct cpr3_regulator *vreg) -+{ -+ int i, j; -+ -+ for (i = vreg->corner_count - 2; i >= 0; i--) { -+ for (j = 0; j < CPR3_RO_COUNT; j++) { -+ if (vreg->corner[i + 1].target_quot[j] -+ && vreg->corner[i].target_quot[j] -+ > vreg->corner[i + 1].target_quot[j]) { -+ cpr3_debug(vreg, "corner %d RO%u target quot=%u > corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", -+ i, j, -+ vreg->corner[i].target_quot[j], -+ i + 1, j, -+ vreg->corner[i + 1].target_quot[j], -+ i, j, -+ vreg->corner[i + 1].target_quot[j]); -+ vreg->corner[i].target_quot[j] -+ = vreg->corner[i + 1].target_quot[j]; -+ } -+ } -+ } -+} -+ -+/** -+ * _cpr3_adjust_target_quotients() - adjust the target quotients for each -+ * corner of the regulator according to input adjustment and -+ * scaling arrays -+ * @vreg: Pointer to the CPR3 regulator -+ * @volt_adjust: Pointer to an array of closed-loop voltage adjustments -+ * with units of microvolts. The array must have -+ * vreg->corner_count number of elements. -+ * @ro_scale: Pointer to a flattened 2D array of RO scaling factors. -+ * The array must have an inner dimension of CPR3_RO_COUNT -+ * and an outer dimension of vreg->corner_count -+ * @label: Null terminated string providing a label for the type -+ * of adjustment. -+ * -+ * Return: true if any corners received a positive voltage adjustment (> 0), -+ * else false -+ */ -+static bool _cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, -+ const int *volt_adjust, const int *ro_scale, const char *label) -+{ -+ int i, j, quot_adjust; -+ bool is_increasing = false; -+ u32 prev_quot; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ for (j = 0; j < CPR3_RO_COUNT; j++) { -+ if (vreg->corner[i].target_quot[j]) { -+ quot_adjust = cpr3_quot_adjustment( -+ ro_scale[i * CPR3_RO_COUNT + j], -+ volt_adjust[i]); -+ if (quot_adjust) { -+ prev_quot = vreg->corner[i]. -+ target_quot[j]; -+ vreg->corner[i].target_quot[j] -+ += quot_adjust; -+ cpr3_debug(vreg, "adjusted corner %d RO%d target quot %s: %u --> %u (%d uV)\n", -+ i, j, label, prev_quot, -+ vreg->corner[i].target_quot[j], -+ volt_adjust[i]); -+ } -+ } -+ } -+ if (volt_adjust[i] > 0) -+ is_increasing = true; -+ } -+ -+ return is_increasing; -+} -+ -+/** -+ * cpr3_adjust_target_quotients() - adjust the target quotients for each -+ * corner according to device tree values and fuse values -+ * @vreg: Pointer to the CPR3 regulator -+ * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length -+ * vreg->fuse_corner_count. This parameter could be null -+ * pointer when no fused adjustments are needed. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg, -+ int *fuse_volt_adjust) -+{ -+ int i, rc; -+ int *volt_adjust, *ro_scale; -+ bool explicit_adjustment, fused_adjustment, is_increasing; -+ -+ explicit_adjustment = of_find_property(vreg->of_node, -+ "qcom,cpr-closed-loop-voltage-adjustment", NULL); -+ fused_adjustment = of_find_property(vreg->of_node, -+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL); -+ -+ if (!explicit_adjustment && !fused_adjustment && !vreg->aging_allowed) { -+ /* No adjustment required. */ -+ return 0; -+ } else if (!of_find_property(vreg->of_node, -+ "qcom,cpr-ro-scaling-factor", NULL)) { -+ cpr3_err(vreg, "qcom,cpr-ro-scaling-factor is required for closed-loop voltage adjustment, but is missing\n"); -+ return -EINVAL; -+ } -+ -+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), -+ GFP_KERNEL); -+ ro_scale = kcalloc(vreg->corner_count * CPR3_RO_COUNT, -+ sizeof(*ro_scale), GFP_KERNEL); -+ if (!volt_adjust || !ro_scale) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-ro-scaling-factor", CPR3_RO_COUNT, ro_scale); -+ if (rc) { -+ cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ memcpy(vreg->corner[i].ro_scale, &ro_scale[i * CPR3_RO_COUNT], -+ sizeof(*ro_scale) * CPR3_RO_COUNT); -+ -+ if (explicit_adjustment) { -+ rc = cpr3_parse_corner_array_property(vreg, -+ "qcom,cpr-closed-loop-voltage-adjustment", -+ 1, volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ _cpr3_adjust_target_quotients(vreg, volt_adjust, ro_scale, -+ "from DT"); -+ cpr3_enforce_inc_quotient_monotonicity(vreg); -+ } -+ -+ if (fused_adjustment && fuse_volt_adjust) { -+ memset(volt_adjust, 0, -+ sizeof(*volt_adjust) * vreg->corner_count); -+ -+ rc = cpr3_apply_closed_loop_offset_voltages(vreg, volt_adjust, -+ fuse_volt_adjust); -+ if (rc) { -+ cpr3_err(vreg, "could not apply fused closed-loop voltage reductions, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ is_increasing = _cpr3_adjust_target_quotients(vreg, volt_adjust, -+ ro_scale, "from fuse"); -+ if (is_increasing) -+ cpr3_enforce_inc_quotient_monotonicity(vreg); -+ else -+ cpr3_enforce_dec_quotient_monotonicity(vreg); -+ } -+ -+done: -+ kfree(volt_adjust); -+ kfree(ro_scale); -+ return rc; -+} ---- /dev/null -+++ b/drivers/regulator/cpr4-apss-regulator.c -@@ -0,0 +1,1819 @@ -+/* -+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#define pr_fmt(fmt) "%s: " fmt, __func__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cpr3-regulator.h" -+ -+#define IPQ807x_APSS_FUSE_CORNERS 4 -+#define IPQ817x_APPS_FUSE_CORNERS 2 -+#define IPQ6018_APSS_FUSE_CORNERS 4 -+#define IPQ9574_APSS_FUSE_CORNERS 4 -+ -+u32 g_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS; -+ -+/** -+ * struct cpr4_ipq807x_apss_fuses - APSS specific fuse data for IPQ807x -+ * @ro_sel: Ring oscillator select fuse parameter value for each -+ * fuse corner -+ * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value -+ * for each fuse corner (raw, not converted to a voltage) -+ * @target_quot: CPR target quotient fuse parameter value for each fuse -+ * corner -+ * @quot_offset: CPR target quotient offset fuse parameter value for each -+ * fuse corner (raw, not unpacked) used for target quotient -+ * interpolation -+ * @speed_bin: Application processor speed bin fuse parameter value for -+ * the given chip -+ * @cpr_fusing_rev: CPR fusing revision fuse parameter value -+ * @boost_cfg: CPR boost configuration fuse parameter value -+ * @boost_voltage: CPR boost voltage fuse parameter value (raw, not -+ * converted to a voltage) -+ * -+ * This struct holds the values for all of the fuses read from memory. -+ */ -+struct cpr4_ipq807x_apss_fuses { -+ u64 ro_sel[IPQ807x_APSS_FUSE_CORNERS]; -+ u64 init_voltage[IPQ807x_APSS_FUSE_CORNERS]; -+ u64 target_quot[IPQ807x_APSS_FUSE_CORNERS]; -+ u64 quot_offset[IPQ807x_APSS_FUSE_CORNERS]; -+ u64 speed_bin; -+ u64 cpr_fusing_rev; -+ u64 boost_cfg; -+ u64 boost_voltage; -+ u64 misc; -+}; -+ -+/* -+ * fuse combo = fusing revision + 8 * (speed bin) -+ * where: fusing revision = 0 - 7 and speed bin = 0 - 7 -+ */ -+#define CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT 64 -+ -+/* -+ * Constants which define the name of each fuse corner. -+ */ -+enum cpr4_ipq807x_apss_fuse_corner { -+ CPR4_IPQ807x_APSS_FUSE_CORNER_SVS = 0, -+ CPR4_IPQ807x_APSS_FUSE_CORNER_NOM = 1, -+ CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO = 2, -+ CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO = 3, -+}; -+ -+static const char * const cpr4_ipq807x_apss_fuse_corner_name[] = { -+ [CPR4_IPQ807x_APSS_FUSE_CORNER_SVS] = "SVS", -+ [CPR4_IPQ807x_APSS_FUSE_CORNER_NOM] = "NOM", -+ [CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO] = "TURBO", -+ [CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO] = "STURBO", -+}; -+ -+/* -+ * IPQ807x APSS fuse parameter locations: -+ * -+ * Structs are organized with the following dimensions: -+ * Outer: 0 to 3 for fuse corners from lowest to highest corner -+ * Inner: large enough to hold the longest set of parameter segments which -+ * fully defines a fuse parameter, +1 (for NULL termination). -+ * Each segment corresponds to a contiguous group of bits from a -+ * single fuse row. These segments are concatentated together in -+ * order to form the full fuse parameter value. The segments for -+ * a given parameter may correspond to different fuse rows. -+ */ -+static struct cpr3_fuse_param -+ipq807x_apss_ro_sel_param[IPQ807x_APSS_FUSE_CORNERS][2] = { -+ {{73, 8, 11}, {} }, -+ {{73, 4, 7}, {} }, -+ {{73, 0, 3}, {} }, -+ {{73, 12, 15}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq807x_apss_init_voltage_param[IPQ807x_APSS_FUSE_CORNERS][2] = { -+ {{71, 18, 23}, {} }, -+ {{71, 12, 17}, {} }, -+ {{71, 6, 11}, {} }, -+ {{71, 0, 5}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq807x_apss_target_quot_param[IPQ807x_APSS_FUSE_CORNERS][2] = { -+ {{72, 32, 43}, {} }, -+ {{72, 20, 31}, {} }, -+ {{72, 8, 19}, {} }, -+ {{72, 44, 55}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq807x_apss_quot_offset_param[IPQ807x_APSS_FUSE_CORNERS][2] = { -+ {{} }, -+ {{71, 46, 52}, {} }, -+ {{71, 39, 45}, {} }, -+ {{71, 32, 38}, {} }, -+}; -+ -+static struct cpr3_fuse_param ipq807x_cpr_fusing_rev_param[] = { -+ {71, 53, 55}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq807x_apss_speed_bin_param[] = { -+ {36, 40, 42}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq807x_cpr_boost_fuse_cfg_param[] = { -+ {36, 43, 45}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq807x_apss_boost_fuse_volt_param[] = { -+ {71, 0, 5}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq807x_misc_fuse_volt_adj_param[] = { -+ {36, 54, 54}, -+ {}, -+}; -+ -+static struct cpr3_fuse_parameters ipq807x_fuse_params = { -+ .apss_ro_sel_param = ipq807x_apss_ro_sel_param, -+ .apss_init_voltage_param = ipq807x_apss_init_voltage_param, -+ .apss_target_quot_param = ipq807x_apss_target_quot_param, -+ .apss_quot_offset_param = ipq807x_apss_quot_offset_param, -+ .cpr_fusing_rev_param = ipq807x_cpr_fusing_rev_param, -+ .apss_speed_bin_param = ipq807x_apss_speed_bin_param, -+ .cpr_boost_fuse_cfg_param = ipq807x_cpr_boost_fuse_cfg_param, -+ .apss_boost_fuse_volt_param = ipq807x_apss_boost_fuse_volt_param, -+ .misc_fuse_volt_adj_param = ipq807x_misc_fuse_volt_adj_param -+}; -+ -+/* -+ * The number of possible values for misc fuse is -+ * 2^(#bits defined for misc fuse) -+ */ -+#define IPQ807x_MISC_FUSE_VAL_COUNT BIT(1) -+ -+/* -+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x -+ */ -+static int ipq807x_apss_fuse_ref_volt -+ [IPQ807x_APSS_FUSE_CORNERS] = { -+ 720000, -+ 864000, -+ 992000, -+ 1064000, -+}; -+ -+#define IPQ807x_APSS_FUSE_STEP_VOLT 8000 -+#define IPQ807x_APSS_VOLTAGE_FUSE_SIZE 6 -+#define IPQ807x_APSS_QUOT_OFFSET_SCALE 5 -+ -+#define IPQ807x_APSS_CPR_SENSOR_COUNT 6 -+ -+#define IPQ807x_APSS_CPR_CLOCK_RATE 19200000 -+ -+#define IPQ807x_APSS_MAX_TEMP_POINTS 3 -+#define IPQ807x_APSS_TEMP_SENSOR_ID_START 4 -+#define IPQ807x_APSS_TEMP_SENSOR_ID_END 13 -+/* -+ * Boost voltage fuse reference and ceiling voltages in microvolts for -+ * IPQ807x. -+ */ -+#define IPQ807x_APSS_BOOST_FUSE_REF_VOLT 1140000 -+#define IPQ807x_APSS_BOOST_CEILING_VOLT 1140000 -+#define IPQ807x_APSS_BOOST_FLOOR_VOLT 900000 -+#define MAX_BOOST_CONFIG_FUSE_VALUE 8 -+ -+#define IPQ807x_APSS_CPR_SDELTA_CORE_COUNT 15 -+ -+#define IPQ807x_APSS_CPR_TCSR_START 8 -+#define IPQ807x_APSS_CPR_TCSR_END 9 -+ -+/* -+ * Array of integer values mapped to each of the boost config fuse values to -+ * indicate boost enable/disable status. -+ */ -+static bool boost_fuse[MAX_BOOST_CONFIG_FUSE_VALUE] = {0, 1, 1, 1, 1, 1, 1, 1}; -+ -+/* -+ * IPQ6018 (Few parameters are changed, remaining are same as IPQ807x) -+ */ -+#define IPQ6018_APSS_FUSE_STEP_VOLT 12500 -+#define IPQ6018_APSS_CPR_CLOCK_RATE 24000000 -+ -+static struct cpr3_fuse_param -+ipq6018_apss_ro_sel_param[IPQ6018_APSS_FUSE_CORNERS][2] = { -+ {{75, 8, 11}, {} }, -+ {{75, 4, 7}, {} }, -+ {{75, 0, 3}, {} }, -+ {{75, 12, 15}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq6018_apss_init_voltage_param[IPQ6018_APSS_FUSE_CORNERS][2] = { -+ {{73, 18, 23}, {} }, -+ {{73, 12, 17}, {} }, -+ {{73, 6, 11}, {} }, -+ {{73, 0, 5}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq6018_apss_target_quot_param[IPQ6018_APSS_FUSE_CORNERS][2] = { -+ {{74, 32, 43}, {} }, -+ {{74, 20, 31}, {} }, -+ {{74, 8, 19}, {} }, -+ {{74, 44, 55}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq6018_apss_quot_offset_param[IPQ6018_APSS_FUSE_CORNERS][2] = { -+ {{} }, -+ {{73, 48, 55}, {} }, -+ {{73, 40, 47}, {} }, -+ {{73, 32, 39}, {} }, -+}; -+ -+static struct cpr3_fuse_param ipq6018_cpr_fusing_rev_param[] = { -+ {75, 16, 18}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq6018_apss_speed_bin_param[] = { -+ {36, 40, 42}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq6018_cpr_boost_fuse_cfg_param[] = { -+ {36, 43, 45}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq6018_apss_boost_fuse_volt_param[] = { -+ {73, 0, 5}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq6018_misc_fuse_volt_adj_param[] = { -+ {36, 54, 54}, -+ {}, -+}; -+ -+static struct cpr3_fuse_parameters ipq6018_fuse_params = { -+ .apss_ro_sel_param = ipq6018_apss_ro_sel_param, -+ .apss_init_voltage_param = ipq6018_apss_init_voltage_param, -+ .apss_target_quot_param = ipq6018_apss_target_quot_param, -+ .apss_quot_offset_param = ipq6018_apss_quot_offset_param, -+ .cpr_fusing_rev_param = ipq6018_cpr_fusing_rev_param, -+ .apss_speed_bin_param = ipq6018_apss_speed_bin_param, -+ .cpr_boost_fuse_cfg_param = ipq6018_cpr_boost_fuse_cfg_param, -+ .apss_boost_fuse_volt_param = ipq6018_apss_boost_fuse_volt_param, -+ .misc_fuse_volt_adj_param = ipq6018_misc_fuse_volt_adj_param -+}; -+ -+ -+/* -+ * Boost voltage fuse reference and ceiling voltages in microvolts for -+ * IPQ6018. -+ */ -+#define IPQ6018_APSS_BOOST_FUSE_REF_VOLT 1140000 -+#define IPQ6018_APSS_BOOST_CEILING_VOLT 1140000 -+#define IPQ6018_APSS_BOOST_FLOOR_VOLT 900000 -+ -+/* -+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x -+ */ -+static int ipq6018_apss_fuse_ref_volt -+ [IPQ6018_APSS_FUSE_CORNERS] = { -+ 725000, -+ 862500, -+ 987500, -+ 1062500, -+}; -+ -+/* -+ * IPQ6018 Memory ACC settings on TCSR -+ * -+ * Turbo_L1: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x10 -+ * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x1 -+ * Other modes: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x0 -+ * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x0 -+ * -+ */ -+#define IPQ6018_APSS_MEM_ACC_TCSR_COUNT 2 -+#define TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x1946178 -+#define TCSR_CUSTOM_VDDAPC0_ACC_1 0x1946124 -+ -+struct mem_acc_tcsr { -+ u32 phy_addr; -+ void __iomem *ioremap_addr; -+ u32 value; -+}; -+ -+static struct mem_acc_tcsr ipq6018_mem_acc_tcsr[IPQ6018_APSS_MEM_ACC_TCSR_COUNT] = { -+ {TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0, NULL, 0x10}, -+ {TCSR_CUSTOM_VDDAPC0_ACC_1, NULL, 0x1}, -+}; -+ -+/* -+ * IPQ9574 (Few parameters are changed, remaining are same as IPQ6018) -+ */ -+#define IPQ9574_APSS_FUSE_STEP_VOLT 10000 -+ -+static struct cpr3_fuse_param -+ipq9574_apss_ro_sel_param[IPQ9574_APSS_FUSE_CORNERS][2] = { -+ {{107, 4, 7}, {} }, -+ {{107, 0, 3}, {} }, -+ {{106, 4, 7}, {} }, -+ {{106, 0, 3}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq9574_apss_init_voltage_param[IPQ9574_APSS_FUSE_CORNERS][2] = { -+ {{104, 24, 29}, {} }, -+ {{104, 18, 23}, {} }, -+ {{104, 12, 17}, {} }, -+ {{104, 6, 11}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq9574_apss_target_quot_param[IPQ9574_APSS_FUSE_CORNERS][2] = { -+ {{106, 32, 43}, {} }, -+ {{106, 20, 31}, {} }, -+ {{106, 8, 19}, {} }, -+ {{106, 44, 55}, {} }, -+}; -+ -+static struct cpr3_fuse_param -+ipq9574_apss_quot_offset_param[IPQ9574_APSS_FUSE_CORNERS][2] = { -+ {{} }, -+ {{105, 48, 55}, {} }, -+ {{105, 40, 47}, {} }, -+ {{105, 32, 39}, {} }, -+}; -+ -+static struct cpr3_fuse_param ipq9574_cpr_fusing_rev_param[] = { -+ {107, 8, 10}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq9574_apss_speed_bin_param[] = { -+ {0, 40, 42}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq9574_cpr_boost_fuse_cfg_param[] = { -+ {0, 43, 45}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq9574_apss_boost_fuse_volt_param[] = { -+ {104, 0, 5}, -+ {}, -+}; -+ -+static struct cpr3_fuse_param ipq9574_misc_fuse_volt_adj_param[] = { -+ {0, 54, 54}, -+ {}, -+}; -+ -+static struct cpr3_fuse_parameters ipq9574_fuse_params = { -+ .apss_ro_sel_param = ipq9574_apss_ro_sel_param, -+ .apss_init_voltage_param = ipq9574_apss_init_voltage_param, -+ .apss_target_quot_param = ipq9574_apss_target_quot_param, -+ .apss_quot_offset_param = ipq9574_apss_quot_offset_param, -+ .cpr_fusing_rev_param = ipq9574_cpr_fusing_rev_param, -+ .apss_speed_bin_param = ipq9574_apss_speed_bin_param, -+ .cpr_boost_fuse_cfg_param = ipq9574_cpr_boost_fuse_cfg_param, -+ .apss_boost_fuse_volt_param = ipq9574_apss_boost_fuse_volt_param, -+ .misc_fuse_volt_adj_param = ipq9574_misc_fuse_volt_adj_param -+}; -+ -+/* -+ * Open loop voltage fuse reference voltages in microvolts for IPQ9574 -+ */ -+static int ipq9574_apss_fuse_ref_volt -+ [IPQ9574_APSS_FUSE_CORNERS] = { -+ 725000, -+ 862500, -+ 987500, -+ 1062500, -+}; -+ -+/** -+ * cpr4_ipq807x_apss_read_fuse_data() - load APSS specific fuse parameter values -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * This function allocates a cpr4_ipq807x_apss_fuses struct, fills it with -+ * values read out of hardware fuses, and finally copies common fuse values -+ * into the CPR3 regulator struct. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_ipq807x_apss_read_fuse_data(struct cpr3_regulator *vreg) -+{ -+ void __iomem *base = vreg->thread->ctrl->fuse_base; -+ struct cpr4_ipq807x_apss_fuses *fuse; -+ int i, rc; -+ -+ fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); -+ if (!fuse) -+ return -ENOMEM; -+ -+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->apss_speed_bin_param, -+ &fuse->speed_bin); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc); -+ return rc; -+ } -+ cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin); -+ -+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_fusing_rev_param, -+ &fuse->cpr_fusing_rev); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", -+ rc); -+ return rc; -+ } -+ cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); -+ -+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->misc_fuse_volt_adj_param, -+ &fuse->misc); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read misc voltage adjustment fuse, rc=%d\n", -+ rc); -+ return rc; -+ } -+ cpr3_info(vreg, "CPR misc fuse value = %llu\n", fuse->misc); -+ if (fuse->misc >= IPQ807x_MISC_FUSE_VAL_COUNT) { -+ cpr3_err(vreg, "CPR misc fuse value = %llu, should be < %lu\n", -+ fuse->misc, IPQ807x_MISC_FUSE_VAL_COUNT); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < g_valid_fuse_count; i++) { -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_init_voltage_param[i], -+ &fuse->init_voltage[i]); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", -+ i, rc); -+ return rc; -+ } -+ -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_target_quot_param[i], -+ &fuse->target_quot[i]); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read fuse-corner %d target quotient fuse, rc=%d\n", -+ i, rc); -+ return rc; -+ } -+ -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_ro_sel_param[i], -+ &fuse->ro_sel[i]); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read fuse-corner %d RO select fuse, rc=%d\n", -+ i, rc); -+ return rc; -+ } -+ -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_quot_offset_param[i], -+ &fuse->quot_offset[i]); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read fuse-corner %d quotient offset fuse, rc=%d\n", -+ i, rc); -+ return rc; -+ } -+ } -+ -+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_boost_fuse_cfg_param, -+ &fuse->boost_cfg); -+ if (rc) { -+ cpr3_err(vreg, "Unable to read CPR boost config fuse, rc=%d\n", -+ rc); -+ return rc; -+ } -+ cpr3_info(vreg, "Voltage boost fuse config = %llu boost = %s\n", -+ fuse->boost_cfg, boost_fuse[fuse->boost_cfg] -+ ? "enable" : "disable"); -+ -+ rc = cpr3_read_fuse_param(base, -+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_boost_fuse_volt_param, -+ &fuse->boost_voltage); -+ if (rc) { -+ cpr3_err(vreg, "failed to read boost fuse voltage, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ vreg->fuse_combo = fuse->cpr_fusing_rev + 8 * fuse->speed_bin; -+ if (vreg->fuse_combo >= CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT) { -+ cpr3_err(vreg, "invalid CPR fuse combo = %d found\n", -+ vreg->fuse_combo); -+ return -EINVAL; -+ } -+ -+ vreg->speed_bin_fuse = fuse->speed_bin; -+ vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; -+ vreg->fuse_corner_count = g_valid_fuse_count; -+ vreg->platform_fuses = fuse; -+ -+ return 0; -+} -+ -+/** -+ * cpr4_apss_parse_corner_data() - parse APSS corner data from device tree -+ * properties of the CPR3 regulator's device node -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_parse_corner_data(struct cpr3_regulator *vreg) -+{ -+ struct device_node *node = vreg->of_node; -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ u32 *temp = NULL; -+ int i, rc; -+ -+ rc = cpr3_parse_common_corner_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, "error reading corner data, rc=%d\n", rc); -+ return rc; -+ } -+ -+ /* If fuse has incorrect RO Select values and dtsi has "qcom,cpr-ro-sel" -+ * entry with RO select values other than zero, then dtsi values will -+ * be used. -+ */ -+ if (of_find_property(node, "qcom,cpr-ro-sel", NULL)) { -+ temp = kcalloc(vreg->fuse_corner_count, sizeof(*temp), -+ GFP_KERNEL); -+ if (!temp) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_array_property(vreg, "qcom,cpr-ro-sel", -+ vreg->fuse_corner_count, temp); -+ if (rc) -+ goto done; -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ if (temp[i] != 0) -+ fuse->ro_sel[i] = temp[i]; -+ } -+ } -+done: -+ kfree(temp); -+ return rc; -+} -+ -+/** -+ * cpr4_apss_parse_misc_fuse_voltage_adjustments() - fill an array from a -+ * portion of the voltage adjustments specified based on -+ * miscellaneous fuse bits. -+ * @vreg: Pointer to the CPR3 regulator -+ * @volt_adjust: Voltage adjustment output data array which must be -+ * of size vreg->corner_count -+ * -+ * cpr3_parse_common_corner_data() must be called for vreg before this function -+ * is called so that speed bin size elements are initialized. -+ * -+ * Two formats are supported for the device tree property: -+ * 1. Length == tuple_list_size * vreg->corner_count -+ * (reading begins at index 0) -+ * 2. Length == tuple_list_size * vreg->speed_bin_corner_sum -+ * (reading begins at index tuple_list_size * vreg->speed_bin_offset) -+ * -+ * Here, tuple_list_size is the number of possible values for misc fuse. -+ * All other property lengths are treated as errors. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_parse_misc_fuse_voltage_adjustments( -+ struct cpr3_regulator *vreg, u32 *volt_adjust) -+{ -+ struct device_node *node = vreg->of_node; -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ int tuple_list_size = IPQ807x_MISC_FUSE_VAL_COUNT; -+ int i, offset, rc, len = 0; -+ const char *prop_name = "qcom,cpr-misc-fuse-voltage-adjustment"; -+ -+ if (!of_find_property(node, prop_name, &len)) { -+ cpr3_err(vreg, "property %s is missing\n", prop_name); -+ return -EINVAL; -+ } -+ -+ if (len == tuple_list_size * vreg->corner_count * sizeof(u32)) { -+ offset = 0; -+ } else if (vreg->speed_bin_corner_sum > 0 && -+ len == tuple_list_size * vreg->speed_bin_corner_sum -+ * sizeof(u32)) { -+ offset = tuple_list_size * vreg->speed_bin_offset -+ + fuse->misc * vreg->corner_count; -+ } else { -+ if (vreg->speed_bin_corner_sum > 0) -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n", -+ prop_name, len, -+ tuple_list_size * vreg->corner_count -+ * sizeof(u32), -+ tuple_list_size * vreg->speed_bin_corner_sum -+ * sizeof(u32)); -+ else -+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu\n", -+ prop_name, len, -+ tuple_list_size * vreg->corner_count -+ * sizeof(u32)); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ rc = of_property_read_u32_index(node, prop_name, offset + i, -+ &volt_adjust[i]); -+ if (rc) { -+ cpr3_err(vreg, "error reading property %s, rc=%d\n", -+ prop_name, rc); -+ return rc; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr4_ipq807x_apss_calculate_open_loop_voltages() - calculate the open-loop -+ * voltage for each corner of a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * If open-loop voltage interpolation is allowed in device tree, then -+ * this function calculates the open-loop voltage for a given corner using -+ * linear interpolation. This interpolation is performed using the processor -+ * frequencies of the lower and higher Fmax corners along with their fused -+ * open-loop voltages. -+ * -+ * If open-loop voltage interpolation is not allowed, then this function uses -+ * the Fmax fused open-loop voltage for all of the corners associated with a -+ * given fuse corner. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_ipq807x_apss_calculate_open_loop_voltages( -+ struct cpr3_regulator *vreg) -+{ -+ struct device_node *node = vreg->of_node; -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ int i, j, rc = 0; -+ bool allow_interpolation; -+ u64 freq_low, volt_low, freq_high, volt_high; -+ int *fuse_volt, *misc_adj_volt; -+ int *fmax_corner; -+ -+ fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt), -+ GFP_KERNEL); -+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), -+ GFP_KERNEL); -+ if (!fuse_volt || !fmax_corner) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->fuse_corner_count; i++) { -+ if (ctrl->cpr_global_setting == CPR_DISABLED) -+ fuse_volt[i] = vreg->cpr4_regulator_data->fuse_ref_volt[i]; -+ else -+ fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( -+ vreg->cpr4_regulator_data->fuse_ref_volt[i], -+ vreg->cpr4_regulator_data->fuse_step_volt, -+ fuse->init_voltage[i], -+ IPQ807x_APSS_VOLTAGE_FUSE_SIZE); -+ -+ /* Log fused open-loop voltage values for debugging purposes. */ -+ cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", -+ cpr4_ipq807x_apss_fuse_corner_name[i], -+ fuse_volt[i]); -+ } -+ -+ rc = cpr3_determine_part_type(vreg, -+ fuse_volt[vreg->fuse_corner_count - 1]); -+ if (rc) { -+ cpr3_err(vreg, "fused part type detection failed failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt); -+ if (rc) { -+ cpr3_err(vreg, "fused open-loop voltage adjustment failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ allow_interpolation = of_property_read_bool(node, -+ "qcom,allow-voltage-interpolation"); -+ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ if (fuse_volt[i] < fuse_volt[i - 1]) { -+ cpr3_info(vreg, "fuse corner %d voltage=%d uV < fuse corner %d voltage=%d uV; overriding: fuse corner %d voltage=%d\n", -+ i, fuse_volt[i], i - 1, fuse_volt[i - 1], -+ i, fuse_volt[i - 1]); -+ fuse_volt[i] = fuse_volt[i - 1]; -+ } -+ } -+ -+ if (!allow_interpolation) { -+ /* Use fused open-loop voltage for lower frequencies. */ -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].open_loop_volt -+ = fuse_volt[vreg->corner[i].cpr_fuse_corner]; -+ goto done; -+ } -+ -+ /* Determine highest corner mapped to each fuse corner */ -+ j = vreg->fuse_corner_count - 1; -+ for (i = vreg->corner_count - 1; i >= 0; i--) { -+ if (vreg->corner[i].cpr_fuse_corner == j) { -+ fmax_corner[j] = i; -+ j--; -+ } -+ } -+ if (j >= 0) { -+ cpr3_err(vreg, "invalid fuse corner mapping\n"); -+ rc = -EINVAL; -+ goto done; -+ } -+ -+ /* -+ * Interpolation is not possible for corners mapped to the lowest fuse -+ * corner so use the fuse corner value directly. -+ */ -+ for (i = 0; i <= fmax_corner[0]; i++) -+ vreg->corner[i].open_loop_volt = fuse_volt[0]; -+ -+ /* Interpolate voltages for the higher fuse corners. */ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; -+ volt_low = fuse_volt[i - 1]; -+ freq_high = vreg->corner[fmax_corner[i]].proc_freq; -+ volt_high = fuse_volt[i]; -+ -+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) -+ vreg->corner[j].open_loop_volt = cpr3_interpolate( -+ freq_low, volt_low, freq_high, volt_high, -+ vreg->corner[j].proc_freq); -+ } -+ -+done: -+ if (rc == 0) { -+ cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n"); -+ for (i = 0; i < vreg->corner_count; i++) -+ cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i, -+ vreg->corner[i].open_loop_volt); -+ -+ rc = cpr3_adjust_open_loop_voltages(vreg); -+ if (rc) -+ cpr3_err(vreg, "open-loop voltage adjustment failed, rc=%d\n", -+ rc); -+ -+ if (of_find_property(node, -+ "qcom,cpr-misc-fuse-voltage-adjustment", -+ NULL)) { -+ misc_adj_volt = kcalloc(vreg->corner_count, -+ sizeof(*misc_adj_volt), GFP_KERNEL); -+ if (!misc_adj_volt) { -+ rc = -ENOMEM; -+ goto _exit; -+ } -+ -+ rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg, -+ misc_adj_volt); -+ if (rc) { -+ cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n", -+ rc); -+ kfree(misc_adj_volt); -+ goto _exit; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ vreg->corner[i].open_loop_volt -+ += misc_adj_volt[i]; -+ kfree(misc_adj_volt); -+ } -+ } -+ -+_exit: -+ kfree(fuse_volt); -+ kfree(fmax_corner); -+ return rc; -+} -+ -+/** -+ * cpr4_ipq807x_apss_set_no_interpolation_quotients() - use the fused target -+ * quotient values for lower frequencies. -+ * @vreg: Pointer to the CPR3 regulator -+ * @volt_adjust: Pointer to array of per-corner closed-loop adjustment -+ * voltages -+ * @volt_adjust_fuse: Pointer to array of per-fuse-corner closed-loop -+ * adjustment voltages -+ * @ro_scale: Pointer to array of per-fuse-corner RO scaling factor -+ * values with units of QUOT/V -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_ipq807x_apss_set_no_interpolation_quotients( -+ struct cpr3_regulator *vreg, int *volt_adjust, -+ int *volt_adjust_fuse, int *ro_scale) -+{ -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ u32 quot, ro; -+ int quot_adjust; -+ int i, fuse_corner; -+ -+ for (i = 0; i < vreg->corner_count; i++) { -+ fuse_corner = vreg->corner[i].cpr_fuse_corner; -+ quot = fuse->target_quot[fuse_corner]; -+ quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner], -+ volt_adjust_fuse[fuse_corner] + -+ volt_adjust[i]); -+ ro = fuse->ro_sel[fuse_corner]; -+ vreg->corner[i].target_quot[ro] = quot + quot_adjust; -+ cpr3_debug(vreg, "corner=%d RO=%u target quot=%u\n", -+ i, ro, quot); -+ -+ if (quot_adjust) -+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %u --> %u (%d uV)\n", -+ i, ro, quot, vreg->corner[i].target_quot[ro], -+ volt_adjust_fuse[fuse_corner] + -+ volt_adjust[i]); -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr4_ipq807x_apss_calculate_target_quotients() - calculate the CPR target -+ * quotient for each corner of a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * If target quotient interpolation is allowed in device tree, then this -+ * function calculates the target quotient for a given corner using linear -+ * interpolation. This interpolation is performed using the processor -+ * frequencies of the lower and higher Fmax corners along with the fused -+ * target quotient and quotient offset of the higher Fmax corner. -+ * -+ * If target quotient interpolation is not allowed, then this function uses -+ * the Fmax fused target quotient for all of the corners associated with a -+ * given fuse corner. -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_ipq807x_apss_calculate_target_quotients( -+ struct cpr3_regulator *vreg) -+{ -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ int rc; -+ bool allow_interpolation; -+ u64 freq_low, freq_high, prev_quot; -+ u64 *quot_low; -+ u64 *quot_high; -+ u32 quot, ro; -+ int i, j, fuse_corner, quot_adjust; -+ int *fmax_corner; -+ int *volt_adjust, *volt_adjust_fuse, *ro_scale; -+ int *voltage_adj_misc; -+ -+ /* Log fused quotient values for debugging purposes. */ -+ for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS; -+ i < vreg->fuse_corner_count; i++) -+ cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu, quot_offset[%2llu]=%4llu\n", -+ cpr4_ipq807x_apss_fuse_corner_name[i], -+ fuse->ro_sel[i], fuse->target_quot[i], -+ fuse->ro_sel[i], fuse->quot_offset[i] * -+ IPQ807x_APSS_QUOT_OFFSET_SCALE); -+ -+ allow_interpolation = of_property_read_bool(vreg->of_node, -+ "qcom,allow-quotient-interpolation"); -+ -+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust), -+ GFP_KERNEL); -+ volt_adjust_fuse = kcalloc(vreg->fuse_corner_count, -+ sizeof(*volt_adjust_fuse), GFP_KERNEL); -+ ro_scale = kcalloc(vreg->fuse_corner_count, sizeof(*ro_scale), -+ GFP_KERNEL); -+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner), -+ GFP_KERNEL); -+ quot_low = kcalloc(vreg->fuse_corner_count, sizeof(*quot_low), -+ GFP_KERNEL); -+ quot_high = kcalloc(vreg->fuse_corner_count, sizeof(*quot_high), -+ GFP_KERNEL); -+ if (!volt_adjust || !volt_adjust_fuse || !ro_scale || -+ !fmax_corner || !quot_low || !quot_high) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ rc = cpr3_parse_closed_loop_voltage_adjustments(vreg, &fuse->ro_sel[0], -+ volt_adjust, volt_adjust_fuse, ro_scale); -+ if (rc) { -+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n", -+ rc); -+ goto done; -+ } -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,cpr-misc-fuse-voltage-adjustment", NULL)) { -+ voltage_adj_misc = kcalloc(vreg->corner_count, -+ sizeof(*voltage_adj_misc), GFP_KERNEL); -+ if (!voltage_adj_misc) { -+ rc = -ENOMEM; -+ goto done; -+ } -+ -+ rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg, -+ voltage_adj_misc); -+ if (rc) { -+ cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n", -+ rc); -+ kfree(voltage_adj_misc); -+ goto done; -+ } -+ -+ for (i = 0; i < vreg->corner_count; i++) -+ volt_adjust[i] += voltage_adj_misc[i]; -+ -+ kfree(voltage_adj_misc); -+ } -+ -+ if (!allow_interpolation) { -+ /* Use fused target quotients for lower frequencies. */ -+ return cpr4_ipq807x_apss_set_no_interpolation_quotients( -+ vreg, volt_adjust, volt_adjust_fuse, ro_scale); -+ } -+ -+ /* Determine highest corner mapped to each fuse corner */ -+ j = vreg->fuse_corner_count - 1; -+ for (i = vreg->corner_count - 1; i >= 0; i--) { -+ if (vreg->corner[i].cpr_fuse_corner == j) { -+ fmax_corner[j] = i; -+ j--; -+ } -+ } -+ if (j >= 0) { -+ cpr3_err(vreg, "invalid fuse corner mapping\n"); -+ rc = -EINVAL; -+ goto done; -+ } -+ -+ /* -+ * Interpolation is not possible for corners mapped to the lowest fuse -+ * corner so use the fuse corner value directly. -+ */ -+ i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS; -+ quot_adjust = cpr3_quot_adjustment(ro_scale[i], volt_adjust_fuse[i]); -+ quot = fuse->target_quot[i] + quot_adjust; -+ quot_high[i] = quot_low[i] = quot; -+ ro = fuse->ro_sel[i]; -+ if (quot_adjust) -+ cpr3_debug(vreg, "adjusted fuse corner %d RO%u target quot: %llu --> %u (%d uV)\n", -+ i, ro, fuse->target_quot[i], quot, volt_adjust_fuse[i]); -+ -+ for (i = 0; i <= fmax_corner[CPR4_IPQ807x_APSS_FUSE_CORNER_SVS]; -+ i++) -+ vreg->corner[i].target_quot[ro] = quot; -+ -+ for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_NOM; -+ i < vreg->fuse_corner_count; i++) { -+ quot_high[i] = fuse->target_quot[i]; -+ if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) -+ quot_low[i] = quot_high[i - 1]; -+ else -+ quot_low[i] = quot_high[i] -+ - fuse->quot_offset[i] -+ * IPQ807x_APSS_QUOT_OFFSET_SCALE; -+ if (quot_high[i] < quot_low[i]) { -+ cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu; overriding: quot_high[%d]=%llu\n", -+ i, quot_high[i], i, quot_low[i], -+ i, quot_low[i]); -+ quot_high[i] = quot_low[i]; -+ } -+ } -+ -+ /* Perform per-fuse-corner target quotient adjustment */ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ quot_adjust = cpr3_quot_adjustment(ro_scale[i], -+ volt_adjust_fuse[i]); -+ if (quot_adjust) { -+ prev_quot = quot_high[i]; -+ quot_high[i] += quot_adjust; -+ cpr3_debug(vreg, "adjusted fuse corner %d RO%llu target quot: %llu --> %llu (%d uV)\n", -+ i, fuse->ro_sel[i], prev_quot, quot_high[i], -+ volt_adjust_fuse[i]); -+ } -+ -+ if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) -+ quot_low[i] = quot_high[i - 1]; -+ else -+ quot_low[i] += cpr3_quot_adjustment(ro_scale[i], -+ volt_adjust_fuse[i - 1]); -+ -+ if (quot_high[i] < quot_low[i]) { -+ cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu after adjustment; overriding: quot_high[%d]=%llu\n", -+ i, quot_high[i], i, quot_low[i], -+ i, quot_low[i]); -+ quot_high[i] = quot_low[i]; -+ } -+ } -+ -+ /* Interpolate voltages for the higher fuse corners. */ -+ for (i = 1; i < vreg->fuse_corner_count; i++) { -+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq; -+ freq_high = vreg->corner[fmax_corner[i]].proc_freq; -+ -+ ro = fuse->ro_sel[i]; -+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++) -+ vreg->corner[j].target_quot[ro] = cpr3_interpolate( -+ freq_low, quot_low[i], freq_high, quot_high[i], -+ vreg->corner[j].proc_freq); -+ } -+ -+ /* Perform per-corner target quotient adjustment */ -+ for (i = 0; i < vreg->corner_count; i++) { -+ fuse_corner = vreg->corner[i].cpr_fuse_corner; -+ ro = fuse->ro_sel[fuse_corner]; -+ quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner], -+ volt_adjust[i]); -+ if (quot_adjust) { -+ prev_quot = vreg->corner[i].target_quot[ro]; -+ vreg->corner[i].target_quot[ro] += quot_adjust; -+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %llu --> %u (%d uV)\n", -+ i, ro, prev_quot, -+ vreg->corner[i].target_quot[ro], -+ volt_adjust[i]); -+ } -+ } -+ -+ /* Ensure that target quotients increase monotonically */ -+ for (i = 1; i < vreg->corner_count; i++) { -+ ro = fuse->ro_sel[vreg->corner[i].cpr_fuse_corner]; -+ if (fuse->ro_sel[vreg->corner[i - 1].cpr_fuse_corner] == ro -+ && vreg->corner[i].target_quot[ro] -+ < vreg->corner[i - 1].target_quot[ro]) { -+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot=%u < adjusted corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n", -+ i, ro, vreg->corner[i].target_quot[ro], -+ i - 1, ro, vreg->corner[i - 1].target_quot[ro], -+ i, ro, vreg->corner[i - 1].target_quot[ro]); -+ vreg->corner[i].target_quot[ro] -+ = vreg->corner[i - 1].target_quot[ro]; -+ } -+ } -+ -+done: -+ kfree(volt_adjust); -+ kfree(volt_adjust_fuse); -+ kfree(ro_scale); -+ kfree(fmax_corner); -+ kfree(quot_low); -+ kfree(quot_high); -+ return rc; -+} -+ -+/** -+ * cpr4_apss_print_settings() - print out APSS CPR configuration settings into -+ * the kernel log for debugging purposes -+ * @vreg: Pointer to the CPR3 regulator -+ */ -+static void cpr4_apss_print_settings(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_corner *corner; -+ int i; -+ -+ cpr3_debug(vreg, "Corner: Frequency (Hz), Fuse Corner, Floor (uV), Open-Loop (uV), Ceiling (uV)\n"); -+ for (i = 0; i < vreg->corner_count; i++) { -+ corner = &vreg->corner[i]; -+ cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n", -+ i, corner->proc_freq, corner->cpr_fuse_corner, -+ corner->floor_volt, corner->open_loop_volt, -+ corner->ceiling_volt); -+ } -+ -+ if (vreg->thread->ctrl->apm) -+ cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n", -+ vreg->thread->ctrl->apm_threshold_volt, -+ vreg->thread->ctrl->apm_adj_volt); -+} -+ -+/** -+ * cpr4_apss_init_thread() - perform steps necessary to initialize the -+ * configuration data for a CPR3 thread -+ * @thread: Pointer to the CPR3 thread -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_init_thread(struct cpr3_thread *thread) -+{ -+ int rc; -+ -+ rc = cpr3_parse_common_thread_data(thread); -+ if (rc) { -+ cpr3_err(thread->ctrl, "thread %u unable to read CPR thread data from device tree, rc=%d\n", -+ thread->thread_id, rc); -+ return rc; -+ } -+ -+ return 0; -+} -+ -+/** -+ * cpr4_apss_parse_temp_adj_properties() - parse temperature based -+ * adjustment properties from device tree. -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_parse_temp_adj_properties(struct cpr3_controller *ctrl) -+{ -+ struct device_node *of_node = ctrl->dev->of_node; -+ int rc, i, len, temp_point_count; -+ -+ if (!of_find_property(of_node, "qcom,cpr-temp-point-map", &len)) { -+ /* -+ * Temperature based adjustments are not defined. Single -+ * temperature band is still valid for per-online-core -+ * adjustments. -+ */ -+ ctrl->temp_band_count = 1; -+ return 0; -+ } -+ -+ temp_point_count = len / sizeof(u32); -+ if (temp_point_count <= 0 || -+ temp_point_count > IPQ807x_APSS_MAX_TEMP_POINTS) { -+ cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n", -+ temp_point_count, IPQ807x_APSS_MAX_TEMP_POINTS); -+ return -EINVAL; -+ } -+ -+ ctrl->temp_points = devm_kcalloc(ctrl->dev, temp_point_count, -+ sizeof(*ctrl->temp_points), GFP_KERNEL); -+ if (!ctrl->temp_points) -+ return -ENOMEM; -+ -+ rc = of_property_read_u32_array(of_node, "qcom,cpr-temp-point-map", -+ ctrl->temp_points, temp_point_count); -+ if (rc) { -+ cpr3_err(ctrl, "error reading property qcom,cpr-temp-point-map, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ for (i = 0; i < temp_point_count; i++) -+ cpr3_debug(ctrl, "Temperature Point %d=%d\n", i, -+ ctrl->temp_points[i]); -+ -+ /* -+ * If t1, t2, and t3 are the temperature points, then the temperature -+ * bands are: (-inf, t1], (t1, t2], (t2, t3], and (t3, inf). -+ */ -+ ctrl->temp_band_count = temp_point_count + 1; -+ cpr3_debug(ctrl, "Number of temp bands =%d\n", ctrl->temp_band_count); -+ -+ rc = of_property_read_u32(of_node, "qcom,cpr-initial-temp-band", -+ &ctrl->initial_temp_band); -+ if (rc) { -+ cpr3_err(ctrl, "error reading qcom,cpr-initial-temp-band, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (ctrl->initial_temp_band >= ctrl->temp_band_count) { -+ cpr3_err(ctrl, "Initial temperature band value %d should be in range [0 - %d]\n", -+ ctrl->initial_temp_band, ctrl->temp_band_count - 1); -+ return -EINVAL; -+ } -+ -+ ctrl->temp_sensor_id_start = IPQ807x_APSS_TEMP_SENSOR_ID_START; -+ ctrl->temp_sensor_id_end = IPQ807x_APSS_TEMP_SENSOR_ID_END; -+ ctrl->allow_temp_adj = true; -+ return rc; -+} -+ -+/** -+ * cpr4_apss_parse_boost_properties() - parse configuration data for boost -+ * voltage adjustment for CPR3 regulator from device tree. -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_parse_boost_properties(struct cpr3_regulator *vreg) -+{ -+ struct cpr3_controller *ctrl = vreg->thread->ctrl; -+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses; -+ struct cpr3_corner *corner; -+ int i, boost_voltage, final_boost_volt, rc = 0; -+ int *boost_table = NULL, *boost_temp_adj = NULL; -+ int boost_voltage_adjust = 0, boost_num_cores = 0; -+ u32 boost_allowed = 0; -+ -+ if (!boost_fuse[fuse->boost_cfg]) -+ /* Voltage boost is disabled in fuse */ -+ return 0; -+ -+ if (of_find_property(vreg->of_node, "qcom,allow-boost", NULL)) { -+ rc = cpr3_parse_array_property(vreg, "qcom,allow-boost", 1, -+ &boost_allowed); -+ if (rc) -+ return rc; -+ } -+ -+ if (!boost_allowed) { -+ /* Voltage boost is not enabled for this regulator */ -+ return 0; -+ } -+ -+ boost_voltage = cpr3_convert_open_loop_voltage_fuse( -+ vreg->cpr4_regulator_data->boost_fuse_ref_volt, -+ vreg->cpr4_regulator_data->fuse_step_volt, -+ fuse->boost_voltage, -+ IPQ807x_APSS_VOLTAGE_FUSE_SIZE); -+ -+ /* Log boost voltage value for debugging purposes. */ -+ cpr3_info(vreg, "Boost open-loop=%7d uV\n", boost_voltage); -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,cpr-boost-voltage-fuse-adjustment", NULL)) { -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,cpr-boost-voltage-fuse-adjustment", -+ 1, &boost_voltage_adjust); -+ if (rc) { -+ cpr3_err(vreg, "qcom,cpr-boost-voltage-fuse-adjustment reading failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ boost_voltage += boost_voltage_adjust; -+ /* Log boost voltage value for debugging purposes. */ -+ cpr3_info(vreg, "Adjusted boost open-loop=%7d uV\n", -+ boost_voltage); -+ } -+ -+ /* Limit boost voltage value between ceiling and floor voltage limits */ -+ boost_voltage = min(boost_voltage, vreg->cpr4_regulator_data->boost_ceiling_volt); -+ boost_voltage = max(boost_voltage, vreg->cpr4_regulator_data->boost_floor_volt); -+ -+ /* -+ * The boost feature can only be used for the highest voltage corner. -+ * Also, keep core-count adjustments disabled when the boost feature -+ * is enabled. -+ */ -+ corner = &vreg->corner[vreg->corner_count - 1]; -+ if (!corner->sdelta) { -+ /* -+ * If core-count/temp adjustments are not defined, the cpr4 -+ * sdelta for this corner will not be allocated. Allocate it -+ * here for boost configuration. -+ */ -+ corner->sdelta = devm_kzalloc(ctrl->dev, -+ sizeof(*corner->sdelta), GFP_KERNEL); -+ if (!corner->sdelta) -+ return -ENOMEM; -+ } -+ corner->sdelta->temp_band_count = ctrl->temp_band_count; -+ -+ rc = of_property_read_u32(vreg->of_node, "qcom,cpr-num-boost-cores", -+ &boost_num_cores); -+ if (rc) { -+ cpr3_err(vreg, "qcom,cpr-num-boost-cores reading failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (boost_num_cores <= 0 || -+ boost_num_cores > IPQ807x_APSS_CPR_SDELTA_CORE_COUNT) { -+ cpr3_err(vreg, "Invalid boost number of cores = %d\n", -+ boost_num_cores); -+ return -EINVAL; -+ } -+ corner->sdelta->boost_num_cores = boost_num_cores; -+ -+ boost_table = devm_kcalloc(ctrl->dev, corner->sdelta->temp_band_count, -+ sizeof(*boost_table), GFP_KERNEL); -+ if (!boost_table) -+ return -ENOMEM; -+ -+ if (of_find_property(vreg->of_node, -+ "qcom,cpr-boost-temp-adjustment", NULL)) { -+ boost_temp_adj = kcalloc(corner->sdelta->temp_band_count, -+ sizeof(*boost_temp_adj), GFP_KERNEL); -+ if (!boost_temp_adj) -+ return -ENOMEM; -+ -+ rc = cpr3_parse_array_property(vreg, -+ "qcom,cpr-boost-temp-adjustment", -+ corner->sdelta->temp_band_count, -+ boost_temp_adj); -+ if (rc) { -+ cpr3_err(vreg, "qcom,cpr-boost-temp-adjustment reading failed, rc=%d\n", -+ rc); -+ goto done; -+ } -+ } -+ -+ for (i = 0; i < corner->sdelta->temp_band_count; i++) { -+ /* Apply static adjustments to boost voltage */ -+ final_boost_volt = boost_voltage + (boost_temp_adj == NULL -+ ? 0 : boost_temp_adj[i]); -+ /* -+ * Limit final adjusted boost voltage value between ceiling -+ * and floor voltage limits -+ */ -+ final_boost_volt = min(final_boost_volt, -+ vreg->cpr4_regulator_data->boost_ceiling_volt); -+ final_boost_volt = max(final_boost_volt, -+ vreg->cpr4_regulator_data->boost_floor_volt); -+ -+ boost_table[i] = (corner->open_loop_volt - final_boost_volt) -+ / ctrl->step_volt; -+ cpr3_debug(vreg, "Adjusted boost voltage margin for temp band %d = %d steps\n", -+ i, boost_table[i]); -+ } -+ -+ corner->ceiling_volt = vreg->cpr4_regulator_data->boost_ceiling_volt; -+ corner->sdelta->boost_table = boost_table; -+ corner->sdelta->allow_boost = true; -+ corner->sdelta->allow_core_count_adj = false; -+ vreg->allow_boost = true; -+ ctrl->allow_boost = true; -+done: -+ kfree(boost_temp_adj); -+ return rc; -+} -+ -+/** -+ * cpr4_apss_init_regulator() - perform all steps necessary to initialize the -+ * configuration data for a CPR3 regulator -+ * @vreg: Pointer to the CPR3 regulator -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_init_regulator(struct cpr3_regulator *vreg) -+{ -+ struct cpr4_ipq807x_apss_fuses *fuse; -+ int rc; -+ -+ rc = cpr4_ipq807x_apss_read_fuse_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); -+ return rc; -+ } -+ -+ fuse = vreg->platform_fuses; -+ -+ rc = cpr4_apss_parse_corner_data(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to read CPR corner data from device tree, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr3_mem_acc_init(vreg); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(vreg, "unable to initialize mem-acc regulator settings, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr4_ipq807x_apss_calculate_open_loop_voltages(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr3_limit_open_loop_voltages(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ cpr3_open_loop_voltage_as_ceiling(vreg); -+ -+ rc = cpr3_limit_floor_voltages(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc); -+ return rc; -+ } -+ -+ rc = cpr4_ipq807x_apss_calculate_target_quotients(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to calculate target quotients, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr4_parse_core_count_temp_voltage_adj(vreg, false); -+ if (rc) { -+ cpr3_err(vreg, "unable to parse temperature and core count voltage adjustments, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (vreg->allow_core_count_adj && (vreg->max_core_count <= 0 -+ || vreg->max_core_count > -+ IPQ807x_APSS_CPR_SDELTA_CORE_COUNT)) { -+ cpr3_err(vreg, "qcom,max-core-count has invalid value = %d\n", -+ vreg->max_core_count); -+ return -EINVAL; -+ } -+ -+ rc = cpr4_apss_parse_boost_properties(vreg); -+ if (rc) { -+ cpr3_err(vreg, "unable to parse boost adjustments, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ cpr4_apss_print_settings(vreg); -+ -+ return rc; -+} -+ -+/** -+ * cpr4_apss_init_controller() - perform APSS CPR4 controller specific -+ * initializations -+ * @ctrl: Pointer to the CPR3 controller -+ * -+ * Return: 0 on success, errno on failure -+ */ -+static int cpr4_apss_init_controller(struct cpr3_controller *ctrl) -+{ -+ int rc; -+ -+ rc = cpr3_parse_common_ctrl_data(ctrl); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = of_property_read_u32(ctrl->dev->of_node, -+ "qcom,cpr-down-error-step-limit", -+ &ctrl->down_error_step_limit); -+ if (rc) { -+ cpr3_err(ctrl, "error reading qcom,cpr-down-error-step-limit, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = of_property_read_u32(ctrl->dev->of_node, -+ "qcom,cpr-up-error-step-limit", -+ &ctrl->up_error_step_limit); -+ if (rc) { -+ cpr3_err(ctrl, "error reading qcom,cpr-up-error-step-limit, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ /* -+ * Use fixed step quotient if specified otherwise use dynamic -+ * calculated per RO step quotient -+ */ -+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-step-quot-fixed", -+ &ctrl->step_quot_fixed); -+ ctrl->use_dynamic_step_quot = ctrl->step_quot_fixed ? false : true; -+ -+ ctrl->saw_use_unit_mV = of_property_read_bool(ctrl->dev->of_node, -+ "qcom,cpr-saw-use-unit-mV"); -+ -+ of_property_read_u32(ctrl->dev->of_node, -+ "qcom,cpr-voltage-settling-time", -+ &ctrl->voltage_settling_time); -+ -+ if (of_find_property(ctrl->dev->of_node, "vdd-limit-supply", NULL)) { -+ ctrl->vdd_limit_regulator = -+ devm_regulator_get(ctrl->dev, "vdd-limit"); -+ if (IS_ERR(ctrl->vdd_limit_regulator)) { -+ rc = PTR_ERR(ctrl->vdd_limit_regulator); -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to request vdd-limit regulator, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ rc = cpr3_apm_init(ctrl); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "unable to initialize APM settings, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr4_apss_parse_temp_adj_properties(ctrl); -+ if (rc) { -+ cpr3_err(ctrl, "unable to parse temperature adjustment properties, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ ctrl->sensor_count = IPQ807x_APSS_CPR_SENSOR_COUNT; -+ -+ /* -+ * APSS only has one thread (0) per controller so the zeroed -+ * array does not need further modification. -+ */ -+ ctrl->sensor_owner = devm_kcalloc(ctrl->dev, ctrl->sensor_count, -+ sizeof(*ctrl->sensor_owner), GFP_KERNEL); -+ if (!ctrl->sensor_owner) -+ return -ENOMEM; -+ -+ ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4; -+ ctrl->supports_hw_closed_loop = false; -+ ctrl->use_hw_closed_loop = of_property_read_bool(ctrl->dev->of_node, -+ "qcom,cpr-hw-closed-loop"); -+ return 0; -+} -+ -+static int cpr4_apss_regulator_suspend(struct platform_device *pdev, -+ pm_message_t state) -+{ -+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev); -+ -+ return cpr3_regulator_suspend(ctrl); -+} -+ -+static int cpr4_apss_regulator_resume(struct platform_device *pdev) -+{ -+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev); -+ -+ return cpr3_regulator_resume(ctrl); -+} -+ -+static void ipq6018_set_mem_acc(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ -+ ipq6018_mem_acc_tcsr[0].ioremap_addr = -+ ioremap(ipq6018_mem_acc_tcsr[0].phy_addr, 0x4); -+ ipq6018_mem_acc_tcsr[1].ioremap_addr = -+ ioremap(ipq6018_mem_acc_tcsr[1].phy_addr, 0x4); -+ -+ if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) && -+ (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) && -+ (vreg->current_corner == (vreg->corner_count - CPR3_CORNER_OFFSET))) { -+ -+ writel_relaxed(ipq6018_mem_acc_tcsr[0].value, -+ ipq6018_mem_acc_tcsr[0].ioremap_addr); -+ writel_relaxed(ipq6018_mem_acc_tcsr[1].value, -+ ipq6018_mem_acc_tcsr[1].ioremap_addr); -+ } -+} -+ -+static void ipq6018_clr_mem_acc(struct regulator_dev *rdev) -+{ -+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); -+ -+ if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) && -+ (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) && -+ (vreg->current_corner != vreg->corner_count - CPR3_CORNER_OFFSET)) { -+ writel_relaxed(0x0, ipq6018_mem_acc_tcsr[0].ioremap_addr); -+ writel_relaxed(0x0, ipq6018_mem_acc_tcsr[1].ioremap_addr); -+ } -+ -+ iounmap(ipq6018_mem_acc_tcsr[0].ioremap_addr); -+ iounmap(ipq6018_mem_acc_tcsr[1].ioremap_addr); -+} -+ -+static struct cpr4_mem_acc_func ipq6018_mem_acc_funcs = { -+ .set_mem_acc = ipq6018_set_mem_acc, -+ .clear_mem_acc = ipq6018_clr_mem_acc -+}; -+ -+static const struct cpr4_reg_data ipq807x_cpr_apss = { -+ .cpr_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS, -+ .fuse_ref_volt = ipq807x_apss_fuse_ref_volt, -+ .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE, -+ .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT, -+ .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT, -+ .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT, -+ .cpr3_fuse_params = &ipq807x_fuse_params, -+ .mem_acc_funcs = NULL, -+}; -+ -+static const struct cpr4_reg_data ipq817x_cpr_apss = { -+ .cpr_valid_fuse_count = IPQ817x_APPS_FUSE_CORNERS, -+ .fuse_ref_volt = ipq807x_apss_fuse_ref_volt, -+ .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE, -+ .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT, -+ .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT, -+ .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT, -+ .cpr3_fuse_params = &ipq807x_fuse_params, -+ .mem_acc_funcs = NULL, -+}; -+ -+static const struct cpr4_reg_data ipq6018_cpr_apss = { -+ .cpr_valid_fuse_count = IPQ6018_APSS_FUSE_CORNERS, -+ .fuse_ref_volt = ipq6018_apss_fuse_ref_volt, -+ .fuse_step_volt = IPQ6018_APSS_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE, -+ .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT, -+ .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT, -+ .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT, -+ .cpr3_fuse_params = &ipq6018_fuse_params, -+ .mem_acc_funcs = &ipq6018_mem_acc_funcs, -+}; -+ -+static const struct cpr4_reg_data ipq9574_cpr_apss = { -+ .cpr_valid_fuse_count = IPQ9574_APSS_FUSE_CORNERS, -+ .fuse_ref_volt = ipq9574_apss_fuse_ref_volt, -+ .fuse_step_volt = IPQ9574_APSS_FUSE_STEP_VOLT, -+ .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE, -+ .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT, -+ .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT, -+ .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT, -+ .cpr3_fuse_params = &ipq9574_fuse_params, -+ .mem_acc_funcs = NULL, -+}; -+ -+static struct of_device_id cpr4_regulator_match_table[] = { -+ { -+ .compatible = "qcom,cpr4-ipq807x-apss-regulator", -+ .data = &ipq807x_cpr_apss -+ }, -+ { -+ .compatible = "qcom,cpr4-ipq817x-apss-regulator", -+ .data = &ipq817x_cpr_apss -+ }, -+ { -+ .compatible = "qcom,cpr4-ipq6018-apss-regulator", -+ .data = &ipq6018_cpr_apss -+ }, -+ { -+ .compatible = "qcom,cpr4-ipq9574-apss-regulator", -+ .data = &ipq9574_cpr_apss -+ }, -+ {} -+}; -+ -+static int cpr4_apss_regulator_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct cpr3_controller *ctrl; -+ const struct of_device_id *match; -+ struct cpr4_reg_data *cpr_data; -+ int i, rc; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "Device tree node is missing\n"); -+ return -EINVAL; -+ } -+ -+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -+ if (!ctrl) -+ return -ENOMEM; -+ -+ match = of_match_device(cpr4_regulator_match_table, &pdev->dev); -+ if (!match) -+ return -ENODEV; -+ -+ cpr_data = (struct cpr4_reg_data *)match->data; -+ g_valid_fuse_count = cpr_data->cpr_valid_fuse_count; -+ dev_info(dev, "CPR valid fuse count: %d\n", g_valid_fuse_count); -+ ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate; -+ -+ ctrl->dev = dev; -+ /* Set to false later if anything precludes CPR operation. */ -+ ctrl->cpr_allowed_hw = true; -+ -+ rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name", -+ &ctrl->name); -+ if (rc) { -+ cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr3_map_fuse_base(ctrl, pdev); -+ if (rc) { -+ cpr3_err(ctrl, "could not map fuse base address\n"); -+ return rc; -+ } -+ -+ rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_APSS_CPR_TCSR_START, -+ IPQ807x_APSS_CPR_TCSR_END); -+ if (rc) { -+ cpr3_err(ctrl, "could not read CPR tcsr setting\n"); -+ return rc; -+ } -+ -+ rc = cpr3_allocate_threads(ctrl, 0, 0); -+ if (rc) { -+ cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ if (ctrl->thread_count != 1) { -+ cpr3_err(ctrl, "expected 1 thread but found %d\n", -+ ctrl->thread_count); -+ return -EINVAL; -+ } -+ -+ rc = cpr4_apss_init_controller(ctrl); -+ if (rc) { -+ if (rc != -EPROBE_DEFER) -+ cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = cpr4_apss_init_thread(&ctrl->thread[0]); -+ if (rc) { -+ cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc); -+ return rc; -+ } -+ -+ for (i = 0; i < ctrl->thread[0].vreg_count; i++) { -+ ctrl->thread[0].vreg[i].cpr4_regulator_data = cpr_data; -+ rc = cpr4_apss_init_regulator(&ctrl->thread[0].vreg[i]); -+ if (rc) { -+ cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n", -+ rc); -+ return rc; -+ } -+ } -+ -+ platform_set_drvdata(pdev, ctrl); -+ -+ return cpr3_regulator_register(pdev, ctrl); -+} -+ -+static int cpr4_apss_regulator_remove(struct platform_device *pdev) -+{ -+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev); -+ -+ return cpr3_regulator_unregister(ctrl); -+} -+ -+static struct platform_driver cpr4_apss_regulator_driver = { -+ .driver = { -+ .name = "qcom,cpr4-apss-regulator", -+ .of_match_table = cpr4_regulator_match_table, -+ .owner = THIS_MODULE, -+ }, -+ .probe = cpr4_apss_regulator_probe, -+ .remove = cpr4_apss_regulator_remove, -+ .suspend = cpr4_apss_regulator_suspend, -+ .resume = cpr4_apss_regulator_resume, -+}; -+ -+static int cpr4_regulator_init(void) -+{ -+ return platform_driver_register(&cpr4_apss_regulator_driver); -+} -+ -+static void cpr4_regulator_exit(void) -+{ -+ platform_driver_unregister(&cpr4_apss_regulator_driver); -+} -+ -+MODULE_DESCRIPTION("CPR4 APSS regulator driver"); -+MODULE_LICENSE("GPL v2"); -+ -+arch_initcall(cpr4_regulator_init); -+module_exit(cpr4_regulator_exit); ---- /dev/null -+++ b/include/soc/qcom/socinfo.h -@@ -0,0 +1,463 @@ -+/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_ -+#define _ARCH_ARM_MACH_MSM_SOCINFO_H_ -+ -+#include -+ -+#define CPU_IPQ8074 323 -+#define CPU_IPQ8072 342 -+#define CPU_IPQ8076 343 -+#define CPU_IPQ8078 344 -+#define CPU_IPQ8070 375 -+#define CPU_IPQ8071 376 -+ -+#define CPU_IPQ8072A 389 -+#define CPU_IPQ8074A 390 -+#define CPU_IPQ8076A 391 -+#define CPU_IPQ8078A 392 -+#define CPU_IPQ8070A 395 -+#define CPU_IPQ8071A 396 -+ -+#define CPU_IPQ8172 397 -+#define CPU_IPQ8173 398 -+#define CPU_IPQ8174 399 -+ -+#define CPU_IPQ6018 402 -+#define CPU_IPQ6028 403 -+#define CPU_IPQ6000 421 -+#define CPU_IPQ6010 422 -+#define CPU_IPQ6005 453 -+ -+#define CPU_IPQ5010 446 -+#define CPU_IPQ5018 447 -+#define CPU_IPQ5028 448 -+#define CPU_IPQ5000 503 -+#define CPU_IPQ0509 504 -+#define CPU_IPQ0518 505 -+ -+#define CPU_IPQ9514 510 -+#define CPU_IPQ9554 512 -+#define CPU_IPQ9570 513 -+#define CPU_IPQ9574 514 -+#define CPU_IPQ9550 511 -+#define CPU_IPQ9510 521 -+ -+static inline int read_ipq_soc_version_major(void) -+{ -+ const int *prop; -+ prop = of_get_property(of_find_node_by_path("/"), "soc_version_major", -+ NULL); -+ -+ if (!prop) -+ return -EINVAL; -+ -+ return le32_to_cpu(*prop); -+} -+ -+static inline int read_ipq_cpu_type(void) -+{ -+ const int *prop; -+ prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL); -+ /* -+ * Return Default CPU type if "cpu_type" property is not found in DTSI -+ */ -+ if (!prop) -+ return CPU_IPQ8074; -+ -+ return le32_to_cpu(*prop); -+} -+ -+static inline int cpu_is_ipq8070(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8070; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8071(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8071; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8072(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8072; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8074(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8074; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8076(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8076; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8078(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8078; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8072a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8072A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8074a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8074A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8076a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8076A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8078a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8078A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8070a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8070A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8071a(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8071A; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8172(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8172; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8173(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8173; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq8174(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ8174; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq6018(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ6018; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq6028(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ6028; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq6000(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ6000; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq6010(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ6010; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq6005(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ6005; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq5010(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ5010; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq5018(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ5018; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq5028(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ5028; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq5000(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ5000; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq0509(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ0509; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq0518(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ0518; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9514(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9514; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9554(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9554; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9570(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9570; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9574(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9574; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9550(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9550; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq9510(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return read_ipq_cpu_type() == CPU_IPQ9510; -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq807x(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq8072() || cpu_is_ipq8074() || -+ cpu_is_ipq8076() || cpu_is_ipq8078() || -+ cpu_is_ipq8070() || cpu_is_ipq8071() || -+ cpu_is_ipq8072a() || cpu_is_ipq8074a() || -+ cpu_is_ipq8076a() || cpu_is_ipq8078a() || -+ cpu_is_ipq8070a() || cpu_is_ipq8071a() || -+ cpu_is_ipq8172() || cpu_is_ipq8173() || -+ cpu_is_ipq8174(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq60xx(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq6018() || cpu_is_ipq6028() || -+ cpu_is_ipq6000() || cpu_is_ipq6010() || -+ cpu_is_ipq6005(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq50xx(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq5010() || cpu_is_ipq5018() || -+ cpu_is_ipq5028() || cpu_is_ipq5000() || -+ cpu_is_ipq0509() || cpu_is_ipq0518(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_ipq95xx(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq9514() || cpu_is_ipq9554() || -+ cpu_is_ipq9570() || cpu_is_ipq9574() || -+ cpu_is_ipq9550() || cpu_is_ipq9510(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_nss_crypto_enabled(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq807x() || cpu_is_ipq60xx() || -+ cpu_is_ipq50xx() || cpu_is_ipq9570() || -+ cpu_is_ipq9550() || cpu_is_ipq9574() || -+ cpu_is_ipq9554(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_internal_wifi_enabled(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq807x() || cpu_is_ipq60xx() || -+ cpu_is_ipq50xx() || cpu_is_ipq9514() || -+ cpu_is_ipq9554() || cpu_is_ipq9574(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_uniphy1_enabled(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq807x() || cpu_is_ipq60xx() || -+ cpu_is_ipq9554() || cpu_is_ipq9570() || -+ cpu_is_ipq9574() || cpu_is_ipq9550(); -+#else -+ return 0; -+#endif -+} -+ -+static inline int cpu_is_uniphy2_enabled(void) -+{ -+#ifdef CONFIG_ARCH_QCOM -+ return cpu_is_ipq807x() || cpu_is_ipq9570() || -+ cpu_is_ipq9574(); -+#else -+ return 0; -+#endif -+} -+ -+#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */ diff --git a/target/linux/ipq807x/patches-5.15/0133-clk-ipq-support-for-resetting-multiple-bits.patch b/target/linux/ipq807x/patches-5.15/0138-clk-ipq-support-for-resetting-multiple-bits.patch similarity index 75% rename from target/linux/ipq807x/patches-5.15/0133-clk-ipq-support-for-resetting-multiple-bits.patch rename to target/linux/ipq807x/patches-5.15/0138-clk-ipq-support-for-resetting-multiple-bits.patch index 93342cfa3..563d9e4ac 100644 --- a/target/linux/ipq807x/patches-5.15/0133-clk-ipq-support-for-resetting-multiple-bits.patch +++ b/target/linux/ipq807x/patches-5.15/0138-clk-ipq-support-for-resetting-multiple-bits.patch @@ -1,7 +1,7 @@ -From e362372fa8d56c669516dc83abe75cd057d94171 Mon Sep 17 00:00:00 2001 +From 2fc17ac5ce7a8c6c7564c4b91e06f2cde62d58be Mon Sep 17 00:00:00 2001 From: Rajkumar Ayyasamy Date: Wed, 18 Mar 2020 17:08:11 +0530 -Subject: [PATCH 133/137] clk: ipq: support for resetting multiple bits +Subject: [PATCH] clk: ipq: support for resetting multiple bits Current reset structure takes only one reset bit and calculates the bitmask in its reset operation. Some of the @@ -24,9 +24,11 @@ Signed-off-by: Rajkumar Ayyasamy drivers/clk/qcom/reset.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) +diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c +index 819d194be8f7..8ad7b50dd534 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c -@@ -28,7 +28,7 @@ qcom_reset_assert(struct reset_controlle +@@ -28,7 +28,7 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; @@ -35,7 +37,7 @@ Signed-off-by: Rajkumar Ayyasamy return regmap_update_bits(rst->regmap, map->reg, mask, mask); } -@@ -42,7 +42,7 @@ qcom_reset_deassert(struct reset_control +@@ -42,7 +42,7 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; @@ -44,6 +46,8 @@ Signed-off-by: Rajkumar Ayyasamy return regmap_update_bits(rst->regmap, map->reg, mask, 0); } +diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h +index 2a08b5e282c7..0410f83bf2bb 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -11,6 +11,7 @@ @@ -54,3 +58,6 @@ Signed-off-by: Rajkumar Ayyasamy }; struct regmap; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch b/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch similarity index 80% rename from target/linux/ipq807x/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch rename to target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch index 1004880b8..5d807d323 100644 --- a/target/linux/ipq807x/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch +++ b/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch @@ -1,7 +1,7 @@ -From ad08de7cb6308521b4a80c427a7cbec84742a729 Mon Sep 17 00:00:00 2001 +From 0981de6ff0a072fd25d919e661ac22890a7a1e34 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 1 Jan 2022 18:15:03 +0100 -Subject: [PATCH 134/137] clk: qcom: ipq8074: add missing networking resets +Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers. @@ -15,9 +15,11 @@ Signed-off-by: Robert Marko include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++ 2 files changed, 28 insertions(+) +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index 4d6e8c47515f..759e676d4110 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4827,6 +4827,20 @@ static const struct qcom_reset_map gcc_i +@@ -4745,6 +4745,20 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_WCSSAON_RESET] = { 0x59010, 0 }, @@ -37,10 +39,12 @@ Signed-off-by: Robert Marko + [GCC_NSSPORT6_RESET] = { 0x68014, 0, BIT(29) | GENMASK(13, 12) }, }; - static struct gdsc *gcc_ipq8074_gdscs[] = { + static const struct of_device_id gcc_ipq8074_match_table[] = { +diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +index 9b1c42bc430c..07402d970959 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -368,6 +368,20 @@ +@@ -367,5 +367,19 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 #define GCC_WCSSAON_RESET 132 @@ -59,5 +63,7 @@ Signed-off-by: Robert Marko +#define GCC_NSSPORT5_RESET 145 +#define GCC_NSSPORT6_RESET 146 - #define USB0_GDSC 0 - #define USB1_GDSC 1 + #endif +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch b/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch new file mode 100644 index 000000000..39cb2b569 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch @@ -0,0 +1,35 @@ +From 1a33a943c643b43033af936f297898b540361c62 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 1 Jan 2022 19:11:55 +0100 +Subject: [PATCH] clk: qcom: ipq8074: disable USB GDSC-s SW_COLLAPSE + +Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB +GDSC-s. + +This could potentially be better handled by utilizing the GDSC driver, but +I am not familiar with it nor do I have datasheets. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq8074.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index 244d1d8468e4..827c37787fa4 100644 +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4820,6 +4820,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + ++ /* Disable SW_COLLAPSE for USB0 GDSCR */ ++ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); ++ /* Disable SW_COLLAPSE for USB1 GDSCR */ ++ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); ++ + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch b/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch new file mode 100644 index 000000000..488914b16 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch @@ -0,0 +1,36 @@ +From 124d46f0397daf0bc13270ee43cc7d8166170f04 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 1 Jan 2022 19:14:59 +0100 +Subject: [PATCH] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock + +UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it +will cause the wait_for_pll() to timeout and thus return the error +indicating that the PLL failed to lock. + +This is bug in Huayra PLL HW for which SW workaround +is to set bit 26 of TEST_CTL register. + +This is ported from the QCA 5.4 based downstream kernel. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq8074.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index 827c37787fa4..cef89ea761d6 100644 +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4825,6 +4825,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) + /* Disable SW_COLLAPSE for USB1 GDSCR */ + regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); + ++ /* SW Workaround for UBI32 Huayra PLL */ ++ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); ++ + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch similarity index 51% rename from target/linux/ipq807x/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch rename to target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch index 9cdcf1710..f3a2f200f 100644 --- a/target/linux/ipq807x/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch +++ b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch @@ -1,7 +1,7 @@ -From 3c47c458fdf4056d4682cf2474e5599d5a916b61 Mon Sep 17 00:00:00 2001 +From f05295ef5e58a042f3a66490f6e75c6af83a329f Mon Sep 17 00:00:00 2001 From: Robert Marko -Date: Sun, 15 May 2022 23:00:42 +0200 -Subject: [PATCH 22/44] clk: qcom: ipq8074: add PPE crypto clock +Date: Sun, 13 Mar 2022 12:46:28 +0100 +Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. @@ -9,15 +9,16 @@ engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com --- - drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) + drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + + 2 files changed, 20 insertions(+) +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index c24e33321f72..6ece246f54a9 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref +@@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; @@ -42,7 +43,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { -@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl +@@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, @@ -50,3 +51,18 @@ Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { +diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +index 07402d970959..3ed155969c5d 100644 +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -233,6 +233,7 @@ + #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 + #define GCC_PCIE0_RCHNG_CLK_SRC 225 + #define GCC_PCIE0_RCHNG_CLK 226 ++#define GCC_CRYPTO_PPE_CLK 227 + + #define GCC_BLSP1_BCR 0 + #define GCC_BLSP1_QUP1_BCR 1 +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0151-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch b/target/linux/ipq807x/patches-5.15/0151-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch deleted file mode 100644 index 81807f619..000000000 --- a/target/linux/ipq807x/patches-5.15/0151-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch +++ /dev/null @@ -1,311 +0,0 @@ -From 6504bc9edeb1a2a54d813f4bb5d0267e7bf827f9 Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Thu, 6 Feb 2020 17:35:42 +0530 -Subject: [PATCH 4/8] clk: ipq8074: Support added for necessary clocks and - reset - -Change-Id: I21a76a44185f766e9b6dcba274392ea8e599718b -Signed-off-by: Praveenkumar I -Signed-off-by: Rajkumar Ayyasamy ---- - drivers/clk/qcom/gcc-ipq8074.c | 238 ++++++++++++++++++- - include/dt-bindings/clock/qcom,gcc-ipq8074.h | 35 ++- - 2 files changed, 258 insertions(+), 15 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -392,6 +392,22 @@ static const struct parent_map gcc_xo_gp - { P_SLEEP_CLK, 6 }, - }; - -+static const char * const gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = { -+ "xo", -+ "gpll4", -+ "gpll0", -+ "gpll6", -+ "gpll0_out_main_div2", -+}; -+ -+static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = { -+ { P_XO, 0 }, -+ { P_GPLL4, 1 }, -+ { P_GPLL0, 2 }, -+ { P_GPLL6, 3 }, -+ { P_GPLL0_DIV2, 4 }, -+}; -+ - static struct clk_alpha_pll gpll0_main = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], -@@ -964,6 +980,12 @@ static const struct freq_tbl ftbl_pcie_a - { } - }; - -+struct freq_tbl ftbl_pcie_rchng_clk_src[] = { -+ F(19200000, P_XO, 1, 0, 0), -+ F(100000000, P_GPLL0, 8, 0, 0), -+ { } -+}; -+ - static struct clk_rcg2 pcie0_axi_clk_src = { - .cmd_rcgr = 0x75054, - .freq_tbl = ftbl_pcie_axi_clk_src, -@@ -2023,6 +2045,78 @@ static struct clk_rcg2 gp3_clk_src = { - }, - }; - -+struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { -+ F(160000000, P_GPLL0_DIV2, 2.5, 0, 0), -+ F(320000000, P_GPLL0, 2.5, 0, 0), -+ F(600000000, P_GPLL6, 2, 0, 0), -+ { } -+}; -+ -+struct clk_rcg2 qdss_tsctr_clk_src = { -+ .cmd_rcgr = 0x29064, -+ .freq_tbl = ftbl_qdss_tsctr_clk_src, -+ .hid_width = 5, -+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "qdss_tsctr_clk_src", -+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, -+ .num_parents = 5, -+ .ops = &clk_rcg2_ops, -+ }, -+}; -+ -+static struct clk_fixed_factor qdss_dap_sync_clk_src = { -+ .mult = 1, -+ .div = 4, -+ .hw.init = &(struct clk_init_data){ -+ .name = "qdss_dap_sync_clk_src", -+ .parent_names = (const char *[]){ -+ "qdss_tsctr_clk_src" -+ }, -+ .num_parents = 1, -+ .ops = &clk_fixed_factor_ops, -+ }, -+}; -+ -+struct freq_tbl ftbl_qdss_at_clk_src[] = { -+ F(66670000, P_GPLL0_DIV2, 6, 0, 0), -+ F(240000000, P_GPLL6, 6, 0, 0), -+ { } -+}; -+ -+struct clk_rcg2 qdss_at_clk_src = { -+ .cmd_rcgr = 0x2900c, -+ .freq_tbl = ftbl_qdss_at_clk_src, -+ .hid_width = 5, -+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "qdss_at_clk_src", -+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, -+ .num_parents = 5, -+ .ops = &clk_rcg2_ops, -+ }, -+}; -+ -+ -+struct freq_tbl ftbl_adss_pwm_clk_src[] = { -+ F(19200000, P_XO, 1, 0, 0), -+ F(200000000, P_GPLL0, 4, 0, 0), -+ { } -+}; -+ -+struct clk_rcg2 adss_pwm_clk_src = { -+ .cmd_rcgr = 0x1c008, -+ .freq_tbl = ftbl_adss_pwm_clk_src, -+ .hid_width = 5, -+ .parent_map = gcc_xo_gpll0_map, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "adss_pwm_clk_src", -+ .parent_data = gcc_xo_gpll0, -+ .num_parents = 2, -+ .ops = &clk_rcg2_ops, -+ }, -+}; -+ - static struct clk_branch gcc_blsp1_ahb_clk = { - .halt_reg = 0x01008, - .clkr = { -@@ -4354,13 +4448,7 @@ static struct clk_branch gcc_gp3_clk = { - }, - }; - --static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(100000000, P_GPLL0, 8, 0, 0), -- { } --}; -- --static struct clk_rcg2 pcie0_rchng_clk_src = { -+struct clk_rcg2 pcie0_rchng_clk_src = { - .cmd_rcgr = 0x75070, - .freq_tbl = ftbl_pcie_rchng_clk_src, - .hid_width = 5, -@@ -4452,6 +4540,114 @@ static const struct alpha_pll_config nss - .alpha_en_mask = BIT(24), - }; - -+static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { -+ .halt_reg = 0x4700c, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x4700c, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_snoc_bus_timeout2_ahb_clk", -+ .parent_names = (const char *[]){ -+ "usb0_master_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { -+ .halt_reg = 0x47014, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x47014, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_snoc_bus_timeout3_ahb_clk", -+ .parent_names = (const char *[]){ -+ "usb1_master_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch gcc_dcc_clk = { -+ .halt_reg = 0x77004, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x77004, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_dcc_clk", -+ .parent_names = (const char *[]){ -+ "pcnoc_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch gcc_qdss_at_clk = { -+ .halt_reg = 0x29024, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x29024, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_qdss_at_clk", -+ .parent_names = (const char *[]){ -+ "qdss_at_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch gcc_qdss_dap_clk = { -+ .halt_reg = 0x29084, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x29084, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_qdss_dap_clk", -+ .parent_names = (const char *[]){ -+ "qdss_dap_sync_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch gcc_adss_pwm_clk = { -+ .halt_reg = 0x1c020, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x1c020, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_adss_pwm_clk", -+ .parent_names = (const char *[]){ -+ "adss_pwm_clk_src" -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_hw *gcc_ipq8074_hws[] = { - &gpll0_out_main_div2.hw, - &gpll6_out_main_div2.hw, -@@ -4460,6 +4656,7 @@ static struct clk_hw *gcc_ipq8074_hws[] - &gcc_xo_div4_clk_src.hw, - &nss_noc_clk_src.hw, - &nss_ppe_cdiv_clk_src.hw, -+ &qdss_dap_sync_clk_src.hw, - }; - - static struct clk_regmap *gcc_ipq8074_clks[] = { -@@ -4691,6 +4888,15 @@ static struct clk_regmap *gcc_ipq8074_cl - [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, - [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, - [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, -+ [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr, -+ [GCC_SNOC_BUS_TIMEOUT3_AHB_CLK] = &gcc_snoc_bus_timeout3_ahb_clk.clkr, -+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, -+ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, -+ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, -+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, -+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, -+ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, -+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, - }; - - static const struct qcom_reset_map gcc_ipq8074_resets[] = { ---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -230,10 +230,19 @@ - #define GCC_GP1_CLK 221 - #define GCC_GP2_CLK 222 - #define GCC_GP3_CLK 223 --#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 --#define GCC_PCIE0_RCHNG_CLK_SRC 225 --#define GCC_PCIE0_RCHNG_CLK 226 --#define GCC_CRYPTO_PPE_CLK 227 -+#define GCC_CRYPTO_PPE_CLK 224 -+#define GCC_PCIE0_RCHNG_CLK_SRC 225 -+#define GCC_PCIE0_RCHNG_CLK 226 -+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 227 -+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 228 -+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 229 -+#define GCC_DCC_CLK 230 -+#define ADSS_PWM_CLK_SRC 231 -+#define GCC_ADSS_PWM_CLK 232 -+#define QDSS_TSCTR_CLK_SRC 233 -+#define QDSS_AT_CLK_SRC 234 -+#define GCC_QDSS_AT_CLK 235 -+#define GCC_QDSS_DAP_CLK 236 - - #define GCC_BLSP1_BCR 0 - #define GCC_BLSP1_QUP1_BCR 1 diff --git a/target/linux/ipq807x/patches-5.15/0152-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch b/target/linux/ipq807x/patches-5.15/0152-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch deleted file mode 100644 index f6cc22ce4..000000000 --- a/target/linux/ipq807x/patches-5.15/0152-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 462aa0c53397ec5bf78e3e7f68aa8a3ca300f4ba Mon Sep 17 00:00:00 2001 -From: Selvam Sathappan Periakaruppan -Date: Tue, 24 Mar 2020 19:09:38 +0530 -Subject: [PATCH 5/8] clk: qcom: ipq8074: Fix gcc_snoc_bus_timeout_ahb_clk - offset - -By default, the ipq8074 V2 clks are provided in the gcc driver. -Updating the gcc_snoc_bus_timeout_ahb_clk offsets also as needed -in ipq8074 V2. - -Change-Id: I5a6e98d002f5c3354a804e55dd9ebb1f83f7f974 -Signed-off-by: Selvam Sathappan Periakaruppan ---- - drivers/clk/qcom/gcc-ipq8074.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4541,10 +4541,10 @@ static const struct alpha_pll_config nss - }; - - static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { -- .halt_reg = 0x4700c, -+ .halt_reg = 0x47014, - .halt_bit = 31, - .clkr = { -- .enable_reg = 0x4700c, -+ .enable_reg = 0x47014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_snoc_bus_timeout2_ahb_clk", -@@ -4559,10 +4559,10 @@ static struct clk_branch gcc_snoc_bus_ti - }; - - static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { -- .halt_reg = 0x47014, -+ .halt_reg = 0x4701C, - .halt_bit = 31, - .clkr = { -- .enable_reg = 0x47014, -+ .enable_reg = 0x4701C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_snoc_bus_timeout3_ahb_clk", diff --git a/target/linux/ipq807x/patches-5.15/0154-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch b/target/linux/ipq807x/patches-5.15/0154-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch deleted file mode 100644 index caff525c8..000000000 --- a/target/linux/ipq807x/patches-5.15/0154-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch +++ /dev/null @@ -1,31 +0,0 @@ -From db9c60394765843f6a77833bc40c27fac8852e97 Mon Sep 17 00:00:00 2001 -From: Balaji Prakash J -Date: Mon, 20 Apr 2020 20:07:51 +0530 -Subject: [PATCH] clk: ipq8074: defer from disabling gcc_sleep_clk_src - -Added CLK_IS_CRITICAL flag in order to defer from -disabling the sleep clock source. - -Once the usb sleep clocks are disabled, clock framework -is trying to disable the sleep clock source also and -the below warning is observed. - -[ 28.235750] gcc_sleep_clk_src status stuck at 'on' -[ 28.235794] WARNING: CPU: 0 PID: 29 at drivers/clk/qcom/clk-branch.c:92 clk_branch_toggle+0x160/0x178 - -Signed-off-by: Balaji Prakash J -Change-Id: I61fab902375716272ad9c426ce71581058f7bd35 ---- - drivers/clk/qcom/gcc-ipq8074.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -1284,6 +1284,7 @@ static struct clk_branch gcc_xo_clk_src - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, -+ .flags = CLK_IS_CRITICAL, - }, - }, - }; diff --git a/target/linux/ipq807x/patches-5.15/0155-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch b/target/linux/ipq807x/patches-5.15/0155-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch deleted file mode 100644 index d5cc4d6fa..000000000 --- a/target/linux/ipq807x/patches-5.15/0155-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001 -From: Balaji Prakash J -Date: Wed, 22 Apr 2020 20:35:30 +0530 -Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties - -All the voting enabled clocks does not support the enable -from CBCR register. So, updated gcc_blsp1_ahb_clk enable -register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE. - -Also, the voting controlled clocks are shared among multiple -components like APSS, RPM, NSS, TZ, etc. So, turning the -voting off from APSS does not make the clock off if it has -been voted from another component. Added the flag -BRANCH_HALT_VOTED in order to skip checking the clock -disable status. - -This change is referred from the below commits, -1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd -2. c8374157d5ae91d3b3e0d513d62808a798b32d3a - -Signed-off-by: Balaji Prakash J -Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230 ---- - drivers/clk/qcom/gcc-ipq8074.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -2120,9 +2120,10 @@ struct clk_rcg2 adss_pwm_clk_src = { - - static struct clk_branch gcc_blsp1_ahb_clk = { - .halt_reg = 0x01008, -+ .halt_check = BRANCH_HALT_VOTED, - .clkr = { -- .enable_reg = 0x01008, -- .enable_mask = BIT(0), -+ .enable_reg = 0x0b004, -+ .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_ahb_clk", - .parent_names = (const char *[]){ diff --git a/target/linux/ipq807x/patches-5.15/0156-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch b/target/linux/ipq807x/patches-5.15/0156-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch deleted file mode 100644 index 407e79c7f..000000000 --- a/target/linux/ipq807x/patches-5.15/0156-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Mon, 4 Sep 2017 15:00:10 +0530 -Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq - -If the parent clock rate is greater than unsigned long max -divided by 2 then the integer overflow is happening while -calculating the clock rate. Since RCG2 uses half integer -dividers, the clock rate is first being multiplied by 2 -followed by division and this multiplication leads to -overflow. - -Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977 -Signed-off-by: Abhishek Sahu -(cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430) -Signed-off-by: Praveenkumar I - -Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e ---- - drivers/clk/qcom/clk-rcg2.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -146,18 +146,18 @@ static int clk_rcg2_set_parent(struct cl - * hid_div n - */ - static unsigned long --calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) -+calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div) - { -+ u64 rate = parent_rate; -+ - if (hid_div) { - rate *= 2; -- rate /= hid_div + 1; -+ do_div(rate, hid_div + 1); - } - - if (mode) { -- u64 tmp = rate; -- tmp *= m; -- do_div(tmp, n); -- rate = tmp; -+ rate *= m; -+ do_div(rate, n); - } - - return rate; diff --git a/target/linux/ipq807x/patches-5.15/0157-clk-qcom-add-support-for-hw-controlled-RCG.patch b/target/linux/ipq807x/patches-5.15/0157-clk-qcom-add-support-for-hw-controlled-RCG.patch deleted file mode 100644 index 6682b8510..000000000 --- a/target/linux/ipq807x/patches-5.15/0157-clk-qcom-add-support-for-hw-controlled-RCG.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 0245360f8e118b67f4015533cfc79314f2d848d5 Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Tue, 13 Jun 2017 15:30:39 +0530 -Subject: [PATCH 2/3] clk: qcom: add support for hw controlled RCG -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The current driver generates stack trace during RCG update if -the RCG is off and new parent source is also disabled. For -hardware controlled RCG’s, clock is forced on during update -process and goes back to off status once switch is completed. -Since the new parent is in disabled state so update bit won’t -be cleared in this case. The check for update bit can be -skipped in this case. - -Signed-off-by: Abhishek Sahu -(cherry picked from commit 84dd0e12f10eebff44a464eb8455205abc4b4178) -Signed-off-by: Praveenkumar I - -Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 ---- - drivers/clk/qcom/clk-rcg.h | 4 ++++ - drivers/clk/qcom/clk-rcg2.c | 27 +++++++++++++++++++++------ - 2 files changed, 25 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -135,6 +135,7 @@ extern const struct clk_ops clk_dyn_rcg_ - * @mnd_width: number of bits in m/n/d values - * @hid_width: number of bits in half integer divider - * @safe_src_index: safe src index value -+ * @flags: RCG2 specific clock flags - * @parent_map: map from software's parent index to hardware's src_sel field - * @freq_tbl: frequency table - * @clkr: regmap clock handle -@@ -145,6 +146,9 @@ struct clk_rcg2 { - u8 mnd_width; - u8 hid_width; - u8 safe_src_index; -+ -+#define CLK_RCG2_HW_CONTROLLED BIT(0) -+ u8 flags; - const struct parent_map *parent_map; - const struct freq_tbl *freq_tbl; - struct clk_regmap clkr; ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -98,7 +98,7 @@ err: - return 0; - } - --static int update_config(struct clk_rcg2 *rcg) -+static int update_config(struct clk_rcg2 *rcg, bool check_update_clear) - { - int count, ret; - u32 cmd; -@@ -110,6 +110,9 @@ static int update_config(struct clk_rcg2 - if (ret) - return ret; - -+ if (!check_update_clear) -+ return 0; -+ - /* Wait for update to take effect */ - for (count = 500; count > 0; count--) { - ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); -@@ -128,14 +131,19 @@ static int clk_rcg2_set_parent(struct cl - { - struct clk_rcg2 *rcg = to_clk_rcg2(hw); - int ret; -+ bool check_update_clear = true; - u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; - -+ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) && -+ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index))) -+ check_update_clear = false; -+ - ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), - CFG_SRC_SEL_MASK, cfg); - if (ret) - return ret; - -- return update_config(rcg); -+ return update_config(rcg, check_update_clear); - } - - /* -@@ -312,12 +320,19 @@ static int __clk_rcg2_configure(struct c - static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) - { - int ret; -+ bool check_update_clear = true; -+ struct clk_hw *hw = &rcg->clkr.hw; -+ int index = qcom_find_src_index(hw, rcg->parent_map, f->src); - - ret = __clk_rcg2_configure(rcg, f); - if (ret) - return ret; - -- return update_config(rcg); -+ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) && -+ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index))) -+ check_update_clear = false; -+ -+ return update_config(rcg, check_update_clear); - } - - static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -910,7 +925,7 @@ static int clk_gfx3d_set_rate_and_parent - if (ret) - return ret; - -- return update_config(rcg); -+ return update_config(rcg, true); - } - - static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -1022,7 +1037,7 @@ static int clk_rcg2_shared_enable(struct - if (ret) - return ret; - -- ret = update_config(rcg); -+ ret = update_config(rcg, true); - if (ret) - return ret; - -@@ -1053,7 +1068,7 @@ static void clk_rcg2_shared_disable(stru - regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, - rcg->safe_src_index << CFG_SRC_SEL_SHIFT); - -- update_config(rcg); -+ update_config(rcg, true); - - clk_rcg2_clear_force_enable(hw); - diff --git a/target/linux/ipq807x/patches-5.15/0158-clk-qcom-ipq8074-add-hw-controlled-flag.patch b/target/linux/ipq807x/patches-5.15/0158-clk-qcom-ipq8074-add-hw-controlled-flag.patch deleted file mode 100644 index b9f743f4e..000000000 --- a/target/linux/ipq807x/patches-5.15/0158-clk-qcom-ipq8074-add-hw-controlled-flag.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 18d04f5cae30725ffa0c1c025f6beb1821c46857 Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Tue, 13 Jun 2017 15:31:34 +0530 -Subject: [PATCH 3/3] clk: qcom: ipq8074: add hw controlled flag -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -These RCG’s are hw controlled so add the -CLK_RCG2_HW_CONTROLLED flag. - -Signed-off-by: Abhishek Sahu -(cherry picked from commit 9a025b8271a95a80e9e769b89154b98b263be860) -Signed-off-by: Praveenkumar I - -Change-Id: Ic5da1551bf46921890955312026b9175a42fe14e ---- - drivers/clk/qcom/gcc-ipq8074.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -644,6 +644,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s - .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, -+ .flags = CLK_RCG2_HW_CONTROLLED, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pcnoc_bfdcd_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, -@@ -1319,6 +1320,7 @@ static struct clk_rcg2 system_noc_bfdcd_ - .freq_tbl = ftbl_system_noc_bfdcd_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, -+ .flags = CLK_RCG2_HW_CONTROLLED, - .clkr.hw.init = &(struct clk_init_data){ - .name = "system_noc_bfdcd_clk_src", - .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2, diff --git a/target/linux/ipq807x/patches-5.15/0159-clk-qcom-clk-rcg2-fix-set-duty-cycle-call.patch b/target/linux/ipq807x/patches-5.15/0159-clk-qcom-clk-rcg2-fix-set-duty-cycle-call.patch deleted file mode 100644 index 66eeaee58..000000000 --- a/target/linux/ipq807x/patches-5.15/0159-clk-qcom-clk-rcg2-fix-set-duty-cycle-call.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -463,7 +463,7 @@ static int clk_rcg2_set_duty_cycle(struc - if (ret) - return ret; - -- return update_config(rcg); -+ return update_config(rcg, true); - } - - const struct clk_ops clk_rcg2_ops = { diff --git a/target/linux/ipq807x/patches-5.15/0300-regulator-add-Qualcomm-CPR-regulators.patch b/target/linux/ipq807x/patches-5.15/0300-regulator-add-Qualcomm-CPR-regulators.patch new file mode 100644 index 000000000..0a7db87ef --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0300-regulator-add-Qualcomm-CPR-regulators.patch @@ -0,0 +1,73 @@ +From c013e84fa1cc1b8cd1ded28639a0f9745360aae6 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 11 Apr 2022 14:35:36 +0200 +Subject: [PATCH] regulator: add Qualcomm CPR regulators + +Allow building Qualcomm CPR regulators. + +Signed-off-by: Robert Marko +--- + drivers/regulator/Kconfig | 33 +++++++++++++++++++++++++++++++++ + drivers/regulator/Makefile | 3 +++ + 2 files changed, 36 insertions(+) + +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index 4fd13b06231f..92164c80cbc4 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1423,5 +1423,38 @@ config REGULATOR_QCOM_LABIBB + boost regulator and IBB can be used as a negative boost regulator + for LCD display panel. + ++config REGULATOR_CPR3 ++ bool "QCOM CPR3 regulator core support" ++ help ++ This driver supports Core Power Reduction (CPR) version 3 controllers ++ which are used by some Qualcomm Technologies, Inc. SoCs to ++ manage important voltage regulators. CPR3 controllers are capable of ++ monitoring several ring oscillator sensing loops simultaneously. The ++ CPR3 controller informs software when the silicon conditions require ++ the supply voltage to be increased or decreased. On certain supply ++ rails, the CPR3 controller is able to propagate the voltage increase ++ or decrease requests all the way to the PMIC without software ++ involvement. ++ ++config REGULATOR_CPR3_NPU ++ bool "QCOM CPR3 regulator for NPU" ++ depends on OF && REGULATOR_CPR3 ++ help ++ This driver supports Qualcomm Technologies, Inc. NPU CPR3 ++ regulator Which will always operate in open loop. ++ ++config REGULATOR_CPR4_APSS ++ bool "QCOM CPR4 regulator for APSS" ++ depends on OF && REGULATOR_CPR3 ++ help ++ This driver supports Qualcomm Technologies, Inc. APSS application ++ processor specific features including memory array power mux (APM) ++ switching, one CPR4 thread which monitor the two APSS clusters that ++ are both powered by a shared supply, hardware closed-loop auto ++ voltage stepping, voltage adjustments based on online core count, ++ voltage adjustments based on temperature readings, and voltage ++ adjustments for performance boost mode. This driver reads both initial ++ voltage and CPR target quotient values out of hardware fuses. ++ + endif + +diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile +index 9e382b50a5ef..2e521cb39e7e 100644 +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -105,6 +105,9 @@ obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o + obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o + obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o + obj-$(CONFIG_REGULATOR_QCOM_USB_VBUS) += qcom_usb_vbus-regulator.o ++obj-$(CONFIG_REGULATOR_CPR3) += cpr3-regulator.o cpr3-util.o ++obj-$(CONFIG_REGULATOR_CPR3_NPU) += cpr3-npu-regulator.o ++obj-$(CONFIG_REGULATOR_CPR4_APSS) += cpr4-apss-regulator.o + obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o + obj-$(CONFIG_REGULATOR_PCA9450) += pca9450-regulator.o + obj-$(CONFIG_REGULATOR_PF8X00) += pf8x00-regulator.o +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0301-power-Add-Qualcomm-APM.patch b/target/linux/ipq807x/patches-5.15/0301-power-Add-Qualcomm-APM.patch new file mode 100644 index 000000000..af3373cea --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0301-power-Add-Qualcomm-APM.patch @@ -0,0 +1,34 @@ +From d90ef31dbb0212b20099a07d34f27dbeb06c5c74 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 11 Apr 2022 14:38:08 +0200 +Subject: [PATCH] power: Add Qualcomm APM + +Allow building Qualcomm APM. + +Signed-off-by: Robert Marko +--- + drivers/power/Kconfig | 1 + + drivers/power/Makefile | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig +index 696bf77a7042..235f3cbf2a54 100644 +--- a/drivers/power/Kconfig ++++ b/drivers/power/Kconfig +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + source "drivers/power/reset/Kconfig" + source "drivers/power/supply/Kconfig" ++source "drivers/power/qcom/Kconfig" +diff --git a/drivers/power/Makefile b/drivers/power/Makefile +index effbf0377f32..cd239e730b2b 100644 +--- a/drivers/power/Makefile ++++ b/drivers/power/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_POWER_RESET) += reset/ + obj-$(CONFIG_POWER_SUPPLY) += supply/ ++obj-$(CONFIG_QCOM_APM) += qcom/ +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0900-arm64-dts-add-OpenWrt-DTS-files.patch b/target/linux/ipq807x/patches-5.15/0900-arm64-dts-add-OpenWrt-DTS-files.patch index 460783749..2cece92a0 100644 --- a/target/linux/ipq807x/patches-5.15/0900-arm64-dts-add-OpenWrt-DTS-files.patch +++ b/target/linux/ipq807x/patches-5.15/0900-arm64-dts-add-OpenWrt-DTS-files.patch @@ -12,11 +12,13 @@ Signed-off-by: Robert Marko --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -4,6 +4,9 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony- +@@ -4,6 +4,11 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony- dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8072-301w.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax6.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax3600.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8071-mf269.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8078-xtr10890.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb diff --git a/target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-label-to-clocks.patch b/target/linux/ipq807x/patches-5.15/0901-arm64-dts-ipq8074-add-label-to-clocks.patch similarity index 60% rename from target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-label-to-clocks.patch rename to target/linux/ipq807x/patches-5.15/0901-arm64-dts-ipq8074-add-label-to-clocks.patch index deafccbeb..759cd2e48 100644 --- a/target/linux/ipq807x/patches-5.15/0135-arm64-dts-ipq8074-add-label-to-clocks.patch +++ b/target/linux/ipq807x/patches-5.15/0901-arm64-dts-ipq8074-add-label-to-clocks.patch @@ -1,7 +1,7 @@ -From c7b874696964bab2de6b08a44168c42a556a077c Mon Sep 17 00:00:00 2001 +From 4bdbb8ddf49ebca198719940c4b6246f90a4251d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 9 Feb 2022 23:13:26 +0100 -Subject: [PATCH 135/137] arm64: dts: ipq8074: add label to clocks +Subject: [PATCH] arm64: dts: ipq8074: add label to clocks Add label to clocks node as that makes it easy to add the NSS fixed clocks that are required in their DTSI. @@ -11,14 +11,19 @@ Signed-off-by: Robert Marko arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index daf59a579b8f..e81fe66669c8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -15,7 +15,7 @@ +@@ -12,7 +12,7 @@ / { + model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; - interrupt-parent = <&intc>; - clocks { + clocks: clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; - clock-frequency = <32768>; + clock-frequency = <32000>; +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/1100-export-ns.patch b/target/linux/ipq807x/patches-5.15/0905-export-ns.patch similarity index 100% rename from target/linux/ipq807x/patches-5.15/1100-export-ns.patch rename to target/linux/ipq807x/patches-5.15/0905-export-ns.patch