mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
4d84789cdd
Manually rebased: hack-5.15/780-usb-net-MeigLink_modem_support.patch Removed upstreamed: mpc85xx/patches-5.15/110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch All other patches automatically rebased. Signed-off-by: Liu Linhui <liulinhui36@gmail.com> Signed-off-by: Liu Linhui <liulinhui36@gmail.com>
50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From 9d38e110e23ce0b858ccd67a8a819dc187529a33 Mon Sep 17 00:00:00 2001
|
|
From: Christian Marangi <ansuelsmth@gmail.com>
|
|
Date: Fri, 8 Jul 2022 23:24:25 +0200
|
|
Subject: [PATCH 101/137] clk: qcom: clk-rcg2: add rcg2 mux ops
|
|
|
|
An RCG may act as a mux that switch between 2 parents.
|
|
This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
|
|
the CPU cluster clock just switches between XO and the PLL that feeds it.
|
|
|
|
Add the required ops to add support for this special configuration and use
|
|
the generic mux function to determine the rate.
|
|
|
|
This way we dont have to keep a essentially dummy frequency table to use
|
|
RCG2 as a mux.
|
|
|
|
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
---
|
|
drivers/clk/qcom/clk-rcg.h | 1 +
|
|
drivers/clk/qcom/clk-rcg2.c | 7 +++++++
|
|
2 files changed, 8 insertions(+)
|
|
|
|
--- a/drivers/clk/qcom/clk-rcg.h
|
|
+++ b/drivers/clk/qcom/clk-rcg.h
|
|
@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
|
|
|
|
extern const struct clk_ops clk_rcg2_ops;
|
|
extern const struct clk_ops clk_rcg2_floor_ops;
|
|
+extern const struct clk_ops clk_rcg2_mux_closest_ops;
|
|
extern const struct clk_ops clk_edp_pixel_ops;
|
|
extern const struct clk_ops clk_byte_ops;
|
|
extern const struct clk_ops clk_byte2_ops;
|
|
--- a/drivers/clk/qcom/clk-rcg2.c
|
|
+++ b/drivers/clk/qcom/clk-rcg2.c
|
|
@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
|
|
};
|
|
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
|
|
|
|
+const struct clk_ops clk_rcg2_mux_closest_ops = {
|
|
+ .determine_rate = __clk_mux_determine_rate_closest,
|
|
+ .get_parent = clk_rcg2_get_parent,
|
|
+ .set_parent = clk_rcg2_set_parent,
|
|
+};
|
|
+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
|
|
+
|
|
struct frac_entry {
|
|
int num;
|
|
int den;
|