Instead of forcing 2.5G PHYs into rate-adapter mode which results higher
energy consumption, lack of support for half-duplex modes and typically
worse performance when linked at speeds less than 2.5G, use SGMII mode
which allows the MAC to follow the PHY speed.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This setting is more suitable for device running OpenWRT.
Most OpenWRT targets are already default to this configuration,
and it has shown better performance in VPN (wireguard).
Signed-off-by: Kien Truong <duckientruong@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport BLOCK OF support patch merged upstream and refresh pending
BLOCK patches.
This is a new way to declare partition table for BLOCK device (eMMC
currently supported) with the use of DTS.
Current pending patch are adapted to not cause regression with current
downstream implementation of a similar functionality.
Also enable the new OF_PARTITION config by default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The previous iteration of MediaTek's PHY patches caused various weird bugs.
Drop culprit patch 733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch
and use the most recent iteration of the patchset which has been posted to the
netdev mailing list.
Link: https://patchwork.kernel.org/project/netdevbpf/list/?series=895513&state=*
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Apply changes suggested by SkyLake Huang for pending series improving
MediaTek Ethernet PHY drivers.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The broadcom PHY driver only has to depend upon PTP_1588_CLOCK_OPTIONAL
if NETWORK_PHY_TIMESTAMPING is enabled. The PTP functionality is stubbed
in this case.
Reflect this circumstance in the dependence condition. This allows to
build the driver as a built-in module even if PTP is built as a module.
This is required to include the broadcom PHY module regardless of the
built-setting of the PTP subsystem. On ath79 (and probably more)
targets with Broadcom PHY, Gigabit operation is currently broken as the
PHY driver is only built as a module in case all kernel-packages are
built. Due to this circumstance, affected devices fall back to using the
generic PHY driver.
Signed-off-by: David Bauer <mail@david-bauer.net>
This backport patch inserted suspend/resume callbacks
for the wrong PHY driver.
Signed-off-by: Marco von Rosenberg <marcovr@selfnet.de>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add support for FORESEE F35SQA001G SPI NAND.
Similar to F35SQA002G, but differs in capacity.
Datasheet:
- https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf
Tested on Xiaomi AX3000T flashed with OpenWRT.
Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Hardware:
- SoC: MediaTek MT7981B
- CPU: 2x 1.3 GHz Cortex-A53
- Flash: 128 MiB SPI NAND
- RAM: 512 MiB
- WLAN: 2.4 GHz, 5 GHz (MediaTek MT7976CN, 802.11ax)
- Ethernet: 1x 10/100/1000/2500 Mbps WAN, 1x10/100/1000 Mbps LAN
- USB 3.0 port
- Buttons: 1 Reset button, 1 slider button
- LEDs: 1x Red, 1x White
- Serial console: internal test points, 115200 8n1
- Power: 5 VDC, 3 A
Installation:
The installation must be done via TFTP by disassembling the router.
On other occasions Cudy has distributed intermediate firmware to make
installation easier, and so I recommend checking the Wiki for this
device if there is a more convenient solution than the one below.
To install using TFTP:
1. Connect to UART.
2. With the router off, press the RESET button. While the router is turning
on, the button should continue to be pressed for at least 5 seconds.
3. A u-boot shell will automatically open.
4. Connect to LAN and set your IP to 192.168.1.88/24. Configure a
TFTP server and an OpenWrt initramfs-kernel.bin firmware file.
5. Run these steps in u-boot using the name of your file.
setenv bootfile initramfs-kernel.bin
tftpboot
bootm
6. If you can reach LuCI or SSH now, just use the sysupgrade image
with the 'Keep settings' option turned off.
Signed-off-by: Luis Mita <luis@luismita.com>
The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Assign pwm function of PWM0 pin to the pwm-fan.
This is mostly just cosmetics as it basically reflects the default
setting of that pin.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add additionals possible pinctrl group for pwm2~7 on pins
pin 4 (GPIO_A) pwm7
pin 58 (JTAG_JTDI) pwm2
pin 59 (JTAG_JTDO) pwm3
pin 60 (JTAG_JTMS) pwm4
pin 61 (JTAG_JTCLK) pwm5
pin 62 (JTAG_JTRST_N) pwm6
They can be useful e.g. on the BPi-R4 as in that way pwm2~6 can be exposed
on the 26-pin header (pwm6 always, pwm2~5 instead of the full UART).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use pending patchset for 2.5GE PHY driver, unifying LED handling
accross all MediaTek Ethernet PHYs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport newly introduced support for 'active-high' property and use
it to correctly implement polarity assignment for Aquantia PHY LEDs.
Previously the 'active-low' property was used to switch a LED PIN to
active-high ("drive VDD" in Aquantia-speak) mode.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
PMD Global Transmit Disable bit should be cleared for normal operation.
This should be HW default, however I found that on Asus RT-AX89X that uses
AQR113C PHY and firmware 5.4 this bit is set by default.
With this bit set the AQR cannot achieve a link with its link-partner and
it took me multiple hours of digging through the vendor GPL source to find
this out, so lets always clear this bit during .config_init() to avoid a
situation like this in the future.
aqr107_wait_processor_intensive_op() is moved up because datasheet notes
that any changes to this bit are processor intensive.
This is a modified version of patch that got merged upstream as AQR113C
has a separate config_init() upstream.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add memory regions and devices used for wireless offloading to the
device tree for MT7988.
This allows using WED on devices with MT7988 SoC and MT7995E, MT7996E or
MT7992E wireless controllers.
Devices with 4 GiB of RAM (or more) will still need ajustments to avoid
running out of swiotlb entries.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
commit eee3c695f3 ("linux-firmware: add offloading firmware for MT7988")
added mt7988_wo_{0,1}.bin in the 'mediatek/mt7988' directory while driver
currently expects the files in the 'mediatek' directory.
Import pending patch which changes the path in the driver header now
that the firmware has been added.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
