kernel: qca-ssdk/qca-nss-dp: update to 12.5 for kernel 6.6 support

2025-04-17 21:03:30 +00:00 · 2024-11-09 23:01:43 +08:00 · 2024-11-09 23:01:43 +08:00 · 2b10822e1b
commit 2b10822e1b
parent f2e1532a7c
40 changed files with 4750 additions and 127 deletions
--- a/package/qca/qca-nss-dp/Makefile
+++ b/package/qca/qca-nss-dp/Makefile
@ -5,9 +5,9 @@ PKG_RELEASE:=2

 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-06-06
-PKG_SOURCE_VERSION:=fa67464466f69f00967cc373d1bdd6025f57eb89
-PKG_MIRROR_HASH:=51bf524382a5cb542c2c80d12a91f87b9736de3ac3c1d4a351c97b3502d68574
+PKG_SOURCE_DATE:=2024-04-16
+PKG_SOURCE_VERSION:=5bf8b91e9fc209f175f9a58723b03055ace3d581
+PKG_MIRROR_HASH:=c50fefd3debbc01040f900c20da9a9bb6ae36aa72a532362aae1152e83c203a0

 PKG_BUILD_PARALLEL:=1
 PKG_FLAGS:=nonshared
@ -39,7 +39,7 @@ EXTRA_CFLAGS+= \

 NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal
 define Build/Configure
-	$(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_SUBTARGET)/nss_$(CONFIG_TARGET_SUBTARGET).h \
+	$(CP) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_SUBTARGET)/nss_$(CONFIG_TARGET_SUBTARGET).h \
 		$(PKG_BUILD_DIR)/exports/nss_dp_arch.h
 endef

@ -47,8 +47,7 @@ define Build/Compile
 	+$(KERNEL_MAKE) $(PKG_JOBS) \
 		-C "$(LINUX_DIR)" \
 		M="$(PKG_BUILD_DIR)" \
-		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \
-		SoC="$(CONFIG_TARGET_SUBTARGET)" \
+		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(CONFIG_TARGET_SUBTARGET)" \
 		modules
 endef

--- a/package/qca/qca-nss-dp/patches/0002-edma_tx_rx-support-newer-kernels-time-stamping-API.patch
+++ b/package/qca/qca-nss-dp/patches/0002-edma_tx_rx-support-newer-kernels-time-stamping-API.patch
@ -40,7 +40,7 @@ Signed-off-by: Baruch Siach <baruch@tkos.co.il>
 		ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0);
 +#else
 +	if (ndev && phy_has_txtstamp(ndev->phydev))
-+		phy_rxtstamp(ndev->phydev, skb, 0);
+		phy_txtstamp(ndev->phydev, skb, 0);
 +#endif
 }
 EXPORT_SYMBOL(nss_phy_tstamp_tx_buf);
--- a/package/qca/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch
+++ b/package/qca/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch
@ -26,7 +26,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>

 --- a/include/nss_dp_dev.h
 +++ b/include/nss_dp_dev.h
-@@ -202,13 +202,10 @@ struct nss_dp_dev {
+@@ -225,13 +225,10 @@ struct nss_dp_dev {
 	unsigned long drv_flags;	/* Driver specific feature flags */
 
 	/* Phy related stuff */
@ -43,7 +43,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/nss_dp_main.c
 +++ b/nss_dp_main.c
-@@ -418,7 +418,7 @@ static int nss_dp_open(struct net_device
+@@ -436,7 +436,7 @@ static int nss_dp_open(struct net_device
 
 	netif_start_queue(netdev);
 
@ -52,7 +52,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 		/* Notify data plane link is up */
 		if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) {
 			netdev_dbg(netdev, "Data plane set link failed\n");
-@@ -615,6 +615,12 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -633,6 +633,12 @@ static int32_t nss_dp_of_get_pdata(struc
 		return -EFAULT;
 	}
 
@ -65,7 +65,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 	if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) {
 		pr_err("%s: error reading mactype\n", np->name);
 		return -EFAULT;
-@@ -635,18 +641,6 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -653,18 +659,6 @@ static int32_t nss_dp_of_get_pdata(struc
 		return -EFAULT;
 #endif
 
@ -84,7 +84,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
 	maddr = (uint8_t *)of_get_mac_address(np);
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0))
-@@ -695,56 +689,6 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -753,56 +747,6 @@ static int32_t nss_dp_of_get_pdata(struc
 	return 0;
 }
 
@ -141,7 +141,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 #ifdef CONFIG_NET_SWITCHDEV
 /*
  * nss_dp_is_phy_dev()
-@@ -803,7 +747,6 @@ static int32_t nss_dp_probe(struct platf
+@@ -861,7 +805,6 @@ static int32_t nss_dp_probe(struct platf
 	struct device_node *np = pdev->dev.of_node;
 	struct nss_gmac_hal_platform_data gmac_hal_pdata;
 	int32_t ret = 0;
@ -149,7 +149,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 #if defined(NSS_DP_PPE_SUPPORT)
 	uint32_t vsi_id;
 	fal_port_t port_id;
-@@ -880,22 +823,14 @@ static int32_t nss_dp_probe(struct platf
+@@ -940,22 +883,16 @@ static int32_t nss_dp_probe(struct platf
 
 	dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
 
@ -161,20 +161,23 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 -		}
 -		snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
 -				dp_priv->miibus->id, dp_priv->phy_mdio_addr);
-
 +	if (dp_priv->phy_node) {
- 		SET_NETDEV_DEV(netdev, &pdev->dev);
 
 -		dp_priv->phydev = phy_connect(netdev, phy_id,
 -				&nss_dp_adjust_link,
 -				dp_priv->phy_mii_type);
 -		if (IS_ERR(dp_priv->phydev)) {
 -			netdev_dbg(netdev, "failed to connect to phy device\n");
+-			goto phy_setup_fail;
+-		}
 +		dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node,
-+		                                 &nss_dp_adjust_link, 0,
-+		                                 dp_priv->phy_mii_type);
+		        &nss_dp_adjust_link, 0,
+		        dp_priv->phy_mii_type);
 +		if (!(dp_priv->phydev)) {
 +			netdev_err(netdev, "failed to connect to phy device\n");
- 			goto phy_setup_fail;
- 		}
+ 			goto phy_setup_fail;
+ 		}
+ 		phy_attached_info(dp_priv->phydev);
 	}
+ 
+ #if defined(NSS_DP_PPE_SUPPORT)
--- a/package/qca/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch
+++ b/package/qca/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch
@ -15,7 +15,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>

 --- a/nss_dp_main.c
 +++ b/nss_dp_main.c
-@@ -746,18 +746,29 @@ static int32_t nss_dp_probe(struct platf
+@@ -804,18 +804,29 @@ static int32_t nss_dp_probe(struct platf
 	struct nss_dp_dev *dp_priv;
 	struct device_node *np = pdev->dev.of_node;
 	struct nss_gmac_hal_platform_data gmac_hal_pdata;
--- a/package/qca/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch
+++ b/package/qca/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch
@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 #define NSS_DP_SWITCH_ID		0
 #define NSS_DP_SW_ETHTYPE_PID		0 /* PPE ethtype profile ID for slow protocols */
-@@ -521,7 +523,76 @@ static struct notifier_block *nss_dp_sw_
+@@ -534,7 +536,76 @@ static struct notifier_block *nss_dp_sw_
 
 #else
 
--- a/package/qca/qca-nss-dp/patches/0010-nss-dp-add-vlan-if.patch
+++ b/package/qca/qca-nss-dp/patches/0010-nss-dp-add-vlan-if.patch
@ -0,0 +1,10 @@
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -18,6 +18,7 @@
+ 
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+#include <linux/if_vlan.h>
+ #include <linux/version.h>
+ #include <linux/of.h>
+ #include <linux/of_net.h>
--- a/package/qca/qca-nss-dp/patches/0011-01-edma_v1-rework-hw_reset-logic-to-permit-rmmod-and-in.patch
+++ b/package/qca/qca-nss-dp/patches/0011-01-edma_v1-rework-hw_reset-logic-to-permit-rmmod-and-in.patch
@ -0,0 +1,43 @@
+From c318c90b824c59539bf2e33618e381293398616c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 15:02:49 +0200
+Subject: [PATCH 1/6] edma_v1: rework hw_reset logic to permit rmmod and insmod
+
+Rework hw_reset logic for edma v1 to permit rmmod and insmod by using
+get_exclusive_released variant (assuming the reset control was released)
+and manually acquire and release it.
+
+This permits rmmod and insmod without triggering warning or receiving
+-EBUSY errors.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ hal/dp_ops/edma_dp/edma_v1/edma_cfg.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
+++ b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
+@@ -719,18 +719,22 @@ int edma_hw_reset(struct edma_hw *ehw)
+ 	struct reset_control *rst;
+ 	struct platform_device *pdev = ehw->pdev;
+ 
+-	rst = devm_reset_control_get(&pdev->dev, EDMA_HW_RESET_ID);
+	rst = devm_reset_control_get_exclusive_released(&pdev->dev, EDMA_HW_RESET_ID);
+ 	if (IS_ERR(rst)) {
+ 		pr_warn("DTS Node: %s does not exist\n", EDMA_HW_RESET_ID);
+ 		return -EINVAL;
+ 	}
+ 
+	reset_control_acquire(rst);
+
+ 	reset_control_assert(rst);
+ 	udelay(100);
+ 
+ 	reset_control_deassert(rst);
+ 	udelay(100);
+ 
+	reset_control_release(rst);
+
+ 	pr_info("EDMA HW Reset completed succesfully\n");
+ 
+ 	return 0;
--- a/package/qca/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch
+++ b/package/qca/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch
@ -0,0 +1,59 @@
+From 079bfe441b274a8c06474be82e4ccc88599a5e0e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:08:46 +0200
+Subject: [PATCH 2/6] nss_dp_switchdev: correctly unregister notifier on
+ dp_remove
+
+Correctly unregister notifier on dp_remove to fix kernel panic on system
+reboot.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ include/nss_dp_dev.h |  1 +
+ nss_dp_main.c        |  4 ++++
+ nss_dp_switchdev.c   | 13 +++++++++++++
+ 3 files changed, 18 insertions(+)
+
+--- a/include/nss_dp_dev.h
+++ b/include/nss_dp_dev.h
+@@ -349,6 +349,7 @@ void nss_dp_set_ethtool_ops(struct net_d
+  */
+ #ifdef CONFIG_NET_SWITCHDEV
+ void nss_dp_switchdev_setup(struct net_device *dev);
+void nss_dp_switchdev_remove(struct net_device *dev);
+ bool nss_dp_is_phy_dev(struct net_device *dev);
+ #endif
+ 
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -970,6 +970,10 @@ static int nss_dp_remove(struct platform
+ 		if (!dp_priv)
+ 			continue;
+ 
+		#ifdef CONFIG_NET_SWITCHDEV
+			nss_dp_switchdev_remove(dp_priv->netdev);
+		#endif
+
+ 		dp_ops = dp_priv->data_plane_ops;
+ 		hal_ops = dp_priv->gmac_hal_ops;
+ 
+--- a/nss_dp_switchdev.c
+++ b/nss_dp_switchdev.c
+@@ -648,4 +648,17 @@ void nss_dp_switchdev_setup(struct net_d
+ 
+ 	switch_init_done = true;
+ }
+
+void nss_dp_switchdev_remove(struct net_device *dev)
+{
+	if (!switch_init_done)
+		return;
+
+	if (nss_dp_sw_ev_nb)
+		unregister_switchdev_notifier(nss_dp_sw_ev_nb);
+
+	unregister_switchdev_blocking_notifier(&nss_dp_switchdev_notifier);
+
+	switch_init_done = false;
+}
+ #endif
--- a/package/qca/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch
+++ b/package/qca/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch
@ -0,0 +1,35 @@
+From ab7b1a361d51157118e1a61ce6530a59bcef4b61 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:10:09 +0200
+Subject: [PATCH 3/6] nss_dp_main: swap dp_exit function call
+
+First unregister nss_dp platform devices then cleanup the HAL.
+
+This is to fix kernel panic by cleaning data that needs to be used by
+platform driver unregister functions.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -1161,6 +1161,8 @@ int __init nss_dp_init(void)
+  */
+ void __exit nss_dp_exit(void)
+ {
+	platform_driver_unregister(&nss_dp_drv);
+
+ 	/*
+ 	 * TODO Move this to soc_ops
+ 	 */
+@@ -1168,8 +1170,6 @@ void __exit nss_dp_exit(void)
+ 		nss_dp_hal_cleanup();
+ 		dp_global_ctx.common_init_done = false;
+ 	}
+-
+-	platform_driver_unregister(&nss_dp_drv);
+ }
+ 
+ module_init(nss_dp_init);
--- a/package/qca/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch
+++ b/package/qca/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch
@ -0,0 +1,35 @@
+From 33dd3aa6d0f9cd240d63f53a49157ae44ebccf87 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:12:11 +0200
+Subject: [PATCH 4/6] nss_dp_main: call unregister_netdev first in dp_remove
+ and carrifer_off
+
+In dp_remove move unregister_netdev up before calling exit and deinit
+and first call netif_carrier_off to stop any traffic from happening and
+prevent kernel panics for napi in the middle of transfer.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -977,6 +977,9 @@ static int nss_dp_remove(struct platform
+ 		dp_ops = dp_priv->data_plane_ops;
+ 		hal_ops = dp_priv->gmac_hal_ops;
+ 
+		netif_carrier_off(dp_priv->netdev);
+		unregister_netdev(dp_priv->netdev);
+
+ 		if (dp_priv->phydev)
+ 			phy_disconnect(dp_priv->phydev);
+ 
+@@ -988,7 +991,6 @@ static int nss_dp_remove(struct platform
+ #endif
+ 		hal_ops->exit(dp_priv->gmac_hal_ctx);
+ 		dp_ops->deinit(dp_priv->dpc);
+-		unregister_netdev(dp_priv->netdev);
+ 		free_netdev(dp_priv->netdev);
+ 		dp_global_ctx.nss_dp[i] = NULL;
+ 	}
--- a/package/qca/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch
+++ b/package/qca/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch
@ -0,0 +1,26 @@
+From 655b07b701271bc00952fe64aeb14f993a48a50e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:17:36 +0200
+Subject: [PATCH 5/6] nss_dp_main: use phy_detach instead of disconnect in
+ dp_remove
+
+Use phy_detach instead of disconnect in dp_remove. On Module remove, phy
+are already disconnected but they need to be detached to be correctly
+reattached later with an insmod.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -981,7 +981,7 @@ static int nss_dp_remove(struct platform
+ 		unregister_netdev(dp_priv->netdev);
+ 
+ 		if (dp_priv->phydev)
+-			phy_disconnect(dp_priv->phydev);
+			phy_detach(dp_priv->phydev);
+ 
+ #if defined(NSS_DP_PPE_SUPPORT)
+ 		/*
--- a/package/qca/qca-nss-dp/patches/0011-06-edma_v1-skip-edma_disable_port-in-edma_cleanup-subse.patch
+++ b/package/qca/qca-nss-dp/patches/0011-06-edma_v1-skip-edma_disable_port-in-edma_cleanup-subse.patch
@ -0,0 +1,37 @@
+From c7c59c6097d94dbab8fc68dae798017bdbc5b3b9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:22:32 +0200
+Subject: [PATCH 6/6] edma_v1: skip edma_disable_port in edma_cleanup
+ subsequent run
+
+Skip edma_disable_port in edma_cleanup subsequent run as it will cause
+the kernel panic as the regs are already freed by previous run of
+edma_cleanup. It's use it's not clear but the call is already done in
+the first run of edma_cleanup. Maybe an oversight never dropped?
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
+@@ -326,9 +326,15 @@ void edma_cleanup(bool is_dp_override)
+ 		 * Disable EDMA only at module exit time, since NSS firmware
+ 		 * depends on this setting.
+ 		 */
+-		if (!is_dp_override) {
+-			edma_disable_port();
+-		}
+		/* This call will make the kernel panic as reg used by
+		 * edma_disable_port are already freed by previous call of
+		 * edma_cleanup. Logic is not clear of WHY this is called.
+		 * Keep this here for reference if someone EVER wants
+		 * to investigate.
+		 */
+		// if (!is_dp_override) {
+		// 	edma_disable_port();
+		// }
+ 		return;
+ 	}
+ 
--- a/package/qca/qca-nss-dp/patches/0012-01-WiP-syn-gmac-use-standard-DMA-api.patch
+++ b/package/qca/qca-nss-dp/patches/0012-01-WiP-syn-gmac-use-standard-DMA-api.patch
@ -0,0 +1,240 @@
+From 5ad8cf24897ff903112967a9662cb13ed4cbbf57 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Mon, 22 Apr 2024 21:47:58 +0800
+Subject: [PATCH 1/2] WiP: syn-gmac: use standard DMA api
+
+Signed-off-by: hzy <hzyitc@outlook.com>
+---
+ hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c | 14 ++++++--
+ hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c |  2 ++
+ hal/dp_ops/syn_gmac_dp/syn_dp_rx.c     | 47 +++++++++++++-------------
+ hal/dp_ops/syn_gmac_dp/syn_dp_tx.c     | 23 ++++---------
+ 4 files changed, 42 insertions(+), 44 deletions(-)
+
+diff --git a/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c b/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c
+index 8cbbcaaf..1c9006c7 100644
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c
+++ b/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c
+@@ -26,6 +26,7 @@ static int syn_dp_cfg_rx_setup_desc_queue(struct syn_dp_info *dev_info)
+ {
+ 	struct syn_dp_info_rx *rx_info = &dev_info->dp_info_rx;
+ 	struct dma_desc_rx *first_desc = NULL;
+	dma_addr_t dma_addr;
+ 	struct net_device *netdev = rx_info->netdev;
+ 
+ 	netdev_dbg(netdev, "Total size of memory required for Rx Descriptors in Ring Mode = %u\n", (uint32_t)((sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE)));
+@@ -33,13 +34,15 @@ static int syn_dp_cfg_rx_setup_desc_queue(struct syn_dp_info *dev_info)
+ 	/*
+ 	 * Allocate cacheable descriptors for Rx
+ 	 */
+-	first_desc = kzalloc(sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE, GFP_KERNEL);
+	first_desc = dma_alloc_coherent(rx_info->dev,
+					sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE,
+					&dma_addr, GFP_KERNEL);
+ 	if (!first_desc) {
+ 		netdev_dbg(netdev, "Error in Rx Descriptor Memory allocation in Ring mode\n");
+ 		return -ENOMEM;
+ 	}
+ 
+-	dev_info->rx_desc_dma_addr = (dma_addr_t)virt_to_phys(first_desc);
+	dev_info->rx_desc_dma_addr = dma_addr;
+ 	rx_info->rx_desc = first_desc;
+ 	syn_dp_gmac_rx_desc_init_ring(rx_info->rx_desc, SYN_DP_RX_DESC_SIZE);
+ 
+@@ -98,6 +101,10 @@ void syn_dp_cfg_rx_cleanup_rings(struct syn_dp_info *dev_info)
+ 	for (i = 0; i < rx_info->busy_rx_desc_cnt; i++) {
+ 		rx_skb_index = (rx_skb_index + i) & SYN_DP_RX_DESC_MAX_INDEX;
+ 		rxdesc = rx_info->rx_desc;
+
+		dma_unmap_single(rx_info->dev, rxdesc->buffer1,
+				 rxdesc->length, DMA_FROM_DEVICE);
+
+ 		skb = rx_info->rx_buf_pool[rx_skb_index].skb;
+ 		if (unlikely(skb != NULL)) {
+ 			dev_kfree_skb_any(skb);
+@@ -105,7 +112,8 @@ void syn_dp_cfg_rx_cleanup_rings(struct syn_dp_info *dev_info)
+ 		}
+ 	}
+ 
+-	kfree(rx_info->rx_desc);
+	dma_free_coherent(rx_info->dev, (sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE),
+			  rx_info->rx_desc, dev_info->rx_desc_dma_addr);
+ 	rx_info->rx_desc = NULL;
+ 	dev_info->rx_desc_dma_addr = (dma_addr_t)0;
+ }
+diff --git a/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c b/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c
+index bf5e19a0..284e8880 100644
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c
+++ b/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c
+@@ -91,6 +91,8 @@ void syn_dp_cfg_tx_cleanup_rings(struct syn_dp_info *dev_info)
+ 		tx_skb_index = syn_dp_tx_inc_index(tx_skb_index, i);
+ 		txdesc = tx_info->tx_desc;
+ 
+		dma_unmap_single(tx_info->dev, txdesc->buffer1, txdesc->length, DMA_TO_DEVICE);
+
+ 		skb = tx_info->tx_buf_pool[tx_skb_index].skb;
+ 		if (unlikely(skb != NULL)) {
+ 			dev_kfree_skb_any(skb);
+diff --git a/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c b/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c
+index 1ddeb7d6..1798d4e7 100644
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c
+++ b/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c
+@@ -73,16 +73,6 @@ static inline void syn_dp_rx_refill_one_desc(struct dma_desc_rx *rx_desc,
+  */
+ static inline void syn_dp_rx_inval_and_flush(struct syn_dp_info_rx *rx_info, uint32_t start, uint32_t end)
+ {
+-	/*
+-	 * Batched flush and invalidation of the rx descriptors
+-	 */
+-	if (end > start) {
+-		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+-	} else {
+-		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[SYN_DP_RX_DESC_MAX_INDEX] + sizeof(struct dma_desc_rx));
+-		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[0], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+-	}
+-
+ 	dsb(st);
+ }
+ 
+@@ -124,15 +114,19 @@ int syn_dp_rx_refill_page_mode(struct syn_dp_info_rx *rx_info)
+ 			break;
+ 		}
+ 
+		skb_fill_page_desc(skb, 0, pg, 0, PAGE_SIZE);
+
+ 		/*
+ 		 * Get virtual address of allocated page.
+ 		 */
+ 		page_addr = page_address(pg);
+-		dma_addr = (dma_addr_t)virt_to_phys(page_addr);
+-
+-		skb_fill_page_desc(skb, 0, pg, 0, PAGE_SIZE);
+		dma_addr  = dma_map_page(rx_info->dev, pg, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+		if (unlikely(dma_mapping_error(rx_info->dev, dma_addr))) {
+			dev_kfree_skb(skb);
+			netdev_dbg(netdev, "DMA mapping failed for empty buffer\n");
+			break;
+		}
+ 
+-		dmac_inv_range_no_dsb(page_addr, (page_addr + PAGE_SIZE));
+ 		rx_refill_idx = rx_info->rx_refill_idx;
+ 		rx_desc = rx_info->rx_desc + rx_refill_idx;
+ 
+@@ -181,8 +175,15 @@ int syn_dp_rx_refill(struct syn_dp_info_rx *rx_info)
+ 
+ 		skb_reserve(skb, SYN_DP_SKB_HEADROOM + NET_IP_ALIGN);
+ 
+-		dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+-		dmac_inv_range_no_dsb((void *)skb->data, (void *)(skb->data + inval_len));
+		dma_addr = dma_map_single(rx_info->dev, skb->data,
+		                          inval_len,
+		                          DMA_FROM_DEVICE);
+		if (unlikely(dma_mapping_error(rx_info->dev, dma_addr))) {
+			dev_kfree_skb(skb);
+			netdev_dbg(netdev, "DMA mapping failed for empty buffer\n");
+			break;
+		}
+
+ 		rx_refill_idx = rx_info->rx_refill_idx;
+ 		rx_desc = rx_info->rx_desc + rx_refill_idx;
+ 
+@@ -407,12 +408,6 @@ int syn_dp_rx(struct syn_dp_info_rx *rx_info, int budget)
+ 	 * this code is executing.
+ 	 */
+ 	end = syn_dp_rx_inc_index(rx_info->rx_idx, busy);
+-	if (end > start) {
+-		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+-	} else {
+-		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[SYN_DP_RX_DESC_MAX_INDEX] + sizeof(struct dma_desc_rx));
+-		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[0], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+-	}
+ 
+ 	dsb(st);
+ 
+@@ -439,8 +434,12 @@ int syn_dp_rx(struct syn_dp_info_rx *rx_info, int budget)
+ 		 * speculative prefetch by CPU may have occurred.
+ 		 */
+ 		frame_length = syn_dp_gmac_get_rx_desc_frame_length(status);
+-		dmac_inv_range((void *)rx_buf->map_addr_virt,
+-			(void *)(((uint8_t *)rx_buf->map_addr_virt) + frame_length));
+		if (likely(!rx_info->page_mode))
+			dma_unmap_single(rx_info->dev, rx_desc->buffer1,
+			                 rx_info->alloc_buf_len, DMA_FROM_DEVICE);
+		else
+			dma_unmap_page(rx_info->dev, rx_desc->buffer1,
+			               PAGE_SIZE, DMA_FROM_DEVICE);
+ 		prefetch((void *)rx_buf->map_addr_virt);
+ 
+ 		rx_next_idx = syn_dp_rx_inc_index(rx_idx, 1);
+diff --git a/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c b/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c
+index c97e252b..6d4adb3f 100644
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c
+++ b/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c
+@@ -104,9 +104,7 @@ static inline struct dma_desc_tx *syn_dp_tx_process_nr_frags(struct syn_dp_info_
+ 		BUG_ON(!length);
+ #endif
+ 
+-		dma_addr = (dma_addr_t)virt_to_phys(frag_addr);
+-
+-		dmac_clean_range_no_dsb(frag_addr, frag_addr + length);
+		dma_addr = dma_map_single(tx_info->dev, frag_addr, length, DMA_TO_DEVICE);
+ 
+ 		*total_length += length;
+ 		tx_desc = syn_dp_tx_set_desc_sg(tx_info, dma_addr, length, DESC_OWN_BY_DMA);
+@@ -150,8 +148,7 @@ int syn_dp_tx_nr_frags(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+ 	/*
+ 	 * Flush the dma for non-paged skb data
+ 	 */
+-	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+-	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + length));
+	dma_addr = dma_map_single(tx_info->dev, skb->data, length, DMA_TO_DEVICE);
+ 
+ 	total_len = length;
+ 
+@@ -256,12 +253,7 @@ int syn_dp_tx_frag_list(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+ 		return NETDEV_TX_BUSY;
+ 	}
+ 
+-	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+-
+-	/*
+-	 * Flush the data area of the head skb
+-	 */
+-	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + length));
+	dma_addr = dma_map_single(tx_info->dev, skb->data, length, DMA_TO_DEVICE);
+ 
+ 	total_len = length;
+ 
+@@ -290,9 +282,7 @@ int syn_dp_tx_frag_list(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+ 		BUG_ON(!length);
+ #endif
+ 
+-		dma_addr = (dma_addr_t)virt_to_phys(iter_skb->data);
+-
+-		dmac_clean_range_no_dsb((void *)iter_skb->data, (void *)(iter_skb->data + length));
+		dma_addr = dma_map_single(tx_info->dev, iter_skb->data, length, DMA_TO_DEVICE);
+ 
+ 		total_len += length;
+ 
+@@ -445,6 +435,7 @@ int syn_dp_tx_complete(struct syn_dp_info_tx *tx_info, int budget)
+ 			break;
+ 		}
+ 
+		dma_unmap_single(tx_info->dev, desc->buffer1, desc->length, DMA_TO_DEVICE);
+ 
+ 		if (likely(status & DESC_TX_LAST)) {
+ 			tx_skb_index = syn_dp_tx_comp_index_get(tx_info);
+@@ -571,9 +562,7 @@ int syn_dp_tx(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+ 		return NETDEV_TX_BUSY;
+ 	}
+ 
+-	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+-
+-	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + skb->len));
+	dma_addr = dma_map_single(tx_info->dev, skb->data, skb->len, DMA_TO_DEVICE);
+ 
+ 	/*
+ 	 * Queue packet to the GMAC rings
+-- 
+2.40.1
+
--- a/package/qca/qca-nss-dp/patches/0012-02-ipq50xx-use-corrent-scm-function-to-write-tcsr.patch
+++ b/package/qca/qca-nss-dp/patches/0012-02-ipq50xx-use-corrent-scm-function-to-write-tcsr.patch
@ -0,0 +1,41 @@
+From ba430b1a512dc1972807a1dd5a8d31a78ac572ff Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Mon, 22 Apr 2024 21:49:18 +0800
+Subject: [PATCH 2/2] ipq50xx: use corrent scm function to write tcsr
+
+Signed-off-by: hzy <hzyitc@outlook.com>
+---
+ hal/soc_ops/ipq50xx/nss_ipq50xx.c | 9 ++-------
+ 1 file changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/hal/soc_ops/ipq50xx/nss_ipq50xx.c b/hal/soc_ops/ipq50xx/nss_ipq50xx.c
+index 3e4491c0..e56de1cc 100644
+--- a/hal/soc_ops/ipq50xx/nss_ipq50xx.c
+++ b/hal/soc_ops/ipq50xx/nss_ipq50xx.c
+@@ -18,7 +18,7 @@
+ 
+ #include <linux/of.h>
+ #include <linux/ioport.h>
+-#include <linux/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_scm.h>
+ #include "nss_dp_hal.h"
+ 
+ /*
+@@ -78,13 +78,8 @@ static void nss_dp_hal_tcsr_set(void)
+ 	 * If TZ is not enabled, we can write to the register directly.
+ 	 */
+ 	if (qcom_scm_is_available()) {
+-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+-		err = qcom_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+		err = qcom_scm_io_writel((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+ 						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+-#else
+-		err = qti_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+-						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+-#endif
+ 		if (err) {
+ 			pr_err("%s: SCM TCSR write error: %d\n", __func__, err);
+ 		}
+-- 
+2.40.1
+
--- a/package/qca/qca-nss-dp/patches/0013-nss_dp_main-support-fixed-link.patch
+++ b/package/qca/qca-nss-dp/patches/0013-nss_dp_main-support-fixed-link.patch
@ -0,0 +1,41 @@
+From 309a1a330ccaa103a7648e944d97a0032116b338 Mon Sep 17 00:00:00 2001
+From: hzy <hzyitc@outlook.com>
+Date: Mon, 22 Apr 2024 21:50:39 +0800
+Subject: [PATCH] nss_dp_main: support fixed-link
+
+Signed-off-by: hzy <hzyitc@outlook.com>
+---
+ nss_dp_main.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/nss_dp_main.c b/nss_dp_main.c
+index 9a09edd5..204063bf 100644
+--- a/nss_dp_main.c
+++ b/nss_dp_main.c
+@@ -619,11 +619,20 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np,
+ 	}
+ 
+ 	dp_priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
+-	if (!dp_priv->phy_node) {
+-		pr_err("%s: error parsing phy-handle\n", np->name);
+-		return -EFAULT;
+	if(!dp_priv->phy_node) {
+		if(of_phy_is_fixed_link(np)) {
+			int ret = of_phy_register_fixed_link(np);
+			if(ret < 0) {
+				pr_err("%s: fail to register fixed-link: %d\n", np->name, ret);
+				return -EFAULT;
+			}
+		}
+		dp_priv->phy_node = of_node_get(np);
+ 	}
+ 
+	if(!dp_priv->phy_node)
+		pr_err("%s: no phy-handle or fixed-link found\n", np->name);
+
+ 	if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) {
+ 		pr_err("%s: error reading mactype\n", np->name);
+ 		return -EFAULT;
+-- 
+2.40.1
+
--- a/package/qca/qca-nss-dp/patches/0014-nss_dp-fix-linux-6.6-support.patch
+++ b/package/qca/qca-nss-dp/patches/0014-nss_dp-fix-linux-6.6-support.patch
@ -0,0 +1,17 @@
+--- a/hal/soc_ops/ipq50xx/nss_ipq50xx.c
+++ b/hal/soc_ops/ipq50xx/nss_ipq50xx.c
+@@ -18,7 +18,14 @@
+ 
+ #include <linux/of.h>
+ #include <linux/ioport.h>
+#include <linux/version.h>
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 2, 0))
+ #include <linux/firmware/qcom/qcom_scm.h>
+#else
+#include <linux/qcom_scm.h>
+#endif
+
+ #include "nss_dp_hal.h"
+ 
+ /*
--- a/package/qca/qca-nss-drv/Makefile
+++ b/package/qca/qca-nss-drv/Makefile
@ -101,6 +101,9 @@ ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x")
 else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx")
    SOC="ipq60xx_64"
 	subtarget:=$(CONFIG_TARGET_SUBTARGET)
+else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx")
+    SOC="ipq50xx_64"
+	subtarget:=$(CONFIG_TARGET_SUBTARGET)
 endif

 define Build/InstallDev
--- a/package/qca/qca-ssdk/Makefile
+++ b/package/qca/qca-ssdk/Makefile
@ -1,15 +1,16 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=qca-ssdk
-PKG_RELEASE:=1
+PKG_RELEASE:=3

 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-06-06
-PKG_SOURCE_VERSION:=74caf88aa3b6793c300f676e4fb1c62da7507be9
-PKG_MIRROR_HASH:=6bdb90919b773f5fb432c8b374c9419feac32ba6583ad82dfec5e41628a32dd9
+PKG_SOURCE_DATE:=2024-06-13
+PKG_SOURCE_VERSION:=c451136ba69d51d60f770365b6d6d60ff2801998
+PKG_MIRROR_HASH:=dad29c6fa3887782e57cbe169f3e2ee739a4c62dc09ec88eeab1109214cd4820

 PKG_FLAGS:=nonshared
+PKG_BUILD_PARALLEL:=1
 PKG_BUILD_FLAGS:=no-lto

 include $(INCLUDE_DIR)/kernel.mk
@ -21,7 +22,7 @@ define KernelPackage/qca-ssdk
  SUBMENU:=Network Devices
  TITLE:=Qualcom SSDK switch driver
  DEPENDS:=@(TARGET_qualcommax)
-  FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko
+  FILES:=$(PKG_BUILD_DIR)/qca-ssdk.ko
  AUTOLOAD:=$(call AutoLoad,30,qca-ssdk)
 endef

@ -31,7 +32,7 @@ endef

 GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/')

-LNX_CONFIG_OPTS = LNX_MAKEOPTS='$(KERNEL_MAKEOPTS)' MODULE_TYPE=KSLIB modules
+LNX_CONFIG_OPTS = LNX_MAKEOPTS='$(KERNEL_MAKEOPTS)' PRJ_PATH=$(PKG_BUILD_DIR) MODULE_TYPE=KSLIB modules

 MAKE_FLAGS+= \
 	TARGET_NAME=$(CONFIG_TARGET_NAME) \
@ -42,16 +43,32 @@ MAKE_FLAGS+= \
 	ARCH=$(LINUX_KARCH) \
 	TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \
 	GCC_VERSION=$(GCC_VERSION) \
-	EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include \
+	EXTRA_CFLAGS="-fno-stack-protector -I$(STAGING_DIR)/usr/include" \
+	SoC=$(CONFIG_TARGET_SUBTARGET) \
+	SHELL="$(BASH)" \
 	PTP_FEATURE=disable SWCONFIG_FEATURE=disable \
+	IN_MP_PHY=FALSE \
+	ISISC_ENABLE=disable MHT_ENABLE=disable \
+	IN_QCA803X_PHY=FALSE IN_QCA808X_PHY=FALSE \
+	IN_MALIBU_PHY=FALSE \
 	$(LNX_CONFIG_OPTS)

+ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x")
+    MAKE_FLAGS+= CHIP_TYPE=HPPE
+endif
+
 ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx")
    MAKE_FLAGS+= CHIP_TYPE=CPPE
-else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x")
-    MAKE_FLAGS+= CHIP_TYPE=HPPE
 endif

+ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx")
+    MAKE_FLAGS+= CHIP_TYPE=MP
+endif
+
+define Build/Compile
+	+$(MAKE) $(PKG_JOBS) $(MAKE_FLAGS) -C $(PKG_BUILD_DIR) $(LNX_CONFIG_OPTS)
+endef
+
 define Build/InstallDev
 	$(INSTALL_DIR) $(1)/usr/include/qca-ssdk
 	$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api
--- a/package/qca/qca-ssdk/patches/0001-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch
+++ b/package/qca/qca-ssdk/patches/0001-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch
@ -1,67 +0,0 @@
-From cdcafa28c857e4d04c9210feb54dc84e427061fe Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 11 Jan 2022 00:28:42 +0100
-Subject: [PATCH 1/2] qca807x: add a LED quirk for Xiaomi AX9000
-
-Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that
-are connected to QCA8075, and that LED is connected to the 100M LED pin.
-
-So, by default it will only work when in 10 or 100Mbit mode, this is quite
-annoying and makes no sense(If they have connected it to the 1000Mbit LED
-pin then it would have worked for 10/100 by default as well).
-
-So, to solve this add a check for system compatible as we cant parse if
-from DTS in any other way and set the 100M LED to blink on 1000Base-T
-as well.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
---
- include/hsl/phy/malibu_phy.h |  2 ++
- src/hsl/phy/malibu_phy.c     | 11 +++++++++++
- 2 files changed, 13 insertions(+)
-
--- a/include/hsl/phy/malibu_phy.h
-+++ b/include/hsl/phy/malibu_phy.h
-@@ -94,6 +94,7 @@ extern "C"
- #define MALIBU_DAC_CTRL_MASK  0x380
- #define MALIBU_DAC_CTRL_VALUE  0x280
- #define MALIBU_LED_1000_CTRL1_100_10_MASK  0x30
-+#define MALIBU_LED_100_CTRL1_1000_MASK  0x40
- 
- #define MALIBU_PHY_EEE_ADV_100M 0x0002
- #define MALIBU_PHY_EEE_ADV_1000M 0x0004
-@@ -118,6 +119,7 @@ extern "C"
- #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH       0x802d
- #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW       0x802e
- #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER       0x802f
-+#define MALIBU_PHY_MMD7_LED_100_CTRL1       0x8074
- #define MALIBU_PHY_MMD7_LED_1000_CTRL1       0x8076
- 
- 
--- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -15,6 +15,8 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
- 
-+#include <linux/of.h>
-+
- #include "sw.h"
- #include "fal_port_ctrl.h"
- #include "hsl_api.h"
-@@ -2716,6 +2718,15 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
- 			led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK;
- 			malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
- 				MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status);
-+			if (of_machine_is_compatible("xiaomi,ax9000")) {
-+				/* add 1000M link LED behavior for Xiaomi AX9000 */
-+				led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
-+					MALIBU_PHY_MMD7_LED_100_CTRL1);
-+				led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK;
-+				led_status |= MALIBU_LED_100_CTRL1_1000_MASK;
-+				malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
-+					MALIBU_PHY_MMD7_LED_100_CTRL1, led_status);
-+			}
- 			/*disable Extended next page*/
- 			phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT);
- 			phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN;
--- a/package/qca/qca-ssdk/patches/0002-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch
+++ b/package/qca/qca-ssdk/patches/0002-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch
@ -1,29 +0,0 @@
-From a750e569aeb4f7b454dbde18cd6d0f2bb1875dfa Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 26 Jan 2022 14:47:33 +0100
-Subject: [PATCH 2/2] qca807x: add a LED quirk for Xiaomi AX3600
-
-AX3600 requires the same LED quirk so that PHY LED-s will blink even
-once Linux resets the PHY.
-
-So, just check for its compatible.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
---
- src/hsl/phy/malibu_phy.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
--- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -2718,8 +2718,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
- 			led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK;
- 			malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
- 				MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status);
-			if (of_machine_is_compatible("xiaomi,ax9000")) {
-				/* add 1000M link LED behavior for Xiaomi AX9000 */
-+			/* add 1000M link LED behavior for Xiaomi boards */
-+			if (of_machine_is_compatible("xiaomi,ax9000") ||
-+			    of_machine_is_compatible("xiaomi,ax3600")) {
- 				led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
- 					MALIBU_PHY_MMD7_LED_100_CTRL1);
- 				led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK;
--- a/package/qca/qca-ssdk/patches/0003-Revert-qca-ssdk-enable-invoking-fdb-del-function-for.patch
+++ b/package/qca/qca-ssdk/patches/0003-Revert-qca-ssdk-enable-invoking-fdb-del-function-for.patch
@ -0,0 +1,30 @@
+From 73c0992a36bc13e9bb373f98ba246dfc1e29a393 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 7 Nov 2023 14:21:43 +0100
+Subject: [PATCH 3/3] Revert "[qca-ssdk]: enable invoking fdb del function for
+ kernel6.1"
+
+This reverts commit a86765ee6a87145f64344f4872cfe8c5e629dd62.
+
+Upstream kernel does not have this call present at all, we currently
+also dont use it, so revert the commit enabling it.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ src/ref/ref_acl.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/src/ref/ref_acl.c
+++ b/src/ref/ref_acl.c
+@@ -229,7 +229,11 @@ _ref_acl_mac_entry_create_rule(a_uint32_
+ 		eth_dev = dev_get_by_name(&init_net, entry->ifname);
+ 		if (eth_dev)
+ 		{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))
+			// TODO: replace with corresponding ver
+#else
+ 			br_fdb_delete_by_netdev(eth_dev, entry->src_mac.uc, 0);
+#endif
+ 			dev_put(eth_dev);
+ 		}
+ 	}
--- a/package/qca/qca-ssdk/patches/0004-SSDK-set-OF-node-for-the-SFP-PHY.patch
+++ b/package/qca/qca-ssdk/patches/0004-SSDK-set-OF-node-for-the-SFP-PHY.patch
@ -0,0 +1,94 @@
+From 00d3c54c611143f57b632e4cd3b42b0a94d82307 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 25 Jun 2023 11:24:09 +0200
+Subject: [PATCH 3/3] SSDK: set OF node for the SFP PHY
+
+Currently, SSDK is creating a fake SFP PHY which has no OF node populated,
+thus making it impossible to pass it to NSS-DP so port can actually work.
+
+We eliminated QCA-s connecting of the PHY by manually creating a string
+and then matching by name and instead only support passing the PHY as
+phandle via phy-handle.
+
+So, lets just use the switch port node to which the SFP is connected to
+anyway and set it as the PHY device OF node so we can pass it to NSS-DP.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ include/hsl/phy/hsl_phy.h |  6 ++++++
+ src/hsl/phy/hsl_phy.c     | 14 ++++++++++++++
+ src/hsl/phy/sfp_phy.c     |  7 +++++++
+ src/init/ssdk_dts.c       |  7 +++++++
+ 4 files changed, 34 insertions(+)
+
+--- a/include/hsl/phy/hsl_phy.h
+++ b/include/hsl/phy/hsl_phy.h
+@@ -584,6 +584,7 @@ typedef struct {
+ 	a_bool_t port_link_status[SW_MAX_NR_PORT];
+ 	a_uint32_t port_mode[SW_MAX_NR_PORT];
+ 	a_uint32_t combo_phy_type[SW_MAX_NR_PORT];
+	struct device_node *port_node[SW_MAX_NR_PORT];
+ } phy_info_t;
+ /*qca808x_end*/
+ #define MALIBU5PORT_PHY         0x004DD0B1
+@@ -1038,3 +1039,8 @@ hsl_phydev_eee_update(a_uint32_t dev_id,
+ #endif				/* __cplusplus */
+ #endif				/* _HSL_PHY_H_ */
+ /*qca808x_end*/
+
+struct device_node*
+hsl_port_node_get(a_uint32_t dev_id, a_uint32_t port_id);
+void
+hsl_port_node_set(a_uint32_t dev_id, a_uint32_t port_id, struct device_node *port_node);
+--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
+@@ -3433,3 +3433,17 @@ hsl_phy_modify_debug(a_uint32_t dev_id,
+ 	return rv;
+ }
+ /*qca808x_end*/
+
+struct device_node*
+hsl_port_node_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	return phy_info[dev_id]->port_node[port_id];
+}
+
+void
+hsl_port_node_set(a_uint32_t dev_id, a_uint32_t port_id, struct device_node *port_node)
+{
+	phy_info[dev_id]->port_node[port_id] = port_node;
+
+	return;
+}
+--- a/src/hsl/phy/sfp_phy.c
+++ b/src/hsl/phy/sfp_phy.c
+@@ -335,6 +335,13 @@ int sfp_phy_device_setup(a_uint32_t dev_
+ 	phy_device_register(phydev);
+ 
+ 	phydev->priv = priv;
+	/*
+	 * Set the PHY OF node in order to be able to later connect the
+	 * fake SFP PHY by passing it as a phandle in phy-handle.
+	 */
+	phydev->mdio.dev.of_node = hsl_port_node_get(dev_id, port);
+	if (!phydev->mdio.dev.of_node)
+		return SW_NOT_FOUND;
+ #if defined(IN_PHY_I2C_MODE)
+ 	if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) {
+ 		if(phydev->drv)
+--- a/src/init/ssdk_dts.c
+++ b/src/init/ssdk_dts.c
+@@ -784,6 +784,13 @@ static sw_error_t ssdk_dt_parse_phy_info
+ 			}
+ 		}
+ 		hsl_port_feature_set(dev_id, port_id, phy_features | PHY_F_INIT);
+
+		/*
+		* Save the port node so it can be passed as the
+		* fake SFP PHY OF node in order to be able to
+		* pass the SFP phy via phy-handle
+		*/
+		hsl_port_node_set(dev_id, port_id, port_node);
+ 	}
+ 
+ 	return rv;
--- a/package/qca/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
+++ b/package/qca/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
@ -0,0 +1,135 @@
+From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Mon, 12 Feb 2024 14:23:04 +0200
+Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018
+
+When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second
+PHY port would overlap with one used by SGMII+ port. SoC has register
+to select different PCS in such case.
+
+Original code used PHY_ID for this decision, which also had other
+issues, but is no longer viable since we moved to upstream QCA807x
+driver.
+
+Introduce DT property port3_pcs_channel to allow describing this in DT.
+Default value is <2>, and for some QCA8072 designs <4> would be needed.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ include/init/ssdk_dts.h            |  2 ++
+ src/adpt/cppe/adpt_cppe_portctrl.c |  4 ++--
+ src/adpt/hppe/adpt_hppe_uniphy.c   |  7 +------
+ src/init/ssdk_dts.c                | 27 +++++++++++++++++++++++++++
+ 4 files changed, 32 insertions(+), 8 deletions(-)
+
+--- a/include/init/ssdk_dts.h
+++ b/include/init/ssdk_dts.h
+@@ -99,6 +99,7 @@ typedef struct
+ 	a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
+ 	a_uint32_t clk_mode;
+ 	a_uint32_t pcie_hw_base;
+	a_uint32_t port3_pcs_channel;
+ 	led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX];
+ } ssdk_dt_cfg;
+ 
+@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
+ struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
+ struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
+ struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id);
+ 
+ int ssdk_switch_device_num_init(void);
+ void ssdk_switch_device_num_exit(void);
+--- a/src/adpt/cppe/adpt_cppe_portctrl.c
+++ b/src/adpt/cppe/adpt_cppe_portctrl.c
+@@ -33,6 +33,7 @@
+ #include "hsl_phy.h"
+ #include "hsl_port_prop.h"
+ #include "hppe_init.h"
+#include "ssdk_dts.h"
+ #include "adpt.h"
+ #include "adpt_hppe.h"
+ #include "adpt_cppe_portctrl.h"
+@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t d
+ 		case SSDK_PHYSICAL_PORT3:
+ 		case SSDK_PHYSICAL_PORT4:
+ 			if (mode0 == PORT_WRAPPER_PSGMII) {
+-				if (hsl_port_phyid_get(dev_id,
+-					SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
+				if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
+ 					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ 						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
+ 					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
+@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
+ {
+ 	a_uint32_t i;
+ 	sw_error_t rv = SW_OK;
+-#if defined(CPPE)
+-	a_uint32_t phy_type = 0;
+-#endif
+ 
+ 	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+ 
+@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
+ 	SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
+ #if defined(CPPE)
+ 	if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
+-		phy_type = hsl_port_phyid_get(dev_id,
+-				SSDK_PHYSICAL_PORT3);
+-		if (phy_type == MALIBU2PORT_PHY) {
+		if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
+ 			SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
+ 			rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
+ 				PORT_WRAPPER_PSGMII);
+--- a/src/init/ssdk_dts.c
+++ b/src/init/ssdk_dts.c
+@@ -272,6 +272,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32
+ 	return cfg->cmnblk_clk;
+ }
+ 
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->port3_pcs_channel;
+}
+
+ #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+ static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
+ 		struct device_node *switch_node, ssdk_init_cfg *cfg)
+@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
+ 
+ 	return;
+ }
+
+static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id,
+		struct device_node *switch_node, ssdk_init_cfg *cfg)
+{
+	const __be32 *port3_pcs_channel;
+	a_uint32_t len = 0;
+
+	port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
+	if (!port3_pcs_channel) {
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
+	}
+	else {
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel =
+			be32_to_cpup(port3_pcs_channel);
+	}
+
+	return;
+}
+
+ #ifdef IN_UNIPHY
+ static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
+ {
+@@ -1354,6 +1380,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
+ 	rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
+ 	SW_RTN_ON_ERROR(rv);
+ 	ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
+	ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_interrupt(*dev_id, switch_node);
--- a/package/qca/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch
+++ b/package/qca/qca-ssdk/patches/103-hsl_phy-add-support-for-AQR114C-B0-PHY.patch
@ -0,0 +1,33 @@
+From ab3b663842f66d0ed290696cee9edb9070a36e8f Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 7 May 2024 10:37:44 +0100
+Subject: [PATCH] hsl_phy: add support for AQR114C-B0 PHY
+
+Add support for AQR114C-B0 PHY.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+---
+ include/hsl/phy/hsl_phy.h | 1 +
+ src/hsl/phy/hsl_phy.c     | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/include/hsl/phy/hsl_phy.h
+++ b/include/hsl/phy/hsl_phy.h
+@@ -613,6 +613,7 @@ typedef struct {
+ #define AQUANTIA_PHY_113C_B0    0x31c31C12
+ #define AQUANTIA_PHY_113C_B1    0x31c31C13
+ #define AQUANTIA_PHY_112C       0x03a1b792
+#define AQUANTIA_PHY_114C_B0    0x31c31c22
+ #define MVL_PHY_X3410           0x31c31DD3
+ 
+ #define PHY_805XV2              0x004DD082
+--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
+@@ -271,6 +271,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
+ 		case AQUANTIA_PHY_113C_B0:
+ 		case AQUANTIA_PHY_113C_B1:
+ 		case AQUANTIA_PHY_112C:
+		case AQUANTIA_PHY_114C_B0:
+ 		case MVL_PHY_X3410:
+ 			phytype = AQUANTIA_PHY_CHIP;
+ 			break;
--- a/package/qca/qca-ssdk/patches/111-hsl_phy-split-MP_PHY-config.patch
+++ b/package/qca/qca-ssdk/patches/111-hsl_phy-split-MP_PHY-config.patch
@ -0,0 +1,104 @@
+diff --git a/config b/config
+index 99d99dff..1f74e4f8 100644
+--- a/config
+++ b/config
+@@ -299,6 +299,7 @@ else ifeq (DESS, $(CHIP_TYPE))
+ else ifeq (MP, $(CHIP_TYPE))
+ 	IN_QCA803X_PHY=TRUE
+ 	IN_QCA808X_PHY=TRUE
+	IN_MP_PHY=TRUE
+ 	IN_SFP_PHY=TRUE
+ 	IN_SFP=TRUE
+ else ifeq (APPE, $(CHIP_TYPE))
+diff --git a/make/linux_opt.mk b/make/linux_opt.mk
+index 6936b754..66b08ef5 100644
+--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
+@@ -183,6 +183,11 @@ endif
+ ifeq (TRUE, $(IN_QCA808X_PHY))
+   MODULE_CFLAG += -DIN_QCA808X_PHY
+ endif
+
+ifeq (TRUE, $(IN_MP_PHY))
+  MODULE_CFLAG += -DIN_MP_PHY
+endif
+
+ ifeq (TRUE, $(IN_SFP_PHY))
+   MODULE_CFLAG += -DIN_SFP_PHY
+ endif
+diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
+index 2c983fff..db60fc72 100644
+--- a/src/adpt/mp/adpt_mp_portctrl.c
+++ b/src/adpt/mp/adpt_mp_portctrl.c
+@@ -92,12 +92,15 @@ static sw_error_t
+ adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
+ {
+ 	sw_error_t rv = 0;
+#ifdef IN_MP_PHY
+ 	a_uint32_t phy_addr;
+ 	hsl_phy_ops_t *phy_drv;
+#endif
+ 
+ 	ADPT_DEV_ID_CHECK(dev_id);
+ 
+ 	if (port_id == SSDK_PHYSICAL_PORT1) {
+#ifdef IN_MP_PHY
+ 		/*internal gephy reset*/
+ 		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id,
+ 				port_id));
+@@ -107,6 +110,7 @@ adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
+ 		SW_RTN_ON_ERROR (rv);
+ 		rv = phy_drv->phy_function_reset(dev_id, phy_addr, PHY_FIFO_RESET);
+ 		SW_RTN_ON_ERROR (rv);
+#endif
+ 	} else if (port_id == SSDK_PHYSICAL_PORT2) {
+ 		rv = adpt_mp_uniphy_adapter_port_reset(dev_id, port_id);
+ 	} else {
+diff --git a/src/hsl/phy/Makefile b/src/hsl/phy/Makefile
+index 68d0679f..0eae9377 100755
+--- a/src/hsl/phy/Makefile
+++ b/src/hsl/phy/Makefile
+@@ -23,7 +23,7 @@ ifeq (ISIS, $(CHIP_TYPE))
+   SRC_LIST = f1_phy.c
+ endif
+ 
+-ifeq (MP, $(CHIP_TYPE))
+ifeq (TRUE, $(IN_MP_PHY))
+   SRC_LIST = mpge_phy.c
+ ifeq (TRUE, $(IN_LED))
+   SRC_LIST += mpge_led.c
+@@ -40,12 +40,6 @@ endif
+ 
+ ifeq (ALL_CHIP, $(CHIP_TYPE))
+      SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c
+-ifneq (,$(filter MP, $(SUPPORT_CHIP)))
+-     SRC_LIST += mpge_phy.c
+-ifeq (TRUE, $(IN_LED))
+-     SRC_LIST += mpge_led.c
+-endif
+-endif
+ endif
+ 
+ ifeq (NONHK_CHIP, $(CHIP_TYPE))
+diff --git a/src/hsl/phy/hsl_phy.c b/src/hsl/phy/hsl_phy.c
+index f2cf90e2..efab2343 100644
+--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
+@@ -28,7 +28,7 @@
+ #if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
+ #include <f2_phy.h>
+ #endif
+-#ifdef MP
+#ifdef IN_MP_PHY
+ #include "mpge_phy.h"
+ #endif
+ #ifdef IN_MALIBU_PHY
+@@ -94,7 +94,7 @@ phy_driver_instance_t ssdk_phy_driver[] =
+ 	#else
+ 	{SFP_PHY_CHIP, {0}, NULL, NULL, NULL},
+ 	#endif
+-	#ifdef MP
+	#ifdef IN_MP_PHY
+ 	{MPGE_PHY_CHIP, {0}, NULL, mpge_phy_init, NULL},
+ 	#else
+ 	{MPGE_PHY_CHIP, {0}, NULL, NULL, NULL},
--- a/package/qca/qca-ssdk/patches/112-init-MP-allow-to-ignore-reset-controlls.patch
+++ b/package/qca/qca-ssdk/patches/112-init-MP-allow-to-ignore-reset-controlls.patch
@ -0,0 +1,17 @@
+diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
+index 71e59452..bc244c6e 100644
+--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
+@@ -1282,10 +1282,8 @@ ssdk_mp_reset_init(void)
+ 
+ 	for (i = 0; i < MP_BCR_RST_MAX; i++) {
+ 		rst = of_reset_control_get(rst_node, mp_rst_ids[i]);
+-		if (IS_ERR(rst)) {
+-			SSDK_ERROR("%s not exist!\n", mp_rst_ids[i]);
+-			return;
+-		}
+		if (IS_ERR(rst))
+			continue;
+ 		ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
+ 		msleep(200);
+ 		ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
--- a/package/qca/qca-ssdk/patches/121-MP-fix-build-issues.patch
+++ b/package/qca/qca-ssdk/patches/121-MP-fix-build-issues.patch
@ -0,0 +1,62 @@
+diff --git a/config b/config
+index 1f74e4f8..58d67648 100644
+--- a/config
+++ b/config
+@@ -374,6 +374,7 @@ ifneq (, $(filter MPPE APPE HPPE CPPE ALL_CHIP, $(CHIP_TYPE)))
+ endif
+ 
+ ifneq (, $(filter MP, $(CHIP_TYPE)))
+	IN_VSI=TRUE
+ 	IN_UNIPHY=TRUE
+ endif
+ 
+@@ -436,35 +437,6 @@ endif
+ # SDK Features According To Specfic Switch  #
+ #############################################
+ ifeq (MP, $(CHIP_TYPE))
+-	ifeq (disable, $(ISISC_ENABLE))
+-		IN_ACL=FALSE
+-		IN_FDB=FALSE
+-		IN_IGMP=FALSE
+-		IN_LEAKY=FALSE
+-		IN_LED=FALSE
+-		IN_MIRROR=FALSE
+-		IN_MISC=FALSE
+-		IN_PORTVLAN=FALSE
+-		IN_QOS=FALSE
+-		IN_RATE=FALSE
+-		IN_STP=FALSE
+-		IN_VLAN=FALSE
+-		IN_REDUCED_ACL=FALSE
+-		IN_COSMAP=FALSE
+-		IN_IP=FALSE
+-		IN_NAT=FALSE
+-		IN_FLOW=FALSE
+-		IN_TRUNK=FALSE
+-		IN_RSS_HASH=FALSE
+-		IN_SEC=FALSE
+-		IN_QM=FALSE
+-		IN_PPPOE=FALSE
+-		IN_VSI=FALSE
+-		IN_SERVCODE=FALSE
+-		IN_BM=FALSE
+-		IN_SHAPER=FALSE
+-		IN_POLICER=FALSE
+-	endif
+ 	IN_CTRLPKT=TRUE
+ endif
+ 
+diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
+index db60fc72..c230e214 100644
+--- a/src/adpt/mp/adpt_mp_portctrl.c
+++ b/src/adpt/mp/adpt_mp_portctrl.c
+@@ -45,7 +45,8 @@ _adpt_mp_gcc_mac_clock_set(a_uint32_t dev_id,
+ static a_bool_t
+ _adpt_mp_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
+ {
+-	ADPT_DEV_ID_CHECK(dev_id);
+	if (dev_id >= SW_MAX_NR_DEV)
+		return A_FALSE;
+ 
+ 	/* force port which connect s17c or other device chip*/
+ 	if (hsl_port_feature_get(dev_id, port_id, PHY_F_FORCE | PHY_F_SFP)) {
--- a/package/qca/qca-ssdk/patches/122-init-replace-ioremap_nocache-with-ioremap.patch
+++ b/package/qca/qca-ssdk/patches/122-init-replace-ioremap_nocache-with-ioremap.patch
@ -0,0 +1,40 @@
+diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
+index bc244c6e..dc45691e 100644
+--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
+@@ -1183,7 +1183,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, a_uint32_t *tcsr_val)
+ {
+ 	void __iomem *tcsr_base = NULL;
+ 
+-	tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+	tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+ 	if (!tcsr_base)
+ 	{
+ 		SSDK_ERROR("Failed to map tcsr eth address!\n");
+@@ -1200,7 +1200,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, a_uint32_t tcsr_val)
+ {
+ 	void __iomem *tcsr_base = NULL;
+ 
+-	tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+	tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+ 	if (!tcsr_base)
+ 	{
+ 		SSDK_ERROR("Failed to map tcsr eth address!\n");
+@@ -1248,7 +1248,7 @@ ssdk_mp_cmnblk_stable_check(void)
+ 	a_uint32_t reg_val;
+ 	int i, loops = 20;
+ 
+-	pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
+	pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
+ 	if (!pll_lock) {
+ 		SSDK_ERROR("Failed to map CMN PLL LOCK register!\n");
+ 		return A_FALSE;
+@@ -1303,7 +1303,7 @@ static void ssdk_cmnblk_pll_src_set(enum cmnblk_pll_src_type pll_source)
+ 	void __iomem *cmn_pll_src_base = NULL;
+ 	a_uint32_t reg_val;
+ 
+-	cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
+	cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
+ 	if (!cmn_pll_src_base) {
+ 		SSDK_ERROR("Failed to map cmn pll source address!\n");
+ 		return;
--- a/package/qca/qca-ssdk/patches/200-allow-parallel-build.patch
+++ b/package/qca/qca-ssdk/patches/200-allow-parallel-build.patch
@ -0,0 +1,50 @@
+--- a/Makefile
+++ b/Makefile
+@@ -1,17 +1,19 @@
+-include ./config
+-
+ ifndef PRJ_PATH
+   PRJ_PATH=$(shell pwd)
+ endif
+ export PRJ_PATH
+ 
+-include ./make/config.mk
+-include ./make/tools.mk
+-include ./make/$(OS)_opt.mk
+include $(PRJ_PATH)/config
+
+include $(PRJ_PATH)/make/config.mk
+include $(PRJ_PATH)/make/tools.mk
+include $(PRJ_PATH)/make/$(OS)_opt.mk
+ 
+ SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile)))
+ SUB_LIB=$(subst src/, , $(SUB_DIR))
+ 
+include $(PRJ_PATH)/Makefile.modules
+
+ ####################################################################
+ # 			SSDK-Style Makefile
+ ####################################################################
+@@ -27,11 +29,7 @@ all: $(BIN_DIR) kslib
+ # 			LNX Modules-Style Makefile
+ ####################################################################
+ modules: $(BIN_DIR) kslib_c
+-	mkdir -p ./temp/;cp * ./temp -a;cd ./temp;cp ../Makefile.modules ./Makefile;
+-	make -C $(SYS_PATH) M=$(PRJ_PATH)/temp $(LNX_MAKEOPTS) modules
+-	cp $(PRJ_PATH)/temp/Module.symvers $(PRJ_PATH)/Module.symvers;
+-	cp temp/*.ko build/bin;
+-	rm -Rf ./temp/*.o ./temp/*.ko ./temp/*.a
+	@$(MAKE) -C $(SYS_PATH) M=$(PRJ_PATH) $(LNX_MAKEOPTS) modules
+ 	@echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished."
+ 
+ kslib_c:
+--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
+@@ -782,6 +782,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
+ ####################################################################
+ # 			cflags for LNX Modules-Style Makefile
+ ####################################################################
+-LNX_LOCAL_CFLAGS += $(MODULE_INC) $(MODULE_CFLAG) ${EXTRA_INC} -DFALLTHROUGH
+LNX_LOCAL_CFLAGS = $(MODULE_INC) $(MODULE_CFLAG) ${EXTRA_INC} -DFALLTHROUGH
+ export LNX_LOCAL_CFLAGS
+ 
--- a/package/qca/qca-ssdk/patches/300-ignore-phy_addr-warning.patch
+++ b/package/qca/qca-ssdk/patches/300-ignore-phy_addr-warning.patch
@ -0,0 +1,71 @@
+--- a/src/hsl/phy/hsl_phy.c
+++ a/src/hsl/phy/hsl_phy.c
+@@ -762,7 +762,7 @@
+ 	*phydev = miibus->phy_map[phy_addr];
+ 	if(*phydev == NULL)
+ 	{
+-		SSDK_ERROR("phy_addr %d phydev is NULL\n", phy_addr);
+		// SSDK_ERROR("phy_addr %d phydev is NULL\n", phy_addr);
+ 		return SW_NOT_INITIALIZED;
+ 	}
+ 	pdev_addr = (*phydev)->addr;
+@@ -772,7 +772,7 @@
+ 	*phydev = mdiobus_get_phy(miibus, phy_addr);
+ 	if(*phydev == NULL)
+ 	{
+-		SSDK_ERROR("phy_addr %d phydev is NULL\n", phy_addr);
+		// SSDK_ERROR("phy_addr %d phydev is NULL\n", phy_addr);
+ 		return SW_NOT_INITIALIZED;
+ 	}
+ 	pdev_addr = (*phydev)->mdio.addr;
+--- a/src/adpt/hppe/adpt_hppe_portctrl.c
+++ b/src/adpt/hppe/adpt_hppe_portctrl.c
+@@ -2277,9 +2277,9 @@
+ 		{
+ 			if(*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_PSGMII)
+ 			{
+-				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+				/* SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+ 					"mode0:%d cannot be supported\n",
+-					port_id, phy_info->port_mode[port_id], *mode0);
+					port_id, phy_info->port_mode[port_id], *mode0); */
+ 				return SW_NOT_SUPPORTED;
+ 			}
+ 			*mode0 = PORT_WRAPPER_PSGMII;
+@@ -2296,9 +2296,9 @@
+ 			if((*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_QSGMII) ||
+ 				port_id == SSDK_PHYSICAL_PORT5)
+ 			{
+-				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+				/* SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+ 					"mode0:%d cannot be supported\n",
+-					port_id, phy_info->port_mode[port_id], *mode0);
+					port_id, phy_info->port_mode[port_id], *mode0); */
+ 				return SW_NOT_SUPPORTED;
+ 			}
+ 			*mode0 = PORT_WRAPPER_QSGMII;
+@@ -2310,9 +2310,9 @@
+ 				if((*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_UQXGMII) ||
+ 					port_id == SSDK_PHYSICAL_PORT5)
+ 				{
+-					SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+					/* SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+ 						"mode0:%d cannot be supported\n",
+-						port_id, phy_info->port_mode[port_id], *mode0);
+						port_id, phy_info->port_mode[port_id], *mode0); */
+ 					return SW_NOT_SUPPORTED;
+ 				}
+ 				*mode0 = PORT_WRAPPER_UQXGMII;
+@@ -2326,10 +2326,10 @@
+ 			{
+ 				if(port_id != SSDK_PHYSICAL_PORT5)
+ 				{
+-					SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+					/* SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+ 						"mode0:%d cannot be supported\n",
+ 						port_id, phy_info->port_mode[port_id],
+-						*mode0);
+						*mode0); */
+ 					return SW_NOT_SUPPORTED;
+ 				}
+ 				else
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ess.dtsi
@ -0,0 +1,116 @@
+#include <dt-bindings/net/qcom-ipq-ess.h>
+
+&soc {
+	ess_instance: ess-instance {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		num_devices = <1>;
+
+		switch: ess-switch@39c00000 {
+			compatible = "qcom,ess-switch-ipq50xx";
+			device_id = <0>;
+			cmnblk_clk = "internal_96MHz";
+			reg = <0x39c00000 0x200000>;
+			switch_access_mode = "local bus";
+			clocks = <&gcc GCC_CMN_BLK_AHB_CLK>,
+				 <&gcc GCC_CMN_BLK_SYS_CLK>,
+				 <&gcc GCC_UNIPHY_AHB_CLK>,
+				 <&gcc GCC_UNIPHY_SYS_CLK>,
+				 <&gcc GCC_MDIO0_AHB_CLK>,
+				 <&gcc GCC_MDIO1_AHB_CLK>,
+				 <&gcc GCC_GMAC0_CFG_CLK>,
+				 <&gcc GCC_GMAC0_SYS_CLK>,
+				 <&gcc GCC_GMAC1_CFG_CLK>,
+				 <&gcc GCC_GMAC1_SYS_CLK>,
+				 <&gcc GCC_GEPHY_RX_CLK>,
+				 <&gcc GCC_GEPHY_TX_CLK>,
+				 <&gcc GCC_UNIPHY_RX_CLK>,
+				 <&gcc GCC_UNIPHY_TX_CLK>,
+				 <&gcc GCC_GMAC0_RX_CLK>,
+				 <&gcc GCC_GMAC0_TX_CLK>,
+				 <&gcc GCC_GMAC1_RX_CLK>,
+				 <&gcc GCC_GMAC1_TX_CLK>,
+				 <&gcc GCC_SNOC_GMAC0_AHB_CLK>,
+				 <&gcc GCC_SNOC_GMAC1_AHB_CLK>,
+				 <&gcc GCC_GMAC0_PTP_CLK>,
+				 <&gcc GCC_GMAC1_PTP_CLK>;
+			clock-names = "cmn_ahb_clk",
+				      "cmn_sys_clk",
+				      "uniphy_ahb_clk",
+				      "uniphy_sys_clk",
+				      "gcc_mdio0_ahb_clk",
+				      "gcc_mdio1_ahb_clk",
+				      "gcc_gmac0_cfg_clk",
+				      "gcc_gmac0_sys_clk",
+				      "gcc_gmac1_cfg_clk",
+				      "gcc_gmac1_sys_clk",
+				      "uniphy0_port1_rx_clk",
+				      "uniphy0_port1_tx_clk",
+				      "uniphy1_port5_rx_clk",
+				      "uniphy1_port5_tx_clk",
+				      "nss_port1_rx_clk",
+				      "nss_port1_tx_clk",
+				      "nss_port2_rx_clk",
+				      "nss_port2_tx_clk",
+				      "gcc_snoc_gmac0_ahb_clk",
+				      "gcc_snoc_gmac1_ahb_clk",
+				      "gcc_gmac0_ptp_clk",
+				      "gcc_gmac1_ptp_clk";
+			resets = <&gcc GCC_GMAC0_BCR>,
+				 <&gcc GCC_GMAC1_BCR>,
+				 <&gcc GCC_UNIPHY_BCR>,
+				 <&gcc GCC_UNIPHY_SOFT_RESET>;
+			reset-names = "gmac0_bcr_rst",
+				      "gmac1_bcr_rst",
+				      "uniphy_bcr_rst",
+				      "uniphy1_soft_rst";
+
+			status = "disabled";
+		};
+	};
+
+	ess-uniphy@98000 {
+		compatible = "qcom,ess-uniphy";
+		reg = <0x98000 0x800>;
+		uniphy_access_mode = "local bus";
+	};
+
+	nss-dp-common {
+		compatible = "qcom,nss-dp-common";
+		qcom,tcsr-base = <0x01937000>;
+	};
+
+	dp1: dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+
+		reg = <0x39C00000 0x10000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
+		clock-names = "nss-snoc-gmac-axi-clk";
+
+		qcom,mactype = <2>; /* GMAC_HAL_TYPE_SYN_GMAC */
+		local-mac-address = [000000000000];
+		phy-mode = "internal";
+		phy-handle = <&ge_phy>;
+
+		status = "disabled";
+	};
+
+	dp2: dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+
+		reg = <0x39D00000 0x10000>;
+		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
+		clock-names = "nss-snoc-gmac-axi-clk";
+
+		qcom,mactype = <2>; /* GMAC_HAL_TYPE_SYN_GMAC */
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+};
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts
@ -0,0 +1,478 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+
+/dts-v1/;
+#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+/ {
+	model = "GL.iNET B3000";
+	compatible = "glinet,gl-b3000", "qcom,ipq5018";
+	
+	interrupt-parent = <&intc>;
+	
+	aliases {
+		serial0 = &blsp1_uart1;
+		
+		ethernet0 = &dp1;
+		ethernet1 = &dp2;
+		label-mac-device = &dp2;
+		
+		led-boot = &led_system_blue;
+		led-failsafe = &led_status_white;
+		led-running = &led_status_white;
+		led-upgrade = &led_system_blue;
+	};
+	chosen {
+		bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1 coherent_pool=2M";
+		stdout-path = "serial0:115200n8";
+	};
+	
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+		led_system_blue: led_system_blue {
+			label = "led_system_blue";
+			gpio = <&tlmm 24 0>;
+			default-state = "on";
+		};
+		
+		led_status_white: led_status_white {
+			label = "led_status_white";
+			gpio = <&tlmm 23 0>;
+			default-state = "off";
+		};
+	};
+	
+	button {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+		button_reset {
+			label = "reset";
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;//<1>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+	reserved-memory {
+		tz_appps@4a400000 {
+			no-map;
+			reg = <0x0 0x4a400000 0x0 0x400000>;
+		};
+		
+		q6_mem_regions: q6_mem_regions@4b000000 {
+			no-map;
+			reg = <0x0 0x4b000000 0x0 0x3000000>;
+		};
+	};
+};
+&switch {
+	status = "okay";
+	switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
+	qcom,port_phyinfo {
+		// MAC0 -> GE Phy -> QCA8337 Phy2
+		port@0 {
+			port_id = <1>;
+			mdiobus = <&mdio0>;
+			phy_address = <7>;
+			phy_dac = <0x10 0x10>;
+			// status = "disabled";
+		};
+		// MAC1 ---SGMII---> QCA8337 SerDes
+		port@1 {
+			port_id = <2>;
+			forced-speed = <1000>;
+			forced-duplex = <1>;
+		};
+	};
+};
+// MAC0 -> GE Phy
+&dp1 {
+	status = "okay";
+};
+// MAC1 ---SGMII---> QCA8337 SerDes
+&dp2 {
+	status = "okay";
+	phy-mode = "sgmii";
+	nvmem-cells = <&macaddr_dp2>;
+	nvmem-cell-names = "mac-address";
+	
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+&mdio0 {
+	status = "okay";
+};
+// IPQ5018 GE Phy -> QCA8337 Phy1
+&ge_phy {
+	status = "okay";
+};
+&mdio1 {
+	status = "okay";
+	pinctrl-0 = <&mdio1_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+	// QCA8337 Phy0 -> WAN
+	qca8337_0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	// QCA8337 Phy1 -> LAN1
+	qca8337_1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	// QCA8337 Phy3 -> LAN2
+	qca8337_2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	// QCA8337 Phy2 -> IPQ5018 GE Phy
+	qca8337_3: ethernet-phy@3 {
+		reg = <3>;
+	};
+	// QCA8337 switch
+	switch0: ethernet-switch@17 {
+		compatible = "qca,qca8337";
+		reg = <17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		switch_cpu_bmp = <0x40>;  /* cpu port bitmap */
+		switch_lan_bmp = <0x0c>; /* lan port bitmap */
+		switch_wan_bmp = <0x02>;  /* wan port bitmap */
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			
+			switch0cpu: port@0 {
+				reg = <0>;
+				label = "cpu";
+				phy-mode = "sgmii";
+				ethernet = <&dp2>;
+				qca,sgmii-enable-pll;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+			// QCA8337 Phy0 -> WAN
+			port@1 {
+				reg = <1>;
+				label = "wan";
+				phy-handle = <&qca8337_0>;
+				port_id = <1>;
+				phy_address = <0>;
+			};
+			
+			// QCA8337 Phy1 -> LAN1
+			port@2 {
+				reg = <2>;
+				label = "lan1";
+				phy-handle = <&qca8337_1>;
+				port_id = <2>;
+				phy_address = <1>;
+			};
+			// QCA8337 Phy3 -> LAN2
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+				phy-handle = <&qca8337_2>;
+				port_id = <3>;
+				phy_address = <2>;
+				
+			};
+		};
+	};
+};
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+&xo_board_clk {
+	clock-frequency = <24000000>;
+};
+&blsp1_uart1 {
+	status = "okay";
+	pinctrl-0 = <&blsp_uart0_pins>;
+	pinctrl-names = "default";
+};
+&crypto {
+	status = "okay";
+};
+&cryptobam {
+	status = "okay";
+};
+&qpic_bam {
+	status = "okay";
+};
+&qpic_nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	partitions {
+		status = "disabled";
+	};
+    nand@0 {
+        compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		nand-ecc-engine = <&qpic_nand>;
+        nand-ecc-strength = <8>;
+        nand-ecc-step-size = <512>;
+        nand-bus-width = <8>;
+        partitions {
+            compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x80000>;
+				read-only;
+			};
+            partition@80000 {
+				label = "0:MIBIB";
+				reg = <0x00080000 0x80000>;
+				read-only;
+			};
+			partition@100000 {
+				label = "0:BOOTCONFIG";
+				reg = <0x00100000 0x40000>;
+				read-only;
+			};
+            partition@140000 {
+				label = "0:QSEE";
+				reg = <0x00140000 0x100000>;
+				read-only;
+			};
+            partition@240000 {
+				label = "0:DEVCFG";
+				reg = <0x00240000 0x40000>;
+				read-only;
+			};
+            partition@280000 {
+				label = "0:CDT";
+				reg = <0x00280000 0x40000>;
+				read-only;
+			};
+            partition@2c0000 {
+				label = "0:APPSBLENV";
+				reg = <0x002c0000 0x80000>;
+			};
+            partition@340000 {
+				label = "0:APPSBL";
+				reg = <0x00340000 0x140000>;
+				read-only;
+			};
+			partition@480000 {
+				label = "0:ART";
+				reg = <0x00480000 0x100000>;
+				read-only;
+				
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					macaddr_dp2: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+			};
+            partition@580000 {
+				label = "0:TRAINING";
+				reg = <0x00580000 0x80000>;
+				read-only;
+			};
+            partition@600000 {
+				label = "CFG";
+				reg = <0x00600000 0x200000>;
+			};
+            partition@800000 {
+				label = "rootfs";
+				reg = <0x00800000 0x7800000>;
+			};
+        };
+    };
+};
+&tlmm {
+	mdio1_pins: mdio-state {
+		mdc-pins {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mdio-pins {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+	
+	leds_pins: leds_pins {
+		led_system_blue {
+			pins = "gpio24";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		
+		led_status_white {
+			pins = "gpio23";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+	button_pins: button_pins {
+		button_reset {
+			pins = "gpio27";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+	
+	qpic_pins: qpic-state {
+		clock-pins {
+			pins = "gpio9";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		cs-pins {
+			pins = "gpio8";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data-pins {
+			pins = "gpio4", "gpio5", "gpio6", "gpio7";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+	blsp_uart0_pins: blsp_uart0_pins {
+		pins =
+			"gpio20", // RX
+			"gpio21"; // TX
+		function = "blsp0_uart0";
+		drive-strength = <8>;
+		bias-disable;
+	};
+};
+
+&tsens {
+	status = "disabled";
+};
+
+&pcie_x2phy {
+	status = "disabled";
+};
+
+&pcie_x2 {
+	status = "disabled";
+	perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
+};
+
+&q6v5_wcss {
+	status = "okay";
+	memory-region = <&q6_mem_regions>;
+	firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt",
+					"ath11k/IPQ5018/hw1.0/m3_fw.mdt",
+					"ath11k/qcn6122/hw1.0/m3_fw.mdt";
+
+	boot-args = 
+			</*       type: */ 0x1 /* PCIE0 */
+		     /*     length: */ 4
+		     /*      PD id: */ 3
+		     /* reset GPIO: */ 15
+		     /*   reserved: */ 0 0>;
+	
+	// IPQ5018
+	q6_wcss_pd1: pd-1 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+		resets =
+			<&gcc GCC_WCSSAON_RESET>,
+			<&gcc GCC_WCSS_BCR>,
+			<&gcc GCC_CE_BCR>;
+		reset-names =
+			"wcss_aon_reset",
+			"wcss_reset",
+			"ce_reset";
+		clocks =
+			<&gcc GCC_WCSS_AHB_S_CLK>,
+			<&gcc GCC_WCSS_ACMT_CLK>,
+			<&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names =
+			"gcc_wcss_ahb_s_clk",
+			"gcc_wcss_acmt_clk",
+			"gcc_wcss_axi_m_clk";
+
+		interrupts-extended =
+			<&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+		qcom,smem-states =
+			<&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+		status = "okay";
+	};
+
+	// QCN6102 5G
+	q6_wcss_pd3: pd-3 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+		interrupts-extended =
+			<&wcss_smp2p_in 24 0>,
+			<&wcss_smp2p_in 25 0>,
+			<&wcss_smp2p_in 28 0>,
+			<&wcss_smp2p_in 27 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+		qcom,smem-states =
+			<&wcss_smp2p_out 24>,
+			<&wcss_smp2p_out 25>,
+			<&wcss_smp2p_out 26>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+
+		status = "okay";
+	};
+};
+&wifi0 {
+	// IPQ5018
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000";
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4c400000>;
+	status = "okay";
+};
+&wifi1 {
+	qcom,rproc = <&q6_wcss_pd3>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
+	qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000";
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4d100000>;
+	qcom,m3-dump-addr = <0x4df00000>;
+	status = "okay";
+};
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts
@ -0,0 +1,695 @@
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Linksys MX2000";
+	compatible = "linksys,mx2000", "qcom,ipq5018";
+
+	aliases {
+		ethernet0 = &dp1;
+		ethernet1 = &dp2;
+		led-boot = &led_system_blue;
+		led-failsafe = &led_system_red;
+		led-running = &led_system_blue;
+		led-upgrade = &led_system_red;
+		serial0 = &blsp1_uart1;
+	};
+
+	chosen {
+		bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M";
+		stdout-path = "serial0:115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		wps-button {
+			label = "wps";
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset-button {
+			label = "reset";
+			gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "pwm-leds";
+
+		led_system_red: red {
+			label = "red:system";
+			pwms = <&pwm 3 1250000>;
+			max-brightness = <255>;
+		};
+
+		green {
+			label = "green:system";
+			pwms = <&pwm 0 1250000>;
+			max-brightness = <255>;
+		};
+
+		led_system_blue: blue {
+			label = "blue:system";
+			pwms = <&pwm 1 1250000>;
+			max-brightness = <255>;
+			//linux,default-trigger = "default-on";
+		};
+	};
+
+	reserved-memory {
+		tz_appps@4a400000 {
+			no-map;
+			reg = <0x0 0x4a400000 0x0 0x400000>;
+		};
+		
+		q6_mem_regions: q6_mem_regions@4b000000 {
+			no-map;
+			reg = <0x0 0x4b000000 0x0 0x3000000>;
+		};
+
+		/* from stock DTS:
+		q6_code_data: q6_code_data@4b000000 {
+			no-map;
+			reg = <0x0 0x4b000000 0x0 0x60000>;
+		};
+
+		q6_ipq5018_data: q6_ipq5018_data@4c400000 {
+			no-map;
+			reg = <0x0 0x4c400000 0x0 0xe00000>;
+		};
+
+		q6_m3_region: m3_dump@4d200000 {
+			no-map;
+			reg = <0x0 0x4d200000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4d300000 {
+			no-map;
+			reg = <0x0 0x4d300000 0x0 0x100000>;
+		};
+
+		q6_caldb_region: q6_caldb_region@4d400000 {
+			no-map;
+			reg = <0x0 0x4d400000 0x0 0x200000>;
+		};
+
+		q6_qcn6122_data1: q6_qcn6122_data1@4d600000 {
+			no-map;
+			reg = <0x0 0x4d600000 0x0 0x1000000>;
+		};
+
+		q6_qcn6122_m3_1: q6_qcn6122_m3_1@4e600000 {
+			no-map;
+			reg = <0x0 0x4e600000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4e700000 {
+			no-map;
+			reg = <0x0 0x4e700000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4e800000 {
+			no-map;
+			reg = <0x0 0x4e800000 0x0 0x500000>;
+		};
+
+		q6_qcn6122_data2: q6_qcn6122_data20@4ed00000 {
+			no-map;
+			reg = <0x0 0x4ed00000 0x0 0x1000000>;
+		};
+
+		q6_qcn6122_m3_2: q6_qcn6122_m3_2@4fd00000 {
+			no-map;
+			reg = <0x0 0x4fd00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_2: q6_qcn6122_etr_2@4fe00000 {
+			no-map;
+			reg = <0x0 0x4fe00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4ff00000 {
+			no-map;
+			reg = <0x0 0x4ff00000 0x0 0x500000>;
+		};
+		*/
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
+
+	qcom,port_phyinfo {
+		// MAC0 -> GE Phy -> QCA8337 Phy4
+		port@0 {
+			port_id = <1>;
+			mdiobus = <&mdio0>;
+			phy_address = <7>;
+			// status = "disabled";
+		};
+
+		// MAC1 ---SGMII---> QCA8337 SerDes
+		port@1 {
+			port_id = <2>;
+			forced-speed = <1000>;
+			forced-duplex = <1>;
+		};
+	};
+};
+
+// MAC0 -> GE Phy
+&dp1 {
+	/*
+	 * ===============================================================
+	 *     _______________________         _______________________
+	 *    |        IPQ5018        |       |        QCA8337        |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | | MAC0 |---| GE Phy |-+--UTP--+-|  Phy4  |---| MAC5 | |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    |_______________________|       |_______________________|
+	 *
+	 * ===============================================================
+	 *
+	 * Current drivers don't support such topology. So dp1 and ge_phy
+	 * are useless. But they can't be disabled dut to qca-ssdk use
+	 * ge_phy to detect IPQ5018 dummy switch.
+	 */
+	status = "okay";
+};
+
+// MAC1 ---SGMII---> QCA8337 SerDes
+&dp2 {
+	status = "okay";
+	phy-mode = "sgmii";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+};
+
+// IPQ5018 GE Phy -> QCA8337 Phy1
+&ge_phy {
+	status = "okay";
+};
+
+&mdio1 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio1_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+	// QCA8337 Phy0 -> IPQ5018 GE Phy
+	qca8337_0: ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	// QCA8337 Phy1 -> WAN
+	qca8337_1: ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	// QCA8337 Phy2 -> LAN1
+	qca8337_2: ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	// QCA8337 Phy3 -> LAN2
+	qca8337_3: ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	// QCA8337 Phy4 -> LAN3
+	qca8337_4: ethernet-phy@4 {
+		reg = <4>;
+	};
+
+	// QCA8337 switch
+	switch1: ethernet-switch@17 {
+		compatible = "qca,qca8337";
+		reg = <17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "cpu1";
+				phy-handle = <&qca8337_0>;
+				status = "disabled";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+				phy-handle = <&qca8337_1>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+				phy-handle = <&qca8337_2>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan2";
+				phy-handle = <&qca8337_3>;
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan3";
+				phy-handle = <&qca8337_4>;
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "cpu";
+				phy-mode = "sgmii";
+				ethernet = <&dp2>;
+				qca,sgmii-enable-pll;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&xo_board_clk {
+	clock-frequency = <24000000>;
+};
+
+&blsp1_uart1 {
+	status = "okay";
+
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+
+	#pwm-cells = <2>;
+	pinctrl-0 = <&pwm_pins>;
+	pinctrl-names = "default";
+};
+
+&qfprom {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	partitions {
+		status = "disabled";
+	};
+
+	nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		nand-ecc-engine = <&qpic_nand>;
+
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "0:MIBIB";
+				reg = <0x00080000 0x20000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:QSEE";
+				reg = <0x00100000 0x100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:DEVCFG";
+				reg = <0x00200000 0x40000>;
+				read-only;
+			};
+
+			partition@240000 {
+				label = "0:CDT";
+				reg = <0x00240000 0x40000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "0:APPSBLENV";
+				reg = <0x00280000 0x20000>;
+			};
+
+			partition@300000 {
+				label = "0:APPSBL";
+				reg = <0x00300000 0x140000>;
+				read-only;
+			};
+
+			partition@440000 {
+				compatible = "nvmem-cells";
+				label = "0:ART";
+				reg = <0x00440000 0x100000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				read-only;
+			};
+
+			partition@540000 {
+				label = "0:TRAINING";
+				reg = <0x00540000 0x80000>;
+				read-only;
+			};
+
+			partition@5c0000 {
+				label = "u_env";
+				reg = <0x005c0000 0x80000>;
+			};
+
+			partition@640000 {
+				label = "s_env";
+				reg = <0x00640000 0x40000>;
+			};
+
+			partition@680000 {
+				label = "devinfo";
+				reg = <0x00680000 0x40000>;
+				read-only;
+			};
+
+			partition@6c0000 {
+				label = "kernel";
+				reg = <0x006c0000 0x5200000>;
+			};
+
+			partition@ec0000 {
+				label = "rootfs";
+				reg = <0x0ec0000 0x4a00000>;
+			};
+
+			partition@58c0000 {
+				label = "alt_kernel";
+				reg = <0x058c0000 0x5200000>;
+			};
+
+			partition@60c0000 {
+				label = "alt_rootfs";
+				reg = <0x060c0000 0x4a00000>;
+			};
+
+			partition@aac0000 {
+				label = "sysdiag";
+				reg = <0x0aac0000 0x200000>;
+				read-only;
+			};
+
+			partition@acc0000 {
+				label = "syscfg";
+				reg = <0x0acc0000 0x4400000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&tlmm {
+	button_pins: button-state {
+		pins = "gpio27", "gpio28";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	mdio1_pins: mdio-state {
+		mdc-pins {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	pwm_pins: pwm-state {
+		mux_1 {
+			pins = "gpio1";
+			function = "pwm1";
+			drive-strength = <8>;
+		};
+
+		mux_2 {
+			pins = "gpio30";
+			function = "pwm3";
+			drive-strength = <8>;
+		};
+
+		mux_3 {
+			pins = "gpio46";
+			function = "pwm0";
+			drive-strength = <8>;
+		};
+	};
+
+	qpic_pins: qpic-state {
+		clock-pins {
+			pins = "gpio9";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cs-pins {
+			pins = "gpio8";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data-pins {
+			pins = "gpio4", "gpio5", "gpio6", "gpio7";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	serial_0_pins: uart0-state {
+		pins = "gpio20", "gpio21";
+		function = "blsp0_uart0";
+		bias-disable;
+	};
+};
+
+&tsens {
+	status = "okay";
+};
+
+&q6v5_wcss {
+	status = "okay";
+
+	memory-region = <&q6_mem_regions>;
+	firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt",
+					"ath11k/IPQ5018/hw1.0/m3_fw.mdt",
+					"ath11k/qcn6122/hw1.0/m3_fw.mdt";
+
+	/*qcom,bootargs_smem = <507>;*/	/* hard-coded in mpd driver */
+	boot-args = 
+			</*       type: */ 0x1 /* PCIE0 */
+			 /*     length: */ 4
+			 /*      PD id: */ 3
+			 /* reset GPIO: */ 15
+			 /*   reserved: */ 0 0>;
+	
+	// IPQ5018
+	q6_wcss_pd1: pd-1 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+
+		resets =
+			<&gcc GCC_WCSSAON_RESET>,
+			<&gcc GCC_WCSS_BCR>,
+			<&gcc GCC_CE_BCR>;
+		reset-names =
+			"wcss_aon_reset",
+			"wcss_reset",
+			"ce_reset";
+
+		clocks =
+			<&gcc GCC_WCSS_AHB_S_CLK>,
+			<&gcc GCC_WCSS_ACMT_CLK>,
+			<&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names =
+			"gcc_wcss_ahb_s_clk",
+			"gcc_wcss_acmt_clk",
+			"gcc_wcss_axi_m_clk";
+
+		// qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
+		interrupts-extended =
+			<&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+		status = "okay";
+	};
+
+	// QCN6102 6G
+	q6_wcss_pd2: pd-2 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+
+		interrupts-extended =
+			<&wcss_smp2p_in 16 0>,
+			<&wcss_smp2p_in 17 0>,
+			<&wcss_smp2p_in 20 0>,
+			<&wcss_smp2p_in 19 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 16>,
+			<&wcss_smp2p_out 17>,
+			<&wcss_smp2p_out 18>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+		status = "disabled";
+	};
+
+	// QCN6102 5G
+	q6_wcss_pd3: pd-3 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+
+		interrupts-extended =
+			<&wcss_smp2p_in 24 0>,
+			<&wcss_smp2p_in 25 0>,
+			<&wcss_smp2p_in 28 0>,
+			<&wcss_smp2p_in 27 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 24>,
+			<&wcss_smp2p_out 25>,
+			<&wcss_smp2p_out 26>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+		status = "okay";
+	};
+};
+
+&wifi0 {
+	// IPQ5018
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,ath11k-calibration-variant = "Linksys-MX2000";
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4c400000>;
+
+	status = "okay";
+};
+
+&wifi1 {
+	// QCN6102 5G
+	qcom,rproc = <&q6_wcss_pd3>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
+	qcom,ath11k-calibration-variant = "Linksys-MX2000";
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4d100000>;
+	qcom,m3-dump-addr = <0x4df00000>;
+
+	status = "okay";
+};
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts
@ -0,0 +1,612 @@
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Linksys MX5500";
+	compatible = "linksys,mx5500", "qcom,ipq5018";
+
+	aliases {
+		ethernet0 = &dp1;
+		ethernet1 = &dp2;
+		led-boot = &led_system_blue;
+		led-failsafe = &led_system_red;
+		led-running = &led_system_blue;
+		led-upgrade = &led_system_red;
+		serial0 = &blsp1_uart1;
+	};
+
+	chosen {
+		bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M";
+		stdout-path = "serial0:115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		wps-button {
+			label = "wps";
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset-button {
+			label = "reset";
+			gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "pwm-leds";
+
+		led_system_red: red {
+			label = "red:system";
+			pwms = <&pwm 3 1250000>;
+			max-brightness = <255>;
+		};
+
+		green {
+			label = "green:system";
+			pwms = <&pwm 0 1250000>;
+			max-brightness = <255>;
+		};
+
+		led_system_blue: blue {
+			label = "blue:system";
+			pwms = <&pwm 1 1250000>;
+			max-brightness = <255>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	reserved-memory {
+		q6_mem_regions: q6_mem_regions@4b000000 {
+			no-map;
+			reg = <0x0 0x4b000000 0x0 0x3000000>;
+		};
+
+		/*
+		q6_region: wcnss@4b000000 {
+			no-map;
+			reg = <0x0 0x4b000000 0x0 0x01800000>;
+		};
+
+		q6_m3_region: m3_dump@4c800000 {
+			no-map;
+			reg = <0x0 0x4c800000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4c900000 {
+			no-map;
+			reg = <0x0 0x4c900000 0x0 0x100000>;
+		};
+
+		q6_caldb_region: q6_caldb_region@4cd00000 {
+			no-map;
+			reg = <0x0 0x4cd00000 0x0 0x200000>;
+		};
+
+		qcn9000_pcie0@4cc00000 {
+			no-map;
+			reg = <0x0 0x4cc00000 0x0 0x01e00000>;
+		};
+		*/
+
+		mhi_region1: dma_pool1@4ea00000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0x0 0x4ea00000 0x0 0x01000000>;
+		};
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
+
+	qcom,port_phyinfo {
+		// MAC0 -> GE Phy -> QCA8337 Phy4
+		port@0 {
+			port_id = <1>;
+			mdiobus = <&mdio0>;
+			phy_address = <7>;
+			// status = "disabled";
+		};
+
+		// MAC1 ---SGMII---> QCA8337 SerDes
+		port@1 {
+			port_id = <2>;
+			forced-speed = <1000>;
+			forced-duplex = <1>;
+		};
+	};
+};
+
+// MAC0 -> GE Phy
+&dp1 {
+	/*
+	 * ===============================================================
+	 *     _______________________         _______________________
+	 *    |        IPQ5018        |       |        QCA8337        |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | | MAC0 |---| GE Phy |-+--UTP--+-|  Phy4  |---| MAC5 | |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | |
+	 *    | +------+   +--------+ |       | +--------+   +------+ |
+	 *    |_______________________|       |_______________________|
+	 *
+	 * ===============================================================
+	 *
+	 * Current drivers don't support such topology. So dp1 and ge_phy
+	 * are useless. But they can't be disabled dut to qca-ssdk use
+	 * ge_phy to detect IPQ5018 dummy switch.
+	 */
+	status = "okay";
+};
+
+// MAC1 ---SGMII---> QCA8337 SerDes
+&dp2 {
+	status = "okay";
+	phy-mode = "sgmii";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+};
+
+// IPQ5018 GE Phy -> QCA8337 Phy1
+&ge_phy {
+	status = "okay";
+};
+
+&mdio1 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio1_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+	// QCA8337 Phy0 -> IPQ5018 GE Phy
+	qca8337_0: ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	// QCA8337 Phy1 -> WAN
+	qca8337_1: ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	// QCA8337 Phy2 -> LAN1
+	qca8337_2: ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	// QCA8337 Phy3 -> LAN2
+	qca8337_3: ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	// QCA8337 Phy4 -> LAN3
+	qca8337_4: ethernet-phy@4 {
+		reg = <4>;
+	};
+
+	// QCA8337 switch
+	switch1: ethernet-switch@10 {
+		compatible = "qca,qca8337";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg = <10>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "cpu1";
+				phy-handle = <&qca8337_0>;
+				status = "disabled";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+				phy-handle = <&qca8337_1>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+				phy-handle = <&qca8337_2>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan2";
+				phy-handle = <&qca8337_3>;
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan3";
+				phy-handle = <&qca8337_4>;
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "cpu";
+				phy-mode = "sgmii";
+				ethernet = <&dp2>;
+				qca,sgmii-enable-pll;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&xo_board_clk {
+	clock-frequency = <24000000>;
+};
+
+&blsp1_uart1 {
+	status = "okay";
+
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+
+	#pwm-cells = <2>;
+
+	pinctrl-0 = <&pwm_pins>;
+	pinctrl-names = "default";
+};
+
+&qfprom {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	partitions {
+		status = "disabled";
+	};
+
+	nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		nand-ecc-engine = <&qpic_nand>;
+
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "0:MIBIB";
+				reg = <0x00080000 0x20000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:QSEE";
+				reg = <0x00100000 0x100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:DEVCFG";
+				reg = <0x00200000 0x40000>;
+				read-only;
+			};
+
+			partition@240000 {
+				label = "0:CDT";
+				reg = <0x00240000 0x40000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "0:APPSBLENV";
+				reg = <0x00280000 0x20000>;
+			};
+
+			partition@300000 {
+				label = "0:APPSBL";
+				reg = <0x00300000 0x140000>;
+				read-only;
+			};
+
+			partition@440000 {
+				compatible = "nvmem-cells";
+				label = "0:ART";
+				reg = <0x00440000 0x100000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				read-only;
+			};
+
+			partition@540000 {
+				label = "0:TRAINING";
+				reg = <0x00540000 0x80000>;
+				read-only;
+			};
+
+			partition@5c0000 {
+				label = "u_env";
+				reg = <0x005c0000 0x80000>;
+			};
+
+			partition@640000 {
+				label = "s_env";
+				reg = <0x00640000 0x40000>;
+			};
+
+			partition@680000 {
+				label = "devinfo";
+				reg = <0x00680000 0x40000>;
+				read-only;
+			};
+
+			partition@6c0000 {
+				label = "kernel";
+				reg = <0x006c0000 0x5200000>;
+			};
+
+			partition@ec0000 {
+				label = "rootfs";
+				reg = <0x0ec0000 0x4a00000>;
+			};
+
+			partition@58c0000 {
+				label = "alt_kernel";
+				reg = <0x058c0000 0x5200000>;
+			};
+
+			partition@60c0000 {
+				label = "alt_rootfs";
+				reg = <0x060c0000 0x4a00000>;
+			};
+
+			partition@aac0000 {
+				label = "sysdiag";
+				reg = <0x0aac0000 0x200000>;
+				read-only;
+			};
+
+			partition@acc0000 {
+				label = "syscfg";
+				reg = <0x0acc0000 0x4400000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&tlmm {
+	button_pins: button-state {
+		pins = "gpio27", "gpio28";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	mdio1_pins: mdio-state {
+		mdc-pins {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	pwm_pins: pwm-state {
+		mux_1 {
+			pins = "gpio1";
+			function = "pwm1";
+			drive-strength = <8>;
+		};
+
+		mux_2 {
+			pins = "gpio30";
+			function = "pwm3";
+			drive-strength = <8>;
+		};
+
+		mux_3 {
+			pins = "gpio46";
+			function = "pwm0";
+			drive-strength = <8>;
+		};
+	};
+
+	qpic_pins: qpic-state {
+		clock-pins {
+			pins = "gpio9";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cs-pins {
+			pins = "gpio8";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data-pins {
+			pins = "gpio4", "gpio5", "gpio6", "gpio7";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	serial_0_pins: uart0-state {
+		pins = "gpio20", "gpio21";
+		function = "blsp0_uart0";
+		bias-disable;
+	};
+};
+
+&tsens {
+	status = "okay";
+};
+
+&pcie_x2phy {
+	status = "okay";
+};
+
+&pcie_x2 {
+	status = "okay";
+
+	perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			status = "okay";
+
+			/* QCN9074: ath11k lacks DT compatible for PCI cards */
+			compatible = "pci17cb,1104";
+			reg = <0x00010000 0 0 0 0>;
+
+			qcom,ath11k-calibration-variant = "Linksys-MX5500";
+		};
+	};
+};
+
+&q6v5_wcss {
+	status = "okay";
+
+	memory-region = <&q6_mem_regions>;
+	firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt",
+					"ath11k/IPQ5018/hw1.0/m3_fw.mdt";
+	
+	// IPQ5018
+	q6_wcss_pd1: pd-1 {
+		firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
+
+		resets =
+			<&gcc GCC_WCSSAON_RESET>,
+			<&gcc GCC_WCSS_BCR>,
+			<&gcc GCC_CE_BCR>;
+		reset-names =
+			"wcss_aon_reset",
+			"wcss_reset",
+			"ce_reset";
+
+		clocks =
+			<&gcc GCC_WCSS_AHB_S_CLK>,
+			<&gcc GCC_WCSS_ACMT_CLK>,
+			<&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names =
+			"gcc_wcss_ahb_s_clk",
+			"gcc_wcss_acmt_clk",
+			"gcc_wcss_axi_m_clk";
+
+		// qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
+		interrupts-extended =
+			<&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+		status = "okay";
+	};
+};
+
+&wifi0 {
+	// IPQ5018
+	qcom,rproc = <&q6_wcss_pd1>;
+	//qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,ath11k-calibration-variant = "Linksys-MX5500";
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4c400000>;
+
+	status = "okay";
+};
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts
@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	model = "JDCloud RE-CS-03";
+	compatible = "jdcloud,re-cs-03", "qcom,ipq5018";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		sdhc1 = &sdhc_1;
+		serial0 = &blsp1_uart1;
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
+
+		led-boot = &led_red;
+		led-failsafe = &led_red;
+		led-running = &led_blue;
+		led-upgrade = &led_green;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+		bootargs-append = " swiotlb=1 coherent_pool=2M";
+	};
+
+	reserved-memory {
+		q6_mem_regions: q6_mem_regions@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 0x3900000>;
+		};
+
+		q6_code_data: q6_code_data@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 01000000>;
+		};
+
+		q6_ipq5018_data: q6_ipq5018_data@4C000000 {
+			no-map;
+			reg = <0x0 0x4C000000 0x0 0xE00000>;
+		};
+
+		m3_dump: m3_dump@4CE00000 {
+			no-map;
+			reg = <0x0 0x4CE00000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4CF00000 {
+			no-map;
+			reg = <0x0 0x4CF00000 0x0 0x100000>;
+		};
+
+		q6_caldb_region: q6_caldb_region@4D000000 {
+			no-map;
+			reg = <0x0 0x4D000000 0x0 0x200000>;
+		};
+
+		q6_qcn6122_data1: q6_qcn6122_data1@4D200000 {
+			no-map;
+			reg = <0x0 0x4D200000 0x0 0x1000000>;
+		};
+
+		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
+			no-map;
+			reg = <0x0 0x4E200000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
+			no-map;
+			reg = <0x0 0x4E300000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E400000 {
+			no-map;
+			reg = <0x0 0x4E400000 0x0 0x500000>;
+		};
+	};
+
+	soc {
+		ess-instance {
+			num_devices = <0x2>;
+
+			ess-switch@0x39c00000 {
+				compatible = "qcom,ess-switch-ipq50xx";
+				device_id = <0>;
+				switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
+				cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
+
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <1>;
+						phy_address = <7>;
+					};
+					port@1 {
+						port_id = <2>;
+						forced-speed = <1000>;
+						forced-duplex = <1>;
+					};
+				};
+			};
+
+			ess-switch1@1 {
+				compatible = "qcom,ess-switch-qca83xx";
+				device_id = <1>;
+				switch_access_mode = "mdio";
+				mdio-bus = <&mdio1>;
+				reset_gpio = <&tlmm 39 0>;
+				switch_cpu_bmp = <0x40>;  /* cpu port bitmap */
+				switch_lan_bmp = <0x1e>; /* lan port bitmap */
+				switch_wan_bmp = <0x0>;  /* wan port bitmap */
+
+				qca,ar8327-initvals = <
+						0x00004 0x7600000   /* PAD0_MODE */
+						0x00008 0x1000000   /* PAD5_MODE */
+						0x0000c 0x80        /* PAD6_MODE */
+						0x00010 0x2613a0    /* PORT6 FORCE MODE*/
+						0x000e4 0xaa545     /* MAC_POWER_SEL */
+						0x000e0 0xc74164de  /* SGMII_CTRL */
+						0x0007c 0x4e        /* PORT0_STATUS */
+						0x00094 0x4e        /* PORT6_STATUS */
+				>;
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <1>;
+						phy_address = <0>;
+					};
+					port@1 {
+						port_id = <2>;
+						phy_address = <1>;
+					};
+					port@2 {
+						port_id = <3>;
+						phy_address = <2>;
+					};
+					port@3 {
+						port_id = <4>;
+						phy_address = <3>;
+					};
+				};
+			};
+		};
+
+		dp1 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
+			clock-names = "nss-snoc-gmac-axi-clk";
+			qcom,id = <1>;
+			reg = <0x39C00000 0x10000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,mactype = <2>;
+			qcom,link-poll = <1>;
+			qcom,phy-mdio-addr = <7>;
+			mdio-bus = <&mdio0>;
+			local-mac-address = [000000000000];
+			phy-mode = "sgmii";
+			qcom,rx-page-mode = <0>;
+		};
+
+		dp2 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
+			clock-names = "nss-snoc-gmac-axi-clk";
+			qcom,id = <2>;
+			reg = <0x39D00000 0x10000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,mactype = <2>;
+			local-mac-address = [000000000000];
+			phy-mode = "sgmii";
+			qcom,rx-page-mode = <0>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+
+		led_blue: status_blue {
+			label = "blue:status";
+			gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_green: status_green {
+			label = "green:status";
+			gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_red: status_red {
+			label = "red:status";
+			gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&blsp1_uart1 {
+	status = "ok";
+};
+
+&mdio0 {
+	status = "ok";
+
+	ethernet-phy@0 {
+		reg = <7>;
+	};
+};
+
+&mdio1 {
+	pinctrl-0 = <&mdio1_pins>;
+	pinctrl-names = "default";
+	phy-reset-gpio = <&tlmm 39 0>;
+	status = "ok";
+
+	ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	ethernet-phy@3 {
+		reg = <3>;
+	};
+};
+
+&q6v5_wcss {
+	compatible = "qcom,ipq5018-q6-mpd";
+	firmware = "IPQ5018/q6_fw.mdt";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	reg = <0x0cd00000 0x4040>,
+	      <0x1938000 0x8>,
+	      <0x193d204 0x4>;
+	reg-names = "qdsp6",
+		    "tcsr-msip",
+		    "tcsr-q6";
+	resets = <&gcc GCC_WCSSAON_RESET>,
+		 <&gcc GCC_WCSS_Q6_BCR>;
+
+	reset-names = "wcss_aon_reset",
+		      "wcss_q6_reset";
+
+	clocks = <&gcc GCC_Q6_AXIS_CLK>,
+		 <&gcc GCC_WCSS_ECAHB_CLK>,
+		 <&gcc GCC_Q6_AXIM_CLK>,
+		 <&gcc GCC_Q6_AXIM2_CLK>,
+		 <&gcc GCC_Q6_AHB_CLK>,
+		 <&gcc GCC_Q6_AHB_S_CLK>,
+		 <&gcc GCC_WCSS_AXI_S_CLK>;
+	clock-names = "gcc_q6_axis_clk",
+		      "gcc_wcss_ecahb_clk",
+		      "gcc_q6_axim_clk",
+		      "gcc_q6_axim2_clk",
+		      "gcc_q6_ahb_clk",
+		      "gcc_q6_ahb_s_clk",
+		      "gcc_wcss_axi_s_clk";
+
+	memory-region = <&q6_mem_regions>, <&q6_etr_region>,
+			<&q6_caldb_region>;
+
+	qcom,rproc = <&q6v5_wcss>;
+	qcom,bootargs_smem = <507>;
+	boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
+		    <0x2 0x4 0x2 0x12 0x0 0x0>;
+
+	q6_wcss_pd1: remoteproc_pd1@4ab000 {
+		compatible = "qcom,ipq5018-wcss-ahb-mpd";
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "IPQ5018/m3_fw.mdt";
+
+		reg = <0x4ab000 0x20>;
+		reg-names = "rmb";
+
+		interrupts-extended = <&wcss_smp2p_in 8 0>,
+				      <&wcss_smp2p_in 9 0>,
+				      <&wcss_smp2p_in 12 0>,
+				      <&wcss_smp2p_in 11 0>;
+		interrupt-names = "fatal",
+				  "ready",
+				  "spawn-ack",
+				  "stop-ack";
+
+		resets = <&gcc GCC_WCSSAON_RESET>,
+			 <&gcc GCC_WCSS_BCR>,
+			 <&gcc GCC_CE_BCR>;
+		reset-names = "wcss_aon_reset",
+			      "wcss_reset",
+			      "ce_reset";
+
+		clocks = <&gcc GCC_WCSS_AHB_S_CLK>,
+			 <&gcc GCC_WCSS_ACMT_CLK>,
+			 <&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names = "gcc_wcss_ahb_s_clk",
+			      "gcc_wcss_acmt_clk",
+			      "gcc_wcss_axi_m_clk";
+
+		qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
+
+		qcom,smem-states = <&wcss_smp2p_out 8>,
+				   <&wcss_smp2p_out 9>,
+				   <&wcss_smp2p_out 10>;
+		qcom,smem-state-names = "shutdown",
+					"stop",
+					"spawn";
+		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
+				<&q6_etr_region>, <&q6_caldb_region>;
+	};
+
+	q6_wcss_pd2: remoteproc_pd2 {
+		compatible = "qcom,ipq5018-wcss-pcie-mpd";
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "qcn6122/m3_fw.mdt";
+
+		interrupts-extended = <&wcss_smp2p_in 16 0>,
+				      <&wcss_smp2p_in 17 0>,
+				      <&wcss_smp2p_in 20 0>,
+				      <&wcss_smp2p_in 19 0>;
+		interrupt-names = "fatal",
+				  "ready",
+				  "spawn-ack",
+				  "stop-ack";
+
+		qcom,smem-states = <&wcss_smp2p_out 16>,
+				   <&wcss_smp2p_out 17>,
+				   <&wcss_smp2p_out 18>;
+		qcom,smem-state-names = "shutdown",
+					"stop",
+					"spawn";
+		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
+				<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
+	};
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&tlmm {
+	button_pins: button_pins {
+		mux {
+			pins = "gpio25", "gpio38";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	leds_pins: leds_pins {
+		mux {
+			pins = "gpio31", "gpio32", "gpio33";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-low;
+		};
+	};
+
+	mdio1_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_1 {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	emmc_pins: emmc_pins {
+		emmc_clk {
+			pins = "gpio9";
+			function = "sdc1_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		emmc_cmd {
+			pins = "gpio8";
+			function = "sdc1_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		emmc_data {
+			pins = "gpio4", "gpio5", "gpio6", "gpio7";
+			function = "sdc1_data";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+};
+
+&wifi0 {
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,board_id = <0x24>;
+	qcom,bdf-addr = <0x0 0x4C000000 0x4C000000 0x0 0x0>;
+	qcom,caldb-addr = <0x0 0x4D000000 0 0 0>;
+	mem-region = <&q6_ipq5018_data>;
+	qcom,caldb-size = <0x200000>;
+	status = "ok";
+};
+
+&wifi1 {
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
+	qcom,rproc = <&q6_wcss_pd2>;
+	qcom,tgt-mem-mode = <1>;
+	qcom,board_id = <0x60>;
+	qcom,bdf-addr = <0x0 0x4D200000 0x4CF00000 0x0 0x0>;
+	qcom,caldb-addr = <0x0 0x4E400000 0 0 0>;
+	mem-region = <&q6_qcn6122_data1>;
+	qcom,caldb-size = <0x500000>;
+	status = "ok";
+};
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@ -0,0 +1,515 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5018 SoC device tree source
+ *
+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <0x80000>;
+			cache-unified;
+		};
+	};
+
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-ipq5018", "qcom,scm";
+			qcom,sdi-enabled;
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x40000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		bootloader@4a800000 {
+			reg = <0x0 0x4a800000 0x0 0x200000>;
+			no-map;
+		};
+
+		sbl@4aa00000 {
+			reg = <0x0 0x4aa00000 0x0 0x100000>;
+			no-map;
+		};
+
+		smem@4ab00000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x4ab00000 0x0 0x100000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		tz_region: tz@4ac00000 {
+			reg = <0x0 0x4ac00000 0x0 0x200000>;
+			no-map;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+
+		usbphy0: phy@5b000 {
+			compatible = "qcom,ipq5018-usb-hsphy";
+			reg = <0x0005b000 0x120>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+		
+		mdio0: mdio@88000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio";
+			reg = <0x88000 0x64>;
+			resets = <&gcc GCC_GEPHY_MDC_SW_ARES>,
+				 <&gcc GCC_GEPHY_DSP_HW_ARES>;
+			clocks = <&gcc GCC_MDIO0_AHB_CLK>;
+			clock-names = "gcc_mdio_ahb_clk";
+			status = "disabled";
+
+			gephy: ethernet-phy@7 {
+				#clock-cells = <1>;
+				reg = <7>;
+				resets = <&gcc GCC_GEPHY_BCR>,
+					 <&gcc GCC_GEPHY_RX_ARES>,
+					 <&gcc GCC_GEPHY_TX_ARES>;
+				clocks = <&gcc GCC_GEPHY_RX_CLK>,
+					 <&gcc GCC_GEPHY_TX_CLK>;
+			};
+		};
+
+		mdio1: mdio@90000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,ipq5018-mdio";
+			reg = <0x90000 0x64>;
+			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
+			clock-names = "gcc_mdio_ahb_clk";
+			status = "disabled";
+		};
+
+		uniphy0: eth-uniphy@98000 {
+			compatible = "qcom,ipq5018-eth-uniphy";
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+			reg = <0x98000 0x800>,
+			      <0x9b000 0x800>,
+			      <0x19475c4 0x4>;
+			reg-names = "uniphy",
+				    "cmn",
+				    "tcsr";
+			clocks = <&gcc GCC_CMN_BLK_AHB_CLK>,
+				 <&gcc GCC_CMN_BLK_SYS_CLK>,
+				 <&gcc GCC_UNIPHY_AHB_CLK>,
+				 <&gcc GCC_UNIPHY_SYS_CLK>,
+				 <&gcc GCC_UNIPHY_RX_CLK>,
+				 <&gcc GCC_UNIPHY_TX_CLK>;
+			resets = <&gcc GCC_UNIPHY_BCR>,
+				 <&gcc GCC_UNIPHY_AHB_ARES>,
+				 <&gcc GCC_UNIPHY_SYS_ARES>,
+				 <&gcc GCC_UNIPHY_RX_ARES>,
+				 <&gcc GCC_UNIPHY_TX_ARES>;
+
+			status = "disabled";
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,ipq5018-tlmm";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 47>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart1_pins: uart1-state {
+				pins = "gpio31", "gpio32", "gpio33", "gpio34";
+				function = "blsp1_uart1";
+				drive-strength = <8>;
+				bias-pull-down;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq5018";
+			reg = <0x01800000 0x80000>;
+			clocks = <&xo_board_clk>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&gephy 0>,
+				 <&gephy 1>,
+				 <&uniphy0 0>,
+				 <&uniphy0 1>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x01905000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		sdhc_1: mmc@7804000 {
+			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x7804000 0x1000>;
+			reg-names = "hc";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board_clk>;
+			clock-names = "iface", "core", "xo";
+			non-removable;
+			status = "disabled";
+		};
+
+		blsp_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1d000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		blsp1_spi1: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x078b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		usb: usb@8af8800 {
+			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
+			reg = <0x08af8800 0x400>;
+
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq";
+
+			clocks = <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			clock-names = "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			resets = <&gcc GCC_USB0_BCR>;
+
+			qcom,select-utmi-as-pipe-clk;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			status = "disabled";
+
+			usb_dwc: usb@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x08a00000 0xe000>;
+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				phy-names = "usb2-phy";
+				phys = <&usbphy0>;
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			reg = <0x0b000000 0x1000>,  /* GICD */
+			      <0x0b002000 0x2000>,  /* GICC */
+			      <0x0b001000 0x1000>,  /* GICH */
+			      <0x0b004000 0x2000>;  /* GICV */
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x0b00a000 0x1ffa>;
+
+			v2m0: v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x00000000 0xff8>;
+				msi-controller;
+			};
+
+			v2m1: v2m@1000 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x00001000 0xff8>;
+				msi-controller;
+			};
+		};
+
+		watchdog: watchdog@b017000 {
+			compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
+			reg = <0x0b017000 0x40>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&sleep_clk>;
+		};
+
+		apcs_glb: mailbox@b111000 {
+			compatible = "qcom,ipq5018-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
+			#mbox-cells = <1>;
+		};
+
+		a53pll: clock@b116000 {
+			compatible = "qcom,ipq5018-a53pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
+		timer@b120000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			frame@b120000 {
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <0>;
+			};
+
+			frame@b123000 {
+				reg = <0xb123000 0x1000>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <1>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b124000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				reg = <0x0b125000 0x1000>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <3>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				reg = <0x0b126000 0x1000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <4>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				reg = <0x0b127000 0x1000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <5>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				reg = <0x0b128000 0x1000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <6>;
+				status = "disabled";
+			};
+		};
+		
+		gmac0: ethernet@39c00000 {
+			compatible = "qcom,ipq50xx-gmac", "snps,dwmac";
+			reg = <0x39C00000 0x10000>;
+			clocks = <&gcc GCC_GMAC0_SYS_CLK>,
+				 <&gcc GCC_GMAC0_CFG_CLK>,
+				 <&gcc GCC_SNOC_GMAC0_AHB_CLK>,
+				 <&gcc GCC_SNOC_GMAC0_AXI_CLK>,
+				 <&gcc GCC_GMAC0_RX_CLK>,
+				 <&gcc GCC_GMAC0_TX_CLK>,
+				 <&gcc GCC_GMAC0_PTP_CLK>;
+			clock-names = "sys",
+				      "cfg",
+				      "ahb",
+				      "axi",
+				      "rx",
+				      "tx",
+				      "ptp";
+			resets = <&gcc GCC_GMAC0_BCR>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+
+			phy-handle = <&gephy>;
+			phy-mode = "sgmii";
+
+			status = "disabled";
+		};
+
+		gmac1: ethernet@39d00000 {
+			compatible = "qcom,ipq50xx-gmac", "snps,dwmac";
+			reg = <0x39D00000 0x10000>;
+			reg-names = "stmmaceth";
+			clocks = <&gcc GCC_GMAC1_SYS_CLK>,
+				 <&gcc GCC_GMAC1_CFG_CLK>,
+				 <&gcc GCC_SNOC_GMAC1_AHB_CLK>,
+				 <&gcc GCC_SNOC_GMAC1_AXI_CLK>,
+				 <&gcc GCC_GMAC1_RX_CLK>,
+				 <&gcc GCC_GMAC1_TX_CLK>,
+				 <&gcc GCC_GMAC1_PTP_CLK>;
+			clock-names = "sys",
+				      "cfg",
+				      "ahb",
+				      "axi",
+				      "rx",
+				      "tx",
+				      "ptp";
+			resets = <&gcc GCC_GMAC1_BCR>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+
+			phys = <&uniphy0>;
+			phy-names = "uniphy";
+
+			status = "disabled";
+		};		
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
--- a/target/linux/qualcommax/files/include/dt-bindings/clock/qcom,gcc-ipq5018.h
+++ b/target/linux/qualcommax/files/include/dt-bindings/clock/qcom,gcc-ipq5018.h
@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+
+#define GPLL0_MAIN					0
+#define GPLL0						1
+#define GPLL2_MAIN					2
+#define GPLL2						3
+#define GPLL4_MAIN					4
+#define GPLL4						5
+#define UBI32_PLL_MAIN					6
+#define UBI32_PLL					7
+#define ADSS_PWM_CLK_SRC				8
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			9
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			10
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			11
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			12
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC			13
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC			14
+#define BLSP1_UART1_APPS_CLK_SRC			15
+#define BLSP1_UART2_APPS_CLK_SRC			16
+#define CRYPTO_CLK_SRC					17
+#define GCC_ADSS_PWM_CLK				18
+#define GCC_BLSP1_AHB_CLK				19
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			20
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			21
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_BTSS_LPO_CLK				28
+#define GCC_CMN_BLK_AHB_CLK				29
+#define GCC_CMN_BLK_SYS_CLK				30
+#define GCC_CRYPTO_AHB_CLK				31
+#define GCC_CRYPTO_AXI_CLK				32
+#define GCC_CRYPTO_CLK					33
+#define GCC_CRYPTO_PPE_CLK				34
+#define GCC_DCC_CLK					35
+#define GCC_GEPHY_RX_CLK				36
+#define GCC_GEPHY_TX_CLK				37
+#define GCC_GMAC0_CFG_CLK				38
+#define GCC_GMAC0_PTP_CLK				39
+#define GCC_GMAC0_RX_CLK				40
+#define GCC_GMAC0_SYS_CLK				41
+#define GCC_GMAC0_TX_CLK				42
+#define GCC_GMAC1_CFG_CLK				43
+#define GCC_GMAC1_PTP_CLK				44
+#define GCC_GMAC1_RX_CLK				45
+#define GCC_GMAC1_SYS_CLK				46
+#define GCC_GMAC1_TX_CLK				47
+#define GCC_GP1_CLK					48
+#define GCC_GP2_CLK					49
+#define GCC_GP3_CLK					50
+#define GCC_LPASS_CORE_AXIM_CLK				51
+#define GCC_LPASS_SWAY_CLK				52
+#define GCC_MDIO0_AHB_CLK				53
+#define GCC_MDIO1_AHB_CLK				54
+#define GCC_PCIE0_AHB_CLK				55
+#define GCC_PCIE0_AUX_CLK				56
+#define GCC_PCIE0_AXI_M_CLK				57
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK			58
+#define GCC_PCIE0_AXI_S_CLK				59
+#define GCC_PCIE0_PIPE_CLK				60
+#define GCC_PCIE1_AHB_CLK				61
+#define GCC_PCIE1_AUX_CLK				62
+#define GCC_PCIE1_AXI_M_CLK				63
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK			64
+#define GCC_PCIE1_AXI_S_CLK				65
+#define GCC_PCIE1_PIPE_CLK				66
+#define GCC_PRNG_AHB_CLK				67
+#define GCC_Q6_AXIM_CLK					68
+#define GCC_Q6_AXIM2_CLK				69
+#define GCC_Q6_AXIS_CLK					70
+#define GCC_Q6_AHB_CLK					71
+#define GCC_Q6_AHB_S_CLK				72
+#define GCC_Q6_TSCTR_1TO2_CLK				73
+#define GCC_Q6SS_ATBM_CLK				74
+#define GCC_Q6SS_PCLKDBG_CLK				75
+#define GCC_Q6SS_TRIG_CLK				76
+#define GCC_QDSS_AT_CLK					77
+#define GCC_QDSS_CFG_AHB_CLK				78
+#define GCC_QDSS_DAP_AHB_CLK				79
+#define GCC_QDSS_DAP_CLK				80
+#define GCC_QDSS_ETR_USB_CLK				81
+#define GCC_QDSS_EUD_AT_CLK				82
+#define GCC_QDSS_STM_CLK				83
+#define GCC_QDSS_TRACECLKIN_CLK				84
+#define GCC_QDSS_TSCTR_DIV8_CLK				85
+#define GCC_QPIC_AHB_CLK				86
+#define GCC_QPIC_CLK					87
+#define GCC_QPIC_IO_MACRO_CLK				88
+#define GCC_SDCC1_AHB_CLK				89
+#define GCC_SDCC1_APPS_CLK				90
+#define GCC_SLEEP_CLK_SRC				91
+#define GCC_SNOC_GMAC0_AHB_CLK				92
+#define GCC_SNOC_GMAC0_AXI_CLK				93
+#define GCC_SNOC_GMAC1_AHB_CLK				94
+#define GCC_SNOC_GMAC1_AXI_CLK				95
+#define GCC_SNOC_LPASS_AXIM_CLK				96
+#define GCC_SNOC_LPASS_SWAY_CLK				97
+#define GCC_SNOC_UBI0_AXI_CLK				98
+#define GCC_SYS_NOC_PCIE0_AXI_CLK			99
+#define GCC_SYS_NOC_PCIE1_AXI_CLK			100
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK			101
+#define GCC_SYS_NOC_USB0_AXI_CLK			102
+#define GCC_SYS_NOC_WCSS_AHB_CLK			103
+#define GCC_UBI0_AXI_CLK				104
+#define GCC_UBI0_CFG_CLK				105
+#define GCC_UBI0_CORE_CLK				106
+#define GCC_UBI0_DBG_CLK				107
+#define GCC_UBI0_NC_AXI_CLK				108
+#define GCC_UBI0_UTCM_CLK				109
+#define GCC_UNIPHY_AHB_CLK				110
+#define GCC_UNIPHY_RX_CLK				111
+#define GCC_UNIPHY_SYS_CLK				112
+#define GCC_UNIPHY_TX_CLK				113
+#define GCC_USB0_AUX_CLK				114
+#define GCC_USB0_EUD_AT_CLK				115
+#define GCC_USB0_LFPS_CLK				116
+#define GCC_USB0_MASTER_CLK				117
+#define GCC_USB0_MOCK_UTMI_CLK				118
+#define GCC_USB0_PHY_CFG_AHB_CLK			119
+#define GCC_USB0_SLEEP_CLK				120
+#define GCC_WCSS_ACMT_CLK				121
+#define GCC_WCSS_AHB_S_CLK				122
+#define GCC_WCSS_AXI_M_CLK				123
+#define GCC_WCSS_AXI_S_CLK				124
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK			125
+#define GCC_WCSS_DBG_IFC_APB_CLK			126
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK			127
+#define GCC_WCSS_DBG_IFC_ATB_CLK			128
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK			129
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK			130
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK			131
+#define GCC_WCSS_DBG_IFC_NTS_CLK			132
+#define GCC_WCSS_ECAHB_CLK				133
+#define GCC_XO_CLK					134
+#define GCC_XO_CLK_SRC					135
+#define GMAC0_RX_CLK_SRC				136
+#define GMAC0_TX_CLK_SRC				137
+#define GMAC1_RX_CLK_SRC				138
+#define GMAC1_TX_CLK_SRC				139
+#define GMAC_CLK_SRC					140
+#define GP1_CLK_SRC					141
+#define GP2_CLK_SRC					142
+#define GP3_CLK_SRC					143
+#define LPASS_AXIM_CLK_SRC				144
+#define LPASS_SWAY_CLK_SRC				145
+#define PCIE0_AUX_CLK_SRC				146
+#define PCIE0_AXI_CLK_SRC				147
+#define PCIE1_AUX_CLK_SRC				148
+#define PCIE1_AXI_CLK_SRC				149
+#define PCNOC_BFDCD_CLK_SRC				150
+#define Q6_AXI_CLK_SRC					151
+#define QDSS_AT_CLK_SRC					152
+#define QDSS_STM_CLK_SRC				153
+#define QDSS_TSCTR_CLK_SRC				154
+#define QDSS_TRACECLKIN_CLK_SRC				155
+#define QPIC_IO_MACRO_CLK_SRC				156
+#define SDCC1_APPS_CLK_SRC				157
+#define SYSTEM_NOC_BFDCD_CLK_SRC			158
+#define UBI0_AXI_CLK_SRC				159
+#define UBI0_CORE_CLK_SRC				160
+#define USB0_AUX_CLK_SRC				161
+#define USB0_LFPS_CLK_SRC				162
+#define USB0_MASTER_CLK_SRC				163
+#define USB0_MOCK_UTMI_CLK_SRC				164
+#define WCSS_AHB_CLK_SRC				165
+#define PCIE0_PIPE_CLK_SRC				166
+#define PCIE1_PIPE_CLK_SRC				167
+#define USB0_PIPE_CLK_SRC				168
+#define GCC_USB0_PIPE_CLK				169
+#define GMAC0_RX_DIV_CLK_SRC				170
+#define GMAC0_TX_DIV_CLK_SRC				171
+#define GMAC1_RX_DIV_CLK_SRC				172
+#define GMAC1_TX_DIV_CLK_SRC				173
+#endif
--- a/target/linux/qualcommax/files/include/dt-bindings/net/qcom-ipq-ess.h
+++ b/target/linux/qualcommax/files/include/dt-bindings/net/qcom-ipq-ess.h
@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _DT_BINDINGS_NET_QCOM_IPQ_ESS_H
+#define _DT_BINDINGS_NET_QCOM_IPQ_ESS_H
+
+#define ESS_PORT0	0x1
+#define ESS_PORT1	0x2
+#define ESS_PORT2	0x4
+#define ESS_PORT3	0x8
+#define ESS_PORT4	0x10
+#define ESS_PORT5	0x20
+#define ESS_PORT6	0x40
+#define ESS_PORT7	0x80
+
+/* SSDK MAC/UNIPHY modes */
+#define MAC_MODE_PSGMII			0x0
+#define MAC_MODE_PSGMII_RGMII5		0x1
+#define MAC_MODE_SGMII0_RGMII5		0x2
+#define MAC_MODE_SGMII1_RGMII5		0x3
+#define MAC_MODE_PSGMII_RMII0		0x4
+#define MAC_MODE_PSGMII_RMII1		0x5
+#define MAC_MODE_PSGMII_RMII0_RMII1	0x6
+#define MAC_MODE_PSGMII_RGMII4		0x7
+#define MAC_MODE_SGMII0_RGMII4		0x8
+#define MAC_MODE_SGMII1_RGMII4		0x9
+#define MAC_MODE_SGMII4_RGMII4		0xa
+#define MAC_MODE_QSGMII			0xb
+#define MAC_MODE_SGMII_PLUS		0xc
+#define MAC_MODE_USXGMII		0xd
+#define MAC_MODE_10GBASE_R		0xe
+#define MAC_MODE_SGMII_CHANNEL0		0xf
+#define MAC_MODE_SGMII_CHANNEL1		0x10
+#define MAC_MODE_SGMII_CHANNEL4		0x11
+#define MAC_MODE_RGMII			0x12
+#define MAC_MODE_PSGMII_FIBER		0x13
+#define MAC_MODE_SGMII_FIBER		0x14
+#define MAC_MODE_UQXGMII		0x15
+#define MAC_MODE_UDXGMII		0x16
+#define MAC_MODE_UQXGMII_3CHANNELS	0x17
+#define MAC_MODE_DISABLED		0xff
+
+#endif /* _DT_BINDINGS_NET_QCOM_IPQ_ESS_H */
--- a/target/linux/qualcommax/files/include/dt-bindings/reset/qcom,gcc-ipq5018.h
+++ b/target/linux/qualcommax/files/include/dt-bindings/reset/qcom,gcc-ipq5018.h
@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	0
+#define GCC_BLSP1_BCR				1
+#define GCC_BLSP1_QUP1_BCR			2
+#define GCC_BLSP1_QUP2_BCR			3
+#define GCC_BLSP1_QUP3_BCR			4
+#define GCC_BLSP1_UART1_BCR			5
+#define GCC_BLSP1_UART2_BCR			6
+#define GCC_BOOT_ROM_BCR			7
+#define GCC_BTSS_BCR				8
+#define GCC_CMN_BLK_BCR				9
+#define GCC_CMN_LDO_BCR				10
+#define GCC_CE_BCR				11
+#define GCC_CRYPTO_BCR				12
+#define GCC_DCC_BCR				13
+#define GCC_DCD_BCR				14
+#define GCC_DDRSS_BCR				15
+#define GCC_EDPD_BCR				16
+#define GCC_GEPHY_BCR				17
+#define GCC_GEPHY_MDC_SW_ARES			18
+#define GCC_GEPHY_DSP_HW_ARES			19
+#define GCC_GEPHY_RX_ARES			20
+#define GCC_GEPHY_TX_ARES			21
+#define GCC_GMAC0_BCR				22
+#define GCC_GMAC0_CFG_ARES			23
+#define GCC_GMAC0_SYS_ARES			24
+#define GCC_GMAC1_BCR				25
+#define GCC_GMAC1_CFG_ARES			26
+#define GCC_GMAC1_SYS_ARES			27
+#define GCC_IMEM_BCR				28
+#define GCC_LPASS_BCR				29
+#define GCC_MDIO0_BCR				30
+#define GCC_MDIO1_BCR				31
+#define GCC_MPM_BCR				32
+#define GCC_PCIE0_BCR				33
+#define GCC_PCIE0_LINK_DOWN_BCR			34
+#define GCC_PCIE0_PHY_BCR			35
+#define GCC_PCIE0PHY_PHY_BCR			36
+#define GCC_PCIE0_PIPE_ARES			37
+#define GCC_PCIE0_SLEEP_ARES			38
+#define GCC_PCIE0_CORE_STICKY_ARES		39
+#define GCC_PCIE0_AXI_MASTER_ARES		40
+#define GCC_PCIE0_AXI_SLAVE_ARES		41
+#define GCC_PCIE0_AHB_ARES			42
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES	43
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		44
+#define GCC_PCIE1_BCR				45
+#define GCC_PCIE1_LINK_DOWN_BCR			46
+#define GCC_PCIE1_PHY_BCR			47
+#define GCC_PCIE1PHY_PHY_BCR			48
+#define GCC_PCIE1_PIPE_ARES			49
+#define GCC_PCIE1_SLEEP_ARES			50
+#define GCC_PCIE1_CORE_STICKY_ARES		51
+#define GCC_PCIE1_AXI_MASTER_ARES		52
+#define GCC_PCIE1_AXI_SLAVE_ARES		53
+#define GCC_PCIE1_AHB_ARES			54
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES	55
+#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES		56
+#define GCC_PCNOC_BCR				57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR		58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR		59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR		60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR		61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR		62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR		63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR		64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR		65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR		66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR		67
+#define GCC_PCNOC_BUS_TIMEOUT10_BCR		68
+#define GCC_PCNOC_BUS_TIMEOUT11_BCR		69
+#define GCC_PRNG_BCR				70
+#define GCC_Q6SS_DBG_ARES			71
+#define GCC_Q6_AHB_S_ARES			72
+#define GCC_Q6_AHB_ARES				73
+#define GCC_Q6_AXIM2_ARES			74
+#define GCC_Q6_AXIM_ARES			75
+#define GCC_Q6_AXIS_ARES			76
+#define GCC_QDSS_BCR				77
+#define GCC_QPIC_BCR				78
+#define GCC_QUSB2_0_PHY_BCR			79
+#define GCC_SDCC1_BCR				80
+#define GCC_SEC_CTRL_BCR			81
+#define GCC_SPDM_BCR				82
+#define GCC_SYSTEM_NOC_BCR			83
+#define GCC_TCSR_BCR				84
+#define GCC_TLMM_BCR				85
+#define GCC_UBI0_AXI_ARES			86
+#define GCC_UBI0_AHB_ARES			87
+#define GCC_UBI0_NC_AXI_ARES			88
+#define GCC_UBI0_DBG_ARES			89
+#define GCC_UBI0_UTCM_ARES			90
+#define GCC_UBI0_CORE_ARES			91
+#define GCC_UBI32_BCR				92
+#define GCC_UNIPHY_BCR				93
+#define GCC_UNIPHY_AHB_ARES			94
+#define GCC_UNIPHY_SYS_ARES			95
+#define GCC_UNIPHY_RX_ARES			96
+#define GCC_UNIPHY_TX_ARES			97
+#define GCC_USB0_BCR				98
+#define GCC_USB0_PHY_BCR			99
+#define GCC_WCSS_BCR				100
+#define GCC_WCSS_DBG_ARES			101
+#define GCC_WCSS_ECAHB_ARES			102
+#define GCC_WCSS_ACMT_ARES			103
+#define GCC_WCSS_DBG_BDG_ARES			104
+#define GCC_WCSS_AHB_S_ARES			105
+#define GCC_WCSS_AXI_M_ARES			106
+#define GCC_WCSS_AXI_S_ARES			107
+#define GCC_WCSS_Q6_BCR				108
+#define GCC_WCSSAON_RESET			109
+#define GCC_UNIPHY_SOFT_RESET			110
+#define GCC_GEPHY_MISC_ARES			111
+
+#endif
--- a/target/linux/qualcommax/patches-6.1/0029-v6.12-dt-bindings-arm-qcom-ids-Add-missing-IDs-for-IPQ-family.patch
+++ b/target/linux/qualcommax/patches-6.1/0029-v6.12-dt-bindings-arm-qcom-ids-Add-missing-IDs-for-IPQ-family.patch
@ -0,0 +1,253 @@
+--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
+@@ -11,40 +11,70 @@
+  * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for
+  * older chipsets (qcom,msm-id) and in socinfo driver:
+  */
+#define QCOM_ID_MSM8260			70
+#define QCOM_ID_MSM8660			71
+#define QCOM_ID_APQ8060			86
+ #define QCOM_ID_MSM8960			87
+ #define QCOM_ID_APQ8064			109
+#define QCOM_ID_MSM8930			116
+#define QCOM_ID_MSM8630			117
+#define QCOM_ID_MSM8230			118
+#define QCOM_ID_APQ8030			119
+#define QCOM_ID_MSM8627			120
+#define QCOM_ID_MSM8227			121
+ #define QCOM_ID_MSM8660A		122
+ #define QCOM_ID_MSM8260A		123
+ #define QCOM_ID_APQ8060A		124
+ #define QCOM_ID_MSM8974			126
+#define QCOM_ID_MSM8225			127
+#define QCOM_ID_MSM8625			129
+ #define QCOM_ID_MPQ8064			130
+ #define QCOM_ID_MSM8960AB		138
+ #define QCOM_ID_APQ8060AB		139
+ #define QCOM_ID_MSM8260AB		140
+ #define QCOM_ID_MSM8660AB		141
+#define QCOM_ID_MSM8930AA		142
+#define QCOM_ID_MSM8630AA		143
+#define QCOM_ID_MSM8230AA		144
+ #define QCOM_ID_MSM8626			145
+ #define QCOM_ID_MSM8610			147
+ #define QCOM_ID_APQ8064AB		153
+#define QCOM_ID_MSM8930AB		154
+#define QCOM_ID_MSM8630AB		155
+#define QCOM_ID_MSM8230AB		156
+#define QCOM_ID_APQ8030AB		157
+ #define QCOM_ID_MSM8226			158
+ #define QCOM_ID_MSM8526			159
+#define QCOM_ID_APQ8030AA		160
+ #define QCOM_ID_MSM8110			161
+ #define QCOM_ID_MSM8210			162
+ #define QCOM_ID_MSM8810			163
+ #define QCOM_ID_MSM8212			164
+ #define QCOM_ID_MSM8612			165
+ #define QCOM_ID_MSM8112			166
+#define QCOM_ID_MSM8125			167
+ #define QCOM_ID_MSM8225Q		168
+ #define QCOM_ID_MSM8625Q		169
+ #define QCOM_ID_MSM8125Q		170
+ #define QCOM_ID_APQ8064AA		172
+ #define QCOM_ID_APQ8084			178
+#define QCOM_ID_MSM8130			179
+#define QCOM_ID_MSM8130AA		180
+#define QCOM_ID_MSM8130AB		181
+#define QCOM_ID_MSM8627AA		182
+#define QCOM_ID_MSM8227AA		183
+ #define QCOM_ID_APQ8074			184
+ #define QCOM_ID_MSM8274			185
+ #define QCOM_ID_MSM8674			186
+#define QCOM_ID_MDM9635			187
+ #define QCOM_ID_MSM8974PRO_AC		194
+ #define QCOM_ID_MSM8126			198
+ #define QCOM_ID_APQ8026			199
+ #define QCOM_ID_MSM8926			200
+#define QCOM_ID_IPQ8062			201
+#define QCOM_ID_IPQ8064			202
+#define QCOM_ID_IPQ8066			203
+#define QCOM_ID_IPQ8068			204
+ #define QCOM_ID_MSM8326			205
+ #define QCOM_ID_MSM8916			206
+ #define QCOM_ID_MSM8994			207
+@@ -68,32 +98,74 @@
+ #define QCOM_ID_MSM8510			225
+ #define QCOM_ID_MSM8512			226
+ #define QCOM_ID_MSM8936			233
+#define QCOM_ID_MDM9640			234
+ #define QCOM_ID_MSM8939			239
+ #define QCOM_ID_APQ8036			240
+ #define QCOM_ID_APQ8039			241
+#define QCOM_ID_MSM8236			242
+#define QCOM_ID_MSM8636			243
+#define QCOM_ID_MSM8909			245
+ #define QCOM_ID_MSM8996			246
+ #define QCOM_ID_APQ8016			247
+ #define QCOM_ID_MSM8216			248
+ #define QCOM_ID_MSM8116			249
+ #define QCOM_ID_MSM8616			250
+ #define QCOM_ID_MSM8992			251
+#define QCOM_ID_APQ8092			252
+ #define QCOM_ID_APQ8094			253
+#define QCOM_ID_MSM8209			258
+#define QCOM_ID_MSM8208			259
+#define QCOM_ID_MDM9209			260
+#define QCOM_ID_MDM9309			261
+#define QCOM_ID_MDM9609			262
+#define QCOM_ID_MSM8239			263
+#define QCOM_ID_MSM8952			264
+#define QCOM_ID_APQ8009			265
+#define QCOM_ID_MSM8956			266
+#define QCOM_ID_MSM8929			268
+#define QCOM_ID_MSM8629			269
+#define QCOM_ID_MSM8229			270
+#define QCOM_ID_APQ8029			271
+#define QCOM_ID_APQ8056			274
+#define QCOM_ID_MSM8609			275
+#define QCOM_ID_APQ8076			277
+#define QCOM_ID_MSM8976			278
+#define QCOM_ID_MDM9650			279
+#define QCOM_ID_IPQ8065			280
+#define QCOM_ID_IPQ8069			281
+#define QCOM_ID_MDM9655			283
+#define QCOM_ID_MDM9250			284
+#define QCOM_ID_MDM9255			285
+#define QCOM_ID_MDM9350			286
+#define QCOM_ID_APQ8052			289
+ #define QCOM_ID_MDM9607			290
+ #define QCOM_ID_APQ8096			291
+ #define QCOM_ID_MSM8998			292
+ #define QCOM_ID_MSM8953			293
+#define QCOM_ID_MSM8937			294
+#define QCOM_ID_APQ8037			295
+ #define QCOM_ID_MDM8207			296
+ #define QCOM_ID_MDM9207			297
+ #define QCOM_ID_MDM9307			298
+ #define QCOM_ID_MDM9628			299
+#define QCOM_ID_MSM8909W		300
+#define QCOM_ID_APQ8009W		301
+#define QCOM_ID_MSM8996L		302
+#define QCOM_ID_MSM8917			303
+ #define QCOM_ID_APQ8053			304
+ #define QCOM_ID_MSM8996SG		305
+#define QCOM_ID_APQ8017			307
+#define QCOM_ID_MSM8217			308
+#define QCOM_ID_MSM8617			309
+ #define QCOM_ID_MSM8996AU		310
+ #define QCOM_ID_APQ8096AU		311
+ #define QCOM_ID_APQ8096SG		312
+#define QCOM_ID_MSM8940			313
+#define QCOM_ID_SDX201			314
+ #define QCOM_ID_SDM660			317
+ #define QCOM_ID_SDM630			318
+ #define QCOM_ID_APQ8098			319
+#define QCOM_ID_MSM8920			320
+ #define QCOM_ID_SDM845			321
+ #define QCOM_ID_MDM9206			322
+ #define QCOM_ID_IPQ8074			323
+@@ -101,7 +173,11 @@
+ #define QCOM_ID_SDM658			325
+ #define QCOM_ID_SDA658			326
+ #define QCOM_ID_SDA630			327
+#define QCOM_ID_MSM8905			331
+#define QCOM_ID_SDX202			333
+#define QCOM_ID_SDM670			336
+ #define QCOM_ID_SDM450			338
+#define QCOM_ID_SM8150			339
+ #define QCOM_ID_SDA845			341
+ #define QCOM_ID_IPQ8072			342
+ #define QCOM_ID_IPQ8076			343
+@@ -111,9 +187,17 @@
+ #define QCOM_ID_SDM632			349
+ #define QCOM_ID_SDA632			350
+ #define QCOM_ID_SDA450			351
+#define QCOM_ID_SDM439			353
+#define QCOM_ID_SDM429			354
+ #define QCOM_ID_SM8250			356
+#define QCOM_ID_SA8155			362
+#define QCOM_ID_SDA439			363
+#define QCOM_ID_SDA429			364
+#define QCOM_ID_SM7150			365
+#define QCOM_ID_SM7150P			366
+ #define QCOM_ID_IPQ8070			375
+ #define QCOM_ID_IPQ8071			376
+#define QCOM_ID_QM215			386
+ #define QCOM_ID_IPQ8072A		389
+ #define QCOM_ID_IPQ8074A		390
+ #define QCOM_ID_IPQ8076A		391
+@@ -126,11 +210,21 @@
+ #define QCOM_ID_IPQ8174			399
+ #define QCOM_ID_IPQ6018			402
+ #define QCOM_ID_IPQ6028			403
+#define QCOM_ID_SDM429W			416
+#define QCOM_ID_SM4250			417
+ #define QCOM_ID_IPQ6000			421
+ #define QCOM_ID_IPQ6010			422
+ #define QCOM_ID_SC7180			425
+ #define QCOM_ID_SM6350			434
+#define QCOM_ID_QCM2150			436
+#define QCOM_ID_SDA429W			437
+ #define QCOM_ID_SM8350			439
+#define QCOM_ID_QCM2290			441
+#define QCOM_ID_SM7125			443
+#define QCOM_ID_SM6115			444
+#define QCOM_ID_IPQ5010			446
+#define QCOM_ID_IPQ5018			447
+#define QCOM_ID_IPQ5028			448
+ #define QCOM_ID_SC8280XP		449
+ #define QCOM_ID_IPQ6005			453
+ #define QCOM_ID_QRB5165			455
+@@ -138,11 +232,52 @@
+ #define QCOM_ID_SM7225			459
+ #define QCOM_ID_SA8295P			460
+ #define QCOM_ID_SA8540P			461
+#define QCOM_ID_QCM4290			469
+#define QCOM_ID_QCS4290			470
+#define QCOM_ID_SM7325			475
+ #define QCOM_ID_SM8450_2		480
+ #define QCOM_ID_SM8450_3		482
+ #define QCOM_ID_SC7280			487
+ #define QCOM_ID_SC7180P			495
+#define QCOM_ID_QCM6490			497
+#define QCOM_ID_SM7325P			499
+#define QCOM_ID_IPQ5000			503
+#define QCOM_ID_IPQ0509			504
+#define QCOM_ID_IPQ0518			505
+ #define QCOM_ID_SM6375			507
+#define QCOM_ID_IPQ9514			510
+#define QCOM_ID_IPQ9550			511
+#define QCOM_ID_IPQ9554			512
+#define QCOM_ID_IPQ9570			513
+#define QCOM_ID_IPQ9574			514
+#define QCOM_ID_SM8550			519
+#define QCOM_ID_IPQ5016			520
+#define QCOM_ID_IPQ9510			521
+#define QCOM_ID_QRB4210			523
+#define QCOM_ID_QRB2210			524
+#define QCOM_ID_SM8475			530
+#define QCOM_ID_SM8475P			531
+#define QCOM_ID_SA8775P			534
+#define QCOM_ID_QRU1000			539
+#define QCOM_ID_SM8475_2		540
+#define QCOM_ID_QDU1000			545
+#define QCOM_ID_X1E80100		555
+#define QCOM_ID_SM8650			557
+#define QCOM_ID_SM4450			568
+#define QCOM_ID_QDU1010			587
+#define QCOM_ID_QRU1032			588
+#define QCOM_ID_QRU1052			589
+#define QCOM_ID_QRU1062			590
+#define QCOM_ID_IPQ5332			592
+#define QCOM_ID_IPQ5322			593
+#define QCOM_ID_IPQ5312			594
+#define QCOM_ID_IPQ5302			595
+#define QCOM_ID_QCS8550			603
+#define QCOM_ID_QCM8550			604
+#define QCOM_ID_IPQ5300			624
+#define QCOM_ID_IPQ5321			650
+#define QCOM_ID_QCS8300			674
+#define QCOM_ID_QCS8275			675
+ 
+ /*
+  * The board type and revision information, used by Qualcomm bootloaders and