mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
88 lines
2.5 KiB
Diff
88 lines
2.5 KiB
Diff
--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -60,6 +60,11 @@ static const struct parent_map gcc_xo_gp
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{ P_GPLL0_DIV2, 4 },
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};
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+static const char * const gcc_xo_gpll0[] = {
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+ "xo",
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+ "gpll0",
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+};
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+
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static const struct parent_map gcc_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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@@ -951,11 +956,6 @@ static struct clk_rcg2 blsp1_uart6_apps_
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},
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};
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-static const struct clk_parent_data gcc_xo_gpll0[] = {
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- { .fw_name = "xo" },
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- { .hw = &gpll0.clkr.hw },
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-};
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-
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static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(200000000, P_GPLL0, 4, 0, 0),
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@@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie0_axi_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie1_axi_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src =
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_ce_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4329,7 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie0_rchng_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4343,9 +4343,9 @@ static struct clk_branch gcc_pcie0_rchng
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_rchng_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_rchng_clk_src.clkr.hw,
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- },
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+ .parent_names = (const char *[]){
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+ "pcie0_rchng_clk_src",
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+ },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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@@ -4361,9 +4361,9 @@ static struct clk_branch gcc_pcie0_axi_s
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_axi_s_bridge_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_axi_clk_src.clkr.hw,
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- },
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+ .parent_names = (const char *[]){
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+ "pcie0_axi_clk_src"
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+ },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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