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ipq807x: refresh 5.10 patches
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lean
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f93cd5e516
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db580cfe63
@ -1,54 +1,88 @@
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From 8d111d707f71bc17c616b0bcca327ee0a3db50e8 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 2 Nov 2020 19:03:59 +0100
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Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops
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Fix PCI-E clock related kernel oops that are causes by missing
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parent_names.
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Without the use of parent_names kernel will panic on
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clk_core_get_parent_by_index() due to a NULL pointer.
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Without this earlycon is needed to even catch the OOPS as it will reset
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the board before serial is initialized.
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Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------
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1 file changed, 5 insertions(+), 6 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
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@@ -60,6 +60,11 @@ static const struct parent_map gcc_xo_gp
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{ P_GPLL0_DIV2, 4 },
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};
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+static const char * const gcc_xo_gpll0[] = {
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+ "xo",
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+ "gpll0",
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+};
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+
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static const struct parent_map gcc_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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@@ -951,11 +956,6 @@ static struct clk_rcg2 blsp1_uart6_apps_
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},
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};
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-static const struct clk_parent_data gcc_xo_gpll0[] = {
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- { .fw_name = "xo" },
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- { .hw = &gpll0.clkr.hw },
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-};
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-
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static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(200000000, P_GPLL0, 4, 0, 0),
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@@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie0_rchng_clk_src",
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- .parent_hws = (const struct clk_hw *[]) {
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- &gpll0.clkr.hw },
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.name = "pcie0_axi_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4344,8 +4343,8 @@ static struct clk_branch gcc_pcie0_rchng
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@@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie1_axi_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src =
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_ce_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4329,7 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie0_rchng_clk_src",
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- .parent_data = gcc_xo_gpll0,
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4343,9 +4343,9 @@ static struct clk_branch gcc_pcie0_rchng
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_rchng_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_rchng_clk_src.clkr.hw,
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- },
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+ .parent_names = (const char *[]){
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+ "pcie0_rchng_clk_src",
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},
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+ },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@@ -4362,8 +4361,8 @@ static struct clk_branch gcc_pcie0_axi_s
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.ops = &clk_branch2_ops,
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@@ -4361,9 +4361,9 @@ static struct clk_branch gcc_pcie0_axi_s
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_axi_s_bridge_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_axi_clk_src.clkr.hw,
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- },
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+ .parent_names = (const char *[]){
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+ "pcie0_axi_clk_src"
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},
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+ },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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@ -86,7 +86,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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}
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/*
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@@ -302,12 +310,19 @@ static int __clk_rcg2_configure(struct c
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@@ -311,12 +319,19 @@ static int __clk_rcg2_configure(struct c
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static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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{
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int ret;
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@ -107,7 +107,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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@@ -786,7 +801,7 @@ static int clk_gfx3d_set_rate_and_parent
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@@ -796,7 +811,7 @@ static int clk_gfx3d_set_rate_and_parent
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if (ret)
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return ret;
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@ -116,7 +116,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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}
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static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
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@@ -898,7 +913,7 @@ static int clk_rcg2_shared_enable(struct
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@@ -908,7 +923,7 @@ static int clk_rcg2_shared_enable(struct
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if (ret)
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return ret;
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@ -125,7 +125,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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if (ret)
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return ret;
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@@ -929,7 +944,7 @@ static void clk_rcg2_shared_disable(stru
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@@ -939,7 +954,7 @@ static void clk_rcg2_shared_disable(stru
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regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
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@ -133,4 +133,4 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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+ update_config(rcg, true);
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clk_rcg2_clear_force_enable(hw);
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