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RK3528 is a cost down SoC with high CPU performance. However, it has poor PCIe performance (same for RK3576). Also CPU 0/1 can't get any rest due to rkbin limitation. Some code references: https://github.com/warpme/minimyth2
111 lines
3.5 KiB
Diff
111 lines
3.5 KiB
Diff
From 4ff037c13c1e7ab16362d39a59ebb8fffb929f99 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Wed, 15 Apr 2020 09:19:09 +0800
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Subject: [PATCH] mmc: dw_mmc-rockchip: add v2 tuning support
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v2 tuning will inherit pre-stage loader's phase
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settings for the first time, and do re-tune if
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necessary. Re-tune will still try the rough degrees,
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for instance, 90, 180, 270, 360 but continue to do the
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fine tuning if sample window isn't good enough.
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Change-Id: I593384ee381d09df5b9adfc29a18eb22517b2764
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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---
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drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -24,6 +24,8 @@ struct dw_mci_rockchip_priv_data {
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struct clk *sample_clk;
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int default_sample_phase;
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int num_phases;
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+ int last_degree;
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+ bool use_v2_tuning;
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};
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static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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@@ -134,6 +136,58 @@ static void dw_mci_rk3288_set_ios(struct
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#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
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(DIV_ROUND_UP((i) * 360, num_phases))
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+static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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+{
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+ struct dw_mci *host = slot->host;
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+ struct dw_mci_rockchip_priv_data *priv = host->priv;
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+ struct mmc_host *mmc = slot->mmc;
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+ u32 degrees[4] = {0, 90, 180, 270}, degree;
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+ int i;
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+ static bool inherit = true;
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+
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+ if (inherit) {
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+ inherit = false;
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+ i = clk_get_phase(priv->sample_clk) / 90;
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+ degree = degrees[i];
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+ goto done;
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+ }
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+
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+ /*
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+ * v2 only support 4 degrees in theory.
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+ * First we inherit sample phases from firmware, which should
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+ * be able work fine, at least in the first place.
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+ * If retune is needed, we search forward to pick the last
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+ * one phase from degree list and loop around until we get one.
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+ * It's impossible all 4 fixed phase won't be able to work.
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+ */
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+ for (i = 0; i < ARRAY_SIZE(degrees); i++) {
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+ degree = degrees[i] + priv->last_degree + 90;
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+ degree = degree % 360;
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+ clk_set_phase(priv->sample_clk, degree);
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+ if (mmc_send_tuning(mmc, opcode, NULL)) {
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+ /*
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+ * Tuning error, the phase is a bad phase,
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+ * then try using the calculated best phase.
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+ */
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+ dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree);
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+ degree = (degree + 180) % 360;
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+ clk_set_phase(priv->sample_clk, degree);
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+ if (!mmc_send_tuning(mmc, opcode, NULL))
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+ break;
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+ }
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+ }
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+
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+ if (i == ARRAY_SIZE(degrees)) {
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+ dev_warn(host->dev, "V2 All phases bad!");
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+ return -EIO;
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+ }
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+
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+done:
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+ dev_info(host->dev, "V2 Successfully tuned phase to %d\n", degree);
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+ priv->last_degree = degree;
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+ return 0;
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+}
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+
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static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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struct dw_mci *host = slot->host;
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@@ -157,6 +211,12 @@ static int dw_mci_rk3288_execute_tuning(
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return -EIO;
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}
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+ if (priv->use_v2_tuning) {
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+ if (!dw_mci_v2_execute_tuning(slot, opcode))
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+ return 0;
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+ /* Otherwise we continue using fine tuning */
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+ }
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+
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ranges = kmalloc_array(priv->num_phases / 2 + 1,
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sizeof(*ranges), GFP_KERNEL);
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if (!ranges)
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@@ -277,6 +337,9 @@ static int dw_mci_rk3288_parse_dt(struct
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&priv->default_sample_phase))
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priv->default_sample_phase = 0;
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+ if (of_property_read_bool(np, "rockchip,use-v2-tuning"))
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+ priv->use_v2_tuning = true;
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+
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priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
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if (IS_ERR(priv->drv_clk))
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dev_dbg(host->dev, "ciu-drive not available\n");
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