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rockchip: add basic support for RK3528(A)

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RK3528 is a cost down SoC with high CPU performance.
However, it has poor PCIe performance (same for RK3576).
Also CPU 0/1 can't get any rest due to rkbin limitation.

Some code references: https://github.com/warpme/minimyth2
This commit is contained in:
aiamadeus 2024-08-16 23:18:15 +08:00
parent 6149067618
commit be32bce9df
30 changed files with 9990 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target/linux/rockchip/armv8/config-6.1
View File

@ -97,6 +97,7 @@ CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_NVMEM=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_COMPAT=y
CONFIG_BRCMSTB_GISB_ARB=y
@ -112,6 +113,7 @@ CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3568=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
@ -135,7 +137,6 @@ CONFIG_COMPAT=y
CONFIG_COMPAT_32BIT_TIME=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
@ -160,6 +161,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
@ -200,7 +202,6 @@ CONFIG_DEVMEM=y
# CONFIG_DEVPORT is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_CMA=y
CONFIG_DMA_DIRECT_REMAP=y
@ -238,7 +239,7 @@ CONFIG_FS_POSIX_ACL=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_GENERIC_ALLOCATOR=y
@ -411,6 +412,7 @@ CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=256
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SYSFS=y
@ -462,6 +464,7 @@ CONFIG_PCI_STUB=y
CONFIG_PCS_XPCS=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_ROCKCHIP_DP=y

7
target/linux/rockchip/armv8/config-6.6
View File

@ -101,6 +101,7 @@ CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_NOTIFIERS=y
CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
@ -116,6 +117,7 @@ CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3588=y
CONFIG_CLONE_BACKWARDS=y
@ -164,6 +166,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
@ -250,7 +253,7 @@ CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
@ -432,6 +435,7 @@ CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=256
CONFIG_NVMEM=y
CONFIG_NVMEM_BLOCK=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
@ -683,7 +687,6 @@ CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_TCPM=y
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_TYPEC_WUSB3801 is not set
# CONFIG_UACCE is not set
# CONFIG_UCLAMP_TASK is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_UNINLINE_SPIN_UNLOCK=y

1406
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

1439
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3528.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

348
target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c
View File

@ -21,7 +21,7 @@
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
#define ROCKCHIP_POLL_PERIOD_US 100
#define ROCKCHIP_POLL_TIMEOUT_US 10000
#define ROCKCHIP_POLL_TIMEOUT_US 50000
#define RK_MAX_RNG_BYTE (32)
/* start of CRYPTO V1 register define */
@ -37,7 +37,8 @@
/* end of CRYPTO V1 register define */
/* start of CRYPTO V2 register define */
#define CRYPTO_V2_RNG_CTL 0x0400
#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400
#define CRYPTO_V2_RNG_CTL 0x0
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
@ -48,11 +49,69 @@
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
#define CRYPTO_V2_RNG_ENABLE BIT(1)
#define CRYPTO_V2_RNG_START BIT(0)
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
#define CRYPTO_V2_RNG_DOUT_0 0x0410
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004
#define CRYPTO_V2_RNG_DOUT_0 0x0010
/* end of CRYPTO V2 register define */
/* start of TRNG_V1 register define */
/* TRNG is no longer subordinate to the Crypto module */
#define TRNG_V1_CTRL 0x0000
#define TRNG_V1_CTRL_NOP _SBF(0, 0x00)
#define TRNG_V1_CTRL_RAND _SBF(0, 0x01)
#define TRNG_V1_CTRL_SEED _SBF(0, 0x02)
#define TRNG_V1_STAT 0x0004
#define TRNG_V1_STAT_SEEDED BIT(9)
#define TRNG_V1_STAT_GENERATING BIT(30)
#define TRNG_V1_STAT_RESEEDING BIT(31)
#define TRNG_V1_MODE 0x0008
#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00)
#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01)
#define TRNG_V1_IE 0x0010
#define TRNG_V1_IE_GLBL_EN BIT(31)
#define TRNG_V1_IE_SEED_DONE_EN BIT(1)
#define TRNG_V1_IE_RAND_RDY_EN BIT(0)
#define TRNG_V1_ISTAT 0x0014
#define TRNG_V1_ISTAT_RAND_RDY BIT(0)
/* RAND0 ~ RAND7 */
#define TRNG_V1_RAND0 0x0020
#define TRNG_V1_RAND7 0x003C
#define TRNG_V1_AUTO_RQSTS 0x0060
#define TRNG_V1_VERSION 0x00F0
#define TRNG_v1_VERSION_CODE 0x46bc
/* end of TRNG_V1 register define */
/* start of RKRNG register define */
#define RKRNG_CTRL 0x0010
#define RKRNG_CTRL_INST_REQ BIT(0)
#define RKRNG_CTRL_RESEED_REQ BIT(1)
#define RKRNG_CTRL_TEST_REQ BIT(2)
#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
#define RKRNG_STATE 0x0014
#define RKRNG_STATE_INST_ACK BIT(0)
#define RKRNG_STATE_RESEED_ACK BIT(1)
#define RKRNG_STATE_TEST_ACK BIT(2)
#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
/* DRNG_DATA_0 ~ DNG_DATA_7 */
#define RKRNG_DRNG_DATA_0 0x0070
#define RKRNG_DRNG_DATA_7 0x008C
/* end of RKRNG register define */
struct rk_rng_soc_data {
u32 default_offset;
int (*rk_rng_init)(struct hwrng *rng);
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
};
@ -99,6 +158,38 @@ static void rk_rng_cleanup(struct hwrng *rng)
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
}
static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret;
int read_len = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
if (!rk_rng->soc_data->rk_rng_read)
return -EFAULT;
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
ret = 0;
while (max > ret) {
read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
max - ret, wait);
if (read_len < 0) {
ret = read_len;
break;
}
ret += read_len;
}
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
size_t size)
{
@ -108,18 +199,12 @@ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
}
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
/* enable osc_ring to get entropy, sample period is set as 100 */
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
@ -128,10 +213,12 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
!(reg_ctrl & CRYPTO_V1_RNG_START),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US);
ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
!(reg_ctrl & CRYPTO_V1_RNG_START),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US, false,
rk_rng, CRYPTO_V1_CTRL);
if (ret < 0)
goto out;
@ -144,24 +231,15 @@ out:
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
CRYPTO_V1_CTRL);
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
/* enable osc_ring to get entropy, sample period is set as 100 */
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
@ -171,12 +249,13 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
reg_ctrl |= CRYPTO_V2_RNG_START;
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
CRYPTO_V2_RNG_CTL);
CRYPTO_V2_RNG_CTL);
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
!(reg_ctrl & CRYPTO_V2_RNG_START),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US);
ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
!(reg_ctrl & CRYPTO_V2_RNG_START),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US, false,
rk_rng, CRYPTO_V2_RNG_CTL);
if (ret < 0)
goto out;
@ -188,28 +267,188 @@ out:
/* close TRNG */
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static int trng_v1_init(struct hwrng *rng)
{
int ret;
uint32_t auto_reseed_cnt = 1000;
uint32_t reg_ctrl, status, version;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
if (version != TRNG_v1_VERSION_CODE) {
dev_err(rk_rng->dev,
"wrong trng version, expected = %08x, actual = %08x\n",
TRNG_V1_VERSION, version);
ret = -EFAULT;
goto exit;
}
status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
if (!(status & TRNG_V1_STAT_SEEDED) ||
(status & TRNG_V1_STAT_GENERATING) ||
(status & TRNG_V1_STAT_RESEEDING)) {
uint32_t mask = TRNG_V1_STAT_SEEDED |
TRNG_V1_STAT_GENERATING |
TRNG_V1_STAT_RESEEDING;
udelay(10);
/* wait for GENERATING and RESEEDING flag to clear */
read_poll_timeout(rk_rng_readl, reg_ctrl,
(reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US, false,
rk_rng, TRNG_V1_STAT);
}
/* clear ISTAT flag because trng may auto reseeding when power on */
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
ret = 0;
exit:
return ret;
}
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
.rk_rng_read = rk_rng_v1_read,
static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
/* clear ISTAT anyway */
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
/* generate 256 bit random */
rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
/*
* Generate 256 bit random data will cost 1024 clock cycles.
* Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
*/
udelay(10);
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
/* wait RAND_RDY triggered */
ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US, false,
rk_rng, TRNG_V1_ISTAT);
if (ret < 0)
goto out;
}
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
/* clear all status flag */
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
out:
/* close TRNG */
rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
return ret;
}
static int rkrng_init(struct hwrng *rng)
{
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
u32 reg = 0;
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
reg = rk_rng_readl(rk_rng, RKRNG_STATE);
rk_rng_writel(rk_rng, reg, RKRNG_STATE);
return 0;
}
static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
u32 reg_ctrl = 0;
int ret;
reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl,
(reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US);
if (ret)
goto exit;
rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret);
exit:
/* close TRNG */
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
return ret;
}
static const struct rk_rng_soc_data crypto_v1_soc_data = {
.default_offset = 0,
.rk_rng_read = crypto_v1_read,
};
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
.rk_rng_read = rk_rng_v2_read,
static const struct rk_rng_soc_data crypto_v2_soc_data = {
.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
.rk_rng_read = crypto_v2_read,
};
static const struct rk_rng_soc_data trng_v1_soc_data = {
.default_offset = 0,
.rk_rng_init = trng_v1_init,
.rk_rng_read = trng_v1_read,
};
static const struct rk_rng_soc_data rkrng_soc_data = {
.default_offset = 0,
.rk_rng_init = rkrng_init,
.rk_rng_read = rkrng_read,
};
static const struct of_device_id rk_rng_dt_match[] = {
{
.compatible = "rockchip,cryptov1-rng",
.data = (void *)&rk_rng_v1_soc_data,
.data = (void *)&crypto_v1_soc_data,
},
{
.compatible = "rockchip,cryptov2-rng",
.data = (void *)&rk_rng_v2_soc_data,
.data = (void *)&crypto_v2_soc_data,
},
{
.compatible = "rockchip,trngv1",
.data = (void *)&trng_v1_soc_data,
},
{
.compatible = "rockchip,rkrng",
.data = (void *)&rkrng_soc_data,
},
{ },
};
@ -222,6 +461,7 @@ static int rk_rng_probe(struct platform_device *pdev)
struct rk_rng *rk_rng;
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
resource_size_t map_size;
dev_dbg(&pdev->dev, "probing...\n");
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
@ -237,13 +477,27 @@ static int rk_rng_probe(struct platform_device *pdev)
rk_rng->rng.init = rk_rng_init;
rk_rng->rng.cleanup = rk_rng_cleanup,
#endif
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
rk_rng->rng.read = rk_rng_read;
rk_rng->rng.quality = 999;
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
if (IS_ERR(rk_rng->mem))
return PTR_ERR(rk_rng->mem);
/* compatible with crypto v2 module */
/*
* With old dtsi configurations, the RNG base was equal to the crypto
* base, so both drivers could not be enabled at the same time.
* RNG base = CRYPTO base + RNG offset
* (Since RK356X, RNG module is no longer belongs to CRYPTO module)
*
* With new dtsi configurations, CRYPTO regs is divided into two parts
* |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
* RNG driver and CRYPTO driver could be enabled at the same time.
*/
if (map_size > rk_rng->soc_data->default_offset)
rk_rng->mem += rk_rng->soc_data->default_offset;
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
if (rk_rng->clk_num < 0) {
dev_err(&pdev->dev, "failed to get clks property\n");
@ -253,7 +507,7 @@ static int rk_rng_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rk_rng);
pm_runtime_set_autosuspend_delay(&pdev->dev,
ROCKCHIP_AUTOSUSPEND_DELAY);
ROCKCHIP_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
@ -263,6 +517,16 @@ static int rk_rng_probe(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
}
/* for some platform need hardware operation when probe */
if (rk_rng->soc_data->rk_rng_init) {
pm_runtime_get_sync(rk_rng->dev);
ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
}
return ret;
}
@ -285,7 +549,7 @@ static int rk_rng_runtime_resume(struct device *dev)
static const struct dev_pm_ops rk_rng_pm_ops = {
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
rk_rng_runtime_resume, NULL)
rk_rng_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};

1124
target/linux/rockchip/files/drivers/clk/rockchip/clk-rk3528.c Normal file
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File diff suppressed because it is too large Load Diff

1538
target/linux/rockchip/files/drivers/pci/controller/dwc/pcie-dw-rkvendor.c Normal file
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File diff suppressed because it is too large Load Diff

269
target/linux/rockchip/files/drivers/pci/controller/dwc/rockchip-pcie-dma.h Normal file
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@ -0,0 +1,269 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*/
#ifndef __SOC_ROCKCHIP_PCIE_DMA_TRX_H
#define __SOC_ROCKCHIP_PCIE_DMA_TRX_H
#include <linux/debugfs.h>
#define PCIE_DMA_TABLE_NUM 32
#define PCIE_DMA_TRX_TYPE_NUM 3
#define PCIE_DMA_CHN0 0x0
#define PCIE_DMA_CHN1 0x1
#define PCIE_DMA_DEFAULT_CHN PCIE_DMA_CHN0
#define PCIE_DMA_DATA_SND_TABLE_OFFSET 0x0
#define PCIE_DMA_DATA_RCV_ACK_TABLE_OFFSET 0x8
#define PCIE_DMA_DATA_FREE_ACK_TABLE_OFFSET 0x10
#define PCIE_DMA_DATA_READ_REMOTE_TABLE_OFFSET 0x18
/* DMA linked list register filed */
#define PCIE_DWC_DMA_CB BIT(0)
#define PCIE_DWC_DMA_TCB BIT(1)
#define PCIE_DWC_DMA_LLP BIT(2)
#define PCIE_DWC_DMA_LIE BIT(3)
#define PCIE_DWC_DMA_RIE BIT(4)
#define PCIE_DWC_DMA_CCS BIT(8)
#define PCIE_DWC_DMA_LLE BIT(9)
#define SET_LL_32(ll, value) \
writel(value, ll)
#define SET_LL_64(ll, value) \
writeq(value, ll)
enum dma_dir {
DMA_FROM_BUS,
DMA_TO_BUS,
};
enum dma_mode {
RK_PCIE_DMA_BLOCK,
RK_PCIE_DMA_LL,
};
/**
* The Channel Control Register for read and write.
*/
union chan_ctrl_lo {
struct {
u32 cb :1; // 0
u32 tcb :1; // 1
u32 llp :1; // 2
u32 lie :1; // 3
u32 rie :1; // 4
u32 cs :2; // 5:6
u32 rsvd1 :1; // 7
u32 ccs :1; // 8
u32 llen :1; // 9
u32 b_64s :1; // 10
u32 b_64d :1; // 11
u32 pf :5; // 12:16
u32 rsvd2 :7; // 17:23
u32 sn :1; // 24
u32 ro :1; // 25
u32 td :1; // 26
u32 tc :3; // 27:29
u32 at :2; // 30:31
};
u32 asdword;
};
/**
* The Channel Control Register high part for read and write.
*/
union chan_ctrl_hi {
struct {
u32 vfenb :1; // 0
u32 vfunc :8; // 1-8
u32 rsvd0 :23; // 9-31
};
u32 asdword;
};
/**
* The Channel Weight Register.
*/
union weight {
struct {
u32 weight0 :5; // 0:4
u32 weight1 :5; // 5:9
u32 weight2 :5; // 10:14
u32 weight3 :5; // 15:19
u32 rsvd :12; // 20:31
};
u32 asdword;
};
/**
* The Doorbell Register for read and write.
*/
union db {
struct {
u32 chnl :3; // 0
u32 reserved0 :28; // 3:30
u32 stop :1; // 31
};
u32 asdword;
};
/**
* The Context Registers for read and write.
*/
struct ctx_regs {
union chan_ctrl_lo ctrllo;
union chan_ctrl_hi ctrlhi;
u32 xfersize;
u32 sarptrlo;
u32 sarptrhi;
u32 darptrlo;
u32 darptrhi;
};
/**
* The Enable Register for read and write.
*/
union enb {
struct {
u32 enb :1; // 0
u32 reserved0 :31; // 1:31
};
u32 asdword;
};
/**
* The Interrupt Status Register for read and write.
*/
union int_status {
struct {
u32 donesta :8;
u32 rsvd0 :8;
u32 abortsta :8;
u32 rsvd1 :8;
};
u32 asdword;
};
/**
* The Interrupt Clear Register for read and write.
*/
union int_clear {
struct {
u32 doneclr :8;
u32 rsvd0 :8;
u32 abortclr :8;
u32 rsvd1 :8;
};
u32 asdword;
};
struct dma_table {
u32 *descs;
int chn;
phys_addr_t phys_descs;
u32 dir;
u32 type;
struct list_head tbl_node;
union enb enb;
struct ctx_regs ctx_reg;
union weight weilo;
union weight weihi;
union db start;
phys_addr_t local;
phys_addr_t bus;
size_t buf_size;
u32 dma_mode;
};
struct rk_edma_lli {
u32 control;
u32 transfer_size;
union {
u64 reg;
struct {
u32 lsb;
u32 msb;
};
} sar;
union {
u64 reg;
struct {
u32 lsb;
u32 msb;
};
} dar;
} __packed;
struct rk_edma_llp {
u32 control;
u32 reserved;
union {
u64 reg;
struct {
u32 lsb;
u32 msb;
};
} llp;
} __packed;
struct dma_trx_obj {
struct device *dev;
int loop_count;
int loop_count_threshold;
void *local_mem_base;
phys_addr_t local_mem_start;
size_t local_mem_size;
phys_addr_t remote_mem_start;
void *region_base;
phys_addr_t region_start;
size_t region_size;
int dma_free;
unsigned long local_write_available;
unsigned long local_read_available;
unsigned long remote_write_available;
spinlock_t tbl_list_lock; /* lock dma table */
struct list_head tbl_list;
struct work_struct dma_trx_work;
wait_queue_head_t event_queue;
struct workqueue_struct *dma_trx_wq;
struct dma_table *table[PCIE_DMA_TABLE_NUM];
struct dma_table *cur;
struct hrtimer scan_timer;
int busno;
void *priv;
struct completion done;
int ref_count;
struct mutex count_mutex;
unsigned long irq_num;
struct dentry *pcie_root;
struct pcie_misc_dev *pcie_dev;
void (*start_dma_func)(struct dma_trx_obj *obj, struct dma_table *table);
void (*config_dma_func)(struct dma_table *table);
int (*get_dma_status)(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir);
int (*cb)(struct dma_trx_obj *obj, u32 chn, enum dma_dir dir);
void (*dma_debug)(struct dma_trx_obj *obj, struct dma_table *table);
ktime_t begin;
ktime_t end;
u64 cache_time_total;
u64 cache_time_avarage;
u32 buffer_size;
u32 rd_buf_size;
u32 wr_buf_size;
u32 ack_base;
u32 set_data_check_pos;
u32 set_local_idx_pos;
u32 set_buf_size_pos;
u32 set_chk_sum_pos;
u32 version;
int addr_reverse;
};
static inline struct dma_trx_obj *pcie_dw_dmatest_register(struct device *dev, bool irq_en)
{
return NULL;
}
#endif

746
target/linux/rockchip/files/include/dt-bindings/clock/rk3528-cru.h Normal file
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@ -0,0 +1,746 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
* Author: Joseph Chen <chenjh@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
/* cru-clocks indices */
/* core clocks */
#define PLL_APLL 1
#define PLL_CPLL 2
#define PLL_GPLL 3
#define PLL_PPLL 4
#define PLL_DPLL 5
#define ARMCLK 6
#define XIN_OSC0_HALF 8
#define CLK_MATRIX_50M_SRC 9
#define CLK_MATRIX_100M_SRC 10
#define CLK_MATRIX_150M_SRC 11
#define CLK_MATRIX_200M_SRC 12
#define CLK_MATRIX_250M_SRC 13
#define CLK_MATRIX_300M_SRC 14
#define CLK_MATRIX_339M_SRC 15
#define CLK_MATRIX_400M_SRC 16
#define CLK_MATRIX_500M_SRC 17
#define CLK_MATRIX_600M_SRC 18
#define CLK_UART0_SRC 19
#define CLK_UART0_FRAC 20
#define SCLK_UART0 21
#define CLK_UART1_SRC 22
#define CLK_UART1_FRAC 23
#define SCLK_UART1 24
#define CLK_UART2_SRC 25
#define CLK_UART2_FRAC 26
#define SCLK_UART2 27
#define CLK_UART3_SRC 28
#define CLK_UART3_FRAC 29
#define SCLK_UART3 30
#define CLK_UART4_SRC 31
#define CLK_UART4_FRAC 32
#define SCLK_UART4 33
#define CLK_UART5_SRC 34
#define CLK_UART5_FRAC 35
#define SCLK_UART5 36
#define CLK_UART6_SRC 37
#define CLK_UART6_FRAC 38
#define SCLK_UART6 39
#define CLK_UART7_SRC 40
#define CLK_UART7_FRAC 41
#define SCLK_UART7 42
#define CLK_I2S0_2CH_SRC 43
#define CLK_I2S0_2CH_FRAC 44
#define MCLK_I2S0_2CH_SAI_SRC 45
#define CLK_I2S3_8CH_SRC 46
#define CLK_I2S3_8CH_FRAC 47
#define MCLK_I2S3_8CH_SAI_SRC 48
#define CLK_I2S1_8CH_SRC 49
#define CLK_I2S1_8CH_FRAC 50
#define MCLK_I2S1_8CH_SAI_SRC 51
#define CLK_I2S2_2CH_SRC 52
#define CLK_I2S2_2CH_FRAC 53
#define MCLK_I2S2_2CH_SAI_SRC 54
#define CLK_SPDIF_SRC 55
#define CLK_SPDIF_FRAC 56
#define MCLK_SPDIF_SRC 57
#define DCLK_VOP_SRC0 58
#define DCLK_VOP_SRC1 59
#define CLK_HSM 60
#define CLK_CORE_SRC_ACS 63
#define CLK_CORE_SRC_PVTMUX 65
#define CLK_CORE_SRC 66
#define CLK_CORE 67
#define ACLK_M_CORE_BIU 68
#define CLK_CORE_PVTPLL_SRC 69
#define PCLK_DBG 70
#define SWCLKTCK 71
#define CLK_SCANHS_CORE 72
#define CLK_SCANHS_ACLKM_CORE 73
#define CLK_SCANHS_PCLK_DBG 74
#define CLK_SCANHS_PCLK_CPU_BIU 76
#define PCLK_CPU_ROOT 77
#define PCLK_CORE_GRF 78
#define PCLK_DAPLITE_BIU 79
#define PCLK_CPU_BIU 80
#define CLK_REF_PVTPLL_CORE 81
#define ACLK_BUS_VOPGL_ROOT 85
#define ACLK_BUS_VOPGL_BIU 86
#define ACLK_BUS_H_ROOT 87
#define ACLK_BUS_H_BIU 88
#define ACLK_BUS_ROOT 89
#define HCLK_BUS_ROOT 90
#define PCLK_BUS_ROOT 91
#define ACLK_BUS_M_ROOT 92
#define ACLK_SYSMEM_BIU 93
#define CLK_TIMER_ROOT 95
#define ACLK_BUS_BIU 96
#define HCLK_BUS_BIU 97
#define PCLK_BUS_BIU 98
#define PCLK_DFT2APB 99
#define PCLK_BUS_GRF 100
#define ACLK_BUS_M_BIU 101
#define ACLK_GIC 102
#define ACLK_SPINLOCK 103
#define ACLK_DMAC 104
#define PCLK_TIMER 105
#define CLK_TIMER0 106
#define CLK_TIMER1 107
#define CLK_TIMER2 108
#define CLK_TIMER3 109
#define CLK_TIMER4 110
#define CLK_TIMER5 111
#define PCLK_JDBCK_DAP 112
#define CLK_JDBCK_DAP 113
#define PCLK_WDT_NS 114
#define TCLK_WDT_NS 115
#define HCLK_TRNG_NS 116
#define PCLK_UART0 117
#define PCLK_DMA2DDR 123
#define ACLK_DMA2DDR 124
#define PCLK_PWM0 126
#define CLK_PWM0 127
#define CLK_CAPTURE_PWM0 128
#define PCLK_PWM1 129
#define CLK_PWM1 130
#define CLK_CAPTURE_PWM1 131
#define PCLK_SCR 134
#define ACLK_DCF 135
#define PCLK_INTMUX 138
#define CLK_PPLL_I 141
#define CLK_PPLL_MUX 142
#define CLK_PPLL_100M_MATRIX 143
#define CLK_PPLL_50M_MATRIX 144
#define CLK_REF_PCIE_INNER_PHY 145
#define CLK_REF_PCIE_100M_PHY 146
#define ACLK_VPU_L_ROOT 147
#define CLK_GMAC1_VPU_25M 148
#define CLK_PPLL_125M_MATRIX 149
#define ACLK_VPU_ROOT 150
#define HCLK_VPU_ROOT 151
#define PCLK_VPU_ROOT 152
#define ACLK_VPU_BIU 153
#define HCLK_VPU_BIU 154
#define PCLK_VPU_BIU 155
#define ACLK_VPU 156
#define HCLK_VPU 157
#define PCLK_CRU_PCIE 158
#define PCLK_VPU_GRF 159
#define HCLK_SFC 160
#define SCLK_SFC 161
#define CCLK_SRC_EMMC 163
#define HCLK_EMMC 164
#define ACLK_EMMC 165
#define BCLK_EMMC 166
#define TCLK_EMMC 167
#define PCLK_GPIO1 168
#define DBCLK_GPIO1 169
#define ACLK_VPU_L_BIU 172
#define PCLK_VPU_IOC 173
#define HCLK_SAI_I2S0 174
#define MCLK_SAI_I2S0 175
#define HCLK_SAI_I2S2 176
#define MCLK_SAI_I2S2 177
#define PCLK_ACODEC 178
#define MCLK_ACODEC_TX 179
#define PCLK_GPIO3 186
#define DBCLK_GPIO3 187
#define PCLK_SPI1 189
#define CLK_SPI1 190
#define SCLK_IN_SPI1 191
#define PCLK_UART2 192
#define PCLK_UART5 194
#define PCLK_UART6 196
#define PCLK_UART7 198
#define PCLK_I2C3 200
#define CLK_I2C3 201
#define PCLK_I2C5 202
#define CLK_I2C5 203
#define PCLK_I2C6 204
#define CLK_I2C6 205
#define ACLK_MAC_VPU 206
#define PCLK_MAC_VPU 207
#define CLK_GMAC1_RMII_VPU 209
#define CLK_GMAC1_SRC_VPU 210
#define PCLK_PCIE 215
#define CLK_PCIE_AUX 216
#define ACLK_PCIE 217
#define HCLK_PCIE_SLV 218
#define HCLK_PCIE_DBI 219
#define PCLK_PCIE_PHY 220
#define PCLK_PIPE_GRF 221
#define CLK_PIPE_USB3OTG_COMBO 230
#define CLK_UTMI_USB3OTG 232
#define CLK_PCIE_PIPE_PHY 235
#define CCLK_SRC_SDIO0 240
#define HCLK_SDIO0 241
#define CCLK_SRC_SDIO1 244
#define HCLK_SDIO1 245
#define CLK_TS_0 246
#define CLK_TS_1 247
#define PCLK_CAN2 250
#define CLK_CAN2 251
#define PCLK_CAN3 252
#define CLK_CAN3 253
#define PCLK_SARADC 256
#define CLK_SARADC 257
#define PCLK_TSADC 258
#define CLK_TSADC 259
#define CLK_TSADC_TSEN 260
#define ACLK_USB3OTG 261
#define CLK_REF_USB3OTG 262
#define CLK_SUSPEND_USB3OTG 263
#define ACLK_GPU_ROOT 269
#define PCLK_GPU_ROOT 270
#define ACLK_GPU_BIU 271
#define PCLK_GPU_BIU 272
#define ACLK_GPU 273
#define CLK_GPU_PVTPLL_SRC 274
#define ACLK_GPU_MALI 275
#define HCLK_RKVENC_ROOT 281
#define ACLK_RKVENC_ROOT 282
#define PCLK_RKVENC_ROOT 283
#define HCLK_RKVENC_BIU 284
#define ACLK_RKVENC_BIU 285
#define PCLK_RKVENC_BIU 286
#define HCLK_RKVENC 287
#define ACLK_RKVENC 288
#define CLK_CORE_RKVENC 289
#define HCLK_SAI_I2S1 290
#define MCLK_SAI_I2S1 291
#define PCLK_I2C1 292
#define CLK_I2C1 293
#define PCLK_I2C0 294
#define CLK_I2C0 295
#define CLK_UART_JTAG 296
#define PCLK_SPI0 297
#define CLK_SPI0 298
#define SCLK_IN_SPI0 299
#define PCLK_GPIO4 300
#define DBCLK_GPIO4 301
#define PCLK_RKVENC_IOC 302
#define HCLK_SPDIF 308
#define MCLK_SPDIF 309
#define HCLK_PDM 310
#define MCLK_PDM 311
#define PCLK_UART1 315
#define PCLK_UART3 317
#define PCLK_RKVENC_GRF 319
#define PCLK_CAN0 320
#define CLK_CAN0 321
#define PCLK_CAN1 322
#define CLK_CAN1 323
#define ACLK_VO_ROOT 324
#define HCLK_VO_ROOT 325
#define PCLK_VO_ROOT 326
#define ACLK_VO_BIU 327
#define HCLK_VO_BIU 328
#define PCLK_VO_BIU 329
#define HCLK_RGA2E 330
#define ACLK_RGA2E 331
#define CLK_CORE_RGA2E 332
#define HCLK_VDPP 333
#define ACLK_VDPP 334
#define CLK_CORE_VDPP 335
#define PCLK_VO_GRF 336
#define PCLK_CRU 337
#define ACLK_VOP_ROOT 338
#define ACLK_VOP_BIU 339
#define HCLK_VOP 340
#define DCLK_VOP0 341
#define DCLK_VOP1 342
#define ACLK_VOP 343
#define PCLK_HDMI 344
#define CLK_SFR_HDMI 345
#define CLK_CEC_HDMI 346
#define CLK_SPDIF_HDMI 347
#define CLK_HDMIPHY_TMDSSRC 348
#define CLK_HDMIPHY_PREP 349
#define PCLK_HDMIPHY 352
#define HCLK_HDCP_KEY 354
#define ACLK_HDCP 355
#define HCLK_HDCP 356
#define PCLK_HDCP 357
#define HCLK_CVBS 358
#define DCLK_CVBS 359
#define DCLK_4X_CVBS 360
#define ACLK_JPEG_DECODER 361
#define HCLK_JPEG_DECODER 362
#define ACLK_VO_L_ROOT 375
#define ACLK_VO_L_BIU 376
#define ACLK_MAC_VO 377
#define PCLK_MAC_VO 378
#define CLK_GMAC0_SRC 379
#define CLK_GMAC0_RMII_50M 380
#define CLK_GMAC0_TX 381
#define CLK_GMAC0_RX 382
#define ACLK_JPEG_ROOT 385
#define ACLK_JPEG_BIU 386
#define HCLK_SAI_I2S3 387
#define MCLK_SAI_I2S3 388
#define CLK_MACPHY 398
#define PCLK_VCDCPHY 399
#define PCLK_GPIO2 404
#define DBCLK_GPIO2 405
#define PCLK_VO_IOC 406
#define CCLK_SRC_SDMMC0 407
#define HCLK_SDMMC0 408
#define PCLK_OTPC_NS 411
#define CLK_SBPI_OTPC_NS 412
#define CLK_USER_OTPC_NS 413
#define CLK_HDMIHDP0 415
#define HCLK_USBHOST 416
#define HCLK_USBHOST_ARB 417
#define CLK_USBHOST_OHCI 418
#define CLK_USBHOST_UTMI 419
#define PCLK_UART4 420
#define PCLK_I2C4 422
#define CLK_I2C4 423
#define PCLK_I2C7 424
#define CLK_I2C7 425
#define PCLK_USBPHY 426
#define CLK_REF_USBPHY 427
#define HCLK_RKVDEC_ROOT 433
#define ACLK_RKVDEC_ROOT_NDFT 434
#define PCLK_DDRPHY_CRU 435
#define HCLK_RKVDEC_BIU 436
#define ACLK_RKVDEC_BIU 437
#define ACLK_RKVDEC 439
#define HCLK_RKVDEC 440
#define CLK_HEVC_CA_RKVDEC 441
#define ACLK_RKVDEC_PVTMUX_ROOT 442
#define CLK_RKVDEC_PVTPLL_SRC 443
#define PCLK_DDR_ROOT 449
#define PCLK_DDR_BIU 450
#define PCLK_DDRC 451
#define PCLK_DDRMON 452
#define CLK_TIMER_DDRMON 453
#define PCLK_MSCH_BIU 454
#define PCLK_DDR_GRF 455
#define PCLK_DDR_HWLP 456
#define PCLK_DDRPHY 457
#define CLK_MSCH_BIU 463
#define ACLK_DDR_UPCTL 464
#define CLK_DDR_UPCTL 465
#define CLK_DDRMON 466
#define ACLK_DDR_SCRAMBLE 467
#define ACLK_SPLIT 468
#define CLK_DDRC_SRC 470
#define CLK_DDR_PHY 471
#define PCLK_OTPC_S 472
#define CLK_SBPI_OTPC_S 473
#define CLK_USER_OTPC_S 474
#define PCLK_KEYREADER 475
#define PCLK_BUS_SGRF 476
#define PCLK_STIMER 477
#define CLK_STIMER0 478
#define CLK_STIMER1 479
#define PCLK_WDT_S 480
#define TCLK_WDT_S 481
#define HCLK_TRNG_S 482
#define HCLK_BOOTROM 486
#define PCLK_DCF 487
#define ACLK_SYSMEM 488
#define HCLK_TSP 489
#define ACLK_TSP 490
#define CLK_CORE_TSP 491
#define CLK_OTPC_ARB 492
#define PCLK_OTP_MASK 493
#define CLK_PMC_OTP 494
#define PCLK_PMU_ROOT 495
#define HCLK_PMU_ROOT 496
#define PCLK_I2C2 497
#define CLK_I2C2 498
#define HCLK_PMU_BIU 500
#define PCLK_PMU_BIU 501
#define FCLK_MCU 502
#define RTC_CLK_MCU 504
#define PCLK_OSCCHK 505
#define CLK_PMU_MCU_JTAG 506
#define PCLK_PMU 508
#define PCLK_GPIO0 509
#define DBCLK_GPIO0 510
#define XIN_OSC0_DIV 511
#define CLK_DEEPSLOW 512
#define CLK_DDR_FAIL_SAFE 513
#define PCLK_PMU_HP_TIMER 514
#define CLK_PMU_HP_TIMER 515
#define CLK_PMU_32K_HP_TIMER 516
#define PCLK_PMU_IOC 517
#define PCLK_PMU_CRU 518
#define PCLK_PMU_GRF 519
#define PCLK_PMU_WDT 520
#define TCLK_PMU_WDT 521
#define PCLK_PMU_MAILBOX 522
#define PCLK_SCRKEYGEN 524
#define CLK_SCRKEYGEN 525
#define CLK_PVTM_OSCCHK 526
#define CLK_REFOUT 530
#define CLK_PVTM_PMU 532
#define PCLK_PVTM_PMU 533
#define PCLK_PMU_SGRF 534
#define HCLK_PMU_SRAM 535
#define CLK_UART0 536
#define CLK_UART1 537
#define CLK_UART2 538
#define CLK_UART3 539
#define CLK_UART4 540
#define CLK_UART5 541
#define CLK_UART6 542
#define CLK_UART7 543
#define MCLK_I2S0_2CH_SAI_SRC_PRE 544
#define MCLK_I2S1_8CH_SAI_SRC_PRE 545
#define MCLK_I2S2_2CH_SAI_SRC_PRE 546
#define MCLK_I2S3_8CH_SAI_SRC_PRE 547
#define MCLK_SDPDIF_SRC_PRE 548
#define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1)
/* grf-clocks indices */
#define SCLK_SDMMC_DRV 1
#define SCLK_SDMMC_SAMPLE 2
#define SCLK_SDIO0_DRV 3
#define SCLK_SDIO0_SAMPLE 4
#define SCLK_SDIO1_DRV 5
#define SCLK_SDIO1_SAMPLE 6
#define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1)
/* scmi-clocks indices */
#define SCMI_PCLK_KEYREADER 0
#define SCMI_HCLK_KLAD 1
#define SCMI_PCLK_KLAD 2
#define SCMI_HCLK_TRNG_S 3
#define SCMI_HCLK_CRYPTO_S 4
#define SCMI_PCLK_WDT_S 5
#define SCMI_TCLK_WDT_S 6
#define SCMI_PCLK_STIMER 7
#define SCMI_CLK_STIMER0 8
#define SCMI_CLK_STIMER1 9
#define SCMI_PCLK_OTP_MASK 10
#define SCMI_PCLK_OTPC_S 11
#define SCMI_CLK_SBPI_OTPC_S 12
#define SCMI_CLK_USER_OTPC_S 13
#define SCMI_CLK_PMC_OTP 14
#define SCMI_CLK_OTPC_ARB 15
#define SCMI_CLK_CORE_TSP 16
#define SCMI_ACLK_TSP 17
#define SCMI_HCLK_TSP 18
#define SCMI_PCLK_DCF 19
#define SCMI_CLK_DDR 20
#define SCMI_CLK_CPU 21
#define SCMI_CLK_GPU 22
#define SCMI_CORE_CRYPTO 23
#define SCMI_ACLK_CRYPTO 24
#define SCMI_PKA_CRYPTO 25
#define SCMI_HCLK_CRYPTO 26
#define SCMI_CORE_CRYPTO_S 27
#define SCMI_ACLK_CRYPTO_S 28
#define SCMI_PKA_CRYPTO_S 29
#define SCMI_CORE_KLAD 30
#define SCMI_ACLK_KLAD 31
#define SCMI_HCLK_TRNG 32
// CRU_SOFTRST_CON03(Offset:0xA0C)
#define SRST_NCOREPORESET0 0x00000030
#define SRST_NCOREPORESET1 0x00000031
#define SRST_NCOREPORESET2 0x00000032
#define SRST_NCOREPORESET3 0x00000033
#define SRST_NCORESET0 0x00000034
#define SRST_NCORESET1 0x00000035
#define SRST_NCORESET2 0x00000036
#define SRST_NCORESET3 0x00000037
#define SRST_NL2RESET 0x00000038
#define SRST_ARESETN_M_CORE_BIU 0x00000039
#define SRST_RESETN_CORE_CRYPTO 0x0000003A
// CRU_SOFTRST_CON05(Offset:0xA14)
#define SRST_PRESETN_DBG 0x0000005D
#define SRST_POTRESETN_DBG 0x0000005E
#define SRST_NTRESETN_DBG 0x0000005F
// CRU_SOFTRST_CON06(Offset:0xA18)
#define SRST_PRESETN_CORE_GRF 0x00000062
#define SRST_PRESETN_DAPLITE_BIU 0x00000063
#define SRST_PRESETN_CPU_BIU 0x00000064
#define SRST_RESETN_REF_PVTPLL_CORE 0x00000067
// CRU_SOFTRST_CON08(Offset:0xA20)
#define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081
#define SRST_ARESETN_BUS_H_BIU 0x00000083
#define SRST_ARESETN_SYSMEM_BIU 0x00000088
#define SRST_ARESETN_BUS_BIU 0x0000008A
#define SRST_HRESETN_BUS_BIU 0x0000008B
#define SRST_PRESETN_BUS_BIU 0x0000008C
#define SRST_PRESETN_DFT2APB 0x0000008D
#define SRST_PRESETN_BUS_GRF 0x0000008F
// CRU_SOFTRST_CON09(Offset:0xA24)
#define SRST_ARESETN_BUS_M_BIU 0x00000090
#define SRST_ARESETN_GIC 0x00000091
#define SRST_ARESETN_SPINLOCK 0x00000092
#define SRST_ARESETN_DMAC 0x00000094
#define SRST_PRESETN_TIMER 0x00000095
#define SRST_RESETN_TIMER0 0x00000096
#define SRST_RESETN_TIMER1 0x00000097
#define SRST_RESETN_TIMER2 0x00000098
#define SRST_RESETN_TIMER3 0x00000099
#define SRST_RESETN_TIMER4 0x0000009A
#define SRST_RESETN_TIMER5 0x0000009B
#define SRST_PRESETN_JDBCK_DAP 0x0000009C
#define SRST_RESETN_JDBCK_DAP 0x0000009D
#define SRST_PRESETN_WDT_NS 0x0000009F
// CRU_SOFTRST_CON10(Offset:0xA28)
#define SRST_TRESETN_WDT_NS 0x000000A0
#define SRST_HRESETN_TRNG_NS 0x000000A3
#define SRST_PRESETN_UART0 0x000000A7
#define SRST_SRESETN_UART0 0x000000A8
#define SRST_RESETN_PKA_CRYPTO 0x000000AA
#define SRST_ARESETN_CRYPTO 0x000000AB
#define SRST_HRESETN_CRYPTO 0x000000AC
#define SRST_PRESETN_DMA2DDR 0x000000AD
#define SRST_ARESETN_DMA2DDR 0x000000AE
// CRU_SOFTRST_CON11(Offset:0xA2C)
#define SRST_PRESETN_PWM0 0x000000B4
#define SRST_RESETN_PWM0 0x000000B5
#define SRST_PRESETN_PWM1 0x000000B7
#define SRST_RESETN_PWM1 0x000000B8
#define SRST_PRESETN_SCR 0x000000BA
#define SRST_ARESETN_DCF 0x000000BB
#define SRST_PRESETN_INTMUX 0x000000BC
// CRU_SOFTRST_CON25(Offset:0xA64)
#define SRST_ARESETN_VPU_BIU 0x00000196
#define SRST_HRESETN_VPU_BIU 0x00000197
#define SRST_PRESETN_VPU_BIU 0x00000198
#define SRST_ARESETN_VPU 0x00000199
#define SRST_HRESETN_VPU 0x0000019A
#define SRST_PRESETN_CRU_PCIE 0x0000019B
#define SRST_PRESETN_VPU_GRF 0x0000019C
#define SRST_HRESETN_SFC 0x0000019D
#define SRST_SRESETN_SFC 0x0000019E
#define SRST_CRESETN_EMMC 0x0000019F
// CRU_SOFTRST_CON26(Offset:0xA68)
#define SRST_HRESETN_EMMC 0x000001A0
#define SRST_ARESETN_EMMC 0x000001A1
#define SRST_BRESETN_EMMC 0x000001A2
#define SRST_TRESETN_EMMC 0x000001A3
#define SRST_PRESETN_GPIO1 0x000001A4
#define SRST_DBRESETN_GPIO1 0x000001A5
#define SRST_ARESETN_VPU_L_BIU 0x000001A6
#define SRST_PRESETN_VPU_IOC 0x000001A8
#define SRST_HRESETN_SAI_I2S0 0x000001A9
#define SRST_MRESETN_SAI_I2S0 0x000001AA
#define SRST_HRESETN_SAI_I2S2 0x000001AB
#define SRST_MRESETN_SAI_I2S2 0x000001AC
#define SRST_PRESETN_ACODEC 0x000001AD
// CRU_SOFTRST_CON27(Offset:0xA6C)
#define SRST_PRESETN_GPIO3 0x000001B0
#define SRST_DBRESETN_GPIO3 0x000001B1
#define SRST_PRESETN_SPI1 0x000001B4
#define SRST_RESETN_SPI1 0x000001B5
#define SRST_PRESETN_UART2 0x000001B7
#define SRST_SRESETN_UART2 0x000001B8
#define SRST_PRESETN_UART5 0x000001B9
#define SRST_SRESETN_UART5 0x000001BA
#define SRST_PRESETN_UART6 0x000001BB
#define SRST_SRESETN_UART6 0x000001BC
#define SRST_PRESETN_UART7 0x000001BD
#define SRST_SRESETN_UART7 0x000001BE
#define SRST_PRESETN_I2C3 0x000001BF
// CRU_SOFTRST_CON28(Offset:0xA70)
#define SRST_RESETN_I2C3 0x000001C0
#define SRST_PRESETN_I2C5 0x000001C1
#define SRST_RESETN_I2C5 0x000001C2
#define SRST_PRESETN_I2C6 0x000001C3
#define SRST_RESETN_I2C6 0x000001C4
#define SRST_ARESETN_MAC 0x000001C5
// CRU_SOFTRST_CON30(Offset:0xA78)
#define SRST_PRESETN_PCIE 0x000001E1
#define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2
#define SRST_RESETN_PCIE_POWER_UP 0x000001E3
#define SRST_PRESETN_PCIE_PHY 0x000001E6
#define SRST_PRESETN_PIPE_GRF 0x000001E7
// CRU_SOFTRST_CON32(Offset:0xA80)
#define SRST_HRESETN_SDIO0 0x00000202
#define SRST_HRESETN_SDIO1 0x00000204
#define SRST_RESETN_TS_0 0x00000205
#define SRST_RESETN_TS_1 0x00000206
#define SRST_PRESETN_CAN2 0x00000207
#define SRST_RESETN_CAN2 0x00000208
#define SRST_PRESETN_CAN3 0x00000209
#define SRST_RESETN_CAN3 0x0000020A
#define SRST_PRESETN_SARADC 0x0000020B
#define SRST_RESETN_SARADC 0x0000020C
#define SRST_RESETN_SARADC_PHY 0x0000020D
#define SRST_PRESETN_TSADC 0x0000020E
#define SRST_RESETN_TSADC 0x0000020F
// CRU_SOFTRST_CON33(Offset:0xA84)
#define SRST_ARESETN_USB3OTG 0x00000211
// CRU_SOFTRST_CON34(Offset:0xA88)
#define SRST_ARESETN_GPU_BIU 0x00000223
#define SRST_PRESETN_GPU_BIU 0x00000225
#define SRST_ARESETN_GPU 0x00000228
#define SRST_RESETN_REF_PVTPLL_GPU 0x00000229
// CRU_SOFTRST_CON36(Offset:0xA90)
#define SRST_HRESETN_RKVENC_BIU 0x00000243
#define SRST_ARESETN_RKVENC_BIU 0x00000244
#define SRST_PRESETN_RKVENC_BIU 0x00000245
#define SRST_HRESETN_RKVENC 0x00000246
#define SRST_ARESETN_RKVENC 0x00000247
#define SRST_RESETN_CORE_RKVENC 0x00000248
#define SRST_HRESETN_SAI_I2S1 0x00000249
#define SRST_MRESETN_SAI_I2S1 0x0000024A
#define SRST_PRESETN_I2C1 0x0000024B
#define SRST_RESETN_I2C1 0x0000024C
#define SRST_PRESETN_I2C0 0x0000024D
#define SRST_RESETN_I2C0 0x0000024E
// CRU_SOFTRST_CON37(Offset:0xA94)
#define SRST_PRESETN_SPI0 0x00000252
#define SRST_RESETN_SPI0 0x00000253
#define SRST_PRESETN_GPIO4 0x00000258
#define SRST_DBRESETN_GPIO4 0x00000259
#define SRST_PRESETN_RKVENC_IOC 0x0000025A
#define SRST_HRESETN_SPDIF 0x0000025E
#define SRST_MRESETN_SPDIF 0x0000025F
// CRU_SOFTRST_CON38(Offset:0xA98)
#define SRST_HRESETN_PDM 0x00000260
#define SRST_MRESETN_PDM 0x00000261
#define SRST_PRESETN_UART1 0x00000262
#define SRST_SRESETN_UART1 0x00000263
#define SRST_PRESETN_UART3 0x00000264
#define SRST_SRESETN_UART3 0x00000265
#define SRST_PRESETN_RKVENC_GRF 0x00000266
#define SRST_PRESETN_CAN0 0x00000267
#define SRST_RESETN_CAN0 0x00000268
#define SRST_PRESETN_CAN1 0x00000269
#define SRST_RESETN_CAN1 0x0000026A
// CRU_SOFTRST_CON39(Offset:0xA9C)
#define SRST_ARESETN_VO_BIU 0x00000273
#define SRST_HRESETN_VO_BIU 0x00000274
#define SRST_PRESETN_VO_BIU 0x00000275
#define SRST_HRESETN_RGA2E 0x00000277
#define SRST_ARESETN_RGA2E 0x00000278
#define SRST_RESETN_CORE_RGA2E 0x00000279
#define SRST_HRESETN_VDPP 0x0000027A
#define SRST_ARESETN_VDPP 0x0000027B
#define SRST_RESETN_CORE_VDPP 0x0000027C
#define SRST_PRESETN_VO_GRF 0x0000027D
#define SRST_PRESETN_CRU 0x0000027F
// CRU_SOFTRST_CON40(Offset:0xAA0)
#define SRST_ARESETN_VOP_BIU 0x00000281
#define SRST_HRESETN_VOP 0x00000282
#define SRST_DRESETN_VOP0 0x00000283
#define SRST_DRESETN_VOP1 0x00000284
#define SRST_ARESETN_VOP 0x00000285
#define SRST_PRESETN_HDMI 0x00000286
#define SRST_HDMI_RESETN 0x00000287
#define SRST_PRESETN_HDMIPHY 0x0000028E
#define SRST_HRESETN_HDCP_KEY 0x0000028F
// CRU_SOFTRST_CON41(Offset:0xAA4)
#define SRST_ARESETN_HDCP 0x00000290
#define SRST_HRESETN_HDCP 0x00000291
#define SRST_PRESETN_HDCP 0x00000292
#define SRST_HRESETN_CVBS 0x00000293
#define SRST_DRESETN_CVBS_VOP 0x00000294
#define SRST_DRESETN_4X_CVBS_VOP 0x00000295
#define SRST_ARESETN_JPEG_DECODER 0x00000296
#define SRST_HRESETN_JPEG_DECODER 0x00000297
#define SRST_ARESETN_VO_L_BIU 0x00000299
#define SRST_ARESETN_MAC_VO 0x0000029A
// CRU_SOFTRST_CON42(Offset:0xAA8)
#define SRST_ARESETN_JPEG_BIU 0x000002A0
#define SRST_HRESETN_SAI_I2S3 0x000002A1
#define SRST_MRESETN_SAI_I2S3 0x000002A2
#define SRST_RESETN_MACPHY 0x000002A3
#define SRST_PRESETN_VCDCPHY 0x000002A4
#define SRST_PRESETN_GPIO2 0x000002A5
#define SRST_DBRESETN_GPIO2 0x000002A6
#define SRST_PRESETN_VO_IOC 0x000002A7
#define SRST_HRESETN_SDMMC0 0x000002A9
#define SRST_PRESETN_OTPC_NS 0x000002AB
#define SRST_RESETN_SBPI_OTPC_NS 0x000002AC
#define SRST_RESETN_USER_OTPC_NS 0x000002AD
// CRU_SOFTRST_CON43(Offset:0xAAC)
#define SRST_RESETN_HDMIHDP0 0x000002B2
#define SRST_HRESETN_USBHOST 0x000002B3
#define SRST_HRESETN_USBHOST_ARB 0x000002B4
#define SRST_RESETN_HOST_UTMI 0x000002B6
#define SRST_PRESETN_UART4 0x000002B7
#define SRST_SRESETN_UART4 0x000002B8
#define SRST_PRESETN_I2C4 0x000002B9
#define SRST_RESETN_I2C4 0x000002BA
#define SRST_PRESETN_I2C7 0x000002BB
#define SRST_RESETN_I2C7 0x000002BC
#define SRST_PRESETN_USBPHY 0x000002BD
#define SRST_RESETN_USBPHY_POR 0x000002BE
#define SRST_RESETN_USBPHY_OTG 0x000002BF
// CRU_SOFTRST_CON44(Offset:0xAB0)
#define SRST_RESETN_USBPHY_HOST 0x000002C0
#define SRST_PRESETN_DDRPHY_CRU 0x000002C4
#define SRST_HRESETN_RKVDEC_BIU 0x000002C6
#define SRST_ARESETN_RKVDEC_BIU 0x000002C7
#define SRST_ARESETN_RKVDEC 0x000002C8
#define SRST_HRESETN_RKVDEC 0x000002C9
#define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB
#define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC
// CRU_SOFTRST_CON45(Offset:0xAB4)
#define SRST_PRESETN_DDR_BIU 0x000002D1
#define SRST_PRESETN_DDRC 0x000002D2
#define SRST_PRESETN_DDRMON 0x000002D3
#define SRST_RESETN_TIMER_DDRMON 0x000002D4
#define SRST_PRESETN_MSCH_BIU 0x000002D5
#define SRST_PRESETN_DDR_GRF 0x000002D6
#define SRST_PRESETN_DDR_HWLP 0x000002D8
#define SRST_PRESETN_DDRPHY 0x000002D9
#define SRST_RESETN_MSCH_BIU 0x000002DA
#define SRST_ARESETN_DDR_UPCTL 0x000002DB
#define SRST_RESETN_DDR_UPCTL 0x000002DC
#define SRST_RESETN_DDRMON 0x000002DD
#define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE
#define SRST_ARESETN_SPLIT 0x000002DF
// CRU_SOFTRST_CON46(Offset:0xAB8)
#define SRST_RESETN_DDR_PHY 0x000002E0
#endif

18
target/linux/rockchip/files/include/dt-bindings/power/rk3528-power.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__
#define __DT_BINDINGS_POWER_RK3528_POWER_H__
/**
* RK3528 idle id Summary.
*/
#define RK3528_PD_PMU 0
#define RK3528_PD_BUS 1
#define RK3528_PD_DDR 2
#define RK3528_PD_MSCH 3
#define RK3528_PD_GPU 4
#define RK3528_PD_RKVDEC 5
#define RK3528_PD_RKVENC 6
#define RK3528_PD_VO 7
#define RK3528_PD_VPU 8
#endif

269
target/linux/rockchip/patches-6.1/301-pinctrl-rockchip-add-rk3528-support.patch Normal file
View File

@ -0,0 +1,269 @@
From ee5af82a6f88fd28849ea6d98cf43fbe9cbbbb19 Mon Sep 17 00:00:00 2001
From: Steven Liu <steven.liu@rock-chips.com>
Date: Thu, 11 Aug 2022 15:15:28 +0800
Subject: [PATCH] pinctrl: rockchip: add rk3528 support
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536
---
drivers/pinctrl/pinctrl-rockchip.c | 196 ++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 196 insertions(+), 1 deletion(-)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2019,6 +2019,150 @@ static int rk3568_calc_pull_reg_and_bit(
return 0;
}
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+ return 0;
+}
+
#define RK3568_DRV_PMU_OFFSET 0x70
#define RK3568_DRV_GRF_OFFSET 0x200
#define RK3568_DRV_BITS_PER_PIN 8
@@ -2342,6 +2486,10 @@ static int rockchip_set_drive_perpin(str
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
+ } else if (ctrl->type == RK3528) {
+ rmask_bits = RK3528_DRV_BITS_PER_PIN;
+ ret = (1 << (strength + 1)) - 1;
+ goto config;
} else if (ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
@@ -2482,6 +2630,7 @@ static int rockchip_get_pull(struct rock
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -2541,6 +2690,7 @@ static int rockchip_set_pull(struct rock
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -2806,6 +2956,7 @@ static bool rockchip_pinconf_pull_valid(
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -3931,6 +4082,49 @@ static struct rockchip_pin_ctrl rk3399_p
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .label = "RK3528-GPIO",
+ .type = RK3528,
+ .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3568_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
@@ -4024,6 +4218,8 @@ static const struct of_device_id rockchi
.data = &rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
.data = &rk3399_pin_ctrl },
+ { .compatible = "rockchip,rk3528-pinctrl",
+ .data = &rk3528_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
RK3328,
RK3368,
RK3399,
+ RK3528,
RK3568,
RK3588,
};

353
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@ -0,0 +1,353 @@
From 1e244fb37e21ce92a32b203cb030510bc3b42d29 Mon Sep 17 00:00:00 2001
From: Shaohan Yao <shaohan.yao@rock-chips.com>
Date: Fri, 9 Sep 2022 14:34:08 +0800
Subject: [PATCH] thermal: rockchip: Support the rk3528 SoC in thermal driver
There are one Temperature Sensor on rk3528, channel 0 is for chip.
Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15
---
drivers/thermal/rockchip_thermal.c | 107 +++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -180,32 +180,55 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_CON 0x04
#define TSADCV2_INT_EN 0x08
#define TSADCV2_INT_PD 0x0c
+#define TSADCV3_AUTO_SRC_CON 0x0c
+#define TSADCV3_HT_INT_EN 0x14
+#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
+#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
+#define TSADCV3_INT_PD 0x24
+#define TSADCV3_HSHUT_PD 0x28
#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
+#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
+#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
+#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
#define TSADCV2_AUTO_PERIOD 0x68
#define TSADCV2_AUTO_PERIOD_HT 0x6c
+#define TSADCV3_AUTO_PERIOD 0x154
+#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV9_Q_MAX 0x210
+#define TSADCV9_FLOW_CON 0x218
#define TSADCV2_AUTO_EN BIT(0)
+#define TSADCV2_AUTO_EN_MASK BIT(16)
#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
+#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
+#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
+#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
+#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
+#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
+#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
+#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
#define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
#define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
#define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
@@ -213,6 +236,9 @@ struct rockchip_thermal_data {
#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -223,6 +249,8 @@ struct rockchip_thermal_data {
#define PX30_GRF_SOC_CON2 0x0408
+#define RK3528_GRF_TSADC_CON 0x40030
+
#define RK3568_GRF_TSADC_CON 0x0600
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
@@ -484,6 +512,45 @@ static const struct tsadc_table rk3399_c
{TSADCV3_DATA_MASK, 125000},
};
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, -40000},
+ {1419, -40000},
+ {1427, -35000},
+ {1435, -30000},
+ {1443, -25000},
+ {1452, -20000},
+ {1460, -15000},
+ {1468, -10000},
+ {1477, -5000},
+ {1486, 0},
+ {1494, 5000},
+ {1502, 10000},
+ {1510, 15000},
+ {1519, 20000},
+ {1527, 25000},
+ {1535, 30000},
+ {1544, 35000},
+ {1552, 40000},
+ {1561, 45000},
+ {1569, 50000},
+ {1578, 55000},
+ {1586, 60000},
+ {1594, 65000},
+ {1603, 70000},
+ {1612, 75000},
+ {1620, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1662, 105000},
+ {1671, 110000},
+ {1679, 115000},
+ {1688, 120000},
+ {1696, 125000},
+ {TSADCV5_DATA_MASK, 125000},
+};
+
static const struct tsadc_table rk3568_code_table[] = {
{0, -40000},
{1584, -40000},
@@ -793,6 +860,37 @@ static void rk_tsadcv7_initialize(struct
}
}
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
+ enum tshut_polarity tshut_polarity)
+{
+ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
+ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
+ regs + TSADCV3_AUTO_PERIOD_HT);
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ regs + TSADCV2_AUTO_CON);
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+ else
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(grf)) {
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
+ udelay(15);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
+ usleep_range(100, 200);
+ }
+}
+
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
@@ -809,6 +907,17 @@ static void rk_tsadcv3_irq_ack(void __io
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
}
+static void rk_tsadcv4_irq_ack(void __iomem *regs)
+{
+ u32 val;
+
+ val = readl_relaxed(regs + TSADCV3_INT_PD);
+ writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
+ val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
+ writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
+ regs + TSADCV3_HSHUT_PD);
+}
+
static void rk_tsadcv2_control(void __iomem *regs, bool enable)
{
u32 val;
@@ -844,6 +953,18 @@ static void rk_tsadcv3_control(void __io
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
}
+static void rk_tsadcv4_control(void __iomem *regs, bool enable)
+{
+ u32 val;
+
+ if (enable)
+ val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
+ else
+ val = TSADCV2_AUTO_EN_MASK;
+
+ writel_relaxed(val, regs + TSADCV2_AUTO_CON);
+}
+
static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int *temp)
{
@@ -854,6 +975,16 @@ static int rk_tsadcv2_get_temp(const str
return rk_tsadcv2_code_to_temp(table, val, temp);
}
+static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int *temp)
+{
+ u32 val;
+
+ val = readl_relaxed(regs + TSADCV3_DATA(chn));
+
+ return rk_tsadcv2_code_to_temp(table, val, temp);
+}
+
static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int temp)
{
@@ -888,6 +1019,33 @@ static int rk_tsadcv2_alarm_temp(const s
return 0;
}
+static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int temp)
+{
+ u32 alarm_value;
+
+ /*
+ * In some cases, some sensors didn't need the trip points, the
+ * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
+ * in the end, ignore this case and disable the high temperature
+ * interrupt.
+ */
+ if (temp == INT_MAX) {
+ writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
+ regs + TSADCV3_HT_INT_EN);
+ return 0;
+ }
+ /* Make sure the value is valid */
+ alarm_value = rk_tsadcv2_temp_to_code(table, temp);
+ if (alarm_value == table->data_mask)
+ return -ERANGE;
+ writel_relaxed(alarm_value & table->data_mask,
+ regs + TSADCV3_COMP_INT(chn));
+ writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
+ regs + TSADCV3_HT_INT_EN);
+ return 0;
+}
+
static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int temp)
{
@@ -907,6 +1065,25 @@ static int rk_tsadcv2_tshut_temp(const s
return 0;
}
+static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int temp)
+{
+ u32 tshut_value;
+
+ /* Make sure the value is valid */
+ tshut_value = rk_tsadcv2_temp_to_code(table, temp);
+ if (tshut_value == table->data_mask)
+ return -ERANGE;
+
+ writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
+
+ /* TSHUT will be valid */
+ writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
+ regs + TSADCV3_AUTO_SRC_CON);
+
+ return 0;
+}
+
static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
enum tshut_mode mode)
{
@@ -924,6 +1101,22 @@ static void rk_tsadcv2_tshut_mode(int ch
writel_relaxed(val, regs + TSADCV2_INT_EN);
}
+static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
+ enum tshut_mode mode)
+{
+ u32 val_gpio, val_cru;
+
+ if (mode == TSHUT_MODE_GPIO) {
+ val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
+ val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
+ } else {
+ val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
+ val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
+ }
+ writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
+ writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
+}
+
static const struct rockchip_tsadc_chip px30_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1119,6 +1312,30 @@ static const struct rockchip_tsadc_chip
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .initialize = rk_tsadcv11_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv3_tshut_mode,
+
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1177,6 +1394,10 @@ static const struct of_device_id of_rock
.data = (void *)&rk3399_tsadc_data,
},
{
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (void *)&rk3528_tsadc_data,
+ },
+ {
.compatible = "rockchip,rk3568-tsadc",
.data = (void *)&rk3568_tsadc_data,
},

61
target/linux/rockchip/patches-6.1/303-soc-rockchip-power-domain-Add-always-on.patch Normal file
View File

@ -0,0 +1,61 @@
From 54d4b6b3014f3122a2235533e6511b0d6ca2cd45 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Wed, 12 Oct 2022 19:25:38 +0800
Subject: [PATCH] soc: rockchip: power-domain: Add always on configuration for
power domain
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic57f7f3a564f7d71b680e3c435d0460474b5a4a0
---
drivers/soc/rockchip/pm_domains.c | 41 +++++++++++++++++++++++--------
1 file changed, 31 insertions(+), 10 deletions(-)
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -44,6 +44,7 @@ struct rockchip_domain_info {
int pwr_w_mask;
int req_w_mask;
int repair_status_mask;
+ bool always_on;
u32 pwr_offset;
u32 req_offset;
};
@@ -527,6 +528,26 @@ static void rockchip_pd_detach_dev(struc
pm_clk_destroy(dev);
}
+static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
+{
+ int error;
+
+ if (pd->genpd.flags & GENPD_FLAG_ALWAYS_ON)
+ return 0;
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+ if (!rockchip_pmu_domain_is_on(pd)) {
+ error = rockchip_pd_power(pd, true);
+ if (error) {
+ dev_err(pd->pmu->dev,
+ "failed to power on domain '%s': %d\n",
+ pd->genpd.name, error);
+ return error;
+ }
+ }
+
+ return 0;
+}
+
static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
struct device_node *node)
{
@@ -645,6 +666,11 @@ static int rockchip_pm_add_one_domain(st
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+ if (pd_info->always_on) {
+ error = rockchip_pd_add_alwasy_on_flag(pd);
+ if (error)
+ goto err_unprepare_clocks;
+ }
pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
pmu->genpd_data.domains[id] = &pd->genpd;

103
target/linux/rockchip/patches-6.1/304-soc-rockchip-power-domain-add-rk3528-support.patch Normal file
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@ -0,0 +1,103 @@
From 2ed777fcd035089bd7996bfa09c023521ecf0e24 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Fri, 30 Sep 2022 20:11:50 +0800
Subject: [PATCH] soc: rockchip: power-domain: add power domain support for
rk3528
This driver is modified to support RK3528 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612
---
drivers/soc/rockchip/pm_domains.c | 47 +++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -30,6 +30,7 @@
#include <dt-bindings/power/rk3366-power.h>
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/power/rk3399-power.h>
+#include <dt-bindings/power/rk3528-power.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/power/rk3588-power.h>
@@ -120,6 +121,20 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
+#define DOMAIN_M_A(_name, pwr, status, req, idle, ack, always, wakeup) \
+{ \
+ .name = _name, \
+ .pwr_w_mask = (pwr) << 16, \
+ .pwr_mask = (pwr), \
+ .status_mask = (status), \
+ .req_w_mask = (req) << 16, \
+ .req_mask = (req), \
+ .idle_mask = (idle), \
+ .ack_mask = (ack), \
+ .always_on = always, \
+ .active_wakeup = wakeup, \
+}
+
#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
@@ -164,6 +179,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3528(name, pwr, req, always, wakeup) \
+ DOMAIN_M_A(name, pwr, pwr, req, req, req, always, wakeup)
+
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
@@ -1037,6 +1055,18 @@ static const struct rockchip_domain_info
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
};
+static const struct rockchip_domain_info rk3528_pm_domains[] = {
+ [RK3528_PD_PMU] = DOMAIN_RK3528("pmu", 0, BIT(0), true, false),
+ [RK3528_PD_BUS] = DOMAIN_RK3528("bus", 0, BIT(1), true, false),
+ [RK3528_PD_DDR] = DOMAIN_RK3528("ddr", 0, BIT(2), true, false),
+ [RK3528_PD_MSCH] = DOMAIN_RK3528("msch", 0, BIT(3), true, false),
+ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4), true, false),
+ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5), true, false),
+ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6), true, false),
+ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7), true, false),
+ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8), true, false),
+};
+
static const struct rockchip_domain_info rk3568_pm_domains[] = {
[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
@@ -1216,6 +1246,17 @@ static const struct rockchip_pmu_info rk
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3528_pmu = {
+ .pwr_offset = 0x1210,
+ .status_offset = 0x1230,
+ .req_offset = 0x1110,
+ .idle_offset = 0x1128,
+ .ack_offset = 0x1120,
+
+ .num_domains = ARRAY_SIZE(rk3528_pm_domains),
+ .domain_info = rk3528_pm_domains,
+};
+
static const struct rockchip_pmu_info rk3568_pmu = {
.pwr_offset = 0xa0,
.status_offset = 0x98,
@@ -1296,6 +1337,10 @@ static const struct of_device_id rockchi
.data = (void *)&rk3399_pmu,
},
{
+ .compatible = "rockchip,rk3528-power-controller",
+ .data = (void *)&rk3528_pmu,
+ },
+ {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},

177
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@ -0,0 +1,177 @@
From 16f512f1e10375dc48aa6c26cedeb7079aba01de Mon Sep 17 00:00:00 2001
From: Joseph Chen <chenjh@rock-chips.com>
Date: Sat, 13 Aug 2022 01:15:20 +0000
Subject: [PATCH] clk: rockchip: Add clock controller for the RK3528
Add the clock tree definition for the new RK3528 SoC.
gmac1 clocks are all controlled by GRF, but CRU helps to abstract
these two clocks for gmac1 since the clock source is from CRU.
The io-in clocks are module phy output clock, gating child
clocks by disabling phy output but not CRU gate.
Add gmac0 clocks.
They are all orphans if clk_gmac0_io_i is not registered by
GMAC driver. But it's fine that GMAC driver only get it but
not to set/get rate.
Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
Allowed to change parent rate.
Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
dclk_vop0 is often used for HDMI, it prefers parent clock from
clk_hdmiphy_pixel_io for better clock quality and any rate.
It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
change parent any more.
Add CLK_SET_RATE_PARENT for aclk_gpu.
Allow aclk_gpu and aclk_gpu_mali to change parent rate.
Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.
set aclk_m_core = core_clk/2.
aclk_m_core signoff is 550M, but we set div=2 for better
performance.
Add CLK_IS_CRITICAL for clk_32k.
Mainly for pvtpll during reboot stage.
Add CLK_IS_CRITICAL for all IOC clocks.
IOC doesn't share clock with GRF. The iomux can't be changed if they
are disabled.
Disable aclk_{vpu,vpu_l,vo}_root rate change
They are all shared by multiple modules, disable rate change
by modules.
Don't register clk_uart_jtag
It's for force jtag uart delay counter. It must be open
for box product without tf card but with uart0.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3528.c | 1187 +++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 28 +
4 files changed, 1223 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk3528.c
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -93,6 +93,13 @@ config CLK_RK3399
help
Build the driver for RK3399 Clock Driver.
+config CLK_RK3528
+ bool "Rockchip RK3528 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3528 Clock Driver.
+
config CLK_RK3568
bool "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_CLK_RK3308) += clk-r
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
+obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -514,6 +514,14 @@ void rockchip_clk_register_branches(stru
ctx->reg_base + list->gate_offset,
list->gate_shift, list->gate_flags, &ctx->lock);
break;
+ case branch_gate_no_set_rate:
+ flags &= ~CLK_SET_RATE_PARENT;
+
+ clk = clk_register_gate(NULL, list->name,
+ list->parent_names[0], flags,
+ ctx->reg_base + list->gate_offset,
+ list->gate_shift, list->gate_flags, &ctx->lock);
+ break;
case branch_composite:
clk = rockchip_clk_register_branch(list->name,
list->parent_names, list->num_parents,
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -207,6 +207,34 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_VPU_GRF_BASE 0x40000
+#define RK3528_VO_GRF_BASE 0x60000
+#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24)
+#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28)
+#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4)
+#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8)
+#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc)
+#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10)
+#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_GLB_CNT_TH 0xc00
+#define RK3528_GLB_SRST_FST 0xc08
+#define RK3528_GLB_SRST_SND 0xc0c
+
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
@@ -345,6 +373,7 @@ struct rockchip_pll_clock {
};
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
@@ -448,6 +477,7 @@ enum rockchip_clk_branch_type {
branch_muxgrf,
branch_divider,
branch_fraction_divider,
+ branch_gate_no_set_rate,
branch_gate,
branch_mmc,
branch_inverter,
@@ -768,6 +798,19 @@ struct rockchip_clk_branch {
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
+ .flags = f, \
+ .gate_offset = o, \
+ .gate_shift = b, \
+ .gate_flags = gf, \
+ }
+
+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \
+ { \
+ .id = _id, \
+ .branch_type = branch_gate_no_set_rate, \
+ .name = cname, \
+ .parent_names = (const char *[]){ pname }, \
+ .num_parents = 1, \
.flags = f, \
.gate_offset = o, \
.gate_shift = b, \

227
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@ -0,0 +1,227 @@
From 61c0ac431798861b0696ccc549138b2eec8a4766 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Sat, 24 Sep 2022 18:29:52 +0800
Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3528
Add constants and callback functions for the dwmac on RK3528 Soc.
As can be seen, the base structure is the same. In addition, there
is an internal phy inside with Gmac0.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 179 +++++++++++++++++-
1 file changed, 173 insertions(+), 6 deletions(-)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1142,6 +1142,201 @@ static const struct rk_gmac_ops rk3399_o
.set_rmii_speed = rk3399_set_rmii_speed,
};
+#define RK3528_VO_GRF_GMAC_CON 0X60018
+#define RK3528_VPU_GRF_GMAC_CON5 0X40018
+#define RK3528_VPU_GRF_GMAC_CON6 0X4001c
+
+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+
+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
+
+#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12)
+#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12)
+
+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
+
+#define RK3528_GMAC1_CLK_RGMII_DIV1 \
+ (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV5 \
+ (GRF_BIT(11) | GRF_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV50 \
+ (GRF_BIT(11) | GRF_CLR_BIT(10))
+
+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
+
+#define RK3528_VO_GRF_MACPHY_CON0 0X6001c
+#define RK3528_VO_GRF_MACPHY_CON1 0X60020
+
+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int id = bsp_priv->id;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (id == 1)
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
+ else
+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
+ RK3528_GMAC0_PHY_INTF_SEL_RMII);
+}
+
+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int val = 0;
+
+ switch (speed) {
+ case 10:
+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case 100:
+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case 1000:
+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
+ break;
+ default:
+ goto err;
+ }
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
+ return;
+err:
+ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
+}
+
+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int val, offset, id = bsp_priv->id;
+
+ switch (speed) {
+ case 10:
+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ break;
+ case 100:
+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ break;
+ default:
+ goto err;
+ }
+
+ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
+ regmap_write(bsp_priv->grf, offset, val);
+
+ return;
+err:
+ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
+}
+
+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
+ bool input, bool enable)
+{
+ unsigned int value, id = bsp_priv->id;
+
+ if (id == 1) {
+ value = input ? RK3528_GMAC1_CLK_SELET_IO :
+ RK3528_GMAC1_CLK_SELET_CRU;
+ value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
+ RK3528_GMAC1_CLK_RMII_GATE;
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
+ } else {
+ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
+ RK3528_GMAC0_CLK_RMII_GATE;
+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
+ }
+}
+
+/* Integrated FEPHY */
+#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
+#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
+#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
+#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
+#define RK_FEPHY_PHY_ID GRF_BIT(11)
+
+#define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0)
+
+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv)
+{
+ struct device *dev = &priv->pdev->dev;
+
+ if (IS_ERR(priv->grf) || !priv->phy_reset) {
+ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
+ __func__);
+ return;
+ }
+
+ unsigned int bgs = RK_FEPHY_BGS;
+
+ reset_control_assert(priv->phy_reset);
+ udelay(20);
+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
+ RK_FEPHY_POWERUP |
+ RK_FEPHY_INTERNAL_RMII_SEL |
+ RK_FEPHY_24M_CLK_SEL |
+ RK_FEPHY_PHY_ID);
+
+ /*if (priv->otp_data > 0)
+ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);*/
+
+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
+ usleep_range(10 * 1000, 12 * 1000);
+ reset_control_deassert(priv->phy_reset);
+ usleep_range(50 * 1000, 60 * 1000);
+}
+
+static const struct rk_gmac_ops rk3528_ops = {
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_rgmii_speed = rk3528_set_rgmii_speed,
+ .set_rmii_speed = rk3528_set_rmii_speed,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .integrated_phy_powerup = rk3528_integrated_sphy_power,
+};
+
#define RK3568_GRF_GMAC0_CON0 0x0380
#define RK3568_GRF_GMAC0_CON1 0x0384
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -2107,6 +2302,7 @@ static const struct of_device_id rk_gmac
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },

64
target/linux/rockchip/patches-6.1/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch Normal file
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@ -0,0 +1,64 @@
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1597,6 +1597,53 @@ static const struct rockchip_usb2phy_cfg
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .num_ports = 2,
+ .clkout_ctl = { 0x041c, 7, 2, 0, 0x27 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x6004c, 15, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x60074, 3, 2, 0, 3 },
+ .bvalid_det_st = { 0x60078, 3, 2, 0, 3 },
+ .bvalid_det_clr = { 0x6007c, 3, 2, 0, 3 },
+ .id_det_en = { 0x60074, 5, 4, 0, 3 },
+ .id_det_st = { 0x60078, 5, 4, 0, 3 },
+ .id_det_clr = { 0x6007c, 5, 4, 0, 3 },
+ .ls_det_en = { 0x60074, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60078, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
+ .utmi_id = { 0x6006c, 6, 6, 0, 1 },
+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x6005c, 15, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x60090, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60094, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x6004c, 3, 0, 5, 1 },
+ .cp_det = { 0x6006c, 19, 19, 0, 1 },
+ .dcp_det = { 0x6006c, 18, 18, 0, 1 },
+ .dp_det = { 0x6006c, 20, 20, 0, 1 },
+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
+ .idp_src_en = { 0x60058, 2, 2, 0, 1 },
+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{
.reg = 0xfe8a0000,
@@ -1713,6 +1760,7 @@ static const struct of_device_id rockchi
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
+ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
{}

176
target/linux/rockchip/patches-6.1/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch Normal file
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@ -0,0 +1,176 @@
From 432666b59bdbef2c386e92dd88be4206203ff8ac Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sat, 8 Oct 2022 15:48:37 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: add support rk3528
1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz
Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 139 +++++++++++++++++-
1 file changed, 138 insertions(+), 1 deletion(-)
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -79,7 +79,7 @@
struct rockchip_combphy_priv;
struct combphy_reg {
- u16 offset;
+ u32 offset;
u16 bitend;
u16 bitstart;
u16 disable;
@@ -89,11 +89,13 @@ struct combphy_reg {
struct rockchip_combphy_grfcfg {
struct combphy_reg pcie_mode_set;
struct combphy_reg usb_mode_set;
+ struct combphy_reg u3otg0_port_en;
struct combphy_reg sgmii_mode_set;
struct combphy_reg qsgmii_mode_set;
struct combphy_reg pipe_rxterm_set;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_txcomp_set;
+ struct combphy_reg pipe_clk_24m;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
@@ -359,6 +361,120 @@ static int rockchip_combphy_probe(struct
return PTR_ERR_OR_ZERO(phy_provider);
}
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ unsigned long rate;
+ u32 val;
+
+ switch (priv->type) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ /* Enable adaptive CTLE for USB3.0 Rx. */
+ val = readl(priv->mmio + 0x200);
+ val &= ~GENMASK(17, 17);
+ val |= 0x01 << 17;
+ writel(val, priv->mmio + 0x200);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ rate = clk_get_rate(priv->refclk);
+
+ switch (rate) {
+ case REF_CLOCK_24MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+ if (priv->type == PHY_TYPE_USB3) {
+ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz. */
+ val = readl(priv->mmio + 0x100);
+ val &= ~GENMASK(10, 0);
+ val |= 0x17d;
+ writel(val, priv->mmio + 0x100);
+ } else if (priv->type == PHY_TYPE_PCIE) {
+ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */
+ val = readl(priv->mmio + 0x218);
+ val |= (1 << 14);
+ writel(val, priv->mmio + 0x218);
+ }
+ break;
+
+ case REF_CLOCK_100MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~(0x7 << 10);
+ val |= 0x2 << 10;
+ writel(val, priv->mmio + 0x18);
+
+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+ val = readl(priv->mmio + 0x108);
+ val &= ~(0x7f7);
+ val |= 0x4f0;
+ writel(val, priv->mmio + 0x108);
+ }
+ break;
+
+ default:
+ dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
+ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
+ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
+ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
+ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
+ /* pipe-grf */
+ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+ .grfcfg = &rk3528_combphy_grfcfgs,
+ .combphy_cfg = rk3528_combphy_cfg,
+};
+
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -561,6 +677,10 @@ static const struct rockchip_combphy_cfg
static const struct of_device_id rockchip_combphy_of_match[] = {
{
+ .compatible = "rockchip,rk3528-naneng-combphy",
+ .data = &rk3528_combphy_cfgs,
+ },
+ {
.compatible = "rockchip,rk3568-naneng-combphy",
.data = &rk3568_combphy_cfgs,
},

107
target/linux/rockchip/patches-6.1/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch Normal file
View File

@ -0,0 +1,107 @@
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -295,19 +295,20 @@ static void dwcmshc_rk3568_set_clock(str
0x3 << 19; /* post-change delay */
sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
- host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
txclk_tapnum = priv->txclk_tapnum;
- if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
- extra = DLL_CMDOUT_SRC_CLK_NEG |
- DLL_CMDOUT_EN_SRC_CLK_NEG |
- DWCMSHC_EMMC_DLL_DLYENA |
- DLL_CMDOUT_TAPNUM_90_DEGREES |
- DLL_CMDOUT_TAPNUM_FROM_SW;
- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+ if (priv->devtype != DWCMSHC_RK3568) {
+ extra = DLL_CMDOUT_SRC_CLK_NEG |
+ DLL_CMDOUT_EN_SRC_CLK_NEG |
+ DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_CMDOUT_TAPNUM_90_DEGREES |
+ DLL_CMDOUT_TAPNUM_FROM_SW;
+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+ }
}
extra = DWCMSHC_EMMC_DLL_DLYENA |
@@ -355,6 +356,15 @@ static const struct sdhci_ops sdhci_dwcm
.adma_write_desc = dwcmshc_adma_write_desc,
};
+static const struct sdhci_ops sdhci_dwcmshc_rk3528_ops = {
+ .set_clock = dwcmshc_rk3568_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .reset = rk35xx_sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+};
+
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
@@ -378,6 +388,14 @@ static const struct sdhci_pltfm_data sdh
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3528_pdata = {
+ .ops = &sdhci_dwcmshc_rk3528_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
{
int err;
@@ -443,6 +461,10 @@ static const struct of_device_id sdhci_d
.data = &sdhci_dwcmshc_rk35xx_pdata,
},
{
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = &sdhci_dwcmshc_rk3528_pdata,
+ },
+ {
.compatible = "snps,dwcmshc-sdhci",
.data = &sdhci_dwcmshc_pdata,
},
@@ -521,17 +543,18 @@ static int dwcmshc_probe(struct platform
host->mmc_host_ops.request = dwcmshc_request;
host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
- if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
+ if ((pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) ||
+ (pltfm_data == &sdhci_dwcmshc_rk3528_pdata)) {
rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
if (!rk_priv) {
err = -ENOMEM;
goto err_clk;
}
- if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
- rk_priv->devtype = DWCMSHC_RK3588;
- else
+ if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3568-dwcmshc"))
rk_priv->devtype = DWCMSHC_RK3568;
+ else
+ rk_priv->devtype = DWCMSHC_RK3588;
priv->priv = rk_priv;
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
+obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rkvendor.o
obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o

110
target/linux/rockchip/patches-6.1/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch Normal file
View File

@ -0,0 +1,110 @@
From 4ff037c13c1e7ab16362d39a59ebb8fffb929f99 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 15 Apr 2020 09:19:09 +0800
Subject: [PATCH] mmc: dw_mmc-rockchip: add v2 tuning support
v2 tuning will inherit pre-stage loader's phase
settings for the first time, and do re-tune if
necessary. Re-tune will still try the rough degrees,
for instance, 90, 180, 270, 360 but continue to do the
fine tuning if sample window isn't good enough.
Change-Id: I593384ee381d09df5b9adfc29a18eb22517b2764
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -24,6 +24,8 @@ struct dw_mci_rockchip_priv_data {
struct clk *sample_clk;
int default_sample_phase;
int num_phases;
+ int last_degree;
+ bool use_v2_tuning;
};
static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
@@ -134,6 +136,58 @@ static void dw_mci_rk3288_set_ios(struct
#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
(DIV_ROUND_UP((i) * 360, num_phases))
+static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
+{
+ struct dw_mci *host = slot->host;
+ struct dw_mci_rockchip_priv_data *priv = host->priv;
+ struct mmc_host *mmc = slot->mmc;
+ u32 degrees[4] = {0, 90, 180, 270}, degree;
+ int i;
+ static bool inherit = true;
+
+ if (inherit) {
+ inherit = false;
+ i = clk_get_phase(priv->sample_clk) / 90;
+ degree = degrees[i];
+ goto done;
+ }
+
+ /*
+ * v2 only support 4 degrees in theory.
+ * First we inherit sample phases from firmware, which should
+ * be able work fine, at least in the first place.
+ * If retune is needed, we search forward to pick the last
+ * one phase from degree list and loop around until we get one.
+ * It's impossible all 4 fixed phase won't be able to work.
+ */
+ for (i = 0; i < ARRAY_SIZE(degrees); i++) {
+ degree = degrees[i] + priv->last_degree + 90;
+ degree = degree % 360;
+ clk_set_phase(priv->sample_clk, degree);
+ if (mmc_send_tuning(mmc, opcode, NULL)) {
+ /*
+ * Tuning error, the phase is a bad phase,
+ * then try using the calculated best phase.
+ */
+ dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree);
+ degree = (degree + 180) % 360;
+ clk_set_phase(priv->sample_clk, degree);
+ if (!mmc_send_tuning(mmc, opcode, NULL))
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(degrees)) {
+ dev_warn(host->dev, "V2 All phases bad!");
+ return -EIO;
+ }
+
+done:
+ dev_info(host->dev, "V2 Successfully tuned phase to %d\n", degree);
+ priv->last_degree = degree;
+ return 0;
+}
+
static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
struct dw_mci *host = slot->host;
@@ -157,6 +211,12 @@ static int dw_mci_rk3288_execute_tuning(
return -EIO;
}
+ if (priv->use_v2_tuning) {
+ if (!dw_mci_v2_execute_tuning(slot, opcode))
+ return 0;
+ /* Otherwise we continue using fine tuning */
+ }
+
ranges = kmalloc_array(priv->num_phases / 2 + 1,
sizeof(*ranges), GFP_KERNEL);
if (!ranges)
@@ -277,6 +337,9 @@ static int dw_mci_rk3288_parse_dt(struct
&priv->default_sample_phase))
priv->default_sample_phase = 0;
+ if (of_property_read_bool(np, "rockchip,use-v2-tuning"))
+ priv->use_v2_tuning = true;
+
priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
if (IS_ERR(priv->drv_clk))
dev_dbg(host->dev, "ciu-drive not available\n");

269
target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch Normal file
View File

@ -0,0 +1,269 @@
From ee5af82a6f88fd28849ea6d98cf43fbe9cbbbb19 Mon Sep 17 00:00:00 2001
From: Steven Liu <steven.liu@rock-chips.com>
Date: Thu, 11 Aug 2022 15:15:28 +0800
Subject: [PATCH] pinctrl: rockchip: add rk3528 support
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536
---
drivers/pinctrl/pinctrl-rockchip.c | 196 ++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 196 insertions(+), 1 deletion(-)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2018,6 +2018,150 @@ static int rk3568_calc_pull_reg_and_bit(
return 0;
}
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+ return 0;
+}
+
#define RK3568_DRV_PMU_OFFSET 0x70
#define RK3568_DRV_GRF_OFFSET 0x200
#define RK3568_DRV_BITS_PER_PIN 8
@@ -2341,6 +2485,10 @@ static int rockchip_set_drive_perpin(str
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
+ } else if (ctrl->type == RK3528) {
+ rmask_bits = RK3528_DRV_BITS_PER_PIN;
+ ret = (1 << (strength + 1)) - 1;
+ goto config;
} else if (ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
@@ -2481,6 +2629,7 @@ static int rockchip_get_pull(struct rock
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -2540,6 +2689,7 @@ static int rockchip_set_pull(struct rock
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -2805,6 +2955,7 @@ static bool rockchip_pinconf_pull_valid(
case RK3328:
case RK3368:
case RK3399:
+ case RK3528:
case RK3568:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -3930,6 +4081,49 @@ static struct rockchip_pin_ctrl rk3399_p
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .label = "RK3528-GPIO",
+ .type = RK3528,
+ .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3568_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
@@ -4023,6 +4217,8 @@ static const struct of_device_id rockchi
.data = &rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
.data = &rk3399_pin_ctrl },
+ { .compatible = "rockchip,rk3528-pinctrl",
+ .data = &rk3528_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
RK3328,
RK3368,
RK3399,
+ RK3528,
RK3568,
RK3588,
};

191
target/linux/rockchip/patches-6.6/302-thermal-rockchip-add-support-for-rk3528.patch Normal file
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@ -0,0 +1,191 @@
From 1e244fb37e21ce92a32b203cb030510bc3b42d29 Mon Sep 17 00:00:00 2001
From: Shaohan Yao <shaohan.yao@rock-chips.com>
Date: Fri, 9 Sep 2022 14:34:08 +0800
Subject: [PATCH] thermal: rockchip: Support the rk3528 SoC in thermal driver
There are one Temperature Sensor on rk3528, channel 0 is for chip.
Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15
---
drivers/thermal/rockchip_thermal.c | 107 +++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -185,6 +185,8 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV3_AUTO_PERIOD 0x154
#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV9_Q_MAX 0x210
+#define TSADCV9_FLOW_CON 0x218
#define TSADCV2_AUTO_EN BIT(0)
#define TSADCV2_AUTO_EN_MASK BIT(16)
@@ -195,6 +197,7 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
@@ -208,9 +211,12 @@ struct rockchip_thermal_data {
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
#define TSADCV4_DATA_MASK 0x1ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
+#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
+#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
#define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
#define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
#define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
@@ -220,6 +226,9 @@ struct rockchip_thermal_data {
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -230,6 +239,8 @@ struct rockchip_thermal_data {
#define PX30_GRF_SOC_CON2 0x0408
+#define RK3528_GRF_TSADC_CON 0x40030
+
#define RK3568_GRF_TSADC_CON 0x0600
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
@@ -497,6 +508,45 @@ static const struct tsadc_table rk3399_c
{TSADCV3_DATA_MASK, 125000},
};
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, -40000},
+ {1419, -40000},
+ {1427, -35000},
+ {1435, -30000},
+ {1443, -25000},
+ {1452, -20000},
+ {1460, -15000},
+ {1468, -10000},
+ {1477, -5000},
+ {1486, 0},
+ {1494, 5000},
+ {1502, 10000},
+ {1510, 15000},
+ {1519, 20000},
+ {1527, 25000},
+ {1535, 30000},
+ {1544, 35000},
+ {1552, 40000},
+ {1561, 45000},
+ {1569, 50000},
+ {1578, 55000},
+ {1586, 60000},
+ {1594, 65000},
+ {1603, 70000},
+ {1612, 75000},
+ {1620, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1662, 105000},
+ {1671, 110000},
+ {1679, 115000},
+ {1688, 120000},
+ {1696, 125000},
+ {TSADCV5_DATA_MASK, 125000},
+};
+
static const struct tsadc_table rk3568_code_table[] = {
{0, -40000},
{1584, -40000},
@@ -834,6 +884,37 @@ static void rk_tsadcv8_initialize(struct
regs + TSADCV2_AUTO_CON);
}
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
+ enum tshut_polarity tshut_polarity)
+{
+ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
+ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
+ regs + TSADCV3_AUTO_PERIOD_HT);
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ regs + TSADCV2_AUTO_CON);
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+ else
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(grf)) {
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
+ udelay(15);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
+ usleep_range(100, 200);
+ }
+}
+
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
@@ -1258,6 +1339,31 @@ static const struct rockchip_tsadc_chip
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ /* cpu, gpu */
+ .chn_offset = 0,
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .initialize = rk_tsadcv11_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv3_tshut_mode,
+
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
/* cpu, gpu */
.chn_offset = 0,
@@ -1338,6 +1444,10 @@ static const struct of_device_id of_rock
.data = (void *)&rk3399_tsadc_data,
},
{
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (void *)&rk3528_tsadc_data,
+ },
+ {
.compatible = "rockchip,rk3568-tsadc",
.data = (void *)&rk3568_tsadc_data,
},

61
target/linux/rockchip/patches-6.6/303-soc-rockchip-power-domain-Add-always-on.patch Normal file
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@ -0,0 +1,61 @@
From 54d4b6b3014f3122a2235533e6511b0d6ca2cd45 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Wed, 12 Oct 2022 19:25:38 +0800
Subject: [PATCH] soc: rockchip: power-domain: Add always on configuration for
power domain
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic57f7f3a564f7d71b680e3c435d0460474b5a4a0
---
drivers/pmdomain/rockchip/pm-domains.c | 41 +++++++++++++++++++++++--------
1 file changed, 31 insertions(+), 10 deletions(-)
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -45,6 +45,7 @@ struct rockchip_domain_info {
int req_w_mask;
int mem_status_mask;
int repair_status_mask;
+ bool always_on;
u32 pwr_offset;
u32 mem_offset;
u32 req_offset;
@@ -612,6 +613,26 @@ static void rockchip_pd_detach_dev(struc
pm_clk_destroy(dev);
}
+static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
+{
+ int error;
+
+ if (pd->genpd.flags & GENPD_FLAG_ALWAYS_ON)
+ return 0;
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+ if (!rockchip_pmu_domain_is_on(pd)) {
+ error = rockchip_pd_power(pd, true);
+ if (error) {
+ dev_err(pd->pmu->dev,
+ "failed to power on domain '%s': %d\n",
+ pd->genpd.name, error);
+ return error;
+ }
+ }
+
+ return 0;
+}
+
static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
struct device_node *node)
{
@@ -730,6 +751,11 @@ static int rockchip_pm_add_one_domain(st
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+ if (pd_info->always_on) {
+ error = rockchip_pd_add_alwasy_on_flag(pd);
+ if (error)
+ goto err_unprepare_clocks;
+ }
pm_genpd_init(&pd->genpd, NULL,
!rockchip_pmu_domain_is_on(pd) ||
(pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));

103
target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch Normal file
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@ -0,0 +1,103 @@
From 2ed777fcd035089bd7996bfa09c023521ecf0e24 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Fri, 30 Sep 2022 20:11:50 +0800
Subject: [PATCH] soc: rockchip: power-domain: add power domain support for
rk3528
This driver is modified to support RK3528 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612
---
drivers/pmdomain/rockchip/pm-domains.c | 47 +++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -30,6 +30,7 @@
#include <dt-bindings/power/rk3366-power.h>
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/power/rk3399-power.h>
+#include <dt-bindings/power/rk3528-power.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/power/rk3588-power.h>
@@ -125,6 +126,20 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
+#define DOMAIN_M_A(_name, pwr, status, req, idle, ack, always, wakeup) \
+{ \
+ .name = _name, \
+ .pwr_w_mask = (pwr) << 16, \
+ .pwr_mask = (pwr), \
+ .status_mask = (status), \
+ .req_w_mask = (req) << 16, \
+ .req_mask = (req), \
+ .idle_mask = (idle), \
+ .ack_mask = (ack), \
+ .always_on = always, \
+ .active_wakeup = wakeup, \
+}
+
#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
@@ -171,6 +186,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3528(name, pwr, req, always, wakeup) \
+ DOMAIN_M_A(name, pwr, pwr, req, req, req, always, wakeup)
+
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
@@ -1125,6 +1143,18 @@ static const struct rockchip_domain_info
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
};
+static const struct rockchip_domain_info rk3528_pm_domains[] = {
+ [RK3528_PD_PMU] = DOMAIN_RK3528("pmu", 0, BIT(0), true, false),
+ [RK3528_PD_BUS] = DOMAIN_RK3528("bus", 0, BIT(1), true, false),
+ [RK3528_PD_DDR] = DOMAIN_RK3528("ddr", 0, BIT(2), true, false),
+ [RK3528_PD_MSCH] = DOMAIN_RK3528("msch", 0, BIT(3), true, false),
+ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4), true, false),
+ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5), true, false),
+ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6), true, false),
+ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7), true, false),
+ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8), true, false),
+};
+
static const struct rockchip_domain_info rk3568_pm_domains[] = {
[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
@@ -1304,6 +1334,17 @@ static const struct rockchip_pmu_info rk
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3528_pmu = {
+ .pwr_offset = 0x1210,
+ .status_offset = 0x1230,
+ .req_offset = 0x1110,
+ .idle_offset = 0x1128,
+ .ack_offset = 0x1120,
+
+ .num_domains = ARRAY_SIZE(rk3528_pm_domains),
+ .domain_info = rk3528_pm_domains,
+};
+
static const struct rockchip_pmu_info rk3568_pmu = {
.pwr_offset = 0xa0,
.status_offset = 0x98,
@@ -1387,6 +1428,10 @@ static const struct of_device_id rockchi
.data = (void *)&rk3399_pmu,
},
{
+ .compatible = "rockchip,rk3528-power-controller",
+ .data = (void *)&rk3528_pmu,
+ },
+ {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},

178
target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch Normal file
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@ -0,0 +1,178 @@
From 16f512f1e10375dc48aa6c26cedeb7079aba01de Mon Sep 17 00:00:00 2001
From: Joseph Chen <chenjh@rock-chips.com>
Date: Sat, 13 Aug 2022 01:15:20 +0000
Subject: [PATCH] clk: rockchip: Add clock controller for the RK3528
Add the clock tree definition for the new RK3528 SoC.
gmac1 clocks are all controlled by GRF, but CRU helps to abstract
these two clocks for gmac1 since the clock source is from CRU.
The io-in clocks are module phy output clock, gating child
clocks by disabling phy output but not CRU gate.
Add gmac0 clocks.
They are all orphans if clk_gmac0_io_i is not registered by
GMAC driver. But it's fine that GMAC driver only get it but
not to set/get rate.
Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
Allowed to change parent rate.
Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
dclk_vop0 is often used for HDMI, it prefers parent clock from
clk_hdmiphy_pixel_io for better clock quality and any rate.
It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
change parent any more.
Add CLK_SET_RATE_PARENT for aclk_gpu.
Allow aclk_gpu and aclk_gpu_mali to change parent rate.
Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.
set aclk_m_core = core_clk/2.
aclk_m_core signoff is 550M, but we set div=2 for better
performance.
Add CLK_IS_CRITICAL for clk_32k.
Mainly for pvtpll during reboot stage.
Add CLK_IS_CRITICAL for all IOC clocks.
IOC doesn't share clock with GRF. The iomux can't be changed if they
are disabled.
Disable aclk_{vpu,vpu_l,vo}_root rate change
They are all shared by multiple modules, disable rate change
by modules.
Don't register clk_uart_jtag
It's for force jtag uart delay counter. It must be open
for box product without tf card but with uart0.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3528.c | 1187 +++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 28 +
4 files changed, 1223 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk3528.c
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -93,6 +93,13 @@ config CLK_RK3399
help
Build the driver for RK3399 Clock Driver.
+config CLK_RK3528
+ bool "Rockchip RK3528 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3528 Clock Driver.
+
config CLK_RK3568
bool "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -27,5 +27,6 @@ obj-$(CONFIG_CLK_RK3308) += clk-r
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
+obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -509,6 +509,14 @@ void rockchip_clk_register_branches(stru
ctx->reg_base + list->gate_offset,
list->gate_shift, list->gate_flags, &ctx->lock);
break;
+ case branch_gate_no_set_rate:
+ flags &= ~CLK_SET_RATE_PARENT;
+
+ clk = clk_register_gate(NULL, list->name,
+ list->parent_names[0], flags,
+ ctx->reg_base + list->gate_offset,
+ list->gate_shift, list->gate_flags, &ctx->lock);
+ break;
case branch_composite:
clk = rockchip_clk_register_branch(list->name,
list->parent_names, list->num_parents,
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -207,6 +207,34 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_VPU_GRF_BASE 0x40000
+#define RK3528_VO_GRF_BASE 0x60000
+#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24)
+#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28)
+#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4)
+#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8)
+#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc)
+#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10)
+#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_GLB_CNT_TH 0xc00
+#define RK3528_GLB_SRST_FST 0xc08
+#define RK3528_GLB_SRST_SND 0xc0c
+
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
@@ -408,6 +436,7 @@ struct rockchip_pll_clock {
};
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
@@ -516,6 +545,7 @@ enum rockchip_clk_branch_type {
branch_muxgrf,
branch_divider,
branch_fraction_divider,
+ branch_gate_no_set_rate,
branch_gate,
branch_mmc,
branch_inverter,
@@ -836,6 +866,19 @@ struct rockchip_clk_branch {
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
+ .flags = f, \
+ .gate_offset = o, \
+ .gate_shift = b, \
+ .gate_flags = gf, \
+ }
+
+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \
+ { \
+ .id = _id, \
+ .branch_type = branch_gate_no_set_rate, \
+ .name = cname, \
+ .parent_names = (const char *[]){ pname }, \
+ .num_parents = 1, \
.flags = f, \
.gate_offset = o, \
.gate_shift = b, \

227
target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch Normal file
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@ -0,0 +1,227 @@
From 61c0ac431798861b0696ccc549138b2eec8a4766 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Sat, 24 Sep 2022 18:29:52 +0800
Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3528
Add constants and callback functions for the dwmac on RK3528 Soc.
As can be seen, the base structure is the same. In addition, there
is an internal phy inside with Gmac0.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 179 +++++++++++++++++-
1 file changed, 173 insertions(+), 6 deletions(-)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1142,6 +1142,201 @@ static const struct rk_gmac_ops rk3399_o
.set_rmii_speed = rk3399_set_rmii_speed,
};
+#define RK3528_VO_GRF_GMAC_CON 0X60018
+#define RK3528_VPU_GRF_GMAC_CON5 0X40018
+#define RK3528_VPU_GRF_GMAC_CON6 0X4001c
+
+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+
+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
+
+#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12)
+#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12)
+
+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
+
+#define RK3528_GMAC1_CLK_RGMII_DIV1 \
+ (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV5 \
+ (GRF_BIT(11) | GRF_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV50 \
+ (GRF_BIT(11) | GRF_CLR_BIT(10))
+
+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
+
+#define RK3528_VO_GRF_MACPHY_CON0 0X6001c
+#define RK3528_VO_GRF_MACPHY_CON1 0X60020
+
+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int id = bsp_priv->id;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (id == 1)
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
+ else
+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
+ RK3528_GMAC0_PHY_INTF_SEL_RMII);
+}
+
+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int val = 0;
+
+ switch (speed) {
+ case 10:
+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case 100:
+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case 1000:
+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
+ break;
+ default:
+ goto err;
+ }
+
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
+ return;
+err:
+ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
+}
+
+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int val, offset, id = bsp_priv->id;
+
+ switch (speed) {
+ case 10:
+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ break;
+ case 100:
+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ break;
+ default:
+ goto err;
+ }
+
+ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
+ regmap_write(bsp_priv->grf, offset, val);
+
+ return;
+err:
+ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
+}
+
+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
+ bool input, bool enable)
+{
+ unsigned int value, id = bsp_priv->id;
+
+ if (id == 1) {
+ value = input ? RK3528_GMAC1_CLK_SELET_IO :
+ RK3528_GMAC1_CLK_SELET_CRU;
+ value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
+ RK3528_GMAC1_CLK_RMII_GATE;
+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
+ } else {
+ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
+ RK3528_GMAC0_CLK_RMII_GATE;
+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
+ }
+}
+
+/* Integrated FEPHY */
+#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
+#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
+#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
+#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
+#define RK_FEPHY_PHY_ID GRF_BIT(11)
+
+#define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0)
+
+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv)
+{
+ struct device *dev = &priv->pdev->dev;
+
+ if (IS_ERR(priv->grf) || !priv->phy_reset) {
+ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
+ __func__);
+ return;
+ }
+
+ unsigned int bgs = RK_FEPHY_BGS;
+
+ reset_control_assert(priv->phy_reset);
+ udelay(20);
+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
+ RK_FEPHY_POWERUP |
+ RK_FEPHY_INTERNAL_RMII_SEL |
+ RK_FEPHY_24M_CLK_SEL |
+ RK_FEPHY_PHY_ID);
+
+ /*if (priv->otp_data > 0)
+ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);*/
+
+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
+ usleep_range(10 * 1000, 12 * 1000);
+ reset_control_deassert(priv->phy_reset);
+ usleep_range(50 * 1000, 60 * 1000);
+}
+
+static const struct rk_gmac_ops rk3528_ops = {
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_rgmii_speed = rk3528_set_rgmii_speed,
+ .set_rmii_speed = rk3528_set_rmii_speed,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .integrated_phy_powerup = rk3528_integrated_sphy_power,
+};
+
#define RK3568_GRF_GMAC0_CON0 0x0380
#define RK3568_GRF_GMAC0_CON1 0x0384
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -2106,6 +2301,7 @@ static const struct of_device_id rk_gmac
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },

64
target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch Normal file
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@ -0,0 +1,64 @@
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1761,6 +1761,53 @@ static const struct rockchip_usb2phy_cfg
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .num_ports = 2,
+ .clkout_ctl = { 0x041c, 7, 2, 0, 0x27 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x6004c, 15, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x60074, 3, 2, 0, 3 },
+ .bvalid_det_st = { 0x60078, 3, 2, 0, 3 },
+ .bvalid_det_clr = { 0x6007c, 3, 2, 0, 3 },
+ .id_det_en = { 0x60074, 5, 4, 0, 3 },
+ .id_det_st = { 0x60078, 5, 4, 0, 3 },
+ .id_det_clr = { 0x6007c, 5, 4, 0, 3 },
+ .ls_det_en = { 0x60074, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60078, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
+ .utmi_id = { 0x6006c, 6, 6, 0, 1 },
+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x6005c, 15, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x60090, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60094, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x6004c, 3, 0, 5, 1 },
+ .cp_det = { 0x6006c, 19, 19, 0, 1 },
+ .dcp_det = { 0x6006c, 18, 18, 0, 1 },
+ .dp_det = { 0x6006c, 20, 20, 0, 1 },
+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
+ .idp_src_en = { 0x60058, 2, 2, 0, 1 },
+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{
.reg = 0xfe8a0000,
@@ -1997,6 +2044,7 @@ static const struct of_device_id rockchi
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
+ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },

176
target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch Normal file
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@ -0,0 +1,176 @@
From 432666b59bdbef2c386e92dd88be4206203ff8ac Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sat, 8 Oct 2022 15:48:37 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: add support rk3528
1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz
Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 139 +++++++++++++++++-
1 file changed, 138 insertions(+), 1 deletion(-)
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -83,7 +83,7 @@
struct rockchip_combphy_priv;
struct combphy_reg {
- u16 offset;
+ u32 offset;
u16 bitend;
u16 bitstart;
u16 disable;
@@ -93,11 +93,13 @@ struct combphy_reg {
struct rockchip_combphy_grfcfg {
struct combphy_reg pcie_mode_set;
struct combphy_reg usb_mode_set;
+ struct combphy_reg u3otg0_port_en;
struct combphy_reg sgmii_mode_set;
struct combphy_reg qsgmii_mode_set;
struct combphy_reg pipe_rxterm_set;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_txcomp_set;
+ struct combphy_reg pipe_clk_24m;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
@@ -378,6 +380,120 @@ static int rockchip_combphy_probe(struct
return PTR_ERR_OR_ZERO(phy_provider);
}
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ unsigned long rate;
+ u32 val;
+
+ switch (priv->type) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ /* Enable adaptive CTLE for USB3.0 Rx. */
+ val = readl(priv->mmio + 0x200);
+ val &= ~GENMASK(17, 17);
+ val |= 0x01 << 17;
+ writel(val, priv->mmio + 0x200);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ rate = clk_get_rate(priv->refclk);
+
+ switch (rate) {
+ case REF_CLOCK_24MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+ if (priv->type == PHY_TYPE_USB3) {
+ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz. */
+ val = readl(priv->mmio + 0x100);
+ val &= ~GENMASK(10, 0);
+ val |= 0x17d;
+ writel(val, priv->mmio + 0x100);
+ } else if (priv->type == PHY_TYPE_PCIE) {
+ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */
+ val = readl(priv->mmio + 0x218);
+ val |= (1 << 14);
+ writel(val, priv->mmio + 0x218);
+ }
+ break;
+
+ case REF_CLOCK_100MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine. */
+ val = readl(priv->mmio + 0x18);
+ val &= ~(0x7 << 10);
+ val |= 0x2 << 10;
+ writel(val, priv->mmio + 0x18);
+
+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+ val = readl(priv->mmio + 0x108);
+ val &= ~(0x7f7);
+ val |= 0x4f0;
+ writel(val, priv->mmio + 0x108);
+ }
+ break;
+
+ default:
+ dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
+ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
+ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
+ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
+ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
+ /* pipe-grf */
+ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+ .grfcfg = &rk3528_combphy_grfcfgs,
+ .combphy_cfg = rk3528_combphy_cfg,
+};
+
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -772,6 +888,10 @@ static const struct rockchip_combphy_cfg
static const struct of_device_id rockchip_combphy_of_match[] = {
{
+ .compatible = "rockchip,rk3528-naneng-combphy",
+ .data = &rk3528_combphy_cfgs,
+ },
+ {
.compatible = "rockchip,rk3568-naneng-combphy",
.data = &rk3568_combphy_cfgs,
},

107
target/linux/rockchip/patches-6.6/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch Normal file
View File

@ -0,0 +1,107 @@
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -296,19 +296,20 @@ static void dwcmshc_rk3568_set_clock(str
0x3 << 19; /* post-change delay */
sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
- host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
txclk_tapnum = priv->txclk_tapnum;
- if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
- extra = DLL_CMDOUT_SRC_CLK_NEG |
- DLL_CMDOUT_EN_SRC_CLK_NEG |
- DWCMSHC_EMMC_DLL_DLYENA |
- DLL_CMDOUT_TAPNUM_90_DEGREES |
- DLL_CMDOUT_TAPNUM_FROM_SW;
- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+ if (priv->devtype != DWCMSHC_RK3568) {
+ extra = DLL_CMDOUT_SRC_CLK_NEG |
+ DLL_CMDOUT_EN_SRC_CLK_NEG |
+ DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_CMDOUT_TAPNUM_90_DEGREES |
+ DLL_CMDOUT_TAPNUM_FROM_SW;
+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+ }
}
extra = DWCMSHC_EMMC_DLL_DLYENA |
@@ -356,6 +357,15 @@ static const struct sdhci_ops sdhci_dwcm
.adma_write_desc = dwcmshc_adma_write_desc,
};
+static const struct sdhci_ops sdhci_dwcmshc_rk3528_ops = {
+ .set_clock = dwcmshc_rk3568_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .reset = rk35xx_sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+};
+
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
@@ -379,6 +389,14 @@ static const struct sdhci_pltfm_data sdh
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3528_pdata = {
+ .ops = &sdhci_dwcmshc_rk3528_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
{
int err;
@@ -444,6 +462,10 @@ static const struct of_device_id sdhci_d
.data = &sdhci_dwcmshc_rk35xx_pdata,
},
{
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = &sdhci_dwcmshc_rk3528_pdata,
+ },
+ {
.compatible = "snps,dwcmshc-sdhci",
.data = &sdhci_dwcmshc_pdata,
},
@@ -523,17 +545,18 @@ static int dwcmshc_probe(struct platform
host->mmc_host_ops.request = dwcmshc_request;
host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
- if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
+ if ((pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) ||
+ (pltfm_data == &sdhci_dwcmshc_rk3528_pdata)) {
rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
if (!rk_priv) {
err = -ENOMEM;
goto err_clk;
}
- if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
- rk_priv->devtype = DWCMSHC_RK3588;
- else
+ if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3568-dwcmshc"))
rk_priv->devtype = DWCMSHC_RK3568;
+ else
+ rk_priv->devtype = DWCMSHC_RK3588;
priv->priv = rk_priv;
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
+obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rkvendor.o
obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o

110
target/linux/rockchip/patches-6.6/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch Normal file
View File

@ -0,0 +1,110 @@
From 4ff037c13c1e7ab16362d39a59ebb8fffb929f99 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 15 Apr 2020 09:19:09 +0800
Subject: [PATCH] mmc: dw_mmc-rockchip: add v2 tuning support
v2 tuning will inherit pre-stage loader's phase
settings for the first time, and do re-tune if
necessary. Re-tune will still try the rough degrees,
for instance, 90, 180, 270, 360 but continue to do the
fine tuning if sample window isn't good enough.
Change-Id: I593384ee381d09df5b9adfc29a18eb22517b2764
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -24,6 +24,8 @@ struct dw_mci_rockchip_priv_data {
struct clk *sample_clk;
int default_sample_phase;
int num_phases;
+ int last_degree;
+ bool use_v2_tuning;
};
static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
@@ -134,6 +136,58 @@ static void dw_mci_rk3288_set_ios(struct
#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
(DIV_ROUND_UP((i) * 360, num_phases))
+static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
+{
+ struct dw_mci *host = slot->host;
+ struct dw_mci_rockchip_priv_data *priv = host->priv;
+ struct mmc_host *mmc = slot->mmc;
+ u32 degrees[4] = {0, 90, 180, 270}, degree;
+ int i;
+ static bool inherit = true;
+
+ if (inherit) {
+ inherit = false;
+ i = clk_get_phase(priv->sample_clk) / 90;
+ degree = degrees[i];
+ goto done;
+ }
+
+ /*
+ * v2 only support 4 degrees in theory.
+ * First we inherit sample phases from firmware, which should
+ * be able work fine, at least in the first place.
+ * If retune is needed, we search forward to pick the last
+ * one phase from degree list and loop around until we get one.
+ * It's impossible all 4 fixed phase won't be able to work.
+ */
+ for (i = 0; i < ARRAY_SIZE(degrees); i++) {
+ degree = degrees[i] + priv->last_degree + 90;
+ degree = degree % 360;
+ clk_set_phase(priv->sample_clk, degree);
+ if (mmc_send_tuning(mmc, opcode, NULL)) {
+ /*
+ * Tuning error, the phase is a bad phase,
+ * then try using the calculated best phase.
+ */
+ dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree);
+ degree = (degree + 180) % 360;
+ clk_set_phase(priv->sample_clk, degree);
+ if (!mmc_send_tuning(mmc, opcode, NULL))
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(degrees)) {
+ dev_warn(host->dev, "V2 All phases bad!");
+ return -EIO;
+ }
+
+done:
+ dev_info(host->dev, "V2 Successfully tuned phase to %d\n", degree);
+ priv->last_degree = degree;
+ return 0;
+}
+
static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
struct dw_mci *host = slot->host;
@@ -157,6 +211,12 @@ static int dw_mci_rk3288_execute_tuning(
return -EIO;
}
+ if (priv->use_v2_tuning) {
+ if (!dw_mci_v2_execute_tuning(slot, opcode))
+ return 0;
+ /* Otherwise we continue using fine tuning */
+ }
+
ranges = kmalloc_array(priv->num_phases / 2 + 1,
sizeof(*ranges), GFP_KERNEL);
if (!ranges)
@@ -277,6 +337,9 @@ static int dw_mci_rk3288_parse_dt(struct
&priv->default_sample_phase))
priv->default_sample_phase = 0;
+ if (of_property_read_bool(np, "rockchip,use-v2-tuning"))
+ priv->use_v2_tuning = true;
+
priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
if (IS_ERR(priv->drv_clk))
dev_dbg(host->dev, "ciu-drive not available\n");