lede/target/linux/rockchip/patches-6.1/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch

From 432666b59bdbef2c386e92dd88be4206203ff8ac Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sat, 8 Oct 2022 15:48:37 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: add support rk3528

1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz

Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
---
 .../rockchip/phy-rockchip-naneng-combphy.c    | 139 +++++++++++++++++-
 1 file changed, 138 insertions(+), 1 deletion(-)

--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -79,7 +79,7 @@
 struct rockchip_combphy_priv;
 
 struct combphy_reg {
-	u16 offset;
+	u32 offset;
 	u16 bitend;
 	u16 bitstart;
 	u16 disable;
@@ -89,11 +89,13 @@ struct combphy_reg {
 struct rockchip_combphy_grfcfg {
 	struct combphy_reg pcie_mode_set;
 	struct combphy_reg usb_mode_set;
+	struct combphy_reg u3otg0_port_en;
 	struct combphy_reg sgmii_mode_set;
 	struct combphy_reg qsgmii_mode_set;
 	struct combphy_reg pipe_rxterm_set;
 	struct combphy_reg pipe_txelec_set;
 	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_24m;
 	struct combphy_reg pipe_clk_25m;
 	struct combphy_reg pipe_clk_100m;
 	struct combphy_reg pipe_phymode_sel;
@@ -359,6 +361,120 @@ static int rockchip_combphy_probe(struct
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum. */
+		val = readl(priv->mmio + 0x18);
+		val &= ~GENMASK(5, 4);
+		val |= 0x01 << 4;
+		writel(val, priv->mmio + 0x18);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum. */
+		val = readl(priv->mmio + 0x18);
+		val &= ~GENMASK(5, 4);
+		val |= 0x01 << 4;
+		writel(val, priv->mmio + 0x18);
+
+		/* Enable adaptive CTLE for USB3.0 Rx. */
+		val = readl(priv->mmio + 0x200);
+		val &= ~GENMASK(17, 17);
+		val |= 0x01 << 17;
+		writel(val, priv->mmio + 0x200);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+		if (priv->type == PHY_TYPE_USB3) {
+			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz. */
+			val = readl(priv->mmio + 0x100);
+			val &= ~GENMASK(10, 0);
+			val |= 0x17d;
+			writel(val, priv->mmio + 0x100);
+		} else if (priv->type == PHY_TYPE_PCIE) {
+			/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
+			val = readl(priv->mmio + 0x218);
+			val |= (1 << 14);
+			writel(val, priv->mmio + 0x218);
+		}
+		break;
+
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO tuning fine. */
+			val = readl(priv->mmio + 0x18);
+			val &= ~(0x7 << 10);
+			val |= 0x2 << 10;
+			writel(val, priv->mmio + 0x18);
+
+			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+			val = readl(priv->mmio + 0x108);
+			val &= ~(0x7f7);
+			val |= 0x4f0;
+			writel(val, priv->mmio + 0x108);
+		}
+		break;
+
+	default:
+		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x48000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x48000, 5, 0, 0x00, 0x04 },
+	.pipe_rxterm_set	= { 0x48000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x48004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x48004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_24m		= { 0x48004, 14, 13, 0x00, 0x00 },
+	.pipe_clk_100m		= { 0x48004, 14, 13, 0x00, 0x02 },
+	.pipe_rxterm_sel	= { 0x48008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x48008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x48008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x4800c, 9, 8, 0x02, 0x01 },
+	.pipe_phy_status	= { 0x48034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x48000, 15, 0, 0x00, 0x110 },
+	.con1_for_pcie		= { 0x48004, 15, 0, 0x00, 0x00 },
+	.con2_for_pcie		= { 0x48008, 15, 0, 0x00, 0x101 },
+	.con3_for_pcie		= { 0x4800c, 15, 0, 0x00, 0x0200 },
+	/* pipe-grf */
+	.u3otg0_port_en		= { 0x40044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+	.grfcfg		= &rk3528_combphy_grfcfgs,
+	.combphy_cfg	= rk3528_combphy_cfg,
+};
+
 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 {
 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -561,6 +677,10 @@ static const struct rockchip_combphy_cfg
 
 static const struct of_device_id rockchip_combphy_of_match[] = {
 	{
+		.compatible = "rockchip,rk3528-naneng-combphy",
+		.data = &rk3528_combphy_cfgs,
+	},
+	{
 		.compatible = "rockchip,rk3568-naneng-combphy",
 		.data = &rk3568_combphy_cfgs,
 	},