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RK3528 is a cost down SoC with high CPU performance. However, it has poor PCIe performance (same for RK3576). Also CPU 0/1 can't get any rest due to rkbin limitation. Some code references: https://github.com/warpme/minimyth2
104 lines
3.6 KiB
Diff
104 lines
3.6 KiB
Diff
From 2ed777fcd035089bd7996bfa09c023521ecf0e24 Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Fri, 30 Sep 2022 20:11:50 +0800
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Subject: [PATCH] soc: rockchip: power-domain: add power domain support for
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rk3528
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This driver is modified to support RK3528 SoCs.
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612
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---
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drivers/soc/rockchip/pm_domains.c | 47 +++++++++++++++++++++++++++++++
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1 file changed, 47 insertions(+)
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--- a/drivers/soc/rockchip/pm_domains.c
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+++ b/drivers/soc/rockchip/pm_domains.c
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@@ -30,6 +30,7 @@
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#include <dt-bindings/power/rk3366-power.h>
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#include <dt-bindings/power/rk3368-power.h>
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#include <dt-bindings/power/rk3399-power.h>
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+#include <dt-bindings/power/rk3528-power.h>
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#include <dt-bindings/power/rk3568-power.h>
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#include <dt-bindings/power/rk3588-power.h>
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@@ -120,6 +121,20 @@ struct rockchip_pmu {
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.active_wakeup = wakeup, \
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}
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+#define DOMAIN_M_A(_name, pwr, status, req, idle, ack, always, wakeup) \
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+{ \
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+ .name = _name, \
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+ .pwr_w_mask = (pwr) << 16, \
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+ .pwr_mask = (pwr), \
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+ .status_mask = (status), \
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+ .req_w_mask = (req) << 16, \
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+ .req_mask = (req), \
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+ .idle_mask = (idle), \
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+ .ack_mask = (ack), \
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+ .always_on = always, \
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+ .active_wakeup = wakeup, \
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+}
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+
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#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
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{ \
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.name = _name, \
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@@ -164,6 +179,9 @@ struct rockchip_pmu {
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#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
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DOMAIN(name, pwr, status, req, req, req, wakeup)
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+#define DOMAIN_RK3528(name, pwr, req, always, wakeup) \
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+ DOMAIN_M_A(name, pwr, pwr, req, req, req, always, wakeup)
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+
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#define DOMAIN_RK3568(name, pwr, req, wakeup) \
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DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
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@@ -1037,6 +1055,18 @@ static const struct rockchip_domain_info
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[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
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};
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+static const struct rockchip_domain_info rk3528_pm_domains[] = {
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+ [RK3528_PD_PMU] = DOMAIN_RK3528("pmu", 0, BIT(0), true, false),
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+ [RK3528_PD_BUS] = DOMAIN_RK3528("bus", 0, BIT(1), true, false),
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+ [RK3528_PD_DDR] = DOMAIN_RK3528("ddr", 0, BIT(2), true, false),
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+ [RK3528_PD_MSCH] = DOMAIN_RK3528("msch", 0, BIT(3), true, false),
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+ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4), true, false),
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+ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5), true, false),
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+ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6), true, false),
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+ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7), true, false),
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+ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8), true, false),
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+};
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+
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static const struct rockchip_domain_info rk3568_pm_domains[] = {
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[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
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[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
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@@ -1216,6 +1246,17 @@ static const struct rockchip_pmu_info rk
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.domain_info = rk3399_pm_domains,
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};
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+static const struct rockchip_pmu_info rk3528_pmu = {
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+ .pwr_offset = 0x1210,
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+ .status_offset = 0x1230,
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+ .req_offset = 0x1110,
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+ .idle_offset = 0x1128,
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+ .ack_offset = 0x1120,
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+
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+ .num_domains = ARRAY_SIZE(rk3528_pm_domains),
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+ .domain_info = rk3528_pm_domains,
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+};
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+
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static const struct rockchip_pmu_info rk3568_pmu = {
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.pwr_offset = 0xa0,
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.status_offset = 0x98,
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@@ -1296,6 +1337,10 @@ static const struct of_device_id rockchi
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.data = (void *)&rk3399_pmu,
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},
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{
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+ .compatible = "rockchip,rk3528-power-controller",
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+ .data = (void *)&rk3528_pmu,
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+ },
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+ {
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.compatible = "rockchip,rk3568-power-controller",
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.data = (void *)&rk3568_pmu,
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},
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