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45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 77f6dfcb20c2dc6a4a2f5303709c6fa0c7b65f30 Mon Sep 17 00:00:00 2001
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From: Valmantas Paliksa <walmis@gmail.com>
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Date: Thu, 12 Dec 2024 12:24:33 +0200
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Subject: [PATCH] Disable PHY_LANE_IDLE_OFF for each instance of rockchip_pcie_phy_power_one
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This patch fixes an issue in the Rockchip PCIe PHY driver where, after
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a warm restart of the rockchip_pcie_phy module, PCIe lanes other than
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lane 0 could remain stuck in the PHY_LANE_IDLE_OFF state. This resulted
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in the PCIe link being restricted to x1 mode, even in configurations
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designed to use multiple lanes.
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Signed-off-by: Valmantas Paliksa <walmis@gmail.com>
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---
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drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
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+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
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@@ -166,6 +166,12 @@ static int rockchip_pcie_phy_power_on(st
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unsigned long timeout;
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mutex_lock(&rk_phy->pcie_mutex);
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+
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+ regmap_write(rk_phy->reg_base,
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+ rk_phy->phy_data->pcie_laneoff,
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+ HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
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+ PHY_LANE_IDLE_MASK,
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+ PHY_LANE_IDLE_A_SHIFT + inst->index));
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if (rk_phy->pwr_cnt++)
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goto err_out;
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@@ -181,12 +187,6 @@ static int rockchip_pcie_phy_power_on(st
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT));
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- regmap_write(rk_phy->reg_base,
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- rk_phy->phy_data->pcie_laneoff,
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- HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
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- PHY_LANE_IDLE_MASK,
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- PHY_LANE_IDLE_A_SHIFT + inst->index));
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-
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/*
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* No documented timeout value for phy operation below,
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* so we make it large enough here. And we use loop-break
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