From 77f6dfcb20c2dc6a4a2f5303709c6fa0c7b65f30 Mon Sep 17 00:00:00 2001 From: Valmantas Paliksa Date: Thu, 12 Dec 2024 12:24:33 +0200 Subject: [PATCH] Disable PHY_LANE_IDLE_OFF for each instance of rockchip_pcie_phy_power_one This patch fixes an issue in the Rockchip PCIe PHY driver where, after a warm restart of the rockchip_pcie_phy module, PCIe lanes other than lane 0 could remain stuck in the PHY_LANE_IDLE_OFF state. This resulted in the PCIe link being restricted to x1 mode, even in configurations designed to use multiple lanes. Signed-off-by: Valmantas Paliksa --- drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -166,6 +166,12 @@ static int rockchip_pcie_phy_power_on(st unsigned long timeout; mutex_lock(&rk_phy->pcie_mutex); + + regmap_write(rk_phy->reg_base, + rk_phy->phy_data->pcie_laneoff, + HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT + inst->index)); if (rk_phy->pwr_cnt++) goto err_out; @@ -181,12 +187,6 @@ static int rockchip_pcie_phy_power_on(st PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT)); - regmap_write(rk_phy->reg_base, - rk_phy->phy_data->pcie_laneoff, - HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, - PHY_LANE_IDLE_MASK, - PHY_LANE_IDLE_A_SHIFT + inst->index)); - /* * No documented timeout value for phy operation below, * so we make it large enough here. And we use loop-break