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56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From ef8c8a638dd459d52d833693b3921010fbd883ff Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Thu, 23 Jan 2025 22:48:20 +0000
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Subject: [PATCH 8/9] mmc: rockchip_sdhci: Gate clock for glitch free phase
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switching
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Enable clock stopping to gate clock during phase code change to ensure
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glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
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on RK3528.
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POST_CHANGE_DLY
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Time taken for phase switching and stable clock output.
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- Less than 4-cycle latency
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PRE_CHANGE_DLY
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Maximum Latency specification between transmit clock and receive clock.
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- Less than 4-cycle latency
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TUNE_CLK_STOP_EN
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Clock stopping control for Tuning and auto-tuning circuit. When enabled,
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clock gate control output is pulled low before changing phase select
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codes. This effectively stops the receive clock. Changing phase code
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when clocks are stopped ensures glitch free phase switching.
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- Clocks stopped during phase code change
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/mmc/rockchip_sdhci.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/drivers/mmc/rockchip_sdhci.c
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+++ b/drivers/mmc/rockchip_sdhci.c
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@@ -50,6 +50,10 @@
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#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
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#define DWCMSHC_CARD_IS_EMMC BIT(0)
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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+#define DWCMSHC_EMMC_AT_CTRL 0x540
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+#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
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+#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
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+#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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@@ -326,6 +330,11 @@ static int rk3568_sdhci_config_dll(struc
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udelay(1);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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+ extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
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+ 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
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+ EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
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+ sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
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+
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/* Init DLL settings */
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extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
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DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
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