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uboot-rockchip: add pending rk3528 support

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aiamadeus 2025-02-25 23:05:36 +08:00
parent 324daf1e8e
commit 36b2cd19df
15 changed files with 6504 additions and 0 deletions
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31
package/boot/uboot-rockchip/Makefile
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@ -183,6 +183,35 @@ define U-Boot/sv901-eaio-rk3399
USE_RKBIN:=1
endef
# RK3528 boards
define U-Boot/rk3528/Default
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):rkbin-rk3528
ATF:=rk3528_bl31_v1.17.elf
TPL:=rk3528_ddr_1056MHz_v1.10.bin
endef
define U-Boot/generic-rk3528
$(U-Boot/rk3528/Default)
NAME:=GENERIC RK3528
BUILD_DEVICES:= \
armsom_sige1 \
hinlink_opc-h28k \
hinlink_opc-h29k \
hinlink_opc-ht2 \
widora_mangopi-m28c \
widora_mangopi-m28k \
widora_mangopi-m28k-pro
endef
define U-Boot/radxa-e20c-rk3528
$(U-Boot/rk3528/Default)
NAME:=Radxa E20C
BUILD_DEVICES:= \
radxa_e20c
endef
# RK3566 boards
define U-Boot/rk3566/Default
@ -384,6 +413,8 @@ define U-Boot/rock5a-rk3588s
endef
UBOOT_TARGETS := \
generic-rk3528 \
radxa-e20c-rk3528 \
nanopi-r3s-rk3566 \
panther-x2-rk3566 \
rock-3c-rk3566 \

210
package/boot/uboot-rockchip/patches/400-arm64-dts-rockchip-Add-base-DT-for-rk3528-SoC.patch Normal file
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@ -0,0 +1,210 @@
From 7983e6c379a917c500eff31f5f9c646cc408e030 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 29 Aug 2024 09:27:04 +0000
Subject: [PATCH] arm64: dts: rockchip: Add base DT for rk3528 SoC
This initial device tree describes CPU, interrupts and UART on the chip
and is able to boot into basic kernel with only UART. Cache information
is omitted for now as there is no precise documentation. Support for
other features will be added later.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20240829092705.6241-4-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 189 +++++++++++++++++++++++
1 file changed, 189 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "rockchip,rk3528";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xin24m: clock-xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfed01000 0 0x1000>,
+ <0x0 0xfed02000 0 0x2000>,
+ <0x0 0xfed04000 0 0x2000>,
+ <0x0 0xfed06000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ };
+
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff9f8000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f8000 0x0 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@ffa00000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa00000 0x0 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffa08000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa08000 0x0 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@ffa10000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa10000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@ffa18000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa18000 0x0 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@ffa20000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa20000 0x0 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@ffa28000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa28000 0x0 0x100>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};

26
package/boot/uboot-rockchip/patches/401-rockchip-mkimage-Add-support-for-RK3528.patch Normal file
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@ -0,0 +1,26 @@
From 37a4c7f5fb6e75e248e84500f27d3945c502e381 Mon Sep 17 00:00:00 2001
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Date: Thu, 23 Jan 2025 22:48:13 +0000
Subject: [PATCH 1/9] rockchip: mkimage: Add support for RK3528
Add support for generating Rockchip Boot Image for RK3528.
Similar to RK3568, the RK3528 has 64 KiB SRAM and 4 KiB of it is
reserved for BootROM.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -134,6 +134,7 @@ static struct spl_info spl_infos[] = {
{ "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};

372
package/boot/uboot-rockchip/patches/402-arch-arm-rockchip-Add-initial-support-for-RK3528.patch Normal file
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@ -0,0 +1,372 @@
From f6c7b9632a51e6c29a8be4e4e6d137a511fbf3fb Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:14 +0000
Subject: [PATCH 2/9] arch: arm: rockchip: Add initial support for RK3528
Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
Add initial arch support for the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/include/asm/arch-rk3528/boot0.h | 9 ++
arch/arm/include/asm/arch-rk3528/gpio.h | 9 ++
arch/arm/mach-rockchip/Kconfig | 50 +++++++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3528/Kconfig | 15 ++
arch/arm/mach-rockchip/rk3528/Makefile | 4 +
arch/arm/mach-rockchip/rk3528/rk3528.c | 137 ++++++++++++++++++
arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 19 +++
drivers/usb/gadget/Kconfig | 1 +
include/configs/rk3528_common.h | 42 ++++++
10 files changed, 287 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3528/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3528/gpio.h
create mode 100644 arch/arm/mach-rockchip/rk3528/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3528/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3528/rk3528.c
create mode 100644 arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
create mode 100644 include/configs/rk3528_common.h
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/boot0.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -309,6 +309,55 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3528
+ bool "Support Rockchip RK3528"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply BOOTSTD_FULL
+ imply DM_RNG
+ imply FIT
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply OF_LIVE
+ imply OF_UPSTREAM
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
+ imply ROCKCHIP_OTP
+ imply SPL_ATF
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_CLK
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
+ imply SPL_LOAD_FIT
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_PINCTRL
+ imply SPL_RAM
+ imply SPL_REGMAP
+ imply SPL_SERIAL
+ imply SPL_SYSCON
+ imply SYS_RELOC_GD_ENV_ADDR
+ imply SYSRESET
+ help
+ The Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
+
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
@@ -626,6 +675,7 @@ source "arch/arm/mach-rockchip/rk3308/Kc
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -0,0 +1,15 @@
+if ROCKCHIP_RK3528
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff370200
+
+config ROCKCHIP_STIMER_BASE
+ default 0xff620000
+
+config SYS_SOC
+ default "rk3528"
+
+config SYS_CONFIG_NAME
+ default "rk3528_common"
+
+endif
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += rk3528.o
+obj-y += syscon_rk3528.o
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define FIREWALL_DDR_BASE 0xff2e0000
+#define FW_DDR_MST6_REG 0x58
+#define FW_DDR_MST7_REG 0x5c
+#define FW_DDR_MST14_REG 0x78
+#define FW_DDR_MST16_REG 0x80
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
+};
+
+static struct mm_region rk3528_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xfc000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x04000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3528_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+
+ /* Set the sdmmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+
+ /* Set the usb to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+
+ return 0;
+}
+
+#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG 0x04
+#define TIMER_EN BIT(0)
+#define HP_LOAD_COUNT0_REG 0x14
+#define HP_LOAD_COUNT1_REG 0x18
+
+void rockchip_stimer_init(void)
+{
+ u32 reg;
+
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
+ return;
+
+ reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+ if (reg & TIMER_EN)
+ return;
+
+ asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+ writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+#define RK3528_OTP_CPU_CODE_OFFSET 0x02
+#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28
+
+int checkboard(void)
+{
+ u8 cpu_code[2], chip_type;
+ struct udevice *dev;
+ char suffix[2];
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x28 */
+ ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return 0;
+ }
+
+ ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1);
+ if (ret < 0) {
+ log_debug("Could not read chip type, ret=%d\n", ret);
+ return 0;
+ }
+
+ suffix[0] = chip_type != 0x1 ? 'A' : '\0';
+ suffix[1] = '\0';
+
+ printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
+ return 0;
+}
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3528_syscon_ids[] = {
+ { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_syscon) = {
+ .name = "rockchip_rk3528_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3528_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -85,6 +85,7 @@ config USB_GADGET_PRODUCT_NUM
default 0x330e if ROCKCHIP_RK3308
default 0x350a if ROCKCHIP_RK3568
default 0x350b if ROCKCHIP_RK3588
+ default 0x350c if ROCKCHIP_RK3528
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
--- /dev/null
+++ b/include/configs/rk3528_common.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __CONFIG_RK3528_COMMON_H
+#define __CONFIG_RK3528_COMMON_H
+
+#define CFG_CPUID_OFFSET 0xa
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0xfe480000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfc000000
+
+#ifndef CONFIG_XPL_BUILD
+
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "script_offset_f=0xffe000\0" \
+ "script_size_f=0x2000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "kernel_addr_r=0x02000000\0" \
+ "kernel_comp_addr_r=0x0a000000\0" \
+ "fdt_addr_r=0x12000000\0" \
+ "fdtoverlay_addr_r=0x12100000\0" \
+ "ramdisk_addr_r=0x12180000\0" \
+ "kernel_comp_size=0x8000000\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* CONFIG_XPL_BUILD */
+
+#endif /* __CONFIG_RK3528_COMMON_H */

76
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@ -0,0 +1,76 @@
From 62e99c283ab507f93e7dadda1b05e5c459f0e60d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:15 +0000
Subject: [PATCH 3/9] ram: rockchip: Add basic support for RK3528
Add support for reading DRAM size information from PMUGRF os_reg18 reg.
Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
instead of os_reg2.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/sdram.c | 3 ++-
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3528.c | 33 +++++++++++++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/rockchip/sdram_rk3528.c
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,7 +110,8 @@ static int rockchip_dram_init_banksize(v
u8 i, j;
if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
- !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
return -ENOTSUPP;
if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3528.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMUGRF_BASE 0xff370000
+#define OS_REG18_REG 0x248
+
+static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = CFG_SYS_SDRAM_BASE;
+ info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG);
+
+ return 0;
+}
+
+static struct ram_ops rk3528_dmc_ops = {
+ .get_info = rk3528_dmc_get_info,
+};
+
+static const struct udevice_id rk3528_dmc_ids[] = {
+ { .compatible = "rockchip,rk3528-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_dmc) = {
+ .name = "rockchip_rk3528_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3528_dmc_ids,
+ .ops = &rk3528_dmc_ops,
+};

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323
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From 62eabfb295366711dfb761ec49bf39432861d45d Mon Sep 17 00:00:00 2001
From: Steven Liu <steven.liu@rock-chips.com>
Date: Thu, 23 Jan 2025 22:48:17 +0000
Subject: [PATCH 5/9] pinctrl: rockchip: Add support for RK3528
Add pinctrl driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
to use regmap_update_bits().
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3528.c | 292 ++++++++++++++++++++++
2 files changed, 293 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3528.c
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, mask;
+ u8 bit;
+ u32 data, rmask;
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ rmask = data | (data >> 16);
+ data |= (mux & mask) << bit;
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ break;
+ case 1:
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ break;
+ default:
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+}
+
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+
+ rk3528_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (drv << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ break;
+ case 1:
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ break;
+ default:
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+}
+
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data, rmask;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EOPNOTSUPP;
+
+ rk3528_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (ret << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ break;
+ case 1:
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ break;
+ default:
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+
+ rk3528_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (enable << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3528_set_mux,
+ .set_pull = rk3528_set_pull,
+ .set_drive = rk3528_set_drive,
+ .set_schmitt = rk3528_set_schmitt,
+};
+
+static const struct udevice_id rk3528_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3528-pinctrl",
+ .data = (ulong)&rk3528_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
+ .name = "rockchip_rk3528_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3528_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};

74
package/boot/uboot-rockchip/patches/406-mmc-rockchip_sdhci-Extend-variant-configuration.patch Normal file
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@ -0,0 +1,74 @@
From 81dbef690f2f9734b67a2db9ac5abb773cb4b948 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:18 +0000
Subject: [PATCH 6/9] mmc: rockchip_sdhci: Extend variant configuration
RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/rockchip_sdhci.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -156,6 +156,9 @@ struct sdhci_data {
u32 flags;
u8 hs200_txclk_tapnum;
u8 hs400_txclk_tapnum;
+ u8 hs400_cmdout_tapnum;
+ u8 hs400_strbin_tapnum;
+ u8 ddr50_strbin_delay_num;
};
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -348,7 +351,7 @@ static int rk3568_sdhci_config_dll(struc
extra = DLL_CMDOUT_SRC_CLK_NEG |
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
- DLL_CMDOUT_TAPNUM_90_DEGREES |
+ data->hs400_cmdout_tapnum |
DLL_CMDOUT_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
}
@@ -360,7 +363,7 @@ static int rk3568_sdhci_config_dll(struc
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_STRBIN_TAPNUM_DEFAULT |
+ data->hs400_strbin_tapnum |
DLL_STRBIN_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
@@ -380,7 +383,7 @@ static int rk3568_sdhci_config_dll(struc
*/
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_STRBIN_DELAY_NUM_SEL |
- DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+ data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}
@@ -654,6 +657,9 @@ static const struct sdhci_data rk3568_da
.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x8,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
};
static const struct sdhci_data rk3588_data = {
@@ -662,6 +668,9 @@ static const struct sdhci_data rk3588_da
.config_dll = rk3568_sdhci_config_dll,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x9,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
};
static const struct udevice_id sdhci_ids[] = {

49
package/boot/uboot-rockchip/patches/407-mmc-rockchip_sdhci-Add-initial-support-for-RK3528.patch Normal file
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@ -0,0 +1,49 @@
From 1d08efe86fd6756ba2b114ad2a256bea2d0e9b9e Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:19 +0000
Subject: [PATCH 7/9] mmc: rockchip_sdhci: Add initial support for RK3528
Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/rockchip_sdhci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -650,6 +650,17 @@ static const struct sdhci_data rk3399_da
.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
};
+static const struct sdhci_data rk3528_data = {
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
+ .hs200_txclk_tapnum = 0xc,
+ .hs400_txclk_tapnum = 0x6,
+ .hs400_cmdout_tapnum = 0x6,
+ .hs400_strbin_tapnum = 0x3,
+ .ddr50_strbin_delay_num = 0xa,
+};
+
static const struct sdhci_data rk3568_data = {
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
@@ -679,6 +690,10 @@ static const struct udevice_id sdhci_ids
.data = (ulong)&rk3399_data,
},
{
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = (ulong)&rk3528_data,
+ },
+ {
.compatible = "rockchip,rk3568-dwcmshc",
.data = (ulong)&rk3568_data,
},

55
package/boot/uboot-rockchip/patches/408-mmc-rockchip_sdhci-Gate-clock-for-glitch-free-phase.patch Normal file
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@ -0,0 +1,55 @@
From ef8c8a638dd459d52d833693b3921010fbd883ff Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:20 +0000
Subject: [PATCH 8/9] mmc: rockchip_sdhci: Gate clock for glitch free phase
switching
Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency
TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/rockchip_sdhci.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -50,6 +50,10 @@
#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
#define DWCMSHC_CARD_IS_EMMC BIT(0)
#define DWCMSHC_ENHANCED_STROBE BIT(8)
+#define DWCMSHC_EMMC_AT_CTRL 0x540
+#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
+#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
+#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
@@ -326,6 +330,11 @@ static int rk3568_sdhci_config_dll(struc
udelay(1);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+ extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
+ 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
+ EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
+
/* Init DLL settings */
extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |

119
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@ -0,0 +1,119 @@
From 4e19cd0a572b6a27b82fef84c30fca69914b7798 Mon Sep 17 00:00:00 2001
From: Lin Jinhan <troy.lin@rock-chips.com>
Date: Thu, 23 Jan 2025 22:48:21 +0000
Subject: [PATCH 9/9] rng: rockchip: Add support for rkrng variant
Add support for rkrng variant, used by e.g. RK3528 and RK3576.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments for mainline.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/rng/rockchip_rng.c | 73 ++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -70,6 +70,27 @@
#define TRNG_v1_VERSION_CODE 0x46BC
/* end of TRNG V1 register define */
+/* start of RKRNG register define */
+#define RKRNG_CTRL 0x0010
+#define RKRNG_CTRL_INST_REQ BIT(0)
+#define RKRNG_CTRL_RESEED_REQ BIT(1)
+#define RKRNG_CTRL_TEST_REQ BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
+
+#define RKRNG_STATE 0x0014
+#define RKRNG_STATE_INST_ACK BIT(0)
+#define RKRNG_STATE_RESEED_ACK BIT(1)
+#define RKRNG_STATE_TEST_ACK BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0 0x0070
+#define RKRNG_DRNG_DATA_7 0x008C
+
+/* end of RKRNG register define */
+
#define RK_RNG_TIME_OUT 50000 /* max 50ms */
#define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
@@ -228,6 +249,49 @@ exit:
return retval;
}
+static int rkrng_init(struct udevice *dev)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ reg = trng_read(pdata, RKRNG_STATE);
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ return 0;
+}
+
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ reg = RKRNG_CTRL_SW_DRNG_REQ;
+
+ rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
+
+ retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
+ (reg & RKRNG_STATE_SW_DRNG_ACK),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ return retval;
+}
+
static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
{
unsigned char *buf = data;
@@ -295,6 +359,11 @@ static const struct rk_rng_soc_data rk_t
.rk_rng_read = rk_trngv1_rng_read,
};
+static const struct rk_rng_soc_data rkrng_soc_data = {
+ .rk_rng_init = rkrng_init,
+ .rk_rng_read = rkrng_rng_read,
+};
+
static const struct dm_rng_ops rockchip_rng_ops = {
.read = rockchip_rng_read,
};
@@ -320,6 +389,10 @@ static const struct udevice_id rockchip_
.compatible = "rockchip,trngv1",
.data = (ulong)&rk_trngv1_soc_data,
},
+ {
+ .compatible = "rockchip,rkrng",
+ .data = (ulong)&rkrng_soc_data,
+ },
{},
};

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package/boot/uboot-rockchip/patches/412-arm-dts-rockchip-Add-rk3528-u-boot.dtsi.patch Normal file
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@ -0,0 +1,371 @@
From efd80d2ddee68e1f070396c67a7f76426d065017 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:23 +0000
Subject: [PATCH 2/4] arm: dts: rockchip: Add rk3528-u-boot.dtsi
Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
with bare minimum nodes to have a booting system from eMMC and SD-card.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-u-boot.dtsi | 354 ++++++++++++++++++++++++++++++++
1 file changed, 354 insertions(+)
create mode 100644 arch/arm/dts/rk3528-u-boot.dtsi
--- /dev/null
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/clock/rk3528-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+
+ dmc {
+ compatible = "rockchip,rk3528-dmc";
+ bootph-all;
+ };
+
+ soc {
+ usb_host0_ehci: usb@ff100000 {
+ compatible = "rockchip,rk3528-ehci", "generic-ehci";
+ reg = <0x0 0xff100000 0x0 0x40000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+ <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff140000 {
+ compatible = "rockchip,rk3528-ohci", "generic-ohci";
+ reg = <0x0 0xff140000 0x0 0x40000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+ <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ grf: syscon@ff300000 {
+ compatible = "rockchip,rk3528-grf",
+ "syscon", "simple-mfd";
+ reg = <0x0 0xff300000 0x0 0x90000>;
+ };
+
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ioc_grf: syscon@ff540000 {
+ compatible = "rockchip,rk3528-ioc-grf", "syscon";
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_PRESETN_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@ffbe0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbe0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
+ <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac";
+ resets = <&cru SRST_ARESETN_MAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc";
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ rng: rng@ffc50000 {
+ compatible = "rockchip,rkrng";
+ reg = <0x0 0xffc50000 0x0 0x200>;
+ };
+
+ otp: otp@ffce0000 {
+ compatible = "rockchip,rk3528-otp",
+ "rockchip,rk3568-otp";
+ reg = <0x0 0xffce0000 0x0 0x4000>;
+ };
+
+ u2phy: usb2phy@ffdf0000 {
+ compatible = "rockchip,rk3528-usb2phy";
+ reg = <0x0 0xffdf0000 0x0 0x10000>;
+ clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+ clock-names = "phyclk", "apb_pclk";
+ #clock-cells = <0>;
+ rockchip,usbgrf = <&grf>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+};
+
+#include "rk3528-pinctrl.dtsi"
+
+&cru {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_strb {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&grf {
+ bootph-all;
+};
+
+&ioc_grf {
+ bootph-all;
+};
+
+&otp {
+ bootph-some-ram;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
+&xin24m {
+ bootph-all;
+};

159
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@ -0,0 +1,159 @@
From e7f5a4ae16f02ddaf2acf59b07e684c95338937d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:24 +0000
Subject: [PATCH 3/4] board: rockchip: Add minimal generic RK3528 board
Add a minimal generic RK3528 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3528 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-generic-u-boot.dtsi | 31 +++++++++++++++++
arch/arm/dts/rk3528-generic.dts | 20 +++++++++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 5 +++
configs/generic-rk3528_defconfig | 41 +++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 12 +++++++
5 files changed, 109 insertions(+)
create mode 100644 arch/arm/dts/rk3528-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-generic.dts
create mode 100644 arch/arm/mach-rockchip/rk3528/MAINTAINERS
create mode 100644 configs/generic-rk3528_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_strb>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_det>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+};
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3528 with eMMC and SD-card enabled
+ */
+
+/dts-v1/;
+#include "rk3528.dtsi"
+
+/ {
+ model = "Generic RK3528";
+ compatible = "rockchip,rk3528";
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -0,0 +1,5 @@
+GENERIC-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-generic*
+F: configs/generic-rk3528_defconfig
--- /dev/null
+++ b/configs/generic-rk3528_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -97,6 +97,9 @@ List of mainline supported Rockchip boar
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rk3528
+ - Generic RK3528 (generic-rk3528)
+
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
- Hardkernel ODROID-M1S (odroid-m1s-rk3566)
@@ -255,6 +258,15 @@ To build rk3399 boards:
make evb-rk3399_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3528 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin
+ make generic-rk3528_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3568 boards:
.. code-block:: bash

199
package/boot/uboot-rockchip/patches/414-board-rockchip-Add-Radxa-E20C.patch Normal file
View File

@ -0,0 +1,199 @@
From 66014f06f4b1d0c39e79fdd45201962913ec27a2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2025 22:48:25 +0000
Subject: [PATCH 4/4] board: rockchip: Add Radxa E20C
The Radxa E20C is an ultra-compact network computer with a RK3528A SoC
that offers a wide range of networking capabilities.
Features tested on a Radxa E20C v1.104:
- SD-card boot
- eMMC boot
- Ethernet
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 93 ++++++++++++++++++++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 ++
configs/radxa-e20c-rk3528_defconfig | 54 +++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 154 insertions(+)
create mode 100644 arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
create mode 100644 configs/radxa-e20c-rk3528_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ vcc_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc5v0_usb20: regulator-5v0-usb20 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_usb20";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_strb>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_det>;
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ phy-supply = <&vcc5v0_usb20>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -3,3 +3,9 @@ M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3528-generic*
F: configs/generic-rk3528_defconfig
+
+RADXA-E20C
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-radxa-e20c*
+F: configs/radxa-e20c-rk3528_defconfig
--- /dev/null
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -99,6 +99,7 @@ List of mainline supported Rockchip boar
* rk3528
- Generic RK3528 (generic-rk3528)
+ - Radxa E20C (radxa-e20c-rk3528)
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)