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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
55 lines
1.8 KiB
Diff
55 lines
1.8 KiB
Diff
From c027fd431bb2326d03d21a57e9f59f7ae414abbf Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Tue, 12 Nov 2019 10:25:25 +0530
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Subject: [PATCH 1005/1011] clk: qcom: ipq6018: update Huayra PLL settings
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1. Updated APSS PLL and UBI PLL settings recommended by ATE.
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2. Added TEST_CTL_VAL configuration for Huayra PLL
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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drivers/clk/qcom/clk-alpha-pll.c | 6 ++++++
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drivers/clk/qcom/gcc-ipq6018.c | 9 ++++++---
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2 files changed, 12 insertions(+), 3 deletions(-)
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--- a/drivers/clk/qcom/clk-alpha-pll.c
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+++ b/drivers/clk/qcom/clk-alpha-pll.c
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@@ -287,6 +287,12 @@ void clk_alpha_pll_configure(struct clk_
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regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
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+ if (config->test_ctl_val != 0)
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+ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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+
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+ if (config->test_ctl_hi_val != 0)
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+ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
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+
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if (pll->flags & SUPPORTS_FSM_MODE)
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qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
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}
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--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -4711,15 +4711,18 @@ static struct clk_branch gcc_dcc_clk = {
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static const struct alpha_pll_config ubi32_pll_config = {
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.l = 0x3e,
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- .alpha = 0x57,
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- .config_ctl_val = 0x240d6aa8,
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- .config_ctl_hi_val = 0x3c2,
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+ .alpha = 0x6667,
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+ .config_ctl_val = 0x240d4828,
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+ .config_ctl_hi_val = 0x6,
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.main_output_mask = BIT(0),
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.aux_output_mask = BIT(1),
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.pre_div_val = 0x0,
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.pre_div_mask = BIT(12),
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.post_div_val = 0x0,
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.post_div_mask = GENMASK(9, 8),
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+ .alpha_en_mask = BIT(24),
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+ .test_ctl_val = 0x1C0000C0,
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+ .test_ctl_hi_val = 0x4000,
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};
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static const struct alpha_pll_config nss_crypto_pll_config = {
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