From c027fd431bb2326d03d21a57e9f59f7ae414abbf Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Tue, 12 Nov 2019 10:25:25 +0530 Subject: [PATCH 1005/1011] clk: qcom: ipq6018: update Huayra PLL settings 1. Updated APSS PLL and UBI PLL settings recommended by ATE. 2. Added TEST_CTL_VAL configuration for Huayra PLL Signed-off-by: Praveenkumar I Signed-off-by: Alexandru Gagniuc --- drivers/clk/qcom/clk-alpha-pll.c | 6 ++++++ drivers/clk/qcom/gcc-ipq6018.c | 9 ++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -287,6 +287,12 @@ void clk_alpha_pll_configure(struct clk_ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + if (config->test_ctl_val != 0) + regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + + if (config->test_ctl_hi_val != 0) + regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + if (pll->flags & SUPPORTS_FSM_MODE) qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); } --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -4711,15 +4711,18 @@ static struct clk_branch gcc_dcc_clk = { static const struct alpha_pll_config ubi32_pll_config = { .l = 0x3e, - .alpha = 0x57, - .config_ctl_val = 0x240d6aa8, - .config_ctl_hi_val = 0x3c2, + .alpha = 0x6667, + .config_ctl_val = 0x240d4828, + .config_ctl_hi_val = 0x6, .main_output_mask = BIT(0), .aux_output_mask = BIT(1), .pre_div_val = 0x0, .pre_div_mask = BIT(12), .post_div_val = 0x0, .post_div_mask = GENMASK(9, 8), + .alpha_en_mask = BIT(24), + .test_ctl_val = 0x1C0000C0, + .test_ctl_hi_val = 0x4000, }; static const struct alpha_pll_config nss_crypto_pll_config = {