Two commits which made their way into Linux stable broke the SATA
support on the BPi-R64.
Fix this by reverting a node rename which broke DT-overlay application
and import a (still pending) patch re-adding the 'syscon' compatible
to the pciesys clock-controller which also contains phy-mode bits
referenced by the ahci_mtk driver expecting to access them using
syscon_regmap_lookup_by_phandle().
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import patch from MediaTek's SDK to support FM25S01B flash.
Also fixes DS35Q1GA flash support in kernel 6.1.
Fixes: c2a01cf ("mediatek: sync kernel 6.1 from upstream")
Backport BLOCK OF support patch merged upstream and refresh pending
BLOCK patches.
This is a new way to declare partition table for BLOCK device (eMMC
currently supported) with the use of DTS.
Current pending patch are adapted to not cause regression with current
downstream implementation of a similar functionality.
Also enable the new OF_PARTITION config by default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The previous iteration of MediaTek's PHY patches caused various weird bugs.
Drop culprit patch 733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch
and use the most recent iteration of the patchset which has been posted to the
netdev mailing list.
Link: https://patchwork.kernel.org/project/netdevbpf/list/?series=895513&state=*
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Apply changes suggested by SkyLake Huang for pending series improving
MediaTek Ethernet PHY drivers.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Hardware:
- SoC: MediaTek MT7981B
- CPU: 2x 1.3 GHz Cortex-A53
- Flash: 128 MiB SPI NAND
- RAM: 512 MiB
- WLAN: 2.4 GHz, 5 GHz (MediaTek MT7976CN, 802.11ax)
- Ethernet: 1x 10/100/1000/2500 Mbps WAN, 1x10/100/1000 Mbps LAN
- USB 3.0 port
- Buttons: 1 Reset button, 1 slider button
- LEDs: 1x Red, 1x White
- Serial console: internal test points, 115200 8n1
- Power: 5 VDC, 3 A
Installation:
The installation must be done via TFTP by disassembling the router.
On other occasions Cudy has distributed intermediate firmware to make
installation easier, and so I recommend checking the Wiki for this
device if there is a more convenient solution than the one below.
To install using TFTP:
1. Connect to UART.
2. With the router off, press the RESET button. While the router is turning
on, the button should continue to be pressed for at least 5 seconds.
3. A u-boot shell will automatically open.
4. Connect to LAN and set your IP to 192.168.1.88/24. Configure a
TFTP server and an OpenWrt initramfs-kernel.bin firmware file.
5. Run these steps in u-boot using the name of your file.
setenv bootfile initramfs-kernel.bin
tftpboot
bootm
6. If you can reach LuCI or SSH now, just use the sysupgrade image
with the 'Keep settings' option turned off.
Signed-off-by: Luis Mita <luis@luismita.com>
The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Assign pwm function of PWM0 pin to the pwm-fan.
This is mostly just cosmetics as it basically reflects the default
setting of that pin.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add additionals possible pinctrl group for pwm2~7 on pins
pin 4 (GPIO_A) pwm7
pin 58 (JTAG_JTDI) pwm2
pin 59 (JTAG_JTDO) pwm3
pin 60 (JTAG_JTMS) pwm4
pin 61 (JTAG_JTCLK) pwm5
pin 62 (JTAG_JTRST_N) pwm6
They can be useful e.g. on the BPi-R4 as in that way pwm2~6 can be exposed
on the 26-pin header (pwm6 always, pwm2~5 instead of the full UART).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use pending patchset for 2.5GE PHY driver, unifying LED handling
accross all MediaTek Ethernet PHYs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add memory regions and devices used for wireless offloading to the
device tree for MT7988.
This allows using WED on devices with MT7988 SoC and MT7995E, MT7996E or
MT7992E wireless controllers.
Devices with 4 GiB of RAM (or more) will still need ajustments to avoid
running out of swiotlb entries.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Fix a use-after-free bug in mtk_wed_setup_tc_block_cb()
which leads to kernel panic when setup multiple ap
interfaces on one band of mt798x.
Signed-off-by: Zheng Zhang <everything411@qq.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
The driver for MediaTek gen3 PCIe hosts de-asserts all reset
signals at the same time using a single register write operation.
Delay the de-assertion of the #PERST signal by 100ms as some PCIe
devices fail to come up otherwise.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
