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rockchip: rk3568 overclock to 2.2GHz

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No sense, use at your own risk.
This commit is contained in:
AmadeusGhost 2023-04-12 00:25:07 +08:00
parent bb084c1d09
commit c28b7a5625
12 changed files with 162 additions and 15 deletions
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4
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
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@ -212,8 +212,8 @@
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;

0
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s-plus.dts Executable file → Normal file
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1
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi
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@ -5,6 +5,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
#include "rk3568-pro-opp.dtsi"
/ {
aliases {

13
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts Executable file → Normal file
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@ -472,7 +472,6 @@
};
&pcie3x1 {
bus-range = <0x10 0x1f>;
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
@ -486,13 +485,12 @@
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
realtek,led-data = <0x78>;
};
};
};
&pcie3x2 {
bus-range = <0x20 0x2f>;
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
@ -506,12 +504,11 @@
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
realtek,led-data = <0x78>;
};
};
};
&pinctrl {
leds {
sys_led_pin: sys-led-pin {
@ -570,10 +567,6 @@
status = "okay";
};
&pwm0 {
status = "disabled";
};
&rng {
status = "okay";
};
@ -685,4 +678,4 @@
remote-endpoint = <&hdmi_in_vp0>;
};
};
#endif
#endif

1
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts
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@ -4,6 +4,7 @@
/dts-v1/;
#include "rk3568-hinlink-opc.dtsi"
#include "rk3568-pro-opp.dtsi"
/ {
model = "HINLINK OPC-H66K Board";

1
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts
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@ -4,6 +4,7 @@
/dts-v1/;
#include "rk3568-hinlink-opc.dtsi"
#include "rk3568-pro-opp.dtsi"
/ {
model = "HINLINK OPC-H68K Board";

18
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&cpu0_opp_table {
opp-2088000000 {
opp-hz = /bits/ 64 <2088000000>;
opp-microvolt = <1200000>;
};
opp-2184000000 {
opp-hz = /bits/ 64 <2184000000>;
opp-microvolt = <1250000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1275000>;
};
};

1
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts
View File

@ -3,6 +3,7 @@
/dts-v1/;
#include "rk3568-fastrhino.dtsi"
#include "rk3568-pro-opp.dtsi"
/ {
model = "FastRhino R66S";

1
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts
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@ -3,6 +3,7 @@
/dts-v1/;
#include "rk3568-fastrhino.dtsi"
#include "rk3568-pro-opp.dtsi"
/ {
model = "FastRhino R68S";

5
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
View File

@ -44,7 +44,6 @@
label = "blue:work";
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-user {
@ -335,8 +334,8 @@
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;

66
target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch Normal file
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@ -0,0 +1,66 @@
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -53,7 +53,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
- clocks = <&scmi_clk 0>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -63,6 +63,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -72,6 +73,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -81,6 +83,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -136,6 +139,7 @@
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
scmi_clk: protocol@14 {
reg = <0x14>;
@@ -193,6 +197,7 @@
scmi_shmem: sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
+ status = "disabled";
};
};
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
}
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11),
+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11),
+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),

66
target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch Normal file
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@ -0,0 +1,66 @@
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -53,7 +53,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
- clocks = <&scmi_clk 0>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -63,6 +63,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -72,6 +73,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -81,6 +83,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -136,6 +139,7 @@
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
scmi_clk: protocol@14 {
reg = <0x14>;
@@ -193,6 +197,7 @@
scmi_shmem: sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
+ status = "disabled";
};
};
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
}
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11),
+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11),
+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9),
+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),