diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi index b9b907674..c6146a733 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi @@ -212,8 +212,8 @@ regulator-name = "vdd_cpu"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; regulator-ramp-delay = <2300>; vin-supply = <&vcc5v0_sys>; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s-plus.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s-plus.dts old mode 100755 new mode 100644 diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi index c3e015937..8babafdfa 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi @@ -5,6 +5,7 @@ #include #include #include "rk3568.dtsi" +#include "rk3568-pro-opp.dtsi" / { aliases { diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts old mode 100755 new mode 100644 index f29ea147f..00d23823c --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts @@ -472,7 +472,6 @@ }; &pcie3x1 { - bus-range = <0x10 0x1f>; num-lanes = <1>; reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -486,13 +485,12 @@ compatible = "pci10ec,8125"; reg = <0x000000 0 0 0 0>; - realtek,led-data = <0x4078>; + realtek,led-data = <0x78>; }; }; }; &pcie3x2 { - bus-range = <0x20 0x2f>; num-lanes = <1>; reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -506,12 +504,11 @@ compatible = "pci10ec,8125"; reg = <0x000000 0 0 0 0>; - realtek,led-data = <0x4078>; + realtek,led-data = <0x78>; }; }; }; - &pinctrl { leds { sys_led_pin: sys-led-pin { @@ -570,10 +567,6 @@ status = "okay"; }; -&pwm0 { - status = "disabled"; -}; - &rng { status = "okay"; }; @@ -685,4 +678,4 @@ remote-endpoint = <&hdmi_in_vp0>; }; }; -#endif \ No newline at end of file +#endif diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts index 2d578dbcf..f290ff379 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "rk3568-hinlink-opc.dtsi" +#include "rk3568-pro-opp.dtsi" / { model = "HINLINK OPC-H66K Board"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts index befa4ee8d..ab93b7768 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "rk3568-hinlink-opc.dtsi" +#include "rk3568-pro-opp.dtsi" / { model = "HINLINK OPC-H68K Board"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi new file mode 100644 index 000000000..6a30ac5b5 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&cpu0_opp_table { + opp-2088000000 { + opp-hz = /bits/ 64 <2088000000>; + opp-microvolt = <1200000>; + }; + + opp-2184000000 { + opp-hz = /bits/ 64 <2184000000>; + opp-microvolt = <1250000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1275000>; + }; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts index 60733c123..9b07bbdf7 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "rk3568-fastrhino.dtsi" +#include "rk3568-pro-opp.dtsi" / { model = "FastRhino R66S"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts index 020b7f015..64a4a5bb2 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "rk3568-fastrhino.dtsi" +#include "rk3568-pro-opp.dtsi" / { model = "FastRhino R68S"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts index 8e1fc8aca..6b14437e7 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts @@ -44,7 +44,6 @@ label = "blue:work"; gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - }; led-user { @@ -335,8 +334,8 @@ regulator-name = "vdd_cpu"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; regulator-ramp-delay = <2300>; vin-supply = <&vcc5v0_sys>; diff --git a/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch b/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch new file mode 100644 index 000000000..7d4b1eb98 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch @@ -0,0 +1,66 @@ +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -53,7 +53,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; +- clocks = <&scmi_clk 0>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -63,6 +63,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -72,6 +73,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -81,6 +83,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -136,6 +139,7 @@ + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; ++ status = "disabled"; + + scmi_clk: protocol@14 { + reg = <0x14>; +@@ -193,6 +197,7 @@ + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; ++ status = "disabled"; + }; + }; + +--- a/drivers/clk/rockchip/clk-rk3568.c ++++ b/drivers/clk/rockchip/clk-rk3568.c +@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + } + + static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { ++ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11), ++ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11), ++ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), diff --git a/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch b/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch new file mode 100644 index 000000000..7d4b1eb98 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch @@ -0,0 +1,66 @@ +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -53,7 +53,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; +- clocks = <&scmi_clk 0>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -63,6 +63,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -72,6 +73,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -81,6 +83,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; ++ clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; +@@ -136,6 +139,7 @@ + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; ++ status = "disabled"; + + scmi_clk: protocol@14 { + reg = <0x14>; +@@ -193,6 +197,7 @@ + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; ++ status = "disabled"; + }; + }; + +--- a/drivers/clk/rockchip/clk-rk3568.c ++++ b/drivers/clk/rockchip/clk-rk3568.c +@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + } + + static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { ++ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11), ++ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11), ++ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9), ++ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),