mirror of
https://github.com/coolsnowwolf/lede.git
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ipq60xx: rename target to qualcommax
This commit is contained in:
coolsnowwolf
parent
8fcf7f0915
commit
b7fcf33b05
@ -8,31 +8,38 @@ touch /etc/config/ubootenv
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board=$(board_name)
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board=$(board_name)
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case "$board" in
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case "$board" in
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dynalink,dl-wrx36)
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compex,wpq873|\
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idx="$(find_mtd_index 0:appsblenv)"
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[ -n "$idx" ] && \
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
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;;
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edgecore,eap102|\
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edgecore,eap102|\
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zyxel,nbg7815)
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zyxel,nbg7815)
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idx="$(find_mtd_index 0:appsblenv)"
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idx="$(find_mtd_index 0:appsblenv)"
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[ -n "$idx" ] && \
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[ -n "$idx" ] && \
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1"
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1"
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;;
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;;
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dynalink,dl-wrx36|\
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netgear,rax120v2|\
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netgear,wax218|\
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netgear,wax620|\
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netgear,wax630)
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idx="$(find_mtd_index 0:appsblenv)"
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[ -n "$idx" ] && \
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
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;;
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edimax,cax1800)
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edimax,cax1800)
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idx="$(find_mtd_index 0:appsblenv)"
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idx="$(find_mtd_index 0:appsblenv)"
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[ -n "$idx" ] && \
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[ -n "$idx" ] && \
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000"
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000"
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;;
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;;
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redmi,ax6|\
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linksys,mr7350|\
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xiaomi,ax3600|\
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linksys,mx4200v1|\
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xiaomi,ax9000)
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linksys,mx4200v2)
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idx="$(find_mtd_index 0:appsblenv)"
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idx="$(find_mtd_index u_env)"
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[ -n "$idx" ] && \
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[ -n "$idx" ] && \
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000"
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ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
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idx2="$(find_mtd_index bdata)"
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;;
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[ -n "$idx2" ] && \
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prpl,haze)
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ubootenv_add_uci_sys_config "/dev/mtd$idx2" "0x0" "0x10000" "0x20000"
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mmcpart="$(find_mmc_part 0:APPSBLENV)"
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[ -n "$mmcpart" ] && \
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ubootenv_add_uci_config "$mmcpart" "0x0" "0x40000" "0x400" "0x100"
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;;
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;;
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qnap,301w)
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qnap,301w)
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idx="$(find_mtd_index 0:appsblenv)"
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idx="$(find_mtd_index 0:appsblenv)"
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@ -1,21 +0,0 @@
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include $(TOPDIR)/rules.mk
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ARCH:=aarch64
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BOARD:=ipq60xx
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BOARDNAME:=Qualcomm Atheros IPQ60xx
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FEATURES:=squashfs ramdisk fpu nand rtc emmc
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KERNELNAME:=Image dtbs
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CPU_TYPE:=cortex-a53
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SUBTARGETS:=generic
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KERNEL_PATCHVER:=5.15
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += \
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kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
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kmod-leds-gpio kmod-gpio-button-hotplug \
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uboot-envtools \
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kmod-qca-nss-dp kmod-qca-nss-drv-64 kmod-qca-nss-drv-pppoe-64 \
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nss-firmware-ipq6018 qca-nss-ecm-64
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$(eval $(call BuildTarget))
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@ -1,25 +0,0 @@
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#!/bin/sh
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#
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# Copyright (C) 2015 OpenWrt.org
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#
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. /lib/functions/uci-defaults.sh
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board_config_update
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board=$(board_name)
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case "$board" in
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cmiot,ax18|\
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zn,m2)
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ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth0"
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ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "wlan1"
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ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "wlan0"
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;;
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*)
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;;
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esac
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board_config_flush
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exit 0
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@ -1,51 +0,0 @@
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. /lib/functions/uci-defaults.sh
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. /lib/functions/system.sh
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setup_network()
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{
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local macaddr
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case $(board_name) in
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cmiot,ax18|\
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qihoo,v6|\
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zn,m2)
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ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0"
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;;
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linksys,mr7350)
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ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3" "eth4"
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;;
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tplink,eap610-outdoor)
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# /tmp/factory_data should be mounted by preinit
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macaddr=$(get_mac_binary /tmp/factory_data/default-mac 0)
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ucidef_set_interface_macaddr "lan" "$macaddr"
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ucidef_set_interface_lan "eth0" "dhcp"
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;;
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*)
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ucidef_set_interface_lan "eth0"
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;;
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esac
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}
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setup_macs()
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{
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case $(board_name) in
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linksys,mr7350)
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wan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
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lan_mac=$(macaddr_add "$wan_mac" 1)
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;;
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qihoo,v6)
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lan_mac=$(mtd_get_mac_ascii factory lanMac)
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wan_mac=$(macaddr_add "$lan_mac" 1)
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;;
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esac
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[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
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[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
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}
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board_config_update
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setup_network
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setup_macs
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board_config_flush
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exit 0
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@ -1,81 +0,0 @@
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#!/bin/sh
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[ -e /lib/firmware/$FIRMWARE ] && exit 0
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. /lib/functions/caldata.sh
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. /lib/functions/system.sh
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board=$(board_name)
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ath11k_generate_macs() {
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case "$board" in
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linksys,mr7350)
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eth=$(mtd_get_mac_ascii devinfo hw_mac_addr)
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;;
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*)
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eth=$(cat /sys/class/net/eth0/address)
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;;
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esac
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touch /lib/firmware/ath11k-macs
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mac1=$(macaddr_add $eth 2)
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mac2=$(macaddr_add $eth 3)
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mac3=$(macaddr_add $eth 4)
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echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
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echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
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echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
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}
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ath11kcal_die() {
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echo "ath11cal: " "$*"
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exit 1
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}
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ath11kcal_extract() {
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local part=$1
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local offset=$2
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local count=$3
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local mtd
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mtd=$(find_mtd_chardev $part)
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[ -n "$mtd" ] || \
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ath11kcal_die "no mtd device found for partition $part"
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dd if=$mtd of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
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ath11kcal_die "failed to extract calibration data from $mtd"
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}
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case "$FIRMWARE" in
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"ath11k/IPQ6018/hw1.0/cal-ahb-c000000.wifi.bin")
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case "$board" in
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cmiot,ax18|\
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linksys,mr7350|\
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qihoo,v6|\
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zn,m2)
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caldata_extract "0:art" 0x1000 0x10000
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;;
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tplink,eap610-outdoor)
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# /tmp/factory_data should be mounted by preinit
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cp /tmp/factory_data/radio "/lib/firmware/$FIRMWARE"
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;;
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*)
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caldata_die "Don't know how to read caldata for $board"
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;;
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esac
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;;
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ath11k-macs)
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case "$board" in
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cmiot,ax18|\
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linksys,mr7350|\
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qihoo,v6|\
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zn,m2)
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ath11k_generate_macs
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;;
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esac
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;;
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*)
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exit 1
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;;
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esac
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@ -1,16 +0,0 @@
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[ "$ACTION" == "add" ] || exit 0
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PHY_NUM=${DEVPATH##*/phy}
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[ -n $PHY_NUM ] || exit 0
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. /lib/functions.sh
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. /lib/functions/system.sh
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case "$(board_name)" in
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tplink,eap610-outdoor)
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# /tmp/factory_data should have been mounted by preinit
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base_mac=$(get_mac_binary /tmp/factory_data/default-mac 0)
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macaddr_add $base_mac $(expr "$PHY_NUM" + 1) > /sys${DEVPATH}/macaddress
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;;
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esac
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@ -1,19 +0,0 @@
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#!/bin/sh
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preinit_mount_factory_data() {
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local mtd_path
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. /lib/functions.sh
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. /lib/functions/system.sh
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case $(board_name) in
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tplink,eap610-outdoor)
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mtd_path=$(find_mtd_chardev "factory_data")
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ubiattach --dev-path="$mtd_path" --devn=1
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mkdir /tmp/factory_data
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mount -o ro,noatime -t ubifs ubi1:ubi_factory_data /tmp/factory_data
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;;
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esac
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}
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boot_hook_add preinit_main preinit_mount_factory_data
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@ -1,104 +0,0 @@
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PART_NAME=firmware
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REQUIRE_IMAGE_METADATA=1
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RAMFS_COPY_BIN='fw_printenv fw_setenv'
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RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
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linksys_get_boot_part() {
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local cur_boot_part
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local args
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# Try to find rootfs from kernel arguments
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read -r args < /proc/cmdline
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for arg in $args; do
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local ubi_mtd_arg=${arg#ubi.mtd=}
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case "$ubi_mtd_arg" in
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rootfs|alt_rootfs)
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echo "$ubi_mtd_arg"
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return
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;;
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esac
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done
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# Fallback to u-boot env (e.g. when running sysfs)
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cur_boot_part="$(/usr/sbin/fw_printenv -n boot_part)"
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case $cur_boot_part in
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1)
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echo rootfs
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;;
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2|*)
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echo alt_rootfs
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;;
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esac
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}
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|
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linksys_prepare_ubi() {
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local oem_ubivol
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|
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local mtdnum
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local ubidev
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mtdnum=$(find_mtd_index "$CI_UBIPART")
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if [ ! "$mtdnum" ]; then
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return
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|
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fi
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|
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ubidev=$(nand_find_ubi "$CI_UBIPART")
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|
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if [ ! "$ubidev" ]; then
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ubiattach --mtdn="$mtdnum"
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|
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ubidev=$(nand_find_ubi "$CI_UBIPART")
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|
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fi
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|
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if [ "$ubidev" ]; then
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oem_ubivol=$(nand_find_volume "$ubidev" squashfs)
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|
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[ "$oem_ubivol" ] && ubirmvol "/dev/$ubidev" --name=squashfs
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|
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fi
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|
||||||
}
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|
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|
||||||
linksys_do_upgrade() {
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|
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local current_boot_slot
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|
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local new_boot_part
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|
||||||
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|
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current_boot_slot=$(linksys_get_boot_part)
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|
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case $current_boot_slot in
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|
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rootfs)
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|
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CI_UBIPART="alt_rootfs"
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|
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CI_KERNPART="alt_kernel"
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new_boot_part=2
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|
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;;
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|
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alt_rootfs)
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CI_UBIPART="rootfs"
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|
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CI_KERNPART="kernel"
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|
||||||
new_boot_part=1
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|
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;;
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esac
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|
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echo "Updating mtd=$CI_UBIPART, boot_part=$new_boot_part"
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|
||||||
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|
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fw_setenv -s - <<-EOF
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|
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boot_part $new_boot_part
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|
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auto_recovery yes
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|
||||||
EOF
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|
||||||
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|
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linksys_prepare_ubi
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|
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nand_do_upgrade "$1"
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|
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}
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|
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|
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platform_check_image() {
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|
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return 0;
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|
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}
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|
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|
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platform_do_upgrade() {
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|
||||||
case "$(board_name)" in
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|
||||||
linksys,mr7350)
|
|
||||||
linksys_do_upgrade "$1"
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|
||||||
;;
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|
||||||
cmiot,ax18|\
|
|
||||||
qihoo,v6|\
|
|
||||||
zn,m2)
|
|
||||||
nand_do_upgrade "$1"
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|
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;;
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|
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*)
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|
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default_do_upgrade "$1"
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|
||||||
;;
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esac
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}
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@ -1,506 +0,0 @@
|
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CONFIG_64BIT=y
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|
||||||
# CONFIG_APQ_GCC_8084 is not set
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|
||||||
# CONFIG_APQ_MMCC_8084 is not set
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|
||||||
CONFIG_AQUANTIA_PHY=y
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|
||||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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|
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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|
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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|
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CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
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|
||||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
|
||||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
|
||||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
|
||||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
|
||||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
|
||||||
CONFIG_ARCH_QCOM=y
|
|
||||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
|
||||||
CONFIG_ARCH_STACKWALK=y
|
|
||||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
|
||||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
|
||||||
CONFIG_ARM64=y
|
|
||||||
CONFIG_ARM64_4K_PAGES=y
|
|
||||||
CONFIG_ARM64_CRYPTO=y
|
|
||||||
CONFIG_ARM64_ERRATUM_1165522=y
|
|
||||||
CONFIG_ARM64_ERRATUM_1286807=y
|
|
||||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
|
||||||
CONFIG_ARM64_PAGE_SHIFT=12
|
|
||||||
CONFIG_ARM64_PA_BITS=48
|
|
||||||
CONFIG_ARM64_PA_BITS_48=y
|
|
||||||
CONFIG_ARM64_PTR_AUTH=y
|
|
||||||
CONFIG_ARM64_PTR_AUTH_KERNEL=y
|
|
||||||
CONFIG_ARM64_SVE=y
|
|
||||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
|
||||||
CONFIG_ARM64_VA_BITS=39
|
|
||||||
CONFIG_ARM64_VA_BITS_39=y
|
|
||||||
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
|
|
||||||
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
|
|
||||||
CONFIG_ARM_AMBA=y
|
|
||||||
CONFIG_ARM_ARCH_TIMER=y
|
|
||||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
|
||||||
CONFIG_ARM_CPUIDLE=y
|
|
||||||
CONFIG_ARM_GIC=y
|
|
||||||
CONFIG_ARM_GIC_V2M=y
|
|
||||||
CONFIG_ARM_GIC_V3=y
|
|
||||||
CONFIG_ARM_GIC_V3_ITS=y
|
|
||||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
|
||||||
# CONFIG_ARM_MHU_V2 is not set
|
|
||||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
|
||||||
CONFIG_ARM_PSCI_FW=y
|
|
||||||
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
|
|
||||||
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
|
|
||||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_BLK_MQ_PCI=y
|
|
||||||
CONFIG_BLK_MQ_VIRTIO=y
|
|
||||||
CONFIG_BLK_PM=y
|
|
||||||
CONFIG_CAVIUM_TX2_ERRATUM_219=y
|
|
||||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
|
||||||
CONFIG_CLONE_BACKWARDS=y
|
|
||||||
CONFIG_COMMON_CLK=y
|
|
||||||
CONFIG_COMMON_CLK_QCOM=y
|
|
||||||
# CONFIG_COMPAT_32BIT_TIME is not set
|
|
||||||
CONFIG_COREDUMP=y
|
|
||||||
CONFIG_CPUFREQ_DT=y
|
|
||||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
|
||||||
CONFIG_CPU_FREQ=y
|
|
||||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
|
||||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
|
||||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
|
||||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
|
||||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
|
||||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
|
||||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
|
||||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
|
||||||
# CONFIG_CPU_FREQ_STAT is not set
|
|
||||||
CONFIG_CPU_FREQ_THERMAL=y
|
|
||||||
CONFIG_CPU_IDLE=y
|
|
||||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
|
||||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
|
||||||
CONFIG_CPU_PM=y
|
|
||||||
CONFIG_CPU_RMAP=y
|
|
||||||
CONFIG_CPU_THERMAL=y
|
|
||||||
CONFIG_CRC16=y
|
|
||||||
CONFIG_CRC8=y
|
|
||||||
CONFIG_CRYPTO_AUTHENC=y
|
|
||||||
CONFIG_CRYPTO_CBC=y
|
|
||||||
CONFIG_CRYPTO_DEFLATE=y
|
|
||||||
CONFIG_CRYPTO_DEV_QCE=y
|
|
||||||
CONFIG_CRYPTO_DEV_QCE_AEAD=y
|
|
||||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
|
|
||||||
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
|
|
||||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
|
|
||||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
|
|
||||||
CONFIG_CRYPTO_DEV_QCE_SHA=y
|
|
||||||
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
|
|
||||||
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
|
|
||||||
CONFIG_CRYPTO_DEV_QCOM_RNG=y
|
|
||||||
CONFIG_CRYPTO_ECB=y
|
|
||||||
CONFIG_CRYPTO_HASH_INFO=y
|
|
||||||
CONFIG_CRYPTO_HW=y
|
|
||||||
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
|
||||||
CONFIG_CRYPTO_LIB_DES=y
|
|
||||||
CONFIG_CRYPTO_LIB_SHA256=y
|
|
||||||
CONFIG_CRYPTO_LZO=y
|
|
||||||
CONFIG_CRYPTO_RNG=y
|
|
||||||
CONFIG_CRYPTO_RNG2=y
|
|
||||||
CONFIG_CRYPTO_SHA1=y
|
|
||||||
CONFIG_CRYPTO_SHA256=y
|
|
||||||
CONFIG_CRYPTO_XTS=y
|
|
||||||
CONFIG_CRYPTO_ZSTD=y
|
|
||||||
CONFIG_DCACHE_WORD_ACCESS=y
|
|
||||||
CONFIG_DEV_COREDUMP=y
|
|
||||||
CONFIG_DMADEVICES=y
|
|
||||||
CONFIG_DMA_DIRECT_REMAP=y
|
|
||||||
CONFIG_DMA_ENGINE=y
|
|
||||||
CONFIG_DMA_OF=y
|
|
||||||
CONFIG_DMA_REMAP=y
|
|
||||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
|
||||||
CONFIG_DTC=y
|
|
||||||
CONFIG_DT_IDLE_STATES=y
|
|
||||||
CONFIG_EDAC_SUPPORT=y
|
|
||||||
CONFIG_FIXED_PHY=y
|
|
||||||
CONFIG_FIX_EARLYCON_MEM=y
|
|
||||||
CONFIG_FRAME_POINTER=y
|
|
||||||
CONFIG_FUJITSU_ERRATUM_010001=y
|
|
||||||
CONFIG_FWNODE_MDIO=y
|
|
||||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
|
||||||
CONFIG_GENERIC_ALLOCATOR=y
|
|
||||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
|
||||||
CONFIG_GENERIC_BUG=y
|
|
||||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
|
||||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
|
||||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
|
||||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
|
||||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
|
||||||
CONFIG_GENERIC_CSUM=y
|
|
||||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
|
||||||
CONFIG_GENERIC_FIND_FIRST_BIT=y
|
|
||||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
|
||||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
|
||||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
|
||||||
CONFIG_GENERIC_IRQ_SHOW=y
|
|
||||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
|
||||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
|
||||||
CONFIG_GENERIC_MSI_IRQ=y
|
|
||||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
|
||||||
CONFIG_GENERIC_PCI_IOMAP=y
|
|
||||||
CONFIG_GENERIC_PHY=y
|
|
||||||
CONFIG_GENERIC_PINCONF=y
|
|
||||||
CONFIG_GENERIC_PINCTRL_GROUPS=y
|
|
||||||
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
|
|
||||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
|
||||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
|
||||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
|
||||||
CONFIG_GENERIC_STRNLEN_USER=y
|
|
||||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
|
||||||
CONFIG_GLOB=y
|
|
||||||
CONFIG_GPIOLIB_IRQCHIP=y
|
|
||||||
CONFIG_GPIO_CDEV=y
|
|
||||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
|
||||||
CONFIG_HARDIRQS_SW_RESEND=y
|
|
||||||
CONFIG_HAS_DMA=y
|
|
||||||
CONFIG_HAS_IOMEM=y
|
|
||||||
CONFIG_HAS_IOPORT_MAP=y
|
|
||||||
CONFIG_HWSPINLOCK=y
|
|
||||||
CONFIG_HWSPINLOCK_QCOM=y
|
|
||||||
CONFIG_I2C=y
|
|
||||||
CONFIG_I2C_BOARDINFO=y
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
CONFIG_I2C_HELPER_AUTO=y
|
|
||||||
# CONFIG_I2C_QCOM_CCI is not set
|
|
||||||
CONFIG_I2C_QUP=y
|
|
||||||
CONFIG_IIO=y
|
|
||||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
|
||||||
CONFIG_INITRAMFS_SOURCE=""
|
|
||||||
CONFIG_IPQ_APSS_6018=y
|
|
||||||
# CONFIG_IPQ_APSS_8074 is not set
|
|
||||||
CONFIG_IPQ_APSS_PLL=y
|
|
||||||
# CONFIG_IPQ_GCC_4019 is not set
|
|
||||||
CONFIG_IPQ_GCC_6018=y
|
|
||||||
# CONFIG_IPQ_GCC_806X is not set
|
|
||||||
# CONFIG_IPQ_GCC_8074 is not set
|
|
||||||
# CONFIG_IPQ_LCC_806X is not set
|
|
||||||
CONFIG_IRQCHIP=y
|
|
||||||
CONFIG_IRQ_DOMAIN=y
|
|
||||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
|
||||||
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
|
|
||||||
CONFIG_IRQ_FORCED_THREADING=y
|
|
||||||
CONFIG_IRQ_WORK=y
|
|
||||||
# CONFIG_KPSS_XCC is not set
|
|
||||||
CONFIG_LIBFDT=y
|
|
||||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
|
||||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
|
||||||
CONFIG_LZO_COMPRESS=y
|
|
||||||
CONFIG_LZO_DECOMPRESS=y
|
|
||||||
CONFIG_MAILBOX=y
|
|
||||||
# CONFIG_MAILBOX_TEST is not set
|
|
||||||
CONFIG_MDIO_BUS=y
|
|
||||||
CONFIG_MDIO_DEVICE=y
|
|
||||||
CONFIG_MDIO_DEVRES=y
|
|
||||||
CONFIG_MDIO_IPQ4019=y
|
|
||||||
# CONFIG_MDM_GCC_9615 is not set
|
|
||||||
# CONFIG_MDM_LCC_9615 is not set
|
|
||||||
CONFIG_MEMFD_CREATE=y
|
|
||||||
# CONFIG_MFD_HI6421_SPMI is not set
|
|
||||||
# CONFIG_MFD_QCOM_RPM is not set
|
|
||||||
CONFIG_MFD_SPMI_PMIC=y
|
|
||||||
CONFIG_MFD_SYSCON=y
|
|
||||||
CONFIG_MIGRATION=y
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_BLOCK=y
|
|
||||||
CONFIG_MMC_BLOCK_MINORS=32
|
|
||||||
CONFIG_MMC_CQHCI=y
|
|
||||||
CONFIG_MMC_SDHCI=y
|
|
||||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
|
||||||
CONFIG_MMC_SDHCI_MSM=y
|
|
||||||
# CONFIG_MMC_SDHCI_PCI is not set
|
|
||||||
CONFIG_MMC_SDHCI_PLTFM=y
|
|
||||||
CONFIG_MODULES_USE_ELF_RELA=y
|
|
||||||
# CONFIG_MSM_GCC_8660 is not set
|
|
||||||
# CONFIG_MSM_GCC_8916 is not set
|
|
||||||
# CONFIG_MSM_GCC_8939 is not set
|
|
||||||
# CONFIG_MSM_GCC_8960 is not set
|
|
||||||
# CONFIG_MSM_GCC_8974 is not set
|
|
||||||
# CONFIG_MSM_GCC_8994 is not set
|
|
||||||
# CONFIG_MSM_GCC_8996 is not set
|
|
||||||
# CONFIG_MSM_GCC_8998 is not set
|
|
||||||
# CONFIG_MSM_GPUCC_8998 is not set
|
|
||||||
# CONFIG_MSM_LCC_8960 is not set
|
|
||||||
# CONFIG_MSM_MMCC_8960 is not set
|
|
||||||
# CONFIG_MSM_MMCC_8974 is not set
|
|
||||||
# CONFIG_MSM_MMCC_8996 is not set
|
|
||||||
# CONFIG_MSM_MMCC_8998 is not set
|
|
||||||
CONFIG_MTD_NAND_CORE=y
|
|
||||||
CONFIG_MTD_NAND_ECC=y
|
|
||||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
|
||||||
CONFIG_MTD_NAND_QCOM=y
|
|
||||||
CONFIG_MTD_QCOMSMEM_PARTS=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_MTD_SPI_NOR=y
|
|
||||||
CONFIG_MTD_UBI=y
|
|
||||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
|
||||||
CONFIG_MTD_UBI_BLOCK=y
|
|
||||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
|
||||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
|
||||||
CONFIG_NEED_DMA_MAP_STATE=y
|
|
||||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
|
||||||
CONFIG_NET_FLOW_LIMIT=y
|
|
||||||
CONFIG_NET_SELFTESTS=y
|
|
||||||
CONFIG_NET_SWITCHDEV=y
|
|
||||||
CONFIG_NLS=y
|
|
||||||
CONFIG_NO_HZ_COMMON=y
|
|
||||||
CONFIG_NO_HZ_IDLE=y
|
|
||||||
CONFIG_NR_CPUS=4
|
|
||||||
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
|
|
||||||
CONFIG_NVMEM=y
|
|
||||||
# CONFIG_NVMEM_SPMI_SDAM is not set
|
|
||||||
CONFIG_NVMEM_SYSFS=y
|
|
||||||
CONFIG_OF=y
|
|
||||||
CONFIG_OF_ADDRESS=y
|
|
||||||
CONFIG_OF_EARLY_FLATTREE=y
|
|
||||||
CONFIG_OF_FLATTREE=y
|
|
||||||
CONFIG_OF_GPIO=y
|
|
||||||
CONFIG_OF_IRQ=y
|
|
||||||
CONFIG_OF_KOBJ=y
|
|
||||||
CONFIG_OF_MDIO=y
|
|
||||||
CONFIG_PADATA=y
|
|
||||||
CONFIG_PARTITION_PERCPU=y
|
|
||||||
CONFIG_PCI=y
|
|
||||||
CONFIG_PCIEAER=y
|
|
||||||
CONFIG_PCIEASPM=y
|
|
||||||
CONFIG_PCIEASPM_DEFAULT=y
|
|
||||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
|
||||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
|
||||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
|
||||||
CONFIG_PCIEPORTBUS=y
|
|
||||||
CONFIG_PCIE_DW=y
|
|
||||||
CONFIG_PCIE_DW_HOST=y
|
|
||||||
CONFIG_PCIE_PME=y
|
|
||||||
CONFIG_PCIE_QCOM=y
|
|
||||||
CONFIG_PCI_DOMAINS=y
|
|
||||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
|
||||||
CONFIG_PCI_MSI=y
|
|
||||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
|
||||||
CONFIG_PGTABLE_LEVELS=3
|
|
||||||
CONFIG_PHYLIB=y
|
|
||||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
|
||||||
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
|
|
||||||
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
|
|
||||||
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
|
|
||||||
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
|
|
||||||
# CONFIG_PHY_QCOM_PCIE2 is not set
|
|
||||||
CONFIG_PHY_QCOM_QMP=y
|
|
||||||
CONFIG_PHY_QCOM_QUSB2=y
|
|
||||||
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
|
|
||||||
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
|
|
||||||
# CONFIG_PHY_QCOM_USB_SS is not set
|
|
||||||
CONFIG_PINCTRL=y
|
|
||||||
# CONFIG_PINCTRL_APQ8064 is not set
|
|
||||||
# CONFIG_PINCTRL_APQ8084 is not set
|
|
||||||
# CONFIG_PINCTRL_IPQ4019 is not set
|
|
||||||
CONFIG_PINCTRL_IPQ6018=y
|
|
||||||
# CONFIG_PINCTRL_IPQ8064 is not set
|
|
||||||
# CONFIG_PINCTRL_IPQ8074 is not set
|
|
||||||
# CONFIG_PINCTRL_MDM9615 is not set
|
|
||||||
CONFIG_PINCTRL_MSM=y
|
|
||||||
# CONFIG_PINCTRL_MSM8226 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8660 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8916 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8960 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8976 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8994 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8996 is not set
|
|
||||||
# CONFIG_PINCTRL_MSM8998 is not set
|
|
||||||
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
|
|
||||||
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
|
|
||||||
# CONFIG_PINCTRL_QCS404 is not set
|
|
||||||
# CONFIG_PINCTRL_SC7180 is not set
|
|
||||||
# CONFIG_PINCTRL_SDM660 is not set
|
|
||||||
# CONFIG_PINCTRL_SDM845 is not set
|
|
||||||
# CONFIG_PINCTRL_SM8150 is not set
|
|
||||||
# CONFIG_PINCTRL_SM8250 is not set
|
|
||||||
CONFIG_PM=y
|
|
||||||
# CONFIG_PM8916_WATCHDOG is not set
|
|
||||||
CONFIG_PM_CLK=y
|
|
||||||
CONFIG_PM_OPP=y
|
|
||||||
CONFIG_POWER_RESET=y
|
|
||||||
# CONFIG_POWER_RESET_MSM is not set
|
|
||||||
# CONFIG_POWER_RESET_QCOM_PON is not set
|
|
||||||
CONFIG_POWER_SUPPLY=y
|
|
||||||
CONFIG_PRINTK_TIME=y
|
|
||||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
|
||||||
# CONFIG_QCOM_A53PLL is not set
|
|
||||||
# CONFIG_QCOM_AOSS_QMP is not set
|
|
||||||
CONFIG_QCOM_APCS_IPC=y
|
|
||||||
CONFIG_QCOM_APM=y
|
|
||||||
# CONFIG_QCOM_APR is not set
|
|
||||||
CONFIG_QCOM_BAM_DMA=y
|
|
||||||
# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
|
|
||||||
# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
|
|
||||||
# CONFIG_QCOM_CLK_APCS_SDX55 is not set
|
|
||||||
CONFIG_QCOM_CLK_SMD_RPM=y
|
|
||||||
# CONFIG_QCOM_COINCELL is not set
|
|
||||||
# CONFIG_QCOM_COMMAND_DB is not set
|
|
||||||
# CONFIG_QCOM_CPR is not set
|
|
||||||
# CONFIG_QCOM_EBI2 is not set
|
|
||||||
# CONFIG_QCOM_FASTRPC is not set
|
|
||||||
# CONFIG_QCOM_GENI_SE is not set
|
|
||||||
# CONFIG_QCOM_GSBI is not set
|
|
||||||
# CONFIG_QCOM_HFPLL is not set
|
|
||||||
# CONFIG_QCOM_IPCC is not set
|
|
||||||
# CONFIG_QCOM_LLCC is not set
|
|
||||||
CONFIG_QCOM_MDT_LOADER=y
|
|
||||||
# CONFIG_QCOM_OCMEM is not set
|
|
||||||
# CONFIG_QCOM_PDC is not set
|
|
||||||
CONFIG_QCOM_PIL_INFO=y
|
|
||||||
# CONFIG_QCOM_Q6V5_ADSP is not set
|
|
||||||
CONFIG_QCOM_Q6V5_COMMON=y
|
|
||||||
# CONFIG_QCOM_Q6V5_MSS is not set
|
|
||||||
# CONFIG_QCOM_Q6V5_PAS is not set
|
|
||||||
CONFIG_QCOM_Q6V5_WCSS=y
|
|
||||||
CONFIG_QCOM_QFPROM=y
|
|
||||||
# CONFIG_QCOM_RMTFS_MEM is not set
|
|
||||||
CONFIG_QCOM_RPMCC=y
|
|
||||||
# CONFIG_QCOM_RPMH is not set
|
|
||||||
CONFIG_QCOM_RPMPD=y
|
|
||||||
CONFIG_QCOM_RPROC_COMMON=y
|
|
||||||
CONFIG_QCOM_SCM=y
|
|
||||||
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
|
||||||
CONFIG_QCOM_SMD_RPM=y
|
|
||||||
CONFIG_QCOM_SMEM=y
|
|
||||||
CONFIG_QCOM_SMEM_STATE=y
|
|
||||||
CONFIG_QCOM_SMP2P=y
|
|
||||||
# CONFIG_QCOM_SMSM is not set
|
|
||||||
CONFIG_QCOM_SOCINFO=y
|
|
||||||
CONFIG_QCOM_SPMI_ADC5=y
|
|
||||||
# CONFIG_QCOM_SYSMON is not set
|
|
||||||
CONFIG_QCOM_TSENS=y
|
|
||||||
CONFIG_QCOM_VADC_COMMON=y
|
|
||||||
# CONFIG_QCOM_WCNSS_CTRL is not set
|
|
||||||
# CONFIG_QCOM_WCNSS_PIL is not set
|
|
||||||
CONFIG_QCOM_WDT=y
|
|
||||||
# CONFIG_QCS_GCC_404 is not set
|
|
||||||
# CONFIG_QCS_Q6SSTOP_404 is not set
|
|
||||||
# CONFIG_QCS_TURING_404 is not set
|
|
||||||
CONFIG_QUEUED_RWLOCKS=y
|
|
||||||
CONFIG_QUEUED_SPINLOCKS=y
|
|
||||||
CONFIG_RAS=y
|
|
||||||
CONFIG_RATIONAL=y
|
|
||||||
CONFIG_REGMAP=y
|
|
||||||
CONFIG_REGMAP_MMIO=y
|
|
||||||
CONFIG_REGMAP_SPMI=y
|
|
||||||
CONFIG_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_CPR3=y
|
|
||||||
# CONFIG_REGULATOR_CPR3_NPU is not set
|
|
||||||
CONFIG_REGULATOR_CPR4_APSS=y
|
|
||||||
# CONFIG_REGULATOR_QCOM_LABIBB is not set
|
|
||||||
CONFIG_REGULATOR_QCOM_SMD_RPM=y
|
|
||||||
CONFIG_REGULATOR_QCOM_SPMI=y
|
|
||||||
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
|
|
||||||
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
|
|
||||||
CONFIG_RELOCATABLE=y
|
|
||||||
CONFIG_REMOTEPROC=y
|
|
||||||
CONFIG_REMOTEPROC_CDEV=y
|
|
||||||
CONFIG_RESET_CONTROLLER=y
|
|
||||||
# CONFIG_RESET_QCOM_AOSS is not set
|
|
||||||
# CONFIG_RESET_QCOM_PDC is not set
|
|
||||||
CONFIG_RFS_ACCEL=y
|
|
||||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
|
||||||
CONFIG_RPMSG=y
|
|
||||||
CONFIG_RPMSG_CHAR=y
|
|
||||||
# CONFIG_RPMSG_NS is not set
|
|
||||||
CONFIG_RPMSG_QCOM_GLINK=y
|
|
||||||
CONFIG_RPMSG_QCOM_GLINK_RPM=y
|
|
||||||
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
|
|
||||||
CONFIG_RPMSG_QCOM_SMD=y
|
|
||||||
CONFIG_RPS=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_DRV_PM8XXX=y
|
|
||||||
CONFIG_RTC_I2C_AND_SPI=y
|
|
||||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
|
||||||
# CONFIG_SCHED_CORE is not set
|
|
||||||
CONFIG_SCHED_MC=y
|
|
||||||
CONFIG_SCHED_SMT=y
|
|
||||||
CONFIG_SCHED_THERMAL_PRESSURE=y
|
|
||||||
CONFIG_SCSI=y
|
|
||||||
CONFIG_SCSI_COMMON=y
|
|
||||||
# CONFIG_SCSI_LOWLEVEL is not set
|
|
||||||
# CONFIG_SCSI_PROC_FS is not set
|
|
||||||
# CONFIG_SC_DISPCC_7180 is not set
|
|
||||||
# CONFIG_SC_GCC_7180 is not set
|
|
||||||
# CONFIG_SC_GPUCC_7180 is not set
|
|
||||||
# CONFIG_SC_LPASS_CORECC_7180 is not set
|
|
||||||
# CONFIG_SC_MSS_7180 is not set
|
|
||||||
# CONFIG_SC_VIDEOCC_7180 is not set
|
|
||||||
# CONFIG_SDM_CAMCC_845 is not set
|
|
||||||
# CONFIG_SDM_DISPCC_845 is not set
|
|
||||||
# CONFIG_SDM_GCC_660 is not set
|
|
||||||
# CONFIG_SDM_GCC_845 is not set
|
|
||||||
# CONFIG_SDM_GPUCC_845 is not set
|
|
||||||
# CONFIG_SDM_LPASSCC_845 is not set
|
|
||||||
# CONFIG_SDM_VIDEOCC_845 is not set
|
|
||||||
CONFIG_SERIAL_8250_FSL=y
|
|
||||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
|
||||||
CONFIG_SERIAL_MSM=y
|
|
||||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
|
||||||
CONFIG_SGL_ALLOC=y
|
|
||||||
CONFIG_SG_POOL=y
|
|
||||||
CONFIG_SMP=y
|
|
||||||
# CONFIG_SM_GCC_8150 is not set
|
|
||||||
# CONFIG_SM_GCC_8250 is not set
|
|
||||||
# CONFIG_SM_GPUCC_8150 is not set
|
|
||||||
# CONFIG_SM_GPUCC_8250 is not set
|
|
||||||
# CONFIG_SM_VIDEOCC_8150 is not set
|
|
||||||
# CONFIG_SM_VIDEOCC_8250 is not set
|
|
||||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
|
||||||
CONFIG_SOC_BUS=y
|
|
||||||
CONFIG_SPARSEMEM=y
|
|
||||||
CONFIG_SPARSEMEM_EXTREME=y
|
|
||||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
|
||||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
|
||||||
CONFIG_SPARSE_IRQ=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_MASTER=y
|
|
||||||
CONFIG_SPI_MEM=y
|
|
||||||
CONFIG_SPI_QUP=y
|
|
||||||
CONFIG_SPMI=y
|
|
||||||
# CONFIG_SPMI_HISI3670 is not set
|
|
||||||
CONFIG_SPMI_MSM_PMIC_ARB=y
|
|
||||||
# CONFIG_SPMI_PMIC_CLKDIV is not set
|
|
||||||
CONFIG_SRCU=y
|
|
||||||
CONFIG_SWIOTLB=y
|
|
||||||
CONFIG_SWPHY=y
|
|
||||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
|
||||||
CONFIG_THERMAL=y
|
|
||||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
|
||||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
|
||||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
|
||||||
CONFIG_THERMAL_OF=y
|
|
||||||
CONFIG_THREAD_INFO_IN_TASK=y
|
|
||||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
|
||||||
CONFIG_TIMER_OF=y
|
|
||||||
CONFIG_TIMER_PROBE=y
|
|
||||||
CONFIG_TREE_RCU=y
|
|
||||||
CONFIG_TREE_SRCU=y
|
|
||||||
CONFIG_UBIFS_FS=y
|
|
||||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
|
||||||
# CONFIG_UCLAMP_TASK is not set
|
|
||||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_COMMON=y
|
|
||||||
CONFIG_USB_SUPPORT=y
|
|
||||||
CONFIG_VIRTIO=y
|
|
||||||
# CONFIG_VIRTIO_BLK is not set
|
|
||||||
# CONFIG_VIRTIO_NET is not set
|
|
||||||
CONFIG_VMAP_STACK=y
|
|
||||||
CONFIG_WANT_DEV_COREDUMP=y
|
|
||||||
CONFIG_WATCHDOG_CORE=y
|
|
||||||
CONFIG_WATCHDOG_SYSFS=y
|
|
||||||
CONFIG_XPS=y
|
|
||||||
CONFIG_XXHASH=y
|
|
||||||
CONFIG_ZLIB_DEFLATE=y
|
|
||||||
CONFIG_ZLIB_INFLATE=y
|
|
||||||
CONFIG_ZONE_DMA32=y
|
|
||||||
CONFIG_ZSTD_COMPRESS=y
|
|
||||||
CONFIG_ZSTD_DECOMPRESS=y
|
|
||||||
@ -1,67 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018-cmiot.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "CMIOT AX18";
|
|
||||||
compatible = "cmiot,ax18", "qcom,ipq6018";
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
led-boot = &led_power;
|
|
||||||
led-failsafe = &led_power;
|
|
||||||
led-running = &led_power;
|
|
||||||
led-upgrade = &led_power;
|
|
||||||
};
|
|
||||||
|
|
||||||
leds {
|
|
||||||
compatible = "gpio-leds";
|
|
||||||
pinctrl-0 = <&leds_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
|
|
||||||
led_power: power {
|
|
||||||
label = "ax18:blue:power";
|
|
||||||
gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wan {
|
|
||||||
label = "ax18:blue:wan";
|
|
||||||
gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wlan2g {
|
|
||||||
label = "ax18:blue:wlan2g";
|
|
||||||
gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wlan5g {
|
|
||||||
label = "ax18:blue:wlan5g";
|
|
||||||
gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wps {
|
|
||||||
label = "ax18:red:wps";
|
|
||||||
gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
leds_pins: leds_pins {
|
|
||||||
mux_0 {
|
|
||||||
pins = "gpio35", "gpio37",
|
|
||||||
"gpio69", "gpio74";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-down;
|
|
||||||
};
|
|
||||||
|
|
||||||
mux_1 {
|
|
||||||
pins = "gpio73";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -1,200 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018.dtsi"
|
|
||||||
#include "ipq6018-upstreamable.dtsi"
|
|
||||||
#include "ipq6018-ess.dtsi"
|
|
||||||
|
|
||||||
#include <dt-bindings/input/input.h>
|
|
||||||
#include <dt-bindings/gpio/gpio.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
qcom,msm-id = <0x192 0x0>;
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart3;
|
|
||||||
|
|
||||||
/* Aliases as required by u-boot to patch MAC addresses */
|
|
||||||
ethernet0 = &dp1;
|
|
||||||
ethernet1 = &dp2;
|
|
||||||
ethernet2 = &dp3;
|
|
||||||
ethernet3 = &dp4;
|
|
||||||
};
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1";
|
|
||||||
};
|
|
||||||
|
|
||||||
keys {
|
|
||||||
compatible = "gpio-keys";
|
|
||||||
|
|
||||||
reset {
|
|
||||||
label = "reset";
|
|
||||||
gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_RESTART>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wps {
|
|
||||||
label = "wps";
|
|
||||||
gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_WPS_BUTTON>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&blsp1_uart3 {
|
|
||||||
pinctrl-0 = <&serial_3_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
mdio_pins: mdio-pins {
|
|
||||||
mdc {
|
|
||||||
pins = "gpio64";
|
|
||||||
function = "mdc";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio {
|
|
||||||
pins = "gpio65";
|
|
||||||
function = "mdio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
button_pins: button_pins {
|
|
||||||
wps_button {
|
|
||||||
pins = "gpio9";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
|
|
||||||
reset_button {
|
|
||||||
pins = "gpio60";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
dp1: dp@1 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001000 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <5>;
|
|
||||||
local-mac-address = [000000000000];
|
|
||||||
phy-handle = <&phy_0>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp2: dp2 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001200 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <1>;
|
|
||||||
local-mac-address = [000000000000];
|
|
||||||
phy-handle = <&phy_1>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp3: dp3 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001400 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <2>;
|
|
||||||
local-mac-address = [000000000000];
|
|
||||||
phy-handle = <&phy_2>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp4: dp4 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001600 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <4>;
|
|
||||||
local-mac-address = [000000000000];
|
|
||||||
phy-handle = <&phy_3>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&edma {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&mdio {
|
|
||||||
status = "okay";
|
|
||||||
pinctrl-0 = <&mdio_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
|
||||||
|
|
||||||
phy_0: ethernet-phy@0 {
|
|
||||||
reg = <4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_1: ethernet-phy@1 {
|
|
||||||
reg = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_2: ethernet-phy@2 {
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_3: ethernet-phy@3 {
|
|
||||||
reg = <3>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&switch {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
|
|
||||||
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
|
|
||||||
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
|
|
||||||
|
|
||||||
qcom,port_phyinfo {
|
|
||||||
port@0 {
|
|
||||||
port_id = <0x01>;
|
|
||||||
phy_address = <0x00>;
|
|
||||||
};
|
|
||||||
port@1 {
|
|
||||||
port_id = <0x02>;
|
|
||||||
phy_address = <0x01>;
|
|
||||||
};
|
|
||||||
port@2 {
|
|
||||||
port_id = <0x04>;
|
|
||||||
phy_address = <0x03>;
|
|
||||||
};
|
|
||||||
port@3 {
|
|
||||||
port_id = <0x05>;
|
|
||||||
phy_address = <0x04>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_bam {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_nand {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
nand@0 {
|
|
||||||
reg = <0>;
|
|
||||||
|
|
||||||
nand-ecc-strength = <4>;
|
|
||||||
nand-ecc-step-size = <512>;
|
|
||||||
nand-bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&wifi {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
@ -1,136 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018.dtsi"
|
|
||||||
#include "ipq6018-upstreamable.dtsi"
|
|
||||||
#include "ipq6018-ess.dtsi"
|
|
||||||
|
|
||||||
#include <dt-bindings/input/input.h>
|
|
||||||
#include <dt-bindings/gpio/gpio.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "TP-Link EAP610-Outdoor";
|
|
||||||
compatible = "tplink,eap610-outdoor", "qcom,ipq6018";
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart3;
|
|
||||||
led-boot = &led_power;
|
|
||||||
led-failsafe = &led_power;
|
|
||||||
led-running = &led_power;
|
|
||||||
led-upgrade = &led_power;
|
|
||||||
};
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
stdout-path = "serial0:115200n8";
|
|
||||||
};
|
|
||||||
|
|
||||||
keys {
|
|
||||||
compatible = "gpio-keys";
|
|
||||||
|
|
||||||
reset {
|
|
||||||
label = "reset";
|
|
||||||
gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_RESTART>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
leds {
|
|
||||||
compatible = "gpio-leds";
|
|
||||||
|
|
||||||
led_power: led-1 {
|
|
||||||
label = "green:power";
|
|
||||||
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&blsp1_uart3 {
|
|
||||||
pinctrl-0 = <&serial_3_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
mdio_pins: mdio-pins {
|
|
||||||
mdc {
|
|
||||||
pins = "gpio64";
|
|
||||||
function = "mdc";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio {
|
|
||||||
pins = "gpio65";
|
|
||||||
function = "mdio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
dp5: dp@5 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001800 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <5>;
|
|
||||||
|
|
||||||
phy-handle = <&rtl8211f_4>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&edma {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&mdio {
|
|
||||||
status = "okay";
|
|
||||||
pinctrl-0 = <&mdio_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
phy-reset-gpio = <&tlmm 0x4b GPIO_ACTIVE_HIGH>;
|
|
||||||
|
|
||||||
rtl8211f_4: ethernet-phy@4 {
|
|
||||||
reg = <4>;
|
|
||||||
reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&switch {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
switch_lan_bmp = <0x20>;
|
|
||||||
switch_wan_bmp = <0x20>;
|
|
||||||
switch_mac_mode = <0xff>;
|
|
||||||
switch_mac_mode1 = <0x0f>;
|
|
||||||
switch_mac_mode2 = <0xff>;
|
|
||||||
|
|
||||||
qcom,port_phyinfo {
|
|
||||||
port@4 {
|
|
||||||
port_id = <0x05>;
|
|
||||||
phy_address = <0x04>;
|
|
||||||
port_mac_sel = "QGMAC_PORT";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_bam {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_nand {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
nand@0 {
|
|
||||||
reg = <0>;
|
|
||||||
|
|
||||||
nand-ecc-strength = <4>;
|
|
||||||
nand-ecc-step-size = <512>;
|
|
||||||
nand-bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&wifi {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
@ -1,412 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
switch: ess-switch@3a000000 {
|
|
||||||
compatible = "qcom,ess-switch-ipq60xx";
|
|
||||||
reg = <0x3a000000 0x1000000>;
|
|
||||||
switch_access_mode = "local bus";
|
|
||||||
mdio-bus = <&mdio>;
|
|
||||||
status = "disabled";
|
|
||||||
|
|
||||||
switch_cpu_bmp = <0x1>;
|
|
||||||
switch_inner_bmp = <0xc0>;
|
|
||||||
bm_tick_mode = <0>;
|
|
||||||
tm_tick_mode = <0>;
|
|
||||||
|
|
||||||
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
|
|
||||||
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_AHB_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_SYS_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY1_AHB_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY1_SYS_CLK>,
|
|
||||||
<&gcc GCC_PORT1_MAC_CLK>,
|
|
||||||
<&gcc GCC_PORT2_MAC_CLK>,
|
|
||||||
<&gcc GCC_PORT3_MAC_CLK>,
|
|
||||||
<&gcc GCC_PORT4_MAC_CLK>,
|
|
||||||
<&gcc GCC_PORT5_MAC_CLK>,
|
|
||||||
<&gcc GCC_NSS_PPE_CLK>,
|
|
||||||
<&gcc GCC_NSS_PPE_CFG_CLK>,
|
|
||||||
<&gcc GCC_NSSNOC_PPE_CLK>,
|
|
||||||
<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
|
|
||||||
<&gcc GCC_NSS_EDMA_CLK>,
|
|
||||||
<&gcc GCC_NSS_EDMA_CFG_CLK>,
|
|
||||||
<&gcc GCC_NSS_PPE_IPE_CLK>,
|
|
||||||
<&gcc GCC_MDIO_AHB_CLK>,
|
|
||||||
<&gcc GCC_NSS_NOC_CLK>,
|
|
||||||
<&gcc GCC_NSSNOC_SNOC_CLK>,
|
|
||||||
<&gcc GCC_NSS_CRYPTO_CLK>,
|
|
||||||
<&gcc GCC_NSS_PTP_REF_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT1_RX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT1_TX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT2_RX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT2_TX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT3_RX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT3_TX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT4_RX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT4_TX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT5_RX_CLK>,
|
|
||||||
<&gcc GCC_NSS_PORT5_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
|
|
||||||
<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
|
|
||||||
<&gcc NSS_PORT5_RX_CLK_SRC>,
|
|
||||||
<&gcc NSS_PORT5_TX_CLK_SRC>,
|
|
||||||
<&gcc GCC_SNOC_NSSNOC_CLK>;
|
|
||||||
clock-names = "cmn_ahb_clk", "cmn_sys_clk", "uniphy0_ahb_clk",
|
|
||||||
"uniphy0_sys_clk", "uniphy1_ahb_clk",
|
|
||||||
"uniphy1_sys_clk", "port1_mac_clk",
|
|
||||||
"port2_mac_clk", "port3_mac_clk", "port4_mac_clk",
|
|
||||||
"port5_mac_clk", "nss_ppe_clk", "nss_ppe_cfg_clk",
|
|
||||||
"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
|
|
||||||
"nss_edma_clk", "nss_edma_cfg_clk",
|
|
||||||
"nss_ppe_ipe_clk", "gcc_mdio_ahb_clk",
|
|
||||||
"gcc_nss_noc_clk", "gcc_nssnoc_snoc_clk",
|
|
||||||
"gcc_nss_crypto_clk", "gcc_nss_ptp_ref_clk",
|
|
||||||
"nss_port1_rx_clk", "nss_port1_tx_clk",
|
|
||||||
"nss_port2_rx_clk", "nss_port2_tx_clk",
|
|
||||||
"nss_port3_rx_clk", "nss_port3_tx_clk",
|
|
||||||
"nss_port4_rx_clk", "nss_port4_tx_clk",
|
|
||||||
"nss_port5_rx_clk", "nss_port5_tx_clk",
|
|
||||||
"uniphy0_port1_rx_clk", "uniphy0_port1_tx_clk",
|
|
||||||
"uniphy0_port2_rx_clk", "uniphy0_port2_tx_clk",
|
|
||||||
"uniphy0_port3_rx_clk", "uniphy0_port3_tx_clk",
|
|
||||||
"uniphy0_port4_rx_clk", "uniphy0_port4_tx_clk",
|
|
||||||
"uniphy0_port5_rx_clk", "uniphy0_port5_tx_clk",
|
|
||||||
"uniphy1_port5_rx_clk", "uniphy1_port5_tx_clk",
|
|
||||||
"nss_port5_rx_clk_src", "nss_port5_tx_clk_src",
|
|
||||||
"gcc_snoc_nssnoc_clk";
|
|
||||||
resets = <&gcc GCC_PPE_FULL_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY0_SOFT_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY0_XPCS_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY1_SOFT_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY1_XPCS_RESET>,
|
|
||||||
<&gcc GCC_NSSPORT1_RESET>,
|
|
||||||
<&gcc GCC_NSSPORT2_RESET>,
|
|
||||||
<&gcc GCC_NSSPORT3_RESET>,
|
|
||||||
<&gcc GCC_NSSPORT4_RESET>,
|
|
||||||
<&gcc GCC_NSSPORT5_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT1_ARES>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT2_ARES>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT3_ARES>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT4_ARES>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT5_ARES>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
|
|
||||||
<&gcc GCC_UNIPHY0_PORT_4_RESET>;
|
|
||||||
reset-names = "ppe_rst", "uniphy0_soft_rst", "uniphy0_xpcs_rst",
|
|
||||||
"uniphy1_soft_rst", "uniphy1_xpcs_rst",
|
|
||||||
"nss_port1_rst", "nss_port2_rst", "nss_port3_rst",
|
|
||||||
"nss_port4_rst", "nss_port5_rst",
|
|
||||||
"uniphy0_port1_dis", "uniphy0_port2_dis",
|
|
||||||
"uniphy0_port3_dis", "uniphy0_port4_dis",
|
|
||||||
"uniphy0_port5_dis", "uniphy0_port_4_5_rst",
|
|
||||||
"uniphy0_port_4_rst";
|
|
||||||
};
|
|
||||||
|
|
||||||
ess-uniphy@7a00000 {
|
|
||||||
compatible = "qcom,ess-uniphy";
|
|
||||||
reg = <0x7a00000 0x30000>;
|
|
||||||
uniphy_access_mode = "local bus";
|
|
||||||
};
|
|
||||||
|
|
||||||
edma: edma@3ab00000 {
|
|
||||||
compatible = "qcom,edma";
|
|
||||||
reg = <0x0 0x3ab00000 0x0 0xabe00>;
|
|
||||||
reg-names = "edma-reg-base";
|
|
||||||
qcom,txdesc-ring-start = <23>;
|
|
||||||
qcom,txdesc-rings = <1>;
|
|
||||||
qcom,txcmpl-ring-start = <23>;
|
|
||||||
qcom,txcmpl-rings = <1>;
|
|
||||||
qcom,rxfill-ring-start = <7>;
|
|
||||||
qcom,rxfill-rings = <1>;
|
|
||||||
qcom,rxdesc-ring-start = <15>;
|
|
||||||
qcom,rxdesc-rings = <1>;
|
|
||||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
resets = <&gcc GCC_EDMA_HW_RESET>;
|
|
||||||
reset-names = "edma_rst";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&switch {
|
|
||||||
port_scheduler_resource {
|
|
||||||
port@0 {
|
|
||||||
port_id = <0>;
|
|
||||||
ucast_queue = <0 143>;
|
|
||||||
mcast_queue = <256 271>;
|
|
||||||
l0sp = <0 35>;
|
|
||||||
l0cdrr = <0 47>;
|
|
||||||
l0edrr = <0 47>;
|
|
||||||
l1cdrr = <0 7>;
|
|
||||||
l1edrr = <0 7>;
|
|
||||||
};
|
|
||||||
port@1 {
|
|
||||||
port_id = <1>;
|
|
||||||
ucast_queue = <144 159>;
|
|
||||||
mcast_queue = <272 275>;
|
|
||||||
l0sp = <36 39>;
|
|
||||||
l0cdrr = <48 63>;
|
|
||||||
l0edrr = <48 63>;
|
|
||||||
l1cdrr = <8 11>;
|
|
||||||
l1edrr = <8 11>;
|
|
||||||
};
|
|
||||||
port@2 {
|
|
||||||
port_id = <2>;
|
|
||||||
ucast_queue = <160 175>;
|
|
||||||
mcast_queue = <276 279>;
|
|
||||||
l0sp = <40 43>;
|
|
||||||
l0cdrr = <64 79>;
|
|
||||||
l0edrr = <64 79>;
|
|
||||||
l1cdrr = <12 15>;
|
|
||||||
l1edrr = <12 15>;
|
|
||||||
};
|
|
||||||
port@3 {
|
|
||||||
port_id = <3>;
|
|
||||||
ucast_queue = <176 191>;
|
|
||||||
mcast_queue = <280 283>;
|
|
||||||
l0sp = <44 47>;
|
|
||||||
l0cdrr = <80 95>;
|
|
||||||
l0edrr = <80 95>;
|
|
||||||
l1cdrr = <16 19>;
|
|
||||||
l1edrr = <16 19>;
|
|
||||||
};
|
|
||||||
port@4 {
|
|
||||||
port_id = <4>;
|
|
||||||
ucast_queue = <192 207>;
|
|
||||||
mcast_queue = <284 287>;
|
|
||||||
l0sp = <48 51>;
|
|
||||||
l0cdrr = <96 111>;
|
|
||||||
l0edrr = <96 111>;
|
|
||||||
l1cdrr = <20 23>;
|
|
||||||
l1edrr = <20 23>;
|
|
||||||
};
|
|
||||||
port@5 {
|
|
||||||
port_id = <5>;
|
|
||||||
ucast_queue = <208 223>;
|
|
||||||
mcast_queue = <288 291>;
|
|
||||||
l0sp = <52 55>;
|
|
||||||
l0cdrr = <112 127>;
|
|
||||||
l0edrr = <112 127>;
|
|
||||||
l1cdrr = <24 27>;
|
|
||||||
l1edrr = <24 27>;
|
|
||||||
};
|
|
||||||
port@6 {
|
|
||||||
port_id = <6>;
|
|
||||||
ucast_queue = <224 239>;
|
|
||||||
mcast_queue = <292 295>;
|
|
||||||
l0sp = <56 59>;
|
|
||||||
l0cdrr = <128 143>;
|
|
||||||
l0edrr = <128 143>;
|
|
||||||
l1cdrr = <28 31>;
|
|
||||||
l1edrr = <28 31>;
|
|
||||||
};
|
|
||||||
port@7 {
|
|
||||||
port_id = <7>;
|
|
||||||
ucast_queue = <240 255>;
|
|
||||||
mcast_queue = <296 299>;
|
|
||||||
l0sp = <60 63>;
|
|
||||||
l0cdrr = <144 159>;
|
|
||||||
l0edrr = <144 159>;
|
|
||||||
l1cdrr = <32 35>;
|
|
||||||
l1edrr = <32 35>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
port_scheduler_config {
|
|
||||||
port@0 {
|
|
||||||
port_id = <0>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <0 1>;
|
|
||||||
cfg = <0 0 0 0>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <0 4 8>;
|
|
||||||
mcast_queue = <256 260>;
|
|
||||||
cfg = <0 0 0 0 0>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
ucast_queue = <1 5 9>;
|
|
||||||
mcast_queue = <257 261>;
|
|
||||||
cfg = <0 1 1 1 1>;
|
|
||||||
};
|
|
||||||
group@2 {
|
|
||||||
ucast_queue = <2 6 10>;
|
|
||||||
mcast_queue = <258 262>;
|
|
||||||
cfg = <0 2 2 2 2>;
|
|
||||||
};
|
|
||||||
group@3 {
|
|
||||||
ucast_queue = <3 7 11>;
|
|
||||||
mcast_queue = <259 263>;
|
|
||||||
cfg = <0 3 3 3 3>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@1 {
|
|
||||||
port_id = <1>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <36>;
|
|
||||||
cfg = <0 8 0 8>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <37>;
|
|
||||||
cfg = <1 9 1 9>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <144>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <272>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <36 0 48 0 48>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@2 {
|
|
||||||
port_id = <2>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <40>;
|
|
||||||
cfg = <0 12 0 12>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <41>;
|
|
||||||
cfg = <1 13 1 13>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <160>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <276>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <40 0 64 0 64>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@3 {
|
|
||||||
port_id = <3>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <44>;
|
|
||||||
cfg = <0 16 0 16>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <45>;
|
|
||||||
cfg = <1 17 1 17>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <176>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <280>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <44 0 80 0 80>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@4 {
|
|
||||||
port_id = <4>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <48>;
|
|
||||||
cfg = <0 20 0 20>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <49>;
|
|
||||||
cfg = <1 21 1 21>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <192>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <284>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <48 0 96 0 96>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@5 {
|
|
||||||
port_id = <5>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <52>;
|
|
||||||
cfg = <0 24 0 24>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <53>;
|
|
||||||
cfg = <1 25 1 25>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <208>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <288>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <52 0 112 0 112>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@6 {
|
|
||||||
port_id = <6>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <56>;
|
|
||||||
cfg = <0 28 0 28>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <57>;
|
|
||||||
cfg = <1 29 1 29>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <224>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <292>;
|
|
||||||
mcast_loop_pri = <4>;
|
|
||||||
cfg = <56 0 128 0 128>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
port@7 {
|
|
||||||
port_id = <7>;
|
|
||||||
l1scheduler {
|
|
||||||
group@0 {
|
|
||||||
sp = <60>;
|
|
||||||
cfg = <0 32 0 32>;
|
|
||||||
};
|
|
||||||
group@1 {
|
|
||||||
sp = <61>;
|
|
||||||
cfg = <1 33 1 33>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
l0scheduler {
|
|
||||||
group@0 {
|
|
||||||
ucast_queue = <240>;
|
|
||||||
ucast_loop_pri = <16>;
|
|
||||||
mcast_queue = <296>;
|
|
||||||
cfg = <60 0 144 0 144>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018-cmiot.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "ZN M2";
|
|
||||||
compatible = "zn,m2", "qcom,ipq6018";
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
led-boot = &led_power;
|
|
||||||
led-failsafe = &led_power;
|
|
||||||
led-running = &led_power;
|
|
||||||
led-upgrade = &led_power;
|
|
||||||
};
|
|
||||||
|
|
||||||
leds {
|
|
||||||
compatible = "gpio-leds";
|
|
||||||
pinctrl-0 = <&leds_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
|
|
||||||
led_power: power {
|
|
||||||
label = "m2:blue:power";
|
|
||||||
gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
mesh {
|
|
||||||
label = "m2:blue:mesh";
|
|
||||||
gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
lan {
|
|
||||||
label = "m2:blue:lan";
|
|
||||||
gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wan {
|
|
||||||
label = "m2:blue:wan";
|
|
||||||
gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wlan5g {
|
|
||||||
label = "m2:blue:wlan5g";
|
|
||||||
gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wlan2g {
|
|
||||||
label = "m2:blue:wlan2g";
|
|
||||||
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
leds_pins: leds_pins {
|
|
||||||
mux {
|
|
||||||
pins = "gpio35", "gpio37",
|
|
||||||
"gpio58", "gpio70",
|
|
||||||
"gpio73", "gpio74";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-down;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -1,249 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018.dtsi"
|
|
||||||
#include "ipq6018-upstreamable.dtsi"
|
|
||||||
#include "ipq6018-ess.dtsi"
|
|
||||||
|
|
||||||
#include <dt-bindings/input/input.h>
|
|
||||||
#include <dt-bindings/gpio/gpio.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "Linksys MR7350";
|
|
||||||
compatible = "linksys,mr7350", "qcom,ipq6018";
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart3;
|
|
||||||
// led-boot = &led_power;
|
|
||||||
// led-failsafe = &led_power;
|
|
||||||
// led-running = &led_power;
|
|
||||||
// led-upgrade = &led_power;
|
|
||||||
};
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
stdout-path = "serial0:115200n8";
|
|
||||||
};
|
|
||||||
|
|
||||||
keys {
|
|
||||||
compatible = "gpio-keys";
|
|
||||||
|
|
||||||
reset {
|
|
||||||
label = "reset";
|
|
||||||
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_RESTART>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wps {
|
|
||||||
label = "reset";
|
|
||||||
gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_WPS_BUTTON>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&blsp1_uart3 {
|
|
||||||
pinctrl-0 = <&serial_3_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
i2c_1_pins: i2c-1-pins {
|
|
||||||
pins = "gpio42", "gpio43";
|
|
||||||
function = "blsp2_i2c";
|
|
||||||
drive-strength = <8>;
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio_pins: mdio-pins {
|
|
||||||
mdc {
|
|
||||||
pins = "gpio64";
|
|
||||||
function = "mdc";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio {
|
|
||||||
pins = "gpio65";
|
|
||||||
function = "mdio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
dp1: dp@1 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001000 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <1>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_0>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp2 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001200 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <2>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_1>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp3 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001400 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <3>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_2>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp4 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001600 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <4>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_3>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp5 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001800 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <5>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_4>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&edma {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&mdio {
|
|
||||||
status = "okay";
|
|
||||||
pinctrl-0 = <&mdio_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
|
||||||
|
|
||||||
phy_0: ethernet-phy@0 {
|
|
||||||
reg = <0>;
|
|
||||||
// reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_1: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_2: ethernet-phy@2 {
|
|
||||||
reg = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_3: ethernet-phy@3 {
|
|
||||||
reg = <3>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_4: ethernet-phy@4 {
|
|
||||||
reg = <4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
&switch {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
switch_lan_bmp = <0x1e>;
|
|
||||||
switch_wan_bmp = <0x20>;
|
|
||||||
switch_mac_mode = <0x00>;
|
|
||||||
switch_mac_mode1 = <0xff>;
|
|
||||||
switch_mac_mode2 = <0xff>;
|
|
||||||
|
|
||||||
qcom,port_phyinfo {
|
|
||||||
port@0 {
|
|
||||||
port_id = <0x01>;
|
|
||||||
phy_address = <0x00>;
|
|
||||||
};
|
|
||||||
port@1 {
|
|
||||||
port_id = <0x02>;
|
|
||||||
phy_address = <0x01>;
|
|
||||||
};
|
|
||||||
port@2 {
|
|
||||||
port_id = <0x03>;
|
|
||||||
phy_address = <0x02>;
|
|
||||||
};
|
|
||||||
port@3 {
|
|
||||||
port_id = <0x04>;
|
|
||||||
phy_address = <0x03>;
|
|
||||||
};
|
|
||||||
port@4 {
|
|
||||||
port_id = <0x05>;
|
|
||||||
phy_address = <0x04>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_bam {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_nand {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
nand@0 {
|
|
||||||
reg = <0>;
|
|
||||||
|
|
||||||
nand-ecc-strength = <4>;
|
|
||||||
nand-ecc-step-size = <512>;
|
|
||||||
nand-bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&qusb_phy_0 {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&ssphy_0 {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&usb3 {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&wifi {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&blsp1_i2c3 {
|
|
||||||
pinctrl-0 = <&i2c_1_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
pca9633: pca9633 {
|
|
||||||
compatible = "nxp,pca9633";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
reg = <0x62>;
|
|
||||||
|
|
||||||
red@0 {
|
|
||||||
label = "red";
|
|
||||||
reg = <0>;
|
|
||||||
};
|
|
||||||
green@1 {
|
|
||||||
label = "green";
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
blue@2 {
|
|
||||||
label = "blue";
|
|
||||||
reg = <2>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -1,120 +0,0 @@
|
|||||||
/ {
|
|
||||||
reserved-memory {
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
nss@40000000 {
|
|
||||||
reg = <0x00 0x40000000 0x00 0x1000000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
|
|
||||||
uboot@4a100000 {
|
|
||||||
reg = <0x00 0x4a100000 0x00 0x400000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
|
|
||||||
sbl@4a500000 {
|
|
||||||
reg = <0x00 0x4a500000 0x00 0x100000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
wifi: wifi@c000000 {
|
|
||||||
compatible = "qcom,ipq6018-wifi";
|
|
||||||
reg = <0x0 0xc000000 0x0 0x1000000>;
|
|
||||||
qcom,rproc = <&q6v5_wcss>;
|
|
||||||
interrupts = <GIC_SPI 0x140 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13f IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13e IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13d IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13c IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13b IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x13a IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x137 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x136 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x19b IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x19a IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x28 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x27 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x12e IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x12d IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x25 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x24 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xef IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xec IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xeb IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xea IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe9 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe8 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe7 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe6 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe5 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe4 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xe0 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xdf IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xcb IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb7 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb4 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb3 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb2 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb1 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xb0 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xa3 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xa2 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0xa0 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x9f IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x9e IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x9d IRQ_TYPE_EDGE_RISING>,
|
|
||||||
<GIC_SPI 0x9c IRQ_TYPE_EDGE_RISING>;
|
|
||||||
interrupt-names = "misc-pulse1", "misc-latch", "sw-exception",
|
|
||||||
"watchdog", "ce0", "ce1", "ce2", "ce3", "ce4",
|
|
||||||
"ce5", "ce6", "ce7", "ce8", "ce9", "ce10",
|
|
||||||
"ce11", "host2wbm-desc-feed",
|
|
||||||
"host2reo-re-injection", "host2reo-command",
|
|
||||||
"host2rxdma-monitor-ring3",
|
|
||||||
"host2rxdma-monitor-ring2",
|
|
||||||
"host2rxdma-monitor-ring1",
|
|
||||||
"reo2ost-exception", "wbm2host-rx-release",
|
|
||||||
"reo2host-status",
|
|
||||||
"reo2host-destination-ring4",
|
|
||||||
"reo2host-destination-ring3",
|
|
||||||
"reo2host-destination-ring2",
|
|
||||||
"reo2host-destination-ring1",
|
|
||||||
"rxdma2host-monitor-destination-mac3",
|
|
||||||
"rxdma2host-monitor-destination-mac2",
|
|
||||||
"rxdma2host-monitor-destination-mac1",
|
|
||||||
"ppdu-end-interrupts-mac3",
|
|
||||||
"ppdu-end-interrupts-mac2",
|
|
||||||
"ppdu-end-interrupts-mac1",
|
|
||||||
"rxdma2host-monitor-status-ring-mac3",
|
|
||||||
"rxdma2host-monitor-status-ring-mac2",
|
|
||||||
"rxdma2host-monitor-status-ring-mac1",
|
|
||||||
"host2rxdma-host-buf-ring-mac3",
|
|
||||||
"host2rxdma-host-buf-ring-mac2",
|
|
||||||
"host2rxdma-host-buf-ring-mac1",
|
|
||||||
"rxdma2host-destination-ring-mac3",
|
|
||||||
"rxdma2host-destination-ring-mac2",
|
|
||||||
"rxdma2host-destination-ring-mac1",
|
|
||||||
"host2tcl-input-ring4",
|
|
||||||
"host2tcl-input-ring3",
|
|
||||||
"host2tcl-input-ring2",
|
|
||||||
"host2tcl-input-ring1",
|
|
||||||
"wbm2host-tx-completions-ring3",
|
|
||||||
"wbm2host-tx-completions-ring2",
|
|
||||||
"wbm2host-tx-completions-ring1",
|
|
||||||
"tcl2host-status-ring";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -1,249 +0,0 @@
|
|||||||
// SPDX-License-Identifier: (GPL-2.0+)
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
|
|
||||||
#include "ipq6018.dtsi"
|
|
||||||
#include "ipq6018-upstreamable.dtsi"
|
|
||||||
#include "ipq6018-ess.dtsi"
|
|
||||||
|
|
||||||
#include <dt-bindings/input/input.h>
|
|
||||||
#include <dt-bindings/gpio/gpio.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "Qihoo 360 V6";
|
|
||||||
compatible = "qihoo,v6", "qcom,ipq6018";
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart3;
|
|
||||||
led-boot = &led_system_orange;
|
|
||||||
led-failsafe = &led_system_red;
|
|
||||||
led-running = &led_system_green;
|
|
||||||
led-upgrade = &led_system_orange;
|
|
||||||
};
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
stdout-path = "serial0:115200n8";
|
|
||||||
};
|
|
||||||
|
|
||||||
leds {
|
|
||||||
compatible = "gpio-leds";
|
|
||||||
pinctrl-0 = <&leds_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
|
|
||||||
led_system_red: system-red {
|
|
||||||
label = "v6:red:status";
|
|
||||||
gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
led_system_orange: system-orange {
|
|
||||||
label = "v6:orange:status";
|
|
||||||
gpios = <&tlmm 72 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
|
|
||||||
led_system_green: system-green {
|
|
||||||
label = "v6:green:status";
|
|
||||||
gpios = <&tlmm 73 GPIO_ACTIVE_HIGH>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
keys {
|
|
||||||
compatible = "gpio-keys";
|
|
||||||
|
|
||||||
reset {
|
|
||||||
label = "reset";
|
|
||||||
gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_RESTART>;
|
|
||||||
};
|
|
||||||
|
|
||||||
wps {
|
|
||||||
label = "wps";
|
|
||||||
gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
|
|
||||||
linux,code = <KEY_WPS_BUTTON>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&blsp1_uart3 {
|
|
||||||
pinctrl-0 = <&serial_3_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&tlmm {
|
|
||||||
|
|
||||||
mdio_pins: mdio-pins {
|
|
||||||
mdc {
|
|
||||||
pins = "gpio64";
|
|
||||||
function = "mdc";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio {
|
|
||||||
pins = "gpio65";
|
|
||||||
function = "mdio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-up;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
leds_pins: leds_pins {
|
|
||||||
mux {
|
|
||||||
pins = "gpio71", "gpio72", "gpio73";
|
|
||||||
function = "gpio";
|
|
||||||
drive-strength = <8>;
|
|
||||||
bias-pull-down;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
&soc {
|
|
||||||
dp1: dp@1 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001000 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <1>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_0>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp2 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001200 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <2>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_1>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp3 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001400 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <3>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_2>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp4 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001600 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <4>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_3>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
|
|
||||||
dp5 {
|
|
||||||
compatible = "qcom,nss-dp";
|
|
||||||
reg = <0x0 0x3a001800 0x0 0x200>;
|
|
||||||
qcom,mactype = <0>;
|
|
||||||
qcom,id = <5>;
|
|
||||||
|
|
||||||
phy-handle = <&phy_4>;
|
|
||||||
phy-mode = "sgmii";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&edma {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&mdio {
|
|
||||||
status = "okay";
|
|
||||||
pinctrl-0 = <&mdio_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
|
||||||
|
|
||||||
phy_0: ethernet-phy@0 {
|
|
||||||
reg = <0>;
|
|
||||||
// reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_1: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_2: ethernet-phy@2 {
|
|
||||||
reg = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_3: ethernet-phy@3 {
|
|
||||||
reg = <3>;
|
|
||||||
};
|
|
||||||
|
|
||||||
phy_4: ethernet-phy@4 {
|
|
||||||
reg = <4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
&switch {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
switch_lan_bmp = <0x1e>;
|
|
||||||
switch_wan_bmp = <0x20>;
|
|
||||||
switch_mac_mode = <0x00>;
|
|
||||||
switch_mac_mode1 = <0xff>;
|
|
||||||
switch_mac_mode2 = <0xff>;
|
|
||||||
|
|
||||||
qcom,port_phyinfo {
|
|
||||||
port@0 {
|
|
||||||
port_id = <0x01>;
|
|
||||||
phy_address = <0x00>;
|
|
||||||
};
|
|
||||||
port@1 {
|
|
||||||
port_id = <0x02>;
|
|
||||||
phy_address = <0x01>;
|
|
||||||
};
|
|
||||||
port@2 {
|
|
||||||
port_id = <0x03>;
|
|
||||||
phy_address = <0x02>;
|
|
||||||
};
|
|
||||||
port@3 {
|
|
||||||
port_id = <0x04>;
|
|
||||||
phy_address = <0x03>;
|
|
||||||
};
|
|
||||||
port@4 {
|
|
||||||
port_id = <0x05>;
|
|
||||||
phy_address = <0x04>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_bam {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&qpic_nand {
|
|
||||||
status = "okay";
|
|
||||||
|
|
||||||
nand@0 {
|
|
||||||
reg = <0>;
|
|
||||||
|
|
||||||
nand-ecc-strength = <4>;
|
|
||||||
nand-ecc-step-size = <512>;
|
|
||||||
nand-bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&wifi {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&ssphy_0 {
|
|
||||||
status = "ok";
|
|
||||||
};
|
|
||||||
|
|
||||||
&qusb_phy_0 {
|
|
||||||
status = "ok";
|
|
||||||
};
|
|
||||||
|
|
||||||
&usb3 {
|
|
||||||
status = "ok";
|
|
||||||
};
|
|
||||||
@ -1 +0,0 @@
|
|||||||
BOARDNAME:=Generic
|
|
||||||
@ -1,18 +0,0 @@
|
|||||||
include $(TOPDIR)/rules.mk
|
|
||||||
include $(INCLUDE_DIR)/image.mk
|
|
||||||
|
|
||||||
define Device/Default
|
|
||||||
PROFILES := Default
|
|
||||||
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
|
|
||||||
KERNEL_LOADADDR := 0x41000000
|
|
||||||
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
|
|
||||||
DEVICE_DTS_CONFIG := config@1
|
|
||||||
DEVICE_DTS_DIR := $(DTS_DIR)/qcom
|
|
||||||
IMAGES := sysupgrade.bin
|
|
||||||
IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
|
|
||||||
IMAGE/sysupgrade.bin/squashfs :=
|
|
||||||
endef
|
|
||||||
|
|
||||||
include $(SUBTARGET).mk
|
|
||||||
|
|
||||||
$(eval $(call BuildImage))
|
|
||||||
@ -1,93 +0,0 @@
|
|||||||
define Device/FitImage
|
|
||||||
KERNEL_SUFFIX := -fit-uImage.itb
|
|
||||||
KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
|
|
||||||
KERNEL_NAME := Image
|
|
||||||
endef
|
|
||||||
|
|
||||||
define Device/FitImageLzma
|
|
||||||
KERNEL_SUFFIX := -fit-uImage.itb
|
|
||||||
KERNEL = kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
|
|
||||||
KERNEL_NAME := Image
|
|
||||||
endef
|
|
||||||
|
|
||||||
define Device/FitzImage
|
|
||||||
KERNEL_SUFFIX := -fit-zImage.itb
|
|
||||||
KERNEL = kernel-bin | fit none $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
|
|
||||||
KERNEL_NAME := zImage
|
|
||||||
endef
|
|
||||||
|
|
||||||
define Device/UbiFit
|
|
||||||
KERNEL_IN_UBI := 1
|
|
||||||
IMAGES := nand-factory.ubi nand-sysupgrade.bin
|
|
||||||
IMAGE/nand-factory.ubi := append-ubi
|
|
||||||
IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
|
|
||||||
endef
|
|
||||||
|
|
||||||
define Device/cmiot_ax18
|
|
||||||
$(call Device/FitImage)
|
|
||||||
$(call Device/UbiFit)
|
|
||||||
DEVICE_VENDOR := CMIOT
|
|
||||||
DEVICE_MODEL := AX18
|
|
||||||
BLOCKSIZE := 128k
|
|
||||||
PAGESIZE := 2048
|
|
||||||
DEVICE_DTS_CONFIG := config@cp03-c1
|
|
||||||
SOC := ipq6018
|
|
||||||
endef
|
|
||||||
TARGET_DEVICES += cmiot_ax18
|
|
||||||
|
|
||||||
define Device/linksys_mr7350
|
|
||||||
$(call Device/FitImage)
|
|
||||||
$(call Device/UbiFit)
|
|
||||||
DEVICE_VENDOR := Linksys
|
|
||||||
DEVICE_MODEL := MR7350
|
|
||||||
BLOCKSIZE := 128k
|
|
||||||
PAGESIZE := 2048
|
|
||||||
SOC := ipq6018
|
|
||||||
DEVICE_PACKAGES := kmod-leds-pca963x
|
|
||||||
endef
|
|
||||||
TARGET_DEVICES += linksys_mr7350
|
|
||||||
|
|
||||||
#define Device/cp01-c1
|
|
||||||
# $(call Device/FitImage)
|
|
||||||
# DEVICE_VENDOR := Qualcomm Technologies
|
|
||||||
# DEVICE_MODEL := AP-CP01-C1
|
|
||||||
# SOC := ipq6018
|
|
||||||
#endef
|
|
||||||
#TARGET_DEVICES += cp01-c1
|
|
||||||
|
|
||||||
#define Device/eap610-outdoor
|
|
||||||
# $(call Device/FitImage)
|
|
||||||
# $(call Device/UbiFit)
|
|
||||||
# DEVICE_VENDOR := TP-Link
|
|
||||||
# DEVICE_MODEL := EAP610-Outdoor
|
|
||||||
# BLOCKSIZE := 128k
|
|
||||||
# PAGESIZE := 2048
|
|
||||||
# SOC := ipq6018
|
|
||||||
# IMAGE/nand-factory.ubi := append-ubi | qsdk-ipq-factory-nand
|
|
||||||
#endef
|
|
||||||
#TARGET_DEVICES += eap610-outdoor
|
|
||||||
|
|
||||||
define Device/360_v6
|
|
||||||
$(call Device/FitImage)
|
|
||||||
$(call Device/UbiFit)
|
|
||||||
DEVICE_VENDOR := Qihoo 360
|
|
||||||
DEVICE_MODEL := V6
|
|
||||||
BLOCKSIZE := 128k
|
|
||||||
PAGESIZE := 2048
|
|
||||||
DEVICE_DTS_CONFIG := config@cp03-c1
|
|
||||||
DEVICE_PACKAGES := ath11k-wifi-qihoo_v6
|
|
||||||
SOC := ipq6018
|
|
||||||
endef
|
|
||||||
TARGET_DEVICES += 360_v6
|
|
||||||
|
|
||||||
define Device/zn_m2
|
|
||||||
$(call Device/FitImage)
|
|
||||||
$(call Device/UbiFit)
|
|
||||||
DEVICE_VENDOR := ZN
|
|
||||||
DEVICE_MODEL := M2
|
|
||||||
BLOCKSIZE := 128k
|
|
||||||
PAGESIZE := 2048
|
|
||||||
DEVICE_DTS_CONFIG := config@cp03-c1
|
|
||||||
SOC := ipq6018
|
|
||||||
endef
|
|
||||||
TARGET_DEVICES += zn_m2
|
|
||||||
@ -1,43 +0,0 @@
|
|||||||
From 3f3f712b16c7d374cfb079ca83684f12fda7884c Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 5 Sep 2021 18:58:16 +0200
|
|
||||||
Subject: [PATCH 01/44] arm64: dts: qcom: ipq8074: add SPMI bus
|
|
||||||
|
|
||||||
IPQ8074 uses SPMI for communication with the PMIC, so
|
|
||||||
since its already supported add the DT node for it.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20210905165816.655275-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++
|
|
||||||
1 file changed, 19 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -320,6 +320,25 @@
|
|
||||||
#reset-cells = <0x1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ spmi_bus: spmi@200f000 {
|
|
||||||
+ compatible = "qcom,spmi-pmic-arb";
|
|
||||||
+ reg = <0x0200f000 0x001000>,
|
|
||||||
+ <0x02400000 0x800000>,
|
|
||||||
+ <0x02c00000 0x800000>,
|
|
||||||
+ <0x03800000 0x200000>,
|
|
||||||
+ <0x0200a000 0x000700>;
|
|
||||||
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
||||||
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
+ interrupt-names = "periph_irq";
|
|
||||||
+ qcom,ee = <0>;
|
|
||||||
+ qcom,channel = <0>;
|
|
||||||
+ #address-cells = <2>;
|
|
||||||
+ #size-cells = <0>;
|
|
||||||
+ interrupt-controller;
|
|
||||||
+ #interrupt-cells = <4>;
|
|
||||||
+ cell-index = <0>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
sdhc_1: sdhci@7824900 {
|
|
||||||
compatible = "qcom,sdhci-msm-v4";
|
|
||||||
reg = <0x7824900 0x500>, <0x7824000 0x800>;
|
|
||||||
@ -1,27 +0,0 @@
|
|||||||
From e5698ba1e94af28e5f54943bcd6de278efc84500 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
Date: Tue, 31 Aug 2021 13:23:25 +0800
|
|
||||||
Subject: [PATCH 02/44] arm64: dts: qcom: Update BAM DMA node name per DT
|
|
||||||
schema
|
|
||||||
|
|
||||||
Follow dma-controller.yaml schema to use `dma-controller` as node name
|
|
||||||
of BAM DMA devices.
|
|
||||||
|
|
||||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -239,7 +239,7 @@
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
- cryptobam: dma@704000 {
|
|
||||||
+ cryptobam: dma-controller@704000 {
|
|
||||||
compatible = "qcom,bam-v1.7.0";
|
|
||||||
reg = <0x00704000 0x20000>;
|
|
||||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
@ -1,40 +0,0 @@
|
|||||||
From 187368d2936edad6342151ae1ac34d95dc2de2c1 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
|
||||||
Date: Fri, 1 Oct 2021 22:54:21 +0800
|
|
||||||
Subject: [PATCH 03/44] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
|
|
||||||
|
|
||||||
Add node to support the QUP5 I2C controller inside of IPQ8074.
|
|
||||||
It is exactly the same as QUP2 controllers.
|
|
||||||
Some routers like ZTE MF269 use this bus.
|
|
||||||
|
|
||||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
|
|
||||||
1 file changed, 15 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -457,6 +457,21 @@
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
+ blsp1_i2c5: i2c@78b9000 {
|
|
||||||
+ compatible = "qcom,i2c-qup-v2.2.1";
|
|
||||||
+ #address-cells = <1>;
|
|
||||||
+ #size-cells = <0>;
|
|
||||||
+ reg = <0x78b9000 0x600>;
|
|
||||||
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
||||||
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
|
|
||||||
+ clock-names = "iface", "core";
|
|
||||||
+ clock-frequency = <400000>;
|
|
||||||
+ dmas = <&blsp_dma 21>, <&blsp_dma 20>;
|
|
||||||
+ dma-names = "rx", "tx";
|
|
||||||
+ status = "disabled";
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
blsp1_i2c6: i2c@78ba000 {
|
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
|
||||||
#address-cells = <1>;
|
|
||||||
@ -1,53 +0,0 @@
|
|||||||
From 4ef751128de689e12e3eccb5d4e2562ef8b42758 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
Date: Wed, 29 Sep 2021 11:42:46 +0800
|
|
||||||
Subject: [PATCH 04/44] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP
|
|
||||||
PHY child node
|
|
||||||
|
|
||||||
'#clock-cells' is a required property of QMP PHY child node, not itself.
|
|
||||||
Move it to fix the dtbs_check warnings.
|
|
||||||
|
|
||||||
There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
|
|
||||||
child nodes already have the property.
|
|
||||||
|
|
||||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
|
||||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -91,7 +91,6 @@
|
|
||||||
ssphy_1: phy@58000 {
|
|
||||||
compatible = "qcom,ipq8074-qmp-usb3-phy";
|
|
||||||
reg = <0x00058000 0x1c4>;
|
|
||||||
- #clock-cells = <1>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges;
|
|
||||||
@@ -112,6 +111,7 @@
|
|
||||||
<0x00058800 0x1f8>, /* PCS */
|
|
||||||
<0x00058600 0x044>; /* PCS misc*/
|
|
||||||
#phy-cells = <0>;
|
|
||||||
+ #clock-cells = <1>;
|
|
||||||
clocks = <&gcc GCC_USB1_PIPE_CLK>;
|
|
||||||
clock-names = "pipe0";
|
|
||||||
clock-output-names = "usb3phy_1_cc_pipe_clk";
|
|
||||||
@@ -134,7 +134,6 @@
|
|
||||||
ssphy_0: phy@78000 {
|
|
||||||
compatible = "qcom,ipq8074-qmp-usb3-phy";
|
|
||||||
reg = <0x00078000 0x1c4>;
|
|
||||||
- #clock-cells = <1>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges;
|
|
||||||
@@ -155,6 +154,7 @@
|
|
||||||
<0x00078800 0x1f8>, /* PCS */
|
|
||||||
<0x00078600 0x044>; /* PCS misc*/
|
|
||||||
#phy-cells = <0>;
|
|
||||||
+ #clock-cells = <1>;
|
|
||||||
clocks = <&gcc GCC_USB0_PIPE_CLK>;
|
|
||||||
clock-names = "pipe0";
|
|
||||||
clock-output-names = "usb3phy_0_cc_pipe_clk";
|
|
||||||
@ -1,36 +0,0 @@
|
|||||||
From 9757a0d4e05b807074f6868ed594a9bf0111d74d Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 7 Oct 2021 13:58:46 +0200
|
|
||||||
Subject: [PATCH 07/44] arm64: dts: qcom: ipq8074: add MDIO bus
|
|
||||||
|
|
||||||
IPQ8074 uses an IPQ4019 compatible MDIO controller that is already
|
|
||||||
supported in the kernel, so add the DT node in order to use it.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++
|
|
||||||
1 file changed, 12 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -231,6 +231,18 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
+ mdio: mdio@90000 {
|
|
||||||
+ compatible = "qcom,ipq4019-mdio";
|
|
||||||
+ reg = <0x00090000 0x64>;
|
|
||||||
+ #address-cells = <1>;
|
|
||||||
+ #size-cells = <0>;
|
|
||||||
+
|
|
||||||
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
|
|
||||||
+ clock-names = "gcc_mdio_ahb_clk";
|
|
||||||
+
|
|
||||||
+ status = "disabled";
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
prng: rng@e3000 {
|
|
||||||
compatible = "qcom,prng-ee";
|
|
||||||
reg = <0x000e3000 0x1000>;
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
From 0064ce4f52ed8fc010c1794114205daa9f598828 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 6 Jan 2022 22:25:12 +0100
|
|
||||||
Subject: [PATCH 09/44] arm64: dts: qcom: ipq8074: add SMEM support
|
|
||||||
|
|
||||||
IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already
|
|
||||||
supported by the kernel add the required DT nodes.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
|
|
||||||
1 file changed, 20 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -76,6 +76,20 @@
|
|
||||||
method = "smc";
|
|
||||||
};
|
|
||||||
|
|
||||||
+ reserved-memory {
|
|
||||||
+ #address-cells = <2>;
|
|
||||||
+ #size-cells = <2>;
|
|
||||||
+ ranges;
|
|
||||||
+
|
|
||||||
+ smem@4ab00000 {
|
|
||||||
+ compatible = "qcom,smem";
|
|
||||||
+ reg = <0x0 0x4ab00000 0x0 0x00100000>;
|
|
||||||
+ no-map;
|
|
||||||
+
|
|
||||||
+ hwlocks = <&tcsr_mutex 0>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
firmware {
|
|
||||||
scm {
|
|
||||||
compatible = "qcom,scm-ipq8074", "qcom,scm";
|
|
||||||
@@ -332,6 +346,12 @@
|
|
||||||
#reset-cells = <0x1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ tcsr_mutex: hwlock@1905000 {
|
|
||||||
+ compatible = "qcom,tcsr-mutex";
|
|
||||||
+ reg = <0x01905000 0x20000>;
|
|
||||||
+ #hwlock-cells = <1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
spmi_bus: spmi@200f000 {
|
|
||||||
compatible = "qcom,spmi-pmic-arb";
|
|
||||||
reg = <0x0200f000 0x001000>,
|
|
||||||
@ -1,30 +0,0 @@
|
|||||||
From d58eeedd46d47db44a5932f7d74efae881d54c9b Mon Sep 17 00:00:00 2001
|
|
||||||
From: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
Date: Fri, 7 Jan 2022 18:24:38 +0530
|
|
||||||
Subject: [PATCH 10/44] arm64: dts: qcom: ipq8074: add the reserved-memory node
|
|
||||||
|
|
||||||
On IPQ8074, 4MB of memory is needed for TZ. So mark that region
|
|
||||||
as reserved.
|
|
||||||
|
|
||||||
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
[bjorn: Squash with existing reserved-memory node]
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
|
|
||||||
1 file changed, 5 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -88,6 +88,11 @@
|
|
||||||
|
|
||||||
hwlocks = <&tcsr_mutex 0>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ memory@4ac00000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
firmware {
|
|
||||||
@ -1,36 +0,0 @@
|
|||||||
From 4f0959ded385c8ed518659aa08cedbd83ae0726a Mon Sep 17 00:00:00 2001
|
|
||||||
From: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
Date: Tue, 8 Feb 2022 21:05:24 +0530
|
|
||||||
Subject: [PATCH 11/44] arm64: dts: qcom: ipq8074: enable the GICv2m support
|
|
||||||
|
|
||||||
GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
|
|
||||||
which supports upto 32 MSI interrupts. Lets add support for the same.
|
|
||||||
|
|
||||||
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
|
|
||||||
1 file changed, 9 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -635,9 +635,18 @@
|
|
||||||
|
|
||||||
intc: interrupt-controller@b000000 {
|
|
||||||
compatible = "qcom,msm-qgic2";
|
|
||||||
+ #address-cells = <1>;
|
|
||||||
+ #size-cells = <1>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <0x3>;
|
|
||||||
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
|
||||||
+ ranges = <0 0xb00a000 0xffd>;
|
|
||||||
+
|
|
||||||
+ v2m@0 {
|
|
||||||
+ compatible = "arm,gic-v2m-frame";
|
|
||||||
+ msi-controller;
|
|
||||||
+ reg = <0x0 0xffd>;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
From 2e21d1f48dc0d0cdbd53ac33b9859c7cb575eecc Mon Sep 17 00:00:00 2001
|
|
||||||
From: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
Date: Wed, 2 Feb 2022 22:05:08 +0530
|
|
||||||
Subject: [PATCH 12/44] arm64: dts: qcom: ipq8074: drop the clock-frequency
|
|
||||||
property
|
|
||||||
|
|
||||||
Drop the clock-frequency property from the MMIO timer node, since it
|
|
||||||
is already configured by the bootloader.
|
|
||||||
|
|
||||||
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
|
|
||||||
1 file changed, 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -671,7 +671,6 @@
|
|
||||||
ranges;
|
|
||||||
compatible = "arm,armv7-timer-mem";
|
|
||||||
reg = <0x0b120000 0x1000>;
|
|
||||||
- clock-frequency = <19200000>;
|
|
||||||
|
|
||||||
frame@b120000 {
|
|
||||||
frame-number = <0>;
|
|
||||||
@ -1,62 +0,0 @@
|
|||||||
From 4647475f588c85138ddf47a17305dd41834e1105 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Tue, 5 Apr 2022 08:34:43 +0200
|
|
||||||
Subject: [PATCH 13/44] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT
|
|
||||||
schema
|
|
||||||
|
|
||||||
The DT schema expects dma channels in tx-rx order. No functional
|
|
||||||
change.
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
|
|
||||||
1 file changed, 8 insertions(+), 8 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -472,8 +472,8 @@
|
|
||||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
|
||||||
clock-names = "iface", "core";
|
|
||||||
clock-frequency = <400000>;
|
|
||||||
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
|
|
||||||
- dma-names = "rx", "tx";
|
|
||||||
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
|
|
||||||
+ dma-names = "tx", "rx";
|
|
||||||
pinctrl-0 = <&i2c_0_pins>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
status = "disabled";
|
|
||||||
@@ -489,8 +489,8 @@
|
|
||||||
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
|
||||||
clock-names = "iface", "core";
|
|
||||||
clock-frequency = <100000>;
|
|
||||||
- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
|
|
||||||
- dma-names = "rx", "tx";
|
|
||||||
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
|
|
||||||
+ dma-names = "tx", "rx";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
@@ -504,8 +504,8 @@
|
|
||||||
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
|
|
||||||
clock-names = "iface", "core";
|
|
||||||
clock-frequency = <400000>;
|
|
||||||
- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
|
|
||||||
- dma-names = "rx", "tx";
|
|
||||||
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
|
|
||||||
+ dma-names = "tx", "rx";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
@@ -519,8 +519,8 @@
|
|
||||||
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
|
||||||
clock-names = "iface", "core";
|
|
||||||
clock-frequency = <100000>;
|
|
||||||
- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
|
|
||||||
- dma-names = "rx", "tx";
|
|
||||||
+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
|
|
||||||
+ dma-names = "tx", "rx";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,69 +0,0 @@
|
|||||||
From 553f1ea4128453cead2d38d5773ec6044c6e7626 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Tue, 5 Apr 2022 08:34:44 +0200
|
|
||||||
Subject: [PATCH 14/44] arm64: dts: qcom: align clocks in I2C/SPI with DT
|
|
||||||
schema
|
|
||||||
|
|
||||||
The DT schema expects clocks core-iface order. No functional change.
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
|
|
||||||
1 file changed, 12 insertions(+), 12 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -468,9 +468,9 @@
|
|
||||||
#size-cells = <0>;
|
|
||||||
reg = <0x078b6000 0x600>;
|
|
||||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
||||||
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
|
||||||
- clock-names = "iface", "core";
|
|
||||||
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
|
|
||||||
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
|
||||||
+ clock-names = "core", "iface";
|
|
||||||
clock-frequency = <400000>;
|
|
||||||
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
@@ -485,9 +485,9 @@
|
|
||||||
#size-cells = <0>;
|
|
||||||
reg = <0x078b7000 0x600>;
|
|
||||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
||||||
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
|
||||||
- clock-names = "iface", "core";
|
|
||||||
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
|
|
||||||
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
|
||||||
+ clock-names = "core", "iface";
|
|
||||||
clock-frequency = <100000>;
|
|
||||||
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
@@ -500,9 +500,9 @@
|
|
||||||
#size-cells = <0>;
|
|
||||||
reg = <0x78b9000 0x600>;
|
|
||||||
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
||||||
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
|
|
||||||
- clock-names = "iface", "core";
|
|
||||||
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
|
|
||||||
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
|
||||||
+ clock-names = "core", "iface";
|
|
||||||
clock-frequency = <400000>;
|
|
||||||
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
@@ -515,9 +515,9 @@
|
|
||||||
#size-cells = <0>;
|
|
||||||
reg = <0x078ba000 0x600>;
|
|
||||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
||||||
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
|
||||||
- clock-names = "iface", "core";
|
|
||||||
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
|
|
||||||
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
|
||||||
+ clock-names = "core", "iface";
|
|
||||||
clock-frequency = <100000>;
|
|
||||||
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
@ -1,37 +0,0 @@
|
|||||||
From 04e91eb95f7a0a9dceed2c1fcb47fbbe7f96ec52 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Wed, 4 May 2022 15:19:16 +0200
|
|
||||||
Subject: [PATCH 15/44] arm64: dts: qcom: correct DWC3 node names and unit
|
|
||||||
addresses
|
|
||||||
|
|
||||||
Align DWC3 USB node names with DT schema ("usb" is expected) and correct
|
|
||||||
the unit addresses to match the "reg" property. This also implies
|
|
||||||
overriding nodes by label, instead of full path.
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
|
|
||||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
|
||||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -579,7 +579,7 @@
|
|
||||||
resets = <&gcc GCC_USB0_BCR>;
|
|
||||||
status = "disabled";
|
|
||||||
|
|
||||||
- dwc_0: dwc3@8a00000 {
|
|
||||||
+ dwc_0: usb@8a00000 {
|
|
||||||
compatible = "snps,dwc3";
|
|
||||||
reg = <0x8a00000 0xcd00>;
|
|
||||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
@@ -619,7 +619,7 @@
|
|
||||||
resets = <&gcc GCC_USB1_BCR>;
|
|
||||||
status = "disabled";
|
|
||||||
|
|
||||||
- dwc_1: dwc3@8c00000 {
|
|
||||||
+ dwc_1: usb@8c00000 {
|
|
||||||
compatible = "snps,dwc3";
|
|
||||||
reg = <0x8c00000 0xcd00>;
|
|
||||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
@ -1,36 +0,0 @@
|
|||||||
From 65b572a6c5bad2c9f3c784ff42d4eddedcfd85cd Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Wed, 4 May 2022 15:19:17 +0200
|
|
||||||
Subject: [PATCH 16/44] arm64: dts: qcom: ipq8074: add dedicated
|
|
||||||
qcom,ipq8074-dwc3 compatible
|
|
||||||
|
|
||||||
Add dedicated compatible for DWC3 USB node name to allow more accurate
|
|
||||||
DT schema matching.
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220504131923.214367-8-krzysztof.kozlowski@linaro.org
|
|
||||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
|
||||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -554,7 +554,7 @@
|
|
||||||
};
|
|
||||||
|
|
||||||
usb_0: usb@8af8800 {
|
|
||||||
- compatible = "qcom,dwc3";
|
|
||||||
+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
|
|
||||||
reg = <0x08af8800 0x400>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
@@ -594,7 +594,7 @@
|
|
||||||
};
|
|
||||||
|
|
||||||
usb_1: usb@8cf8800 {
|
|
||||||
- compatible = "qcom,dwc3";
|
|
||||||
+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
|
|
||||||
reg = <0x08cf8800 0x400>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
@ -1,39 +0,0 @@
|
|||||||
From e8949160470080b4c24139cfb88accc25e589f70 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Wed, 4 May 2022 15:19:22 +0200
|
|
||||||
Subject: [PATCH 17/44] arm64: dts: qcom: align DWC3 USB clocks with DT schema
|
|
||||||
|
|
||||||
Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
|
|
||||||
No functional impact expected.
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
|
|
||||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
|
|
||||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -564,8 +564,8 @@
|
|
||||||
<&gcc GCC_USB0_MASTER_CLK>,
|
|
||||||
<&gcc GCC_USB0_SLEEP_CLK>,
|
|
||||||
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
||||||
- clock-names = "sys_noc_axi",
|
|
||||||
- "master",
|
|
||||||
+ clock-names = "cfg_noc",
|
|
||||||
+ "core",
|
|
||||||
"sleep",
|
|
||||||
"mock_utmi";
|
|
||||||
|
|
||||||
@@ -604,8 +604,8 @@
|
|
||||||
<&gcc GCC_USB1_MASTER_CLK>,
|
|
||||||
<&gcc GCC_USB1_SLEEP_CLK>,
|
|
||||||
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
|
|
||||||
- clock-names = "sys_noc_axi",
|
|
||||||
- "master",
|
|
||||||
+ clock-names = "cfg_noc",
|
|
||||||
+ "core",
|
|
||||||
"sleep",
|
|
||||||
"mock_utmi";
|
|
||||||
|
|
||||||
@ -1,36 +0,0 @@
|
|||||||
From af38dc1085f574d575c886c0800645c8b7d4b874 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Date: Thu, 26 May 2022 22:42:47 +0200
|
|
||||||
Subject: [PATCH 18/44] arm64: dts: qcom: adjust whitespace around '='
|
|
||||||
|
|
||||||
Fix whitespace coding style: use single space instead of tabs or
|
|
||||||
multiple spaces around '=' sign in property assignment. No functional
|
|
||||||
changes (same DTB).
|
|
||||||
|
|
||||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
|
||||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -119,7 +119,7 @@
|
|
||||||
<&xo>;
|
|
||||||
clock-names = "aux", "cfg_ahb", "ref";
|
|
||||||
|
|
||||||
- resets = <&gcc GCC_USB1_PHY_BCR>,
|
|
||||||
+ resets = <&gcc GCC_USB1_PHY_BCR>,
|
|
||||||
<&gcc GCC_USB3PHY_1_PHY_BCR>;
|
|
||||||
reset-names = "phy","common";
|
|
||||||
status = "disabled";
|
|
||||||
@@ -162,7 +162,7 @@
|
|
||||||
<&xo>;
|
|
||||||
clock-names = "aux", "cfg_ahb", "ref";
|
|
||||||
|
|
||||||
- resets = <&gcc GCC_USB0_PHY_BCR>,
|
|
||||||
+ resets = <&gcc GCC_USB0_PHY_BCR>,
|
|
||||||
<&gcc GCC_USB3PHY_0_PHY_BCR>;
|
|
||||||
reset-names = "phy","common";
|
|
||||||
status = "disabled";
|
|
||||||
@ -1,34 +0,0 @@
|
|||||||
From 0d7e4bd5d554ac7471724f80aa67b664f3539f47 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Date: Sun, 15 May 2022 03:24:19 +0530
|
|
||||||
Subject: [PATCH 19/44] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
|
|
||||||
|
|
||||||
Since the Qualcomm sdhci-msm device-tree binding has been converted
|
|
||||||
to yaml format, 'make dtbs_check' reports issues with
|
|
||||||
inconsistent 'sdhci@' convention used for specifying the
|
|
||||||
sdhci nodes. The generic mmc bindings expect 'mmc@' format
|
|
||||||
instead.
|
|
||||||
|
|
||||||
Fix the same.
|
|
||||||
|
|
||||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Cc: Rob Herring <robh@kernel.org>
|
|
||||||
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
[bjorn: Moved non-arm64 changes to separate commit]
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -376,7 +376,7 @@
|
|
||||||
cell-index = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
- sdhc_1: sdhci@7824900 {
|
|
||||||
+ sdhc_1: mmc@7824900 {
|
|
||||||
compatible = "qcom,sdhci-msm-v4";
|
|
||||||
reg = <0x7824900 0x500>, <0x7824000 0x800>;
|
|
||||||
reg-names = "hc_mem", "core_mem";
|
|
||||||
@ -1,47 +0,0 @@
|
|||||||
From d923ec8397673773a3d22dc3ac0c5fccd22cd405 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Date: Sun, 15 May 2022 03:24:22 +0530
|
|
||||||
Subject: [PATCH 20/44] arm64: dts: qcom: Fix ordering of 'clocks' &
|
|
||||||
'clock-names' for sdhci nodes
|
|
||||||
|
|
||||||
Since the Qualcomm sdhci-msm device-tree binding has been converted
|
|
||||||
to yaml format, 'make dtbs_check' reports a number of issues with
|
|
||||||
ordering of 'clocks' & 'clock-names' for sdhci nodes:
|
|
||||||
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
|
|
||||||
clock-names:0: 'iface' was expected
|
|
||||||
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
|
|
||||||
clock-names:1: 'core' was expected
|
|
||||||
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
|
|
||||||
clock-names:2: 'xo' was expected
|
|
||||||
|
|
||||||
Fix the same by updating the offending 'dts' files.
|
|
||||||
|
|
||||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Cc: Rob Herring <robh@kernel.org>
|
|
||||||
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
|
|
||||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -385,10 +385,10 @@
|
|
||||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-names = "hc_irq", "pwr_irq";
|
|
||||||
|
|
||||||
- clocks = <&xo>,
|
|
||||||
- <&gcc GCC_SDCC1_AHB_CLK>,
|
|
||||||
- <&gcc GCC_SDCC1_APPS_CLK>;
|
|
||||||
- clock-names = "xo", "iface", "core";
|
|
||||||
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
||||||
+ <&gcc GCC_SDCC1_APPS_CLK>,
|
|
||||||
+ <&xo>;
|
|
||||||
+ clock-names = "iface", "core", "xo";
|
|
||||||
max-frequency = <384000000>;
|
|
||||||
mmc-ddr-1_8v;
|
|
||||||
mmc-hs200-1_8v;
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From f56aefe67c7652d38293afa83333c9228a9fbc35 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 15 May 2022 23:00:41 +0200
|
|
||||||
Subject: [PATCH 21/44] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock
|
|
||||||
|
|
||||||
Add binding for the PPE crypto clock in IPQ8074.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
@@ -233,6 +233,7 @@
|
|
||||||
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
|
|
||||||
#define GCC_PCIE0_RCHNG_CLK_SRC 225
|
|
||||||
#define GCC_PCIE0_RCHNG_CLK 226
|
|
||||||
+#define GCC_CRYPTO_PPE_CLK 227
|
|
||||||
|
|
||||||
#define GCC_BLSP1_BCR 0
|
|
||||||
#define GCC_BLSP1_QUP1_BCR 1
|
|
||||||
@ -1,52 +0,0 @@
|
|||||||
From 3c47c458fdf4056d4682cf2474e5599d5a916b61 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 15 May 2022 23:00:42 +0200
|
|
||||||
Subject: [PATCH 22/44] clk: qcom: ipq8074: add PPE crypto clock
|
|
||||||
|
|
||||||
The built-in PPE engine has a dedicated clock for the EIP-197 crypto
|
|
||||||
engine.
|
|
||||||
|
|
||||||
So, since the required clock currently missing add support for it.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
|
|
||||||
1 file changed, 19 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct clk_branch gcc_crypto_ppe_clk = {
|
|
||||||
+ .halt_reg = 0x68310,
|
|
||||||
+ .halt_bit = 31,
|
|
||||||
+ .clkr = {
|
|
||||||
+ .enable_reg = 0x68310,
|
|
||||||
+ .enable_mask = BIT(0),
|
|
||||||
+ .hw.init = &(struct clk_init_data){
|
|
||||||
+ .name = "gcc_crypto_ppe_clk",
|
|
||||||
+ .parent_names = (const char *[]){
|
|
||||||
+ "nss_ppe_clk_src"
|
|
||||||
+ },
|
|
||||||
+ .num_parents = 1,
|
|
||||||
+ .flags = CLK_SET_RATE_PARENT,
|
|
||||||
+ .ops = &clk_branch2_ops,
|
|
||||||
+ },
|
|
||||||
+ },
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
|
|
||||||
.halt_reg = 0x6830c,
|
|
||||||
.clkr = {
|
|
||||||
@@ -4649,6 +4667,7 @@ static struct clk_regmap *gcc_ipq8074_cl
|
|
||||||
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
|
|
||||||
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
|
|
||||||
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
|
|
||||||
+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From c0823201046e5a79823e3ff5fa4f0a9b5fcda14d Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 15 May 2022 23:00:45 +0200
|
|
||||||
Subject: [PATCH 23/44] dt-bindings: clock: qcom: ipq8074: add USB GDSCs
|
|
||||||
|
|
||||||
Add bindings for the USB GDSCs found in IPQ8074 GCC.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++
|
|
||||||
1 file changed, 3 insertions(+)
|
|
||||||
|
|
||||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
@@ -368,4 +368,7 @@
|
|
||||||
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
|
||||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
|
||||||
|
|
||||||
+#define USB0_GDSC 0
|
|
||||||
+#define USB1_GDSC 1
|
|
||||||
+
|
|
||||||
#endif
|
|
||||||
@ -1,79 +0,0 @@
|
|||||||
From 248fb3267c23749059baa231e21650a68771abef Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 15 May 2022 23:00:46 +0200
|
|
||||||
Subject: [PATCH 24/44] clk: qcom: ipq8074: add USB GDSCs
|
|
||||||
|
|
||||||
Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/Kconfig | 1 +
|
|
||||||
drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
|
|
||||||
2 files changed, 25 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/Kconfig
|
|
||||||
+++ b/drivers/clk/qcom/Kconfig
|
|
||||||
@@ -167,6 +167,7 @@ config IPQ_LCC_806X
|
|
||||||
|
|
||||||
config IPQ_GCC_8074
|
|
||||||
tristate "IPQ8074 Global Clock Controller"
|
|
||||||
+ select QCOM_GDSC
|
|
||||||
help
|
|
||||||
Support for global clock controller on ipq8074 devices.
|
|
||||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
|
||||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
@@ -22,6 +22,7 @@
|
|
||||||
#include "clk-alpha-pll.h"
|
|
||||||
#include "clk-regmap-divider.h"
|
|
||||||
#include "clk-regmap-mux.h"
|
|
||||||
+#include "gdsc.h"
|
|
||||||
#include "reset.h"
|
|
||||||
|
|
||||||
enum {
|
|
||||||
@@ -4402,6 +4403,22 @@ static struct clk_branch gcc_pcie0_axi_s
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct gdsc usb0_gdsc = {
|
|
||||||
+ .gdscr = 0x3e078,
|
|
||||||
+ .pd = {
|
|
||||||
+ .name = "usb0_gdsc",
|
|
||||||
+ },
|
|
||||||
+ .pwrsts = PWRSTS_OFF_ON,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static struct gdsc usb1_gdsc = {
|
|
||||||
+ .gdscr = 0x3f078,
|
|
||||||
+ .pd = {
|
|
||||||
+ .name = "usb1_gdsc",
|
|
||||||
+ },
|
|
||||||
+ .pwrsts = PWRSTS_OFF_ON,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct alpha_pll_config ubi32_pll_config = {
|
|
||||||
.l = 0x4e,
|
|
||||||
.config_ctl_val = 0x200d4aa8,
|
|
||||||
@@ -4805,6 +4822,11 @@ static const struct qcom_reset_map gcc_i
|
|
||||||
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct gdsc *gcc_ipq8074_gdscs[] = {
|
|
||||||
+ [USB0_GDSC] = &usb0_gdsc,
|
|
||||||
+ [USB1_GDSC] = &usb1_gdsc,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct of_device_id gcc_ipq8074_match_table[] = {
|
|
||||||
{ .compatible = "qcom,gcc-ipq8074" },
|
|
||||||
{ }
|
|
||||||
@@ -4827,6 +4849,8 @@ static const struct qcom_cc_desc gcc_ipq
|
|
||||||
.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
|
|
||||||
.clk_hws = gcc_ipq8074_hws,
|
|
||||||
.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
|
|
||||||
+ .gdscs = gcc_ipq8074_gdscs,
|
|
||||||
+ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
|
|
||||||
};
|
|
||||||
|
|
||||||
static int gcc_ipq8074_probe(struct platform_device *pdev)
|
|
||||||
@ -1,43 +0,0 @@
|
|||||||
From e8516c04110438230314ddbe94879ecb4a5db5df Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 15 May 2022 23:00:48 +0200
|
|
||||||
Subject: [PATCH 25/44] arm64: dts: qcom: ipq8074: add USB power domains
|
|
||||||
|
|
||||||
Add USB power domains provided by GCC GDSCs.
|
|
||||||
Add the required #power-domain-cells to the GCC as well.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220515210048.483898-11-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
|
|
||||||
1 file changed, 5 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -348,6 +348,7 @@
|
|
||||||
compatible = "qcom,gcc-ipq8074";
|
|
||||||
reg = <0x01800000 0x80000>;
|
|
||||||
#clock-cells = <0x1>;
|
|
||||||
+ #power-domain-cells = <1>;
|
|
||||||
#reset-cells = <0x1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
@@ -576,6 +577,8 @@
|
|
||||||
<133330000>,
|
|
||||||
<19200000>;
|
|
||||||
|
|
||||||
+ power-domains = <&gcc USB0_GDSC>;
|
|
||||||
+
|
|
||||||
resets = <&gcc GCC_USB0_BCR>;
|
|
||||||
status = "disabled";
|
|
||||||
|
|
||||||
@@ -616,6 +619,8 @@
|
|
||||||
<133330000>,
|
|
||||||
<19200000>;
|
|
||||||
|
|
||||||
+ power-domains = <&gcc USB1_GDSC>;
|
|
||||||
+
|
|
||||||
resets = <&gcc GCC_USB1_BCR>;
|
|
||||||
status = "disabled";
|
|
||||||
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
From 510f246cf8f6af8c0d7a46d22448b812fd9a14a4 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 4 Jul 2022 13:33:18 +0200
|
|
||||||
Subject: [PATCH 26/44] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC
|
|
||||||
node
|
|
||||||
|
|
||||||
The ARM timer is usually considered not part of SoC node, just like
|
|
||||||
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
|
|
||||||
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
|
|
||||||
From schema: dtschema/schemas/simple-bus.yaml
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
[bjorn: Moved node after "soc" for alphabetical ordering]
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
|
|
||||||
1 file changed, 8 insertions(+), 8 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -654,14 +654,6 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
- timer {
|
|
||||||
- compatible = "arm,armv8-timer";
|
|
||||||
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
||||||
- };
|
|
||||||
-
|
|
||||||
watchdog: watchdog@b017000 {
|
|
||||||
compatible = "qcom,kpss-wdt";
|
|
||||||
reg = <0xb017000 0x1000>;
|
|
||||||
@@ -853,4 +845,12 @@
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ timer {
|
|
||||||
+ compatible = "arm,armv8-timer";
|
|
||||||
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
@ -1,27 +0,0 @@
|
|||||||
From 8cef5828706a1584b4dadf3f4b707a392bc8c231 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 4 Jul 2022 16:35:54 +0200
|
|
||||||
Subject: [PATCH 27/44] arm64: dts: qcom: ipq8074: add reset to SDHCI
|
|
||||||
|
|
||||||
Add reset to SDHCI controller so it can be reset to avoid timeout issues
|
|
||||||
after software reset due to bootloader set configuration.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
|
|
||||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -390,6 +390,7 @@
|
|
||||||
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
||||||
<&xo>;
|
|
||||||
clock-names = "iface", "core", "xo";
|
|
||||||
+ resets = <&gcc GCC_SDCC1_BCR>;
|
|
||||||
max-frequency = <384000000>;
|
|
||||||
mmc-ddr-1_8v;
|
|
||||||
mmc-hs200-1_8v;
|
|
||||||
@ -1,36 +0,0 @@
|
|||||||
From 2bf80b5de7c2598972af28adc09e8e667b528d11 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Johan Hovold <johan+linaro@kernel.org>
|
|
||||||
Date: Tue, 5 Jul 2022 13:40:22 +0200
|
|
||||||
Subject: [PATCH 28/44] arm64: dts: qcom: ipq8074: drop USB PHY clock index
|
|
||||||
|
|
||||||
The QMP USB PHY provides a single clock so drop the redundant clock
|
|
||||||
index.
|
|
||||||
|
|
||||||
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
|
||||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -130,7 +130,7 @@
|
|
||||||
<0x00058800 0x1f8>, /* PCS */
|
|
||||||
<0x00058600 0x044>; /* PCS misc*/
|
|
||||||
#phy-cells = <0>;
|
|
||||||
- #clock-cells = <1>;
|
|
||||||
+ #clock-cells = <0>;
|
|
||||||
clocks = <&gcc GCC_USB1_PIPE_CLK>;
|
|
||||||
clock-names = "pipe0";
|
|
||||||
clock-output-names = "usb3phy_1_cc_pipe_clk";
|
|
||||||
@@ -173,7 +173,7 @@
|
|
||||||
<0x00078800 0x1f8>, /* PCS */
|
|
||||||
<0x00078600 0x044>; /* PCS misc*/
|
|
||||||
#phy-cells = <0>;
|
|
||||||
- #clock-cells = <1>;
|
|
||||||
+ #clock-cells = <0>;
|
|
||||||
clocks = <&gcc GCC_USB0_PIPE_CLK>;
|
|
||||||
clock-names = "pipe0";
|
|
||||||
clock-output-names = "usb3phy_0_cc_pipe_clk";
|
|
||||||
@ -1,37 +0,0 @@
|
|||||||
From 73ea147a5caa82c94486076186af2c7dc1894a97 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 7 Jul 2022 19:37:33 +0200
|
|
||||||
Subject: [PATCH 29/44] arm64: dts: qcom: ipq8074: add APCS node
|
|
||||||
|
|
||||||
APCS now has support for providing the APSS clocks as the child device
|
|
||||||
for IPQ8074.
|
|
||||||
|
|
||||||
So, add the required DT node for it as it will later be used as the CPU
|
|
||||||
clocksource.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
[bjorn: Sorted node based on address]
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
|
|
||||||
1 file changed, 8 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -663,6 +663,14 @@
|
|
||||||
timeout-sec = <30>;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ apcs_glb: mailbox@b111000 {
|
|
||||||
+ compatible = "qcom,ipq8074-apcs-apps-global";
|
|
||||||
+ reg = <0x0b111000 0x6000>;
|
|
||||||
+
|
|
||||||
+ #clock-cells = <1>;
|
|
||||||
+ #mbox-cells = <1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
timer@b120000 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
@ -1,55 +0,0 @@
|
|||||||
From 254bf23fe2e0c73d75a0bf4f37579e15433b75e0 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 8 Jul 2022 15:38:45 +0200
|
|
||||||
Subject: [PATCH 30/44] arm64: dts: qcom: ipq8074: add #size/address-cells to
|
|
||||||
DTSI
|
|
||||||
|
|
||||||
Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating
|
|
||||||
the same properties in board DTS files.
|
|
||||||
|
|
||||||
Remove the mentioned properties from current board DTS files.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 --
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 ---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++
|
|
||||||
3 files changed, 3 insertions(+), 5 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
@@ -5,8 +5,6 @@
|
|
||||||
#include "ipq8074.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
- #address-cells = <0x2>;
|
|
||||||
- #size-cells = <0x2>;
|
|
||||||
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
|
|
||||||
compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
|
|
||||||
interrupt-parent = <&intc>;
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
|
|
||||||
@@ -7,9 +7,6 @@
|
|
||||||
#include "ipq8074.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
- #address-cells = <0x2>;
|
|
||||||
- #size-cells = <0x2>;
|
|
||||||
-
|
|
||||||
interrupt-parent = <&intc>;
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -7,6 +7,9 @@
|
|
||||||
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
+ #address-cells = <2>;
|
|
||||||
+ #size-cells = <2>;
|
|
||||||
+
|
|
||||||
model = "Qualcomm Technologies, Inc. IPQ8074";
|
|
||||||
compatible = "qcom,ipq8074";
|
|
||||||
|
|
||||||
@ -1,50 +0,0 @@
|
|||||||
From 520877b4d26ba4e6d08b5e9579f166ca2a934e81 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 8 Jul 2022 15:38:46 +0200
|
|
||||||
Subject: [PATCH 31/44] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI
|
|
||||||
|
|
||||||
Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board
|
|
||||||
DTS file.
|
|
||||||
|
|
||||||
Remove interrupt-parent from existing board DTS files.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 1 -
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 --
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
|
|
||||||
3 files changed, 1 insertion(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
@@ -7,7 +7,6 @@
|
|
||||||
/ {
|
|
||||||
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
|
|
||||||
compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
|
|
||||||
- interrupt-parent = <&intc>;
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart5;
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
|
|
||||||
@@ -7,8 +7,6 @@
|
|
||||||
#include "ipq8074.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
- interrupt-parent = <&intc>;
|
|
||||||
-
|
|
||||||
aliases {
|
|
||||||
serial0 = &blsp1_uart5;
|
|
||||||
};
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -12,6 +12,7 @@
|
|
||||||
|
|
||||||
model = "Qualcomm Technologies, Inc. IPQ8074";
|
|
||||||
compatible = "qcom,ipq8074";
|
|
||||||
+ interrupt-parent = <&intc>;
|
|
||||||
|
|
||||||
clocks {
|
|
||||||
sleep_clk: sleep_clk {
|
|
||||||
@ -1,58 +0,0 @@
|
|||||||
From 8928dcb644461e72608dbea26af4d072868ae41b Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 4 Jul 2022 23:23:54 +0200
|
|
||||||
Subject: [PATCH 32/44] regulator: qcom_spmi: add support for HT_P150
|
|
||||||
|
|
||||||
HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout
|
|
||||||
found in PMP8074 and PMS405 PMIC-s.
|
|
||||||
|
|
||||||
Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V
|
|
||||||
but the actual MAX output voltage depends on the exact LDO in each of
|
|
||||||
the PMIC-s.
|
|
||||||
|
|
||||||
It has a max current of 150mA, voltage step of 8mV.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Link: https://lore.kernel.org/r/20220704212402.1715182-4-robimarko@gmail.com
|
|
||||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
|
|
||||||
1 file changed, 7 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
+++ b/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
@@ -164,6 +164,7 @@ enum spmi_regulator_subtype {
|
|
||||||
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
|
|
||||||
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
|
|
||||||
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
|
|
||||||
+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum spmi_common_regulator_registers {
|
|
||||||
@@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_
|
|
||||||
SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct spmi_voltage_range ht_p150_ranges[] = {
|
|
||||||
+ SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static DEFINE_SPMI_SET_POINTS(pldo);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(nldo1);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(nldo2);
|
|
||||||
@@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(ht_nldo);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(hfs430);
|
|
||||||
+static DEFINE_SPMI_SET_POINTS(ht_p150);
|
|
||||||
|
|
||||||
static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
|
|
||||||
int len)
|
|
||||||
@@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_h
|
|
||||||
|
|
||||||
static const struct spmi_regulator_mapping supported_regulators[] = {
|
|
||||||
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
|
|
||||||
+ SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
|
|
||||||
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
|
|
||||||
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
|
|
||||||
SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
|
|
||||||
@ -1,59 +0,0 @@
|
|||||||
From 2ba036ce8e99673073adc5ac62e7768a47725567 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 4 Jul 2022 23:23:55 +0200
|
|
||||||
Subject: [PATCH 33/44] regulator: qcom_spmi: add support for HT_P600
|
|
||||||
|
|
||||||
HT_P600 is a LDO PMOS regulator based on LV P600 using HFS430 layout
|
|
||||||
found in PMP8074 and PMS405 PMIC-s.
|
|
||||||
|
|
||||||
Both PMP8074 and PMS405 define the programmable range as 1.704 to 1.896V
|
|
||||||
but the actual MAX output voltage depends on the exact LDO in each of
|
|
||||||
the PMIC-s.
|
|
||||||
Their usual voltage that they are used is 1.8V.
|
|
||||||
|
|
||||||
It has a max current of 600mA, voltage step of 8mV.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Link: https://lore.kernel.org/r/20220704212402.1715182-5-robimarko@gmail.com
|
|
||||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
|
|
||||||
1 file changed, 7 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
+++ b/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
@@ -165,6 +165,7 @@ enum spmi_regulator_subtype {
|
|
||||||
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
|
|
||||||
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
|
|
||||||
SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
|
|
||||||
+ SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum spmi_common_regulator_registers {
|
|
||||||
@@ -549,6 +550,10 @@ static struct spmi_voltage_range ht_p150
|
|
||||||
SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct spmi_voltage_range ht_p600_ranges[] = {
|
|
||||||
+ SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static DEFINE_SPMI_SET_POINTS(pldo);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(nldo1);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(nldo2);
|
|
||||||
@@ -570,6 +575,7 @@ static DEFINE_SPMI_SET_POINTS(ht_lvpldo)
|
|
||||||
static DEFINE_SPMI_SET_POINTS(ht_nldo);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(hfs430);
|
|
||||||
static DEFINE_SPMI_SET_POINTS(ht_p150);
|
|
||||||
+static DEFINE_SPMI_SET_POINTS(ht_p600);
|
|
||||||
|
|
||||||
static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
|
|
||||||
int len)
|
|
||||||
@@ -1464,6 +1470,7 @@ static const struct regulator_ops spmi_h
|
|
||||||
|
|
||||||
static const struct spmi_regulator_mapping supported_regulators[] = {
|
|
||||||
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
|
|
||||||
+ SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
|
|
||||||
SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
|
|
||||||
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
|
|
||||||
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
|
|
||||||
@ -1,69 +0,0 @@
|
|||||||
From 933b687758646242fc7410edb06da70fe7540cdc Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 4 Jul 2022 23:23:57 +0200
|
|
||||||
Subject: [PATCH 34/44] regulator: qcom_spmi: add support for PMP8074
|
|
||||||
regulators
|
|
||||||
|
|
||||||
PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s.
|
|
||||||
|
|
||||||
It features 5 HF-SMPS and 13 LDO regulators.
|
|
||||||
|
|
||||||
HF-SMPS regulators are Buck HFS430 regulators.
|
|
||||||
L1, L2 and L3 are HT_N1200_ST subtype LDO regulators.
|
|
||||||
L4 is HT_N300_ST subtype LDO regulator.
|
|
||||||
L5 and L6 are HT_P600 subtype LDO regulators.
|
|
||||||
L7, L11, L12 and L13 are HT_P150 subtype LDO regulators.
|
|
||||||
L10 is HT_P50 subtype LDO regulator.
|
|
||||||
|
|
||||||
This commit adds support for all of the buck regulators and LDO-s except
|
|
||||||
for L10 as I dont have documentation on its output voltage range.
|
|
||||||
|
|
||||||
S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores
|
|
||||||
and L11 is the SDIO/eMMC I/O voltage regulator required for high speeds.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Link: https://lore.kernel.org/r/20220704212402.1715182-7-robimarko@gmail.com
|
|
||||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/regulator/qcom_spmi-regulator.c | 23 +++++++++++++++++++++++
|
|
||||||
1 file changed, 23 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
+++ b/drivers/regulator/qcom_spmi-regulator.c
|
|
||||||
@@ -2101,6 +2101,28 @@ static const struct spmi_regulator_data
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
|
|
||||||
+static const struct spmi_regulator_data pmp8074_regulators[] = {
|
|
||||||
+ { "s1", 0x1400, "vdd_s1"},
|
|
||||||
+ { "s2", 0x1700, "vdd_s2"},
|
|
||||||
+ { "s3", 0x1a00, "vdd_s3"},
|
|
||||||
+ { "s4", 0x1d00, "vdd_s4"},
|
|
||||||
+ { "s5", 0x2000, "vdd_s5"},
|
|
||||||
+ { "l1", 0x4000, "vdd_l1_l2"},
|
|
||||||
+ { "l2", 0x4100, "vdd_l1_l2"},
|
|
||||||
+ { "l3", 0x4200, "vdd_l3_l8"},
|
|
||||||
+ { "l4", 0x4300, "vdd_l4"},
|
|
||||||
+ { "l5", 0x4400, "vdd_l5_l6_l15"},
|
|
||||||
+ { "l6", 0x4500, "vdd_l5_l6_l15"},
|
|
||||||
+ { "l7", 0x4600, "vdd_l7"},
|
|
||||||
+ { "l8", 0x4700, "vdd_l3_l8"},
|
|
||||||
+ { "l9", 0x4800, "vdd_l9"},
|
|
||||||
+ /* l10 is currently unsupported HT_P50 */
|
|
||||||
+ { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
|
|
||||||
+ { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
|
|
||||||
+ { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
|
|
||||||
+ { }
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct spmi_regulator_data pms405_regulators[] = {
|
|
||||||
{ "s3", 0x1a00, "vdd_s3"},
|
|
||||||
{ }
|
|
||||||
@@ -2117,6 +2139,7 @@ static const struct of_device_id qcom_sp
|
|
||||||
{ .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
|
|
||||||
{ .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
|
|
||||||
{ .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
|
|
||||||
+ { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
|
|
||||||
{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From 55545dc54f015387dccfb3c8fe20115c5f21b8a7 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 11 Jul 2022 22:34:05 +0200
|
|
||||||
Subject: [PATCH 35/44] pinctrl: qcom-pmic-gpio: add support for PMP8074
|
|
||||||
|
|
||||||
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
|
|
||||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
||||||
---
|
|
||||||
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++
|
|
||||||
1 file changed, 2 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
|
|
||||||
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
|
|
||||||
@@ -1167,6 +1167,8 @@ static const struct of_device_id pmic_gp
|
|
||||||
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
|
|
||||||
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
|
|
||||||
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
|
|
||||||
+ /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
|
|
||||||
+ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
|
|
||||||
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
|
|
||||||
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
|
|
||||||
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
|
|
||||||
@ -1,60 +0,0 @@
|
|||||||
From f76d65737cff6f41f0fab7a46a742d89c08fd652 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Date: Sun, 17 Oct 2021 09:12:16 -0700
|
|
||||||
Subject: [PATCH 36/44] mfd: qcom-spmi-pmic: Sort compatibles in the driver
|
|
||||||
|
|
||||||
Sort the compatibles in the driver, to make it easier to validate that
|
|
||||||
the DT binding and driver are in sync.
|
|
||||||
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211017161218.2378176-2-bjorn.andersson@linaro.org
|
|
||||||
---
|
|
||||||
drivers/mfd/qcom-spmi-pmic.c | 30 +++++++++++++++---------------
|
|
||||||
1 file changed, 15 insertions(+), 15 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
+++ b/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
@@ -40,27 +40,27 @@
|
|
||||||
#define PM660_SUBTYPE 0x1B
|
|
||||||
|
|
||||||
static const struct of_device_id pmic_spmi_id_table[] = {
|
|
||||||
- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
|
|
||||||
- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
From b4f85660d09360b2ef9f04e51890fbf9935bf759 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Date: Sun, 17 Oct 2021 09:12:18 -0700
|
|
||||||
Subject: [PATCH 37/44] mfd: qcom-spmi-pmic: Add missing PMICs supported by
|
|
||||||
socinfo
|
|
||||||
|
|
||||||
The Qualcomm socinfo driver has eight more PMICs described, add these to
|
|
||||||
the SPMI PMIC driver as well.
|
|
||||||
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211017161218.2378176-4-bjorn.andersson@linaro.org
|
|
||||||
---
|
|
||||||
drivers/mfd/qcom-spmi-pmic.c | 17 +++++++++++++++++
|
|
||||||
1 file changed, 17 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
+++ b/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
@@ -31,6 +31,8 @@
|
|
||||||
#define PM8916_SUBTYPE 0x0b
|
|
||||||
#define PM8004_SUBTYPE 0x0c
|
|
||||||
#define PM8909_SUBTYPE 0x0d
|
|
||||||
+#define PM8028_SUBTYPE 0x0e
|
|
||||||
+#define PM8901_SUBTYPE 0x0f
|
|
||||||
#define PM8950_SUBTYPE 0x10
|
|
||||||
#define PMI8950_SUBTYPE 0x11
|
|
||||||
#define PM8998_SUBTYPE 0x14
|
|
||||||
@@ -38,6 +40,13 @@
|
|
||||||
#define PM8005_SUBTYPE 0x18
|
|
||||||
#define PM660L_SUBTYPE 0x1A
|
|
||||||
#define PM660_SUBTYPE 0x1B
|
|
||||||
+#define PM8150_SUBTYPE 0x1E
|
|
||||||
+#define PM8150L_SUBTYPE 0x1f
|
|
||||||
+#define PM8150B_SUBTYPE 0x20
|
|
||||||
+#define PMK8002_SUBTYPE 0x21
|
|
||||||
+#define PM8009_SUBTYPE 0x24
|
|
||||||
+#define PM8150C_SUBTYPE 0x26
|
|
||||||
+#define SMB2351_SUBTYPE 0x29
|
|
||||||
|
|
||||||
static const struct of_device_id pmic_spmi_id_table[] = {
|
|
||||||
{ .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
|
|
||||||
@@ -45,9 +54,15 @@ static const struct of_device_id pmic_sp
|
|
||||||
{ .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
|
|
||||||
@@ -60,6 +75,8 @@ static const struct of_device_id pmic_sp
|
|
||||||
{ .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
@ -1,27 +0,0 @@
|
|||||||
From 1aa9a70ca9a1d3bb5139030fd9fc340d8525a7d7 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 19 Aug 2022 00:18:13 +0200
|
|
||||||
Subject: [PATCH 38/44] iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2
|
|
||||||
ADC5
|
|
||||||
|
|
||||||
Add support for ADC5_VREF_VADC channel to rev2 ADC5 channel list.
|
|
||||||
This channel measures the VADC reference LDO output.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Link: https://lore.kernel.org/r/20220818221815.346233-3-robimarko@gmail.com
|
|
||||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
||||||
---
|
|
||||||
drivers/iio/adc/qcom-spmi-adc5.c | 2 ++
|
|
||||||
1 file changed, 2 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/iio/adc/qcom-spmi-adc5.c
|
|
||||||
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
|
|
||||||
@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_c
|
|
||||||
SCALE_HW_CALIB_DEFAULT)
|
|
||||||
[ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
|
|
||||||
SCALE_HW_CALIB_DEFAULT)
|
|
||||||
+ [ADC5_VREF_VADC] = ADC5_CHAN_VOLT("vref_vadc", 0,
|
|
||||||
+ SCALE_HW_CALIB_DEFAULT)
|
|
||||||
[ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
|
|
||||||
SCALE_HW_CALIB_DEFAULT)
|
|
||||||
[ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
|
|
||||||
@ -1,47 +0,0 @@
|
|||||||
From 8454872e52992108308e44aa974b441558fa1fc9 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Tue, 23 Aug 2022 22:43:51 +0200
|
|
||||||
Subject: [PATCH 39/44] phy: qcom-qmp-pcie: make pipe clock rate configurable
|
|
||||||
|
|
||||||
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
|
|
||||||
like every other PCIe QMP PHY does, so make it configurable as part of the
|
|
||||||
qmp_phy_cfg.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
|
|
||||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
|
|
||||||
1 file changed, 12 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
|
|
||||||
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
|
|
||||||
@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
|
|
||||||
/* true, if PHY has secondary tx/rx lanes to be configured */
|
|
||||||
bool is_dual_lane_phy;
|
|
||||||
|
|
||||||
+ /* QMP PHY pipe clock interface rate */
|
|
||||||
+ unsigned long pipe_clock_rate;
|
|
||||||
+
|
|
||||||
/* true, if PCS block has no separate SW_RESET register */
|
|
||||||
bool no_pcs_sw_reset;
|
|
||||||
};
|
|
||||||
@@ -5139,8 +5142,15 @@ static int phy_pipe_clk_register(struct
|
|
||||||
|
|
||||||
init.ops = &clk_fixed_rate_ops;
|
|
||||||
|
|
||||||
- /* controllers using QMP phys use 125MHz pipe clock interface */
|
|
||||||
- fixed->fixed_rate = 125000000;
|
|
||||||
+ /*
|
|
||||||
+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
|
|
||||||
+ * unless other frequency is specified in the PHY config.
|
|
||||||
+ */
|
|
||||||
+ if (qmp->phys[0]->cfg->pipe_clock_rate)
|
|
||||||
+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
|
|
||||||
+ else
|
|
||||||
+ fixed->fixed_rate = 125000000;
|
|
||||||
+
|
|
||||||
fixed->hw.init = &init;
|
|
||||||
|
|
||||||
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
|
|
||||||
@ -1,201 +0,0 @@
|
|||||||
From 6702bed8d48e29bd51c4b702b0baf18c5b1814c1 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Tue, 23 Aug 2022 22:47:40 +0200
|
|
||||||
Subject: [PATCH 40/44] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY
|
|
||||||
support
|
|
||||||
|
|
||||||
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
|
|
||||||
Gen2 one is already supported, so add the support for the Gen3 one.
|
|
||||||
It uses the same register layout as IPQ6018.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com
|
|
||||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++
|
|
||||||
1 file changed, 160 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
|
|
||||||
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
|
|
||||||
@@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq
|
|
||||||
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
|
|
||||||
};
|
|
||||||
|
|
||||||
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
|
|
||||||
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
|
|
||||||
+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
|
|
||||||
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
||||||
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
|
|
||||||
@@ -3168,6 +3295,36 @@ static const struct qmp_phy_cfg ipq8074_
|
|
||||||
.pwrdn_delay_max = 1005, /* us */
|
|
||||||
};
|
|
||||||
|
|
||||||
+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
|
|
||||||
+ .type = PHY_TYPE_PCIE,
|
|
||||||
+ .nlanes = 1,
|
|
||||||
+
|
|
||||||
+ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
|
|
||||||
+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
|
|
||||||
+ .tx_tbl = ipq8074_pcie_gen3_tx_tbl,
|
|
||||||
+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
|
|
||||||
+ .rx_tbl = ipq8074_pcie_gen3_rx_tbl,
|
|
||||||
+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
|
|
||||||
+ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
|
|
||||||
+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
|
|
||||||
+ .clk_list = ipq8074_pciephy_clk_l,
|
|
||||||
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
|
|
||||||
+ .reset_list = ipq8074_pciephy_reset_l,
|
|
||||||
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
||||||
+ .vreg_list = NULL,
|
|
||||||
+ .num_vregs = 0,
|
|
||||||
+ .regs = ipq_pciephy_gen3_regs_layout,
|
|
||||||
+
|
|
||||||
+ .start_ctrl = SERDES_START | PCS_START,
|
|
||||||
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
||||||
+
|
|
||||||
+ .has_pwrdn_delay = true,
|
|
||||||
+ .pwrdn_delay_min = 995, /* us */
|
|
||||||
+ .pwrdn_delay_max = 1005, /* us */
|
|
||||||
+
|
|
||||||
+ .pipe_clock_rate = 250000000,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
|
|
||||||
.type = PHY_TYPE_PCIE,
|
|
||||||
.nlanes = 1,
|
|
||||||
@@ -5571,6 +5728,9 @@ static const struct of_device_id qcom_qm
|
|
||||||
.compatible = "qcom,ipq8074-qmp-pcie-phy",
|
|
||||||
.data = &ipq8074_pciephy_cfg,
|
|
||||||
}, {
|
|
||||||
+ .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
|
|
||||||
+ .data = &ipq8074_pciephy_gen3_cfg,
|
|
||||||
+ }, {
|
|
||||||
.compatible = "qcom,ipq6018-qmp-pcie-phy",
|
|
||||||
.data = &ipq6018_pciephy_cfg,
|
|
||||||
}, {
|
|
||||||
@ -1,50 +0,0 @@
|
|||||||
From 70835efbc6c9dbc4e652aa60a250ecb1a2160a9b Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sun, 5 Sep 2021 19:11:31 +0200
|
|
||||||
Subject: [PATCH 41/44] soc: qcom: socinfo: Add IPQ8074 family ID-s
|
|
||||||
|
|
||||||
IPQ8074 family SoC ID-s are missing, so lets add them based on
|
|
||||||
the downstream driver.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Kathiravan T <kathirav@codeaurora.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20210905171131.660885-1-robimarko@gmail.com
|
|
||||||
---
|
|
||||||
drivers/soc/qcom/socinfo.c | 12 ++++++++++++
|
|
||||||
1 file changed, 12 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/soc/qcom/socinfo.c
|
|
||||||
+++ b/drivers/soc/qcom/socinfo.c
|
|
||||||
@@ -281,19 +281,31 @@ static const struct soc_id soc_id[] = {
|
|
||||||
{ 319, "APQ8098" },
|
|
||||||
{ 321, "SDM845" },
|
|
||||||
{ 322, "MDM9206" },
|
|
||||||
+ { 323, "IPQ8074" },
|
|
||||||
{ 324, "SDA660" },
|
|
||||||
{ 325, "SDM658" },
|
|
||||||
{ 326, "SDA658" },
|
|
||||||
{ 327, "SDA630" },
|
|
||||||
{ 338, "SDM450" },
|
|
||||||
{ 341, "SDA845" },
|
|
||||||
+ { 342, "IPQ8072" },
|
|
||||||
+ { 343, "IPQ8076" },
|
|
||||||
+ { 344, "IPQ8078" },
|
|
||||||
{ 345, "SDM636" },
|
|
||||||
{ 346, "SDA636" },
|
|
||||||
{ 349, "SDM632" },
|
|
||||||
{ 350, "SDA632" },
|
|
||||||
{ 351, "SDA450" },
|
|
||||||
{ 356, "SM8250" },
|
|
||||||
+ { 375, "IPQ8070" },
|
|
||||||
+ { 376, "IPQ8071" },
|
|
||||||
+ { 389, "IPQ8072A" },
|
|
||||||
+ { 390, "IPQ8074A" },
|
|
||||||
+ { 391, "IPQ8076A" },
|
|
||||||
+ { 392, "IPQ8078A" },
|
|
||||||
{ 394, "SM6125" },
|
|
||||||
+ { 395, "IPQ8070A" },
|
|
||||||
+ { 396, "IPQ8071A" },
|
|
||||||
{ 402, "IPQ6018" },
|
|
||||||
{ 403, "IPQ6028" },
|
|
||||||
{ 421, "IPQ6000" },
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
From 66dafdaad281e0a0eb2045ffb1f8dcf72e25989f Mon Sep 17 00:00:00 2001
|
|
||||||
From: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
Date: Mon, 7 Feb 2022 16:51:24 +0200
|
|
||||||
Subject: [PATCH 42/44] PCI: dwc: tegra: move GEN3_RELATED DBI register to
|
|
||||||
common header
|
|
||||||
|
|
||||||
These are common dwc macros that will be used for other platforms.
|
|
||||||
|
|
||||||
Reviewed-by: Rob Herring <robh@kernel.org>
|
|
||||||
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
---
|
|
||||||
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
|
|
||||||
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
|
|
||||||
2 files changed, 6 insertions(+), 6 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-designware.h
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-designware.h
|
|
||||||
@@ -74,6 +74,12 @@
|
|
||||||
#define PCIE_MSI_INTR0_MASK 0x82C
|
|
||||||
#define PCIE_MSI_INTR0_STATUS 0x830
|
|
||||||
|
|
||||||
+#define GEN3_RELATED_OFF 0x890
|
|
||||||
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
|
||||||
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
|
||||||
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
|
||||||
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
|
||||||
+
|
|
||||||
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
|
|
||||||
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
|
|
||||||
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
||||||
@@ -194,12 +194,6 @@
|
|
||||||
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
|
|
||||||
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
|
|
||||||
|
|
||||||
-#define GEN3_RELATED_OFF 0x890
|
|
||||||
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
|
||||||
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
|
||||||
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
|
||||||
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
|
||||||
-
|
|
||||||
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
|
|
||||||
#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
|
|
||||||
#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
|
|
||||||
@ -1,46 +0,0 @@
|
|||||||
From 55299da8c17f23249497ee8868a5a268c6e3fbcc Mon Sep 17 00:00:00 2001
|
|
||||||
From: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
Date: Mon, 7 Feb 2022 16:51:25 +0200
|
|
||||||
Subject: [PATCH 43/44] PCI: qcom: Define slot capabilities using
|
|
||||||
PCI_EXP_SLTCAP_*
|
|
||||||
|
|
||||||
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
|
|
||||||
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
|
|
||||||
describe its meaning.
|
|
||||||
|
|
||||||
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
---
|
|
||||||
drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
|
|
||||||
1 file changed, 13 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
@@ -69,7 +69,18 @@
|
|
||||||
#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
|
||||||
#define CFG_BRIDGE_SB_INIT BIT(0)
|
|
||||||
|
|
||||||
-#define PCIE_CAP_LINK1_VAL 0x2FD7F
|
|
||||||
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
|
|
||||||
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
|
|
||||||
+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
|
|
||||||
+ PCI_EXP_SLTCAP_PCP | \
|
|
||||||
+ PCI_EXP_SLTCAP_MRLSP | \
|
|
||||||
+ PCI_EXP_SLTCAP_AIP | \
|
|
||||||
+ PCI_EXP_SLTCAP_PIP | \
|
|
||||||
+ PCI_EXP_SLTCAP_HPS | \
|
|
||||||
+ PCI_EXP_SLTCAP_HPC | \
|
|
||||||
+ PCI_EXP_SLTCAP_EIP | \
|
|
||||||
+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
|
|
||||||
+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
|
|
||||||
|
|
||||||
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
|
|
||||||
|
|
||||||
@@ -1125,7 +1136,7 @@ static int qcom_pcie_post_init_2_3_3(str
|
|
||||||
|
|
||||||
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
|
|
||||||
writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
|
|
||||||
- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
|
||||||
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
|
||||||
|
|
||||||
val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
|
||||||
val &= ~PCI_EXP_LNKCAP_ASPMS;
|
|
||||||
@ -1,212 +0,0 @@
|
|||||||
From b9d02fcefdf166671356a08dd621429e63541b22 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
|
|
||||||
Date: Thu, 10 Feb 2022 18:02:47 +0100
|
|
||||||
Subject: [PATCH 44/44] PCI: qcom: Add IPQ60xx support
|
|
||||||
|
|
||||||
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
|
|
||||||
platform.
|
|
||||||
|
|
||||||
The code is based on downstream[1] Codeaurora kernel v5.4 (branch
|
|
||||||
win.linuxopenwrt.2.0).
|
|
||||||
|
|
||||||
Split out the DBI registers access part from .init into .post_init. DBI
|
|
||||||
registers are only accessible after phy_power_on().
|
|
||||||
|
|
||||||
[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
|
|
||||||
|
|
||||||
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
|
|
||||||
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
---
|
|
||||||
drivers/pci/controller/dwc/pcie-designware.h | 1 +
|
|
||||||
drivers/pci/controller/dwc/pcie-qcom.c | 135 +++++++++++++++++++
|
|
||||||
2 files changed, 136 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-designware.h
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-designware.h
|
|
||||||
@@ -76,6 +76,7 @@
|
|
||||||
|
|
||||||
#define GEN3_RELATED_OFF 0x890
|
|
||||||
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
|
||||||
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
|
|
||||||
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
|
||||||
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
|
||||||
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
@@ -52,6 +52,10 @@
|
|
||||||
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
|
|
||||||
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
|
|
||||||
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
|
|
||||||
+#define AHB_CLK_EN BIT(0)
|
|
||||||
+#define MSTR_AXI_CLK_EN BIT(1)
|
|
||||||
+#define BYPASS BIT(4)
|
|
||||||
+
|
|
||||||
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
|
|
||||||
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
|
|
||||||
#define PCIE20_PARF_LTSSM 0x1B0
|
|
||||||
@@ -179,6 +183,11 @@ struct qcom_pcie_resources_2_7_0 {
|
|
||||||
struct clk *pipe_clk;
|
|
||||||
};
|
|
||||||
|
|
||||||
+struct qcom_pcie_resources_2_9_0 {
|
|
||||||
+ struct clk_bulk_data clks[5];
|
|
||||||
+ struct reset_control *rst;
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
union qcom_pcie_resources {
|
|
||||||
struct qcom_pcie_resources_1_0_0 v1_0_0;
|
|
||||||
struct qcom_pcie_resources_2_1_0 v2_1_0;
|
|
||||||
@@ -186,6 +195,7 @@ union qcom_pcie_resources {
|
|
||||||
struct qcom_pcie_resources_2_3_3 v2_3_3;
|
|
||||||
struct qcom_pcie_resources_2_4_0 v2_4_0;
|
|
||||||
struct qcom_pcie_resources_2_7_0 v2_7_0;
|
|
||||||
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct qcom_pcie;
|
|
||||||
@@ -1276,6 +1286,121 @@ static void qcom_pcie_post_deinit_2_7_0(
|
|
||||||
clk_disable_unprepare(res->pipe_clk);
|
|
||||||
}
|
|
||||||
|
|
||||||
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
|
|
||||||
+{
|
|
||||||
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
|
|
||||||
+ struct dw_pcie *pci = pcie->pci;
|
|
||||||
+ struct device *dev = pci->dev;
|
|
||||||
+ int ret;
|
|
||||||
+
|
|
||||||
+ res->clks[0].id = "iface";
|
|
||||||
+ res->clks[1].id = "axi_m";
|
|
||||||
+ res->clks[2].id = "axi_s";
|
|
||||||
+ res->clks[3].id = "axi_bridge";
|
|
||||||
+ res->clks[4].id = "rchng";
|
|
||||||
+
|
|
||||||
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
|
|
||||||
+ if (ret < 0)
|
|
||||||
+ return ret;
|
|
||||||
+
|
|
||||||
+ res->rst = devm_reset_control_array_get_exclusive(dev);
|
|
||||||
+ if (IS_ERR(res->rst))
|
|
||||||
+ return PTR_ERR(res->rst);
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
|
|
||||||
+{
|
|
||||||
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
|
|
||||||
+
|
|
||||||
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
|
|
||||||
+{
|
|
||||||
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
|
|
||||||
+ struct device *dev = pcie->pci->dev;
|
|
||||||
+ int ret;
|
|
||||||
+
|
|
||||||
+ ret = reset_control_assert(res->rst);
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(dev, "reset assert failed (%d)\n", ret);
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ /*
|
|
||||||
+ * Delay periods before and after reset deassert are working values
|
|
||||||
+ * from downstream Codeaurora kernel
|
|
||||||
+ */
|
|
||||||
+ usleep_range(2000, 2500);
|
|
||||||
+
|
|
||||||
+ ret = reset_control_deassert(res->rst);
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ usleep_range(2000, 2500);
|
|
||||||
+
|
|
||||||
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
|
|
||||||
+ if (ret)
|
|
||||||
+ goto err_reset;
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+
|
|
||||||
+err_reset:
|
|
||||||
+ reset_control_assert(res->rst);
|
|
||||||
+
|
|
||||||
+ return ret;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
|
|
||||||
+{
|
|
||||||
+ struct dw_pcie *pci = pcie->pci;
|
|
||||||
+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
|
||||||
+ u32 val;
|
|
||||||
+ int i;
|
|
||||||
+
|
|
||||||
+ writel(SLV_ADDR_SPACE_SZ,
|
|
||||||
+ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
|
|
||||||
+
|
|
||||||
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
|
||||||
+ val &= ~BIT(0);
|
|
||||||
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
|
|
||||||
+
|
|
||||||
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
|
|
||||||
+
|
|
||||||
+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
|
|
||||||
+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
|
|
||||||
+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
|
|
||||||
+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS
|
|
||||||
+ | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
|
|
||||||
+ pci->dbi_base + GEN3_RELATED_OFF);
|
|
||||||
+
|
|
||||||
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
|
|
||||||
+ | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
|
|
||||||
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
|
|
||||||
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
|
|
||||||
+
|
|
||||||
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
|
|
||||||
+
|
|
||||||
+ dw_pcie_dbi_ro_wr_en(pci);
|
|
||||||
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
|
||||||
+
|
|
||||||
+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
|
||||||
+ val &= ~PCI_EXP_LNKCAP_ASPMS;
|
|
||||||
+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
|
||||||
+
|
|
||||||
+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
|
|
||||||
+ PCI_EXP_DEVCTL2);
|
|
||||||
+
|
|
||||||
+ for (i = 0; i < 256; i++)
|
|
||||||
+ writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N
|
|
||||||
+ + (4 * i));
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
static int qcom_pcie_link_up(struct dw_pcie *pci)
|
|
||||||
{
|
|
||||||
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
|
||||||
@@ -1467,6 +1592,15 @@ static const struct qcom_pcie_ops ops_1_
|
|
||||||
.config_sid = qcom_pcie_config_sid_sm8250,
|
|
||||||
};
|
|
||||||
|
|
||||||
+/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
|
|
||||||
+static const struct qcom_pcie_ops ops_2_9_0 = {
|
|
||||||
+ .get_resources = qcom_pcie_get_resources_2_9_0,
|
|
||||||
+ .init = qcom_pcie_init_2_9_0,
|
|
||||||
+ .post_init = qcom_pcie_post_init_2_9_0,
|
|
||||||
+ .deinit = qcom_pcie_deinit_2_9_0,
|
|
||||||
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
||||||
.link_up = qcom_pcie_link_up,
|
|
||||||
.start_link = qcom_pcie_start_link,
|
|
||||||
@@ -1565,6 +1699,7 @@ static const struct of_device_id qcom_pc
|
|
||||||
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
|
|
||||||
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
|
|
||||||
{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
|
|
||||||
+ { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,70 +0,0 @@
|
|||||||
From 2dc8319c43ccc511a38f441ab4f7aa120af9a9fb Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Wed, 22 Dec 2021 12:23:34 +0100
|
|
||||||
Subject: [PATCH 100/137] arm64: dts: ipq8074: add reserved memory nodes
|
|
||||||
|
|
||||||
IPQ8074 has multiple reserved memory ranges, if they are not defined
|
|
||||||
then weird things tend to happen, board hangs and resets when PCI or
|
|
||||||
WLAN is used etc.
|
|
||||||
|
|
||||||
So, to avoid all of that add the reserved memory nodes from the downstream
|
|
||||||
5.4 kernel from QCA.
|
|
||||||
This is their default layout meant for devices with 1GB of RAM, but
|
|
||||||
devices with lower ammounts can override the Q6 node.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
|
|
||||||
1 file changed, 35 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -85,6 +85,26 @@
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
+ nss@40000000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x40000000 0x0 0x01000000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ tzapp_region: tzapp@4a400000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ uboot@4a600000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x4a600000 0x0 0x00400000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ sbl@4aa00000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
smem@4ab00000 {
|
|
||||||
compatible = "qcom,smem";
|
|
||||||
reg = <0x0 0x4ab00000 0x0 0x00100000>;
|
|
||||||
@@ -97,6 +117,21 @@
|
|
||||||
no-map;
|
|
||||||
reg = <0x0 0x4ac00000 0x0 0x00400000>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ q6_region: wcnss@4b000000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ q6_etr_region: q6_etr_dump@50f00000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x50f00000 0x0 0x00100000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ m3_dump_region: m3_dump@51000000 {
|
|
||||||
+ no-map;
|
|
||||||
+ reg = <0x0 0x51000000 0x0 0x100000>;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
firmware {
|
|
||||||
@ -1,49 +0,0 @@
|
|||||||
From 9d38e110e23ce0b858ccd67a8a819dc187529a33 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
|
||||||
Date: Fri, 8 Jul 2022 23:24:25 +0200
|
|
||||||
Subject: [PATCH 101/137] clk: qcom: clk-rcg2: add rcg2 mux ops
|
|
||||||
|
|
||||||
An RCG may act as a mux that switch between 2 parents.
|
|
||||||
This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
|
|
||||||
the CPU cluster clock just switches between XO and the PLL that feeds it.
|
|
||||||
|
|
||||||
Add the required ops to add support for this special configuration and use
|
|
||||||
the generic mux function to determine the rate.
|
|
||||||
|
|
||||||
This way we dont have to keep a essentially dummy frequency table to use
|
|
||||||
RCG2 as a mux.
|
|
||||||
|
|
||||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/clk-rcg.h | 1 +
|
|
||||||
drivers/clk/qcom/clk-rcg2.c | 7 +++++++
|
|
||||||
2 files changed, 8 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/clk-rcg.h
|
|
||||||
+++ b/drivers/clk/qcom/clk-rcg.h
|
|
||||||
@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
|
|
||||||
|
|
||||||
extern const struct clk_ops clk_rcg2_ops;
|
|
||||||
extern const struct clk_ops clk_rcg2_floor_ops;
|
|
||||||
+extern const struct clk_ops clk_rcg2_mux_closest_ops;
|
|
||||||
extern const struct clk_ops clk_edp_pixel_ops;
|
|
||||||
extern const struct clk_ops clk_byte_ops;
|
|
||||||
extern const struct clk_ops clk_byte2_ops;
|
|
||||||
--- a/drivers/clk/qcom/clk-rcg2.c
|
|
||||||
+++ b/drivers/clk/qcom/clk-rcg2.c
|
|
||||||
@@ -471,6 +471,13 @@ const struct clk_ops clk_rcg2_floor_ops
|
|
||||||
};
|
|
||||||
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
|
|
||||||
|
|
||||||
+const struct clk_ops clk_rcg2_mux_closest_ops = {
|
|
||||||
+ .determine_rate = __clk_mux_determine_rate_closest,
|
|
||||||
+ .get_parent = clk_rcg2_get_parent,
|
|
||||||
+ .set_parent = clk_rcg2_set_parent,
|
|
||||||
+};
|
|
||||||
+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
|
|
||||||
+
|
|
||||||
struct frac_entry {
|
|
||||||
int num;
|
|
||||||
int den;
|
|
||||||
@ -1,61 +0,0 @@
|
|||||||
From d2b31da4eae2175ff86f28f596b54abde08d382f Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sat, 9 Jul 2022 00:18:45 +0200
|
|
||||||
Subject: [PATCH 102/137] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
|
|
||||||
|
|
||||||
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
|
|
||||||
IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
|
|
||||||
currently broken.
|
|
||||||
|
|
||||||
More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
|
|
||||||
clock.
|
|
||||||
However after debugging why it was always stuck at 800Mhz, it was figured
|
|
||||||
out that its not regmap_mux compatible at all.
|
|
||||||
It is a simple mux but it uses RCG2 register layout and control bits, so
|
|
||||||
utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
|
|
||||||
having to provide a dummy frequency table.
|
|
||||||
|
|
||||||
While we are here, use ARRAY_SIZE for number of parents.
|
|
||||||
|
|
||||||
Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
|
|
||||||
|
|
||||||
Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
|
|
||||||
1 file changed, 6 insertions(+), 7 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/apss-ipq6018.c
|
|
||||||
+++ b/drivers/clk/qcom/apss-ipq6018.c
|
|
||||||
@@ -16,7 +16,7 @@
|
|
||||||
#include "clk-regmap.h"
|
|
||||||
#include "clk-branch.h"
|
|
||||||
#include "clk-alpha-pll.h"
|
|
||||||
-#include "clk-regmap-mux.h"
|
|
||||||
+#include "clk-rcg.h"
|
|
||||||
|
|
||||||
enum {
|
|
||||||
P_XO,
|
|
||||||
@@ -33,16 +33,15 @@ static const struct parent_map parents_a
|
|
||||||
{ P_APSS_PLL_EARLY, 5 },
|
|
||||||
};
|
|
||||||
|
|
||||||
-static struct clk_regmap_mux apcs_alias0_clk_src = {
|
|
||||||
- .reg = 0x0050,
|
|
||||||
- .width = 3,
|
|
||||||
- .shift = 7,
|
|
||||||
+static struct clk_rcg2 apcs_alias0_clk_src = {
|
|
||||||
+ .cmd_rcgr = 0x0050,
|
|
||||||
+ .hid_width = 5,
|
|
||||||
.parent_map = parents_apcs_alias0_clk_src_map,
|
|
||||||
.clkr.hw.init = &(struct clk_init_data){
|
|
||||||
.name = "apcs_alias0_clk_src",
|
|
||||||
.parent_data = parents_apcs_alias0_clk_src,
|
|
||||||
- .num_parents = 2,
|
|
||||||
- .ops = &clk_regmap_mux_closest_ops,
|
|
||||||
+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
|
|
||||||
+ .ops = &clk_rcg2_mux_closest_ops,
|
|
||||||
.flags = CLK_SET_RATE_PARENT,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
@ -1,68 +0,0 @@
|
|||||||
From 8878f39722eeacbb40babe82ad763d8d20214018 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sat, 9 Jul 2022 00:32:04 +0200
|
|
||||||
Subject: [PATCH 104/137] clk: qcom: apss-ipq-pll: use OF match data for Alpha
|
|
||||||
PLL config
|
|
||||||
|
|
||||||
Convert the driver to use OF match data for providing the Alpha PLL config
|
|
||||||
per compatible.
|
|
||||||
This is required for IPQ8074 support since it uses a different Alpha PLL
|
|
||||||
config.
|
|
||||||
|
|
||||||
While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make
|
|
||||||
it clear that it is for IPQ6018 only.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/apss-ipq-pll.c | 12 +++++++++---
|
|
||||||
1 file changed, 9 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
+++ b/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
@@ -2,6 +2,7 @@
|
|
||||||
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
|
||||||
#include <linux/clk-provider.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
+#include <linux/of_device.h>
|
|
||||||
#include <linux/platform_device.h>
|
|
||||||
#include <linux/regmap.h>
|
|
||||||
|
|
||||||
@@ -36,7 +37,7 @@ static struct clk_alpha_pll ipq_pll = {
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
-static const struct alpha_pll_config ipq_pll_config = {
|
|
||||||
+static const struct alpha_pll_config ipq6018_pll_config = {
|
|
||||||
.l = 0x37,
|
|
||||||
.config_ctl_val = 0x04141200,
|
|
||||||
.config_ctl_hi_val = 0x0,
|
|
||||||
@@ -54,6 +55,7 @@ static const struct regmap_config ipq_pl
|
|
||||||
|
|
||||||
static int apss_ipq_pll_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
+ const struct alpha_pll_config *ipq_pll_config;
|
|
||||||
struct device *dev = &pdev->dev;
|
|
||||||
struct regmap *regmap;
|
|
||||||
void __iomem *base;
|
|
||||||
@@ -67,7 +69,11 @@ static int apss_ipq_pll_probe(struct pla
|
|
||||||
if (IS_ERR(regmap))
|
|
||||||
return PTR_ERR(regmap);
|
|
||||||
|
|
||||||
- clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
|
|
||||||
+ ipq_pll_config = of_device_get_match_data(&pdev->dev);
|
|
||||||
+ if (!ipq_pll_config)
|
|
||||||
+ return -ENODEV;
|
|
||||||
+
|
|
||||||
+ clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
|
|
||||||
|
|
||||||
ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
|
|
||||||
if (ret)
|
|
||||||
@@ -78,7 +84,7 @@ static int apss_ipq_pll_probe(struct pla
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id apss_ipq_pll_match_table[] = {
|
|
||||||
- { .compatible = "qcom,ipq6018-a53pll" },
|
|
||||||
+ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
|
|
||||||
@ -1,38 +0,0 @@
|
|||||||
From 426edd7e45e9eaf18c433739ceeb51e6f2f8e190 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 11 Jul 2022 22:40:52 +0200
|
|
||||||
Subject: [PATCH 105/137] clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL
|
|
||||||
config
|
|
||||||
|
|
||||||
Update the IPQ6018 Alpha PLL config to the latest one from the downstream
|
|
||||||
5.4 kernel[1].
|
|
||||||
|
|
||||||
This one should match the production SoC-s.
|
|
||||||
|
|
||||||
Tested on IPQ6018 CP01-C1 reference board.
|
|
||||||
|
|
||||||
[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/apss-ipq-pll.c | 8 ++++++--
|
|
||||||
1 file changed, 6 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
+++ b/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
@@ -39,10 +39,14 @@ static struct clk_alpha_pll ipq_pll = {
|
|
||||||
|
|
||||||
static const struct alpha_pll_config ipq6018_pll_config = {
|
|
||||||
.l = 0x37,
|
|
||||||
- .config_ctl_val = 0x04141200,
|
|
||||||
- .config_ctl_hi_val = 0x0,
|
|
||||||
+ .config_ctl_val = 0x240d4828,
|
|
||||||
+ .config_ctl_hi_val = 0x6,
|
|
||||||
.early_output_mask = BIT(3),
|
|
||||||
+ .aux2_output_mask = BIT(2),
|
|
||||||
+ .aux_output_mask = BIT(1),
|
|
||||||
.main_output_mask = BIT(0),
|
|
||||||
+ .test_ctl_val = 0x1c0000C0,
|
|
||||||
+ .test_ctl_hi_val = 0x4000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct regmap_config ipq_pll_regmap_config = {
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
From c633afe32123157370f21aeaf3d705ca584fc754 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 11 Jul 2022 14:23:08 +0200
|
|
||||||
Subject: [PATCH 106/137] clk: qcom: apss-ipq-pll: add support for IPQ8074
|
|
||||||
|
|
||||||
Add support for IPQ8074 since it uses the same PLL setup, however it uses
|
|
||||||
slightly different Alpha PLL config.
|
|
||||||
|
|
||||||
Alpha PLL config was obtained by dumping PLL registers from a running
|
|
||||||
device.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
Changes in v2:
|
|
||||||
* Drop hardcoded compatible check for IPQ6018 to do the PLL config and
|
|
||||||
utilize match data provided by previous commit
|
|
||||||
* Add IPQ8074 Alpha PLL config using match data
|
|
||||||
* Update commit description to reflect changes
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++
|
|
||||||
1 file changed, 13 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
+++ b/drivers/clk/qcom/apss-ipq-pll.c
|
|
||||||
@@ -49,6 +49,18 @@ static const struct alpha_pll_config ipq
|
|
||||||
.test_ctl_hi_val = 0x4000,
|
|
||||||
};
|
|
||||||
|
|
||||||
+static const struct alpha_pll_config ipq8074_pll_config = {
|
|
||||||
+ .l = 0x48,
|
|
||||||
+ .config_ctl_val = 0x200d4828,
|
|
||||||
+ .config_ctl_hi_val = 0x6,
|
|
||||||
+ .early_output_mask = BIT(3),
|
|
||||||
+ .aux2_output_mask = BIT(2),
|
|
||||||
+ .aux_output_mask = BIT(1),
|
|
||||||
+ .main_output_mask = BIT(0),
|
|
||||||
+ .test_ctl_val = 0x1c000000,
|
|
||||||
+ .test_ctl_hi_val = 0x4000,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct regmap_config ipq_pll_regmap_config = {
|
|
||||||
.reg_bits = 32,
|
|
||||||
.reg_stride = 4,
|
|
||||||
@@ -89,6 +101,7 @@ static int apss_ipq_pll_probe(struct pla
|
|
||||||
|
|
||||||
static const struct of_device_id apss_ipq_pll_match_table[] = {
|
|
||||||
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
|
|
||||||
+ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
|
|
||||||
@ -1,31 +0,0 @@
|
|||||||
From f3d524334069e69554eaecd8adf75284dff7c9d9 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 18 Aug 2022 23:15:43 +0200
|
|
||||||
Subject: [PATCH 107/137] arm64: dts: qcom: ipq8074: correct APCS register
|
|
||||||
space size
|
|
||||||
|
|
||||||
APCS DTS addition that was merged, was not supposed to get merged as it
|
|
||||||
was part of patch series that was superseded by 2 more patch series
|
|
||||||
that resolved issues with this one and greatly simplified things.
|
|
||||||
|
|
||||||
Since it already got merged, start by correcting the register space
|
|
||||||
size as APCS will not be providing regmap for PLL and it will conflict
|
|
||||||
with the standalone A53 PLL node.
|
|
||||||
|
|
||||||
Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node")
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -704,7 +704,7 @@
|
|
||||||
|
|
||||||
apcs_glb: mailbox@b111000 {
|
|
||||||
compatible = "qcom,ipq8074-apcs-apps-global";
|
|
||||||
- reg = <0x0b111000 0x6000>;
|
|
||||||
+ reg = <0x0b111000 0x1000>;
|
|
||||||
|
|
||||||
#clock-cells = <1>;
|
|
||||||
#mbox-cells = <1>;
|
|
||||||
@ -1,30 +0,0 @@
|
|||||||
From be028f5f79b8af6ea16ffeea486e216acdf80789 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 18 Aug 2022 23:21:06 +0200
|
|
||||||
Subject: [PATCH 108/137] arm64: dts: qcom: ipq8074: add A53 PLL node
|
|
||||||
|
|
||||||
Add the required node for A53 PLL which will be used to provide the CPU
|
|
||||||
clock via APCS for APSS scaling.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
|
|
||||||
1 file changed, 8 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -710,6 +710,14 @@
|
|
||||||
#mbox-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ a53pll: clock@b116000 {
|
|
||||||
+ compatible = "qcom,ipq8074-a53pll";
|
|
||||||
+ reg = <0x0b116000 0x40>;
|
|
||||||
+ #clock-cells = <0>;
|
|
||||||
+ clocks = <&xo>;
|
|
||||||
+ clock-names = "xo";
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
timer@b120000 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
@ -1,50 +0,0 @@
|
|||||||
From ded0538937e9edf8b217d2082fd30af3bf7bd10b Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Tue, 28 Dec 2021 20:59:18 +0100
|
|
||||||
Subject: [PATCH 109/137] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock
|
|
||||||
support
|
|
||||||
|
|
||||||
IPQ8074 has the APSS clock controller utilizing the same register space as
|
|
||||||
the APCS, so provide access to the APSS utilizing a child device like
|
|
||||||
IPQ6018.
|
|
||||||
|
|
||||||
IPQ6018 and IPQ8074 use the same controller and driver, so just utilize
|
|
||||||
IPQ6018 match data for IPQ8074.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
||||||
---
|
|
||||||
Changes in v7:
|
|
||||||
* Dont max_register modifications
|
|
||||||
* Drop custom IPQ8074 match data and use IPQ6018 one as they share the
|
|
||||||
controller and driver
|
|
||||||
|
|
||||||
Changes in v5:
|
|
||||||
* Use lower case hex for max_register
|
|
||||||
* Update the APSS clock name to match the new one without commas
|
|
||||||
---
|
|
||||||
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 6 +-----
|
|
||||||
1 file changed, 1 insertion(+), 5 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
|
|
||||||
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
|
|
||||||
@@ -33,10 +33,6 @@ static const struct qcom_apcs_ipc_data i
|
|
||||||
.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
|
|
||||||
};
|
|
||||||
|
|
||||||
-static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
|
|
||||||
- .offset = 8, .clk_name = NULL
|
|
||||||
-};
|
|
||||||
-
|
|
||||||
static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
|
|
||||||
.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
|
|
||||||
};
|
|
||||||
@@ -160,7 +156,7 @@ static int qcom_apcs_ipc_remove(struct p
|
|
||||||
/* .data is the offset of the ipc register within the global block */
|
|
||||||
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
|
|
||||||
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
|
|
||||||
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
|
|
||||||
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
|
|
||||||
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
|
|
||||||
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
|
|
||||||
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
|
|
||||||
@ -1,29 +0,0 @@
|
|||||||
From 0a36a586424feabf9ce9436379f9d061b7844155 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 18 Aug 2022 23:25:00 +0200
|
|
||||||
Subject: [PATCH 110/137] arm64: dts: qcom: ipq8074: add clocks to APCS
|
|
||||||
|
|
||||||
APCS now has support for providing the APSS clocks as the child device
|
|
||||||
for IPQ8074.
|
|
||||||
|
|
||||||
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
|
|
||||||
clocksource for APSS scaling.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
|
|
||||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -705,8 +705,9 @@
|
|
||||||
apcs_glb: mailbox@b111000 {
|
|
||||||
compatible = "qcom,ipq8074-apcs-apps-global";
|
|
||||||
reg = <0x0b111000 0x1000>;
|
|
||||||
-
|
|
||||||
#clock-cells = <1>;
|
|
||||||
+ clocks = <&a53pll>, <&xo>;
|
|
||||||
+ clock-names = "pll", "xo";
|
|
||||||
#mbox-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
From f086c5659cd54946b618ae4c695a8c05096f267a Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Mon, 20 Dec 2021 15:01:36 +0100
|
|
||||||
Subject: [PATCH 111/137] PCI: qcom: add IPQ8074 Gen3 support
|
|
||||||
|
|
||||||
IPQ8074 has one Gen2 and one Gen3 port, Gen3 port is the same one as
|
|
||||||
in IPQ6018, so reuse the support but just add the missing clocks.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
drivers/pci/controller/dwc/pcie-qcom.c | 9 ++++++---
|
|
||||||
1 file changed, 6 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
|
||||||
@@ -184,7 +184,7 @@ struct qcom_pcie_resources_2_7_0 {
|
|
||||||
};
|
|
||||||
|
|
||||||
struct qcom_pcie_resources_2_9_0 {
|
|
||||||
- struct clk_bulk_data clks[5];
|
|
||||||
+ struct clk_bulk_data clks[7];
|
|
||||||
struct reset_control *rst;
|
|
||||||
};
|
|
||||||
|
|
||||||
@@ -1296,8 +1296,10 @@ static int qcom_pcie_get_resources_2_9_0
|
|
||||||
res->clks[0].id = "iface";
|
|
||||||
res->clks[1].id = "axi_m";
|
|
||||||
res->clks[2].id = "axi_s";
|
|
||||||
- res->clks[3].id = "axi_bridge";
|
|
||||||
- res->clks[4].id = "rchng";
|
|
||||||
+ res->clks[3].id = "ahb";
|
|
||||||
+ res->clks[4].id = "aux";
|
|
||||||
+ res->clks[5].id = "axi_bridge";
|
|
||||||
+ res->clks[6].id = "rchng";
|
|
||||||
|
|
||||||
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
|
|
||||||
if (ret < 0)
|
|
||||||
@@ -1700,6 +1702,7 @@ static const struct of_device_id qcom_pc
|
|
||||||
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
|
|
||||||
{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
|
|
||||||
{ .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 },
|
|
||||||
+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &ops_2_9_0 },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,155 +0,0 @@
|
|||||||
From 84e13a5267e43bb0a6a1f764211fda7769dc9cbe Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:05 +0530
|
|
||||||
Subject: [PATCH 113/137] remoteproc: qcom: Add PRNG proxy clock
|
|
||||||
|
|
||||||
PRNG clock is needed by the secure PIL, support for the same
|
|
||||||
is added in subsequent patches.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
|
|
||||||
1 file changed, 47 insertions(+), 18 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -91,19 +91,6 @@ enum {
|
|
||||||
WCSS_QCS404,
|
|
||||||
};
|
|
||||||
|
|
||||||
-struct wcss_data {
|
|
||||||
- const char *firmware_name;
|
|
||||||
- unsigned int crash_reason_smem;
|
|
||||||
- u32 version;
|
|
||||||
- bool aon_reset_required;
|
|
||||||
- bool wcss_q6_reset_required;
|
|
||||||
- const char *ssr_name;
|
|
||||||
- const char *sysmon_name;
|
|
||||||
- int ssctl_id;
|
|
||||||
- const struct rproc_ops *ops;
|
|
||||||
- bool requires_force_stop;
|
|
||||||
-};
|
|
||||||
-
|
|
||||||
struct q6v5_wcss {
|
|
||||||
struct device *dev;
|
|
||||||
|
|
||||||
@@ -128,6 +115,7 @@ struct q6v5_wcss {
|
|
||||||
struct clk *qdsp6ss_xo_cbcr;
|
|
||||||
struct clk *qdsp6ss_core_gfmux;
|
|
||||||
struct clk *lcc_bcr_sleep;
|
|
||||||
+ struct clk *prng_clk;
|
|
||||||
struct regulator *cx_supply;
|
|
||||||
struct qcom_sysmon *sysmon;
|
|
||||||
|
|
||||||
@@ -151,6 +139,21 @@ struct q6v5_wcss {
|
|
||||||
struct qcom_rproc_ssr ssr_subdev;
|
|
||||||
};
|
|
||||||
|
|
||||||
+struct wcss_data {
|
|
||||||
+ int (*init_clock)(struct q6v5_wcss *wcss);
|
|
||||||
+ int (*init_regulator)(struct q6v5_wcss *wcss);
|
|
||||||
+ const char *firmware_name;
|
|
||||||
+ unsigned int crash_reason_smem;
|
|
||||||
+ u32 version;
|
|
||||||
+ bool aon_reset_required;
|
|
||||||
+ bool wcss_q6_reset_required;
|
|
||||||
+ const char *ssr_name;
|
|
||||||
+ const char *sysmon_name;
|
|
||||||
+ int ssctl_id;
|
|
||||||
+ const struct rproc_ops *ops;
|
|
||||||
+ bool requires_force_stop;
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
|
|
||||||
struct q6v5_wcss *wcss = rproc->priv;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
+ ret = clk_prepare_enable(wcss->prng_clk);
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(wcss->dev, "prng clock enable failed\n");
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
qcom_q6v5_prepare(&wcss->q6v5);
|
|
||||||
|
|
||||||
/* Release Q6 and WCSS reset */
|
|
||||||
@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
+ clk_disable_unprepare(wcss->prng_clk);
|
|
||||||
qcom_q6v5_unprepare(&wcss->q6v5);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
|
|
||||||
+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
|
|
||||||
+{
|
|
||||||
+ int ret;
|
|
||||||
+
|
|
||||||
+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
|
|
||||||
+ if (IS_ERR(wcss->prng_clk)) {
|
|
||||||
+ ret = PTR_ERR(wcss->prng_clk);
|
|
||||||
+ if (ret != -EPROBE_DEFER)
|
|
||||||
+ dev_err(wcss->dev, "Failed to get prng clock\n");
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int qcs404_init_clock(struct q6v5_wcss *wcss)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
|
|
||||||
+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
|
|
||||||
{
|
|
||||||
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
|
|
||||||
if (IS_ERR(wcss->cx_supply))
|
|
||||||
@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
if (ret)
|
|
||||||
goto free_rproc;
|
|
||||||
|
|
||||||
- if (wcss->version == WCSS_QCS404) {
|
|
||||||
- ret = q6v5_wcss_init_clock(wcss);
|
|
||||||
+ if (desc->init_clock) {
|
|
||||||
+ ret = desc->init_clock(wcss);
|
|
||||||
if (ret)
|
|
||||||
goto free_rproc;
|
|
||||||
+ }
|
|
||||||
|
|
||||||
- ret = q6v5_wcss_init_regulator(wcss);
|
|
||||||
+ if (desc->init_regulator) {
|
|
||||||
+ ret = desc->init_regulator(wcss);
|
|
||||||
if (ret)
|
|
||||||
goto free_rproc;
|
|
||||||
}
|
|
||||||
@@ -1086,6 +1112,7 @@ static int q6v5_wcss_remove(struct platf
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct wcss_data wcss_ipq8074_res_init = {
|
|
||||||
+ .init_clock = ipq8074_init_clock,
|
|
||||||
.firmware_name = "IPQ8074/q6_fw.mdt",
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
.aon_reset_required = true,
|
|
||||||
@@ -1095,6 +1122,8 @@ static const struct wcss_data wcss_ipq80
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct wcss_data wcss_qcs404_res_init = {
|
|
||||||
+ .init_clock = qcs404_init_clock,
|
|
||||||
+ .init_regulator = qcs404_init_regulator,
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
.firmware_name = "wcnss.mdt",
|
|
||||||
.version = WCSS_QCS404,
|
|
||||||
@ -1,143 +0,0 @@
|
|||||||
From cb3b9e284104fd7fe4aa92a37df005577aed2c40 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:06 +0530
|
|
||||||
Subject: [PATCH 114/137] remoteproc: qcom: Add secure PIL support
|
|
||||||
|
|
||||||
IPQ8074 uses secure PIL. Hence, adding the support for the same.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
|
|
||||||
1 file changed, 40 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -18,6 +18,7 @@
|
|
||||||
#include <linux/regulator/consumer.h>
|
|
||||||
#include <linux/reset.h>
|
|
||||||
#include <linux/soc/qcom/mdt_loader.h>
|
|
||||||
+#include <linux/qcom_scm.h>
|
|
||||||
#include "qcom_common.h"
|
|
||||||
#include "qcom_pil_info.h"
|
|
||||||
#include "qcom_q6v5.h"
|
|
||||||
@@ -86,6 +87,9 @@
|
|
||||||
#define TCSR_WCSS_CLK_ENABLE 0x14
|
|
||||||
|
|
||||||
#define MAX_HALT_REG 3
|
|
||||||
+
|
|
||||||
+#define WCNSS_PAS_ID 6
|
|
||||||
+
|
|
||||||
enum {
|
|
||||||
WCSS_IPQ8074,
|
|
||||||
WCSS_QCS404,
|
|
||||||
@@ -134,6 +138,7 @@ struct q6v5_wcss {
|
|
||||||
unsigned int crash_reason_smem;
|
|
||||||
u32 version;
|
|
||||||
bool requires_force_stop;
|
|
||||||
+ bool need_mem_protection;
|
|
||||||
|
|
||||||
struct qcom_rproc_glink glink_subdev;
|
|
||||||
struct qcom_rproc_ssr ssr_subdev;
|
|
||||||
@@ -152,6 +157,7 @@ struct wcss_data {
|
|
||||||
int ssctl_id;
|
|
||||||
const struct rproc_ops *ops;
|
|
||||||
bool requires_force_stop;
|
|
||||||
+ bool need_mem_protection;
|
|
||||||
};
|
|
||||||
|
|
||||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
|
||||||
@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
|
|
||||||
|
|
||||||
qcom_q6v5_prepare(&wcss->q6v5);
|
|
||||||
|
|
||||||
+ if (wcss->need_mem_protection) {
|
|
||||||
+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(wcss->dev, "wcss_reset failed\n");
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+ goto wait_for_reset;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
/* Release Q6 and WCSS reset */
|
|
||||||
ret = reset_control_deassert(wcss->wcss_reset);
|
|
||||||
if (ret) {
|
|
||||||
@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
|
|
||||||
if (ret)
|
|
||||||
goto wcss_q6_reset;
|
|
||||||
|
|
||||||
+wait_for_reset:
|
|
||||||
ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
|
|
||||||
if (ret == -ETIMEDOUT)
|
|
||||||
dev_err(wcss->dev, "start timed out\n");
|
|
||||||
@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
|
|
||||||
struct q6v5_wcss *wcss = rproc->priv;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
+ if (wcss->need_mem_protection) {
|
|
||||||
+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(wcss->dev, "not able to shutdown\n");
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+ goto pas_done;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
/* WCSS powerdown */
|
|
||||||
if (wcss->requires_force_stop) {
|
|
||||||
ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
|
|
||||||
@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
+pas_done:
|
|
||||||
clk_disable_unprepare(wcss->prng_clk);
|
|
||||||
qcom_q6v5_unprepare(&wcss->q6v5);
|
|
||||||
|
|
||||||
@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
|
|
||||||
struct q6v5_wcss *wcss = rproc->priv;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
|
|
||||||
- 0, wcss->mem_region, wcss->mem_phys,
|
|
||||||
- wcss->mem_size, &wcss->mem_reloc);
|
|
||||||
+ if (wcss->need_mem_protection)
|
|
||||||
+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
|
|
||||||
+ WCNSS_PAS_ID, wcss->mem_region,
|
|
||||||
+ wcss->mem_phys, wcss->mem_size,
|
|
||||||
+ &wcss->mem_reloc);
|
|
||||||
+ else
|
|
||||||
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
|
|
||||||
+ 0, wcss->mem_region, wcss->mem_phys,
|
|
||||||
+ wcss->mem_size, &wcss->mem_reloc);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
+ if (desc->need_mem_protection && !qcom_scm_is_available())
|
|
||||||
+ return -EPROBE_DEFER;
|
|
||||||
+
|
|
||||||
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
|
|
||||||
desc->firmware_name, sizeof(*wcss));
|
|
||||||
if (!rproc) {
|
|
||||||
@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
|
|
||||||
wcss->version = desc->version;
|
|
||||||
wcss->requires_force_stop = desc->requires_force_stop;
|
|
||||||
+ wcss->need_mem_protection = desc->need_mem_protection;
|
|
||||||
|
|
||||||
ret = q6v5_wcss_init_mmio(wcss, pdev);
|
|
||||||
if (ret)
|
|
||||||
@@ -1119,6 +1155,7 @@ static const struct wcss_data wcss_ipq80
|
|
||||||
.wcss_q6_reset_required = true,
|
|
||||||
.ops = &q6v5_wcss_ipq8074_ops,
|
|
||||||
.requires_force_stop = true,
|
|
||||||
+ .need_mem_protection = true,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct wcss_data wcss_qcs404_res_init = {
|
|
||||||
@ -1,104 +0,0 @@
|
|||||||
From bcb2c37f265924ac43642f1f97c964dd546b3cb5 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:07 +0530
|
|
||||||
Subject: [PATCH 115/137] remoteproc: qcom: Add support for split q6 + m3 wlan
|
|
||||||
firmware
|
|
||||||
|
|
||||||
IPQ8074 supports split firmware for q6 and m3 as well.
|
|
||||||
So add support for loading the m3 firmware before q6.
|
|
||||||
Now the drivers works fine for both split and unified
|
|
||||||
firmwares.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
|
|
||||||
1 file changed, 29 insertions(+), 4 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -139,6 +139,7 @@ struct q6v5_wcss {
|
|
||||||
u32 version;
|
|
||||||
bool requires_force_stop;
|
|
||||||
bool need_mem_protection;
|
|
||||||
+ const char *m3_firmware_name;
|
|
||||||
|
|
||||||
struct qcom_rproc_glink glink_subdev;
|
|
||||||
struct qcom_rproc_ssr ssr_subdev;
|
|
||||||
@@ -147,7 +148,8 @@ struct q6v5_wcss {
|
|
||||||
struct wcss_data {
|
|
||||||
int (*init_clock)(struct q6v5_wcss *wcss);
|
|
||||||
int (*init_regulator)(struct q6v5_wcss *wcss);
|
|
||||||
- const char *firmware_name;
|
|
||||||
+ const char *q6_firmware_name;
|
|
||||||
+ const char *m3_firmware_name;
|
|
||||||
unsigned int crash_reason_smem;
|
|
||||||
u32 version;
|
|
||||||
bool aon_reset_required;
|
|
||||||
@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
|
|
||||||
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
|
|
||||||
{
|
|
||||||
struct q6v5_wcss *wcss = rproc->priv;
|
|
||||||
+ const struct firmware *m3_fw;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
+ if (wcss->m3_firmware_name) {
|
|
||||||
+ ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
|
|
||||||
+ wcss->dev);
|
|
||||||
+ if (ret)
|
|
||||||
+ goto skip_m3;
|
|
||||||
+
|
|
||||||
+ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
|
|
||||||
+ wcss->m3_firmware_name, 0,
|
|
||||||
+ wcss->mem_region, wcss->mem_phys,
|
|
||||||
+ wcss->mem_size, &wcss->mem_reloc);
|
|
||||||
+
|
|
||||||
+ release_firmware(m3_fw);
|
|
||||||
+
|
|
||||||
+ if (ret) {
|
|
||||||
+ dev_err(wcss->dev, "can't load m3_fw.bXX\n");
|
|
||||||
+ return ret;
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+skip_m3:
|
|
||||||
if (wcss->need_mem_protection)
|
|
||||||
ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
|
|
||||||
WCNSS_PAS_ID, wcss->mem_region,
|
|
||||||
@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
return -EPROBE_DEFER;
|
|
||||||
|
|
||||||
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
|
|
||||||
- desc->firmware_name, sizeof(*wcss));
|
|
||||||
+ desc->q6_firmware_name, sizeof(*wcss));
|
|
||||||
if (!rproc) {
|
|
||||||
dev_err(&pdev->dev, "failed to allocate rproc\n");
|
|
||||||
return -ENOMEM;
|
|
||||||
@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
wcss->version = desc->version;
|
|
||||||
wcss->requires_force_stop = desc->requires_force_stop;
|
|
||||||
wcss->need_mem_protection = desc->need_mem_protection;
|
|
||||||
+ wcss->m3_firmware_name = desc->m3_firmware_name;
|
|
||||||
|
|
||||||
ret = q6v5_wcss_init_mmio(wcss, pdev);
|
|
||||||
if (ret)
|
|
||||||
@@ -1149,7 +1173,8 @@ static int q6v5_wcss_remove(struct platf
|
|
||||||
|
|
||||||
static const struct wcss_data wcss_ipq8074_res_init = {
|
|
||||||
.init_clock = ipq8074_init_clock,
|
|
||||||
- .firmware_name = "IPQ8074/q6_fw.mdt",
|
|
||||||
+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
|
|
||||||
+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
.aon_reset_required = true,
|
|
||||||
.wcss_q6_reset_required = true,
|
|
||||||
@@ -1162,7 +1187,7 @@ static const struct wcss_data wcss_qcs40
|
|
||||||
.init_clock = qcs404_init_clock,
|
|
||||||
.init_regulator = qcs404_init_regulator,
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
- .firmware_name = "wcnss.mdt",
|
|
||||||
+ .q6_firmware_name = "wcnss.mdt",
|
|
||||||
.version = WCSS_QCS404,
|
|
||||||
.aon_reset_required = false,
|
|
||||||
.wcss_q6_reset_required = false,
|
|
||||||
@ -1,24 +0,0 @@
|
|||||||
From 5b717749ce49853f495ebac227c72013622b0810 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:08 +0530
|
|
||||||
Subject: [PATCH 116/137] remoteproc: qcom: Add ssr subdevice identifier
|
|
||||||
|
|
||||||
Add name for ssr subdevice on IPQ8074 SoC.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -1178,6 +1178,7 @@ static const struct wcss_data wcss_ipq80
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
.aon_reset_required = true,
|
|
||||||
.wcss_q6_reset_required = true,
|
|
||||||
+ .ssr_name = "q6wcss",
|
|
||||||
.ops = &q6v5_wcss_ipq8074_ops,
|
|
||||||
.requires_force_stop = true,
|
|
||||||
.need_mem_protection = true,
|
|
||||||
@ -1,80 +0,0 @@
|
|||||||
From 3bc5b97ecbb003e413ae76b332b0ccdba05ef6bc Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:09 +0530
|
|
||||||
Subject: [PATCH 117/137] remoteproc: qcom: Update regmap offsets for halt
|
|
||||||
register
|
|
||||||
|
|
||||||
Fixed issue in reading halt-regs parameter from device-tree.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
|
|
||||||
1 file changed, 14 insertions(+), 8 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -86,7 +86,7 @@
|
|
||||||
#define TCSR_WCSS_CLK_MASK 0x1F
|
|
||||||
#define TCSR_WCSS_CLK_ENABLE 0x14
|
|
||||||
|
|
||||||
-#define MAX_HALT_REG 3
|
|
||||||
+#define MAX_HALT_REG 4
|
|
||||||
|
|
||||||
#define WCNSS_PAS_ID 6
|
|
||||||
|
|
||||||
@@ -154,6 +154,7 @@ struct wcss_data {
|
|
||||||
u32 version;
|
|
||||||
bool aon_reset_required;
|
|
||||||
bool wcss_q6_reset_required;
|
|
||||||
+ bool bcr_reset_required;
|
|
||||||
const char *ssr_name;
|
|
||||||
const char *sysmon_name;
|
|
||||||
int ssctl_id;
|
|
||||||
@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
|
|
||||||
- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
|
|
||||||
- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
|
|
||||||
- return PTR_ERR(wcss->wcss_q6_bcr_reset);
|
|
||||||
+ if (desc->bcr_reset_required) {
|
|
||||||
+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
|
|
||||||
+ "wcss_q6_bcr_reset");
|
|
||||||
+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
|
|
||||||
+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
|
|
||||||
+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
|
|
||||||
+ }
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
- wcss->halt_q6 = halt_reg[0];
|
|
||||||
- wcss->halt_wcss = halt_reg[1];
|
|
||||||
- wcss->halt_nc = halt_reg[2];
|
|
||||||
+ wcss->halt_q6 = halt_reg[1];
|
|
||||||
+ wcss->halt_wcss = halt_reg[2];
|
|
||||||
+ wcss->halt_nc = halt_reg[3];
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
@@ -1178,6 +1182,7 @@ static const struct wcss_data wcss_ipq80
|
|
||||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
|
||||||
.aon_reset_required = true,
|
|
||||||
.wcss_q6_reset_required = true,
|
|
||||||
+ .bcr_reset_required = false,
|
|
||||||
.ssr_name = "q6wcss",
|
|
||||||
.ops = &q6v5_wcss_ipq8074_ops,
|
|
||||||
.requires_force_stop = true,
|
|
||||||
@@ -1192,6 +1197,7 @@ static const struct wcss_data wcss_qcs40
|
|
||||||
.version = WCSS_QCS404,
|
|
||||||
.aon_reset_required = false,
|
|
||||||
.wcss_q6_reset_required = false,
|
|
||||||
+ .bcr_reset_required = true,
|
|
||||||
.ssr_name = "mpss",
|
|
||||||
.sysmon_name = "wcnss",
|
|
||||||
.ssctl_id = 0x12,
|
|
||||||
@ -1,138 +0,0 @@
|
|||||||
From 24a47e4619d90266188d26be04c0c29854294f06 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 28 Apr 2022 14:58:16 +0200
|
|
||||||
Subject: [PATCH 118/137] drivers: thermal: tsens: Add support for combined
|
|
||||||
interrupt
|
|
||||||
|
|
||||||
Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
|
|
||||||
signaling both up/low and critical trips.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
Changes in v7:
|
|
||||||
* Rebase to apply on next-20220818
|
|
||||||
|
|
||||||
Changes in v6:
|
|
||||||
* Check critical IRQ handler return, simplify up/low return
|
|
||||||
---
|
|
||||||
drivers/thermal/qcom/tsens-8960.c | 1 +
|
|
||||||
drivers/thermal/qcom/tsens-v0_1.c | 1 +
|
|
||||||
drivers/thermal/qcom/tsens-v1.c | 1 +
|
|
||||||
drivers/thermal/qcom/tsens-v2.c | 1 +
|
|
||||||
drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
|
|
||||||
drivers/thermal/qcom/tsens.h | 2 ++
|
|
||||||
6 files changed, 38 insertions(+), 6 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/thermal/qcom/tsens-8960.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-8960.c
|
|
||||||
@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
|
|
||||||
static struct tsens_features tsens_8960_feat = {
|
|
||||||
.ver_major = VER_0,
|
|
||||||
.crit_int = 0,
|
|
||||||
+ .combo_int = 0,
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 0,
|
|
||||||
.max_sensors = 11,
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v0_1.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v0_1.c
|
|
||||||
@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
|
|
||||||
static struct tsens_features tsens_v0_1_feat = {
|
|
||||||
.ver_major = VER_0_1,
|
|
||||||
.crit_int = 0,
|
|
||||||
+ .combo_int = 0,
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 11,
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v1.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v1.c
|
|
||||||
@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
|
|
||||||
static struct tsens_features tsens_v1_feat = {
|
|
||||||
.ver_major = VER_1_X,
|
|
||||||
.crit_int = 0,
|
|
||||||
+ .combo_int = 0,
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 11,
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
@@ -31,6 +31,7 @@
|
|
||||||
static struct tsens_features tsens_v2_feat = {
|
|
||||||
.ver_major = VER_2_X,
|
|
||||||
.crit_int = 1,
|
|
||||||
+ .combo_int = 0,
|
|
||||||
.adc = 0,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 16,
|
|
||||||
--- a/drivers/thermal/qcom/tsens.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.c
|
|
||||||
@@ -531,6 +531,27 @@ static irqreturn_t tsens_irq_thread(int
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
|
|
||||||
+/**
|
|
||||||
+ * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts
|
|
||||||
+ * @irq: irq number
|
|
||||||
+ * @data: tsens controller private data
|
|
||||||
+ *
|
|
||||||
+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
|
|
||||||
+ * critical handler first and then the up/low one.
|
|
||||||
+ *
|
|
||||||
+ * Return: IRQ_HANDLED
|
|
||||||
+ */
|
|
||||||
+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
|
|
||||||
+{
|
|
||||||
+ irqreturn_t ret;
|
|
||||||
+
|
|
||||||
+ ret = tsens_critical_irq_thread(irq, data);
|
|
||||||
+ if (ret != IRQ_HANDLED)
|
|
||||||
+ return ret;
|
|
||||||
+
|
|
||||||
+ return tsens_irq_thread(irq, data);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static int tsens_set_trips(void *_sensor, int low, int high)
|
|
||||||
{
|
|
||||||
struct tsens_sensor *s = _sensor;
|
|
||||||
@@ -1081,13 +1102,18 @@ static int tsens_register(struct tsens_p
|
|
||||||
tsens_mC_to_hw(priv->sensor, 0));
|
|
||||||
}
|
|
||||||
|
|
||||||
- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
|
|
||||||
- if (ret < 0)
|
|
||||||
- return ret;
|
|
||||||
+ if (priv->feat->combo_int) {
|
|
||||||
+ ret = tsens_register_irq(priv, "combined",
|
|
||||||
+ tsens_combined_irq_thread);
|
|
||||||
+ } else {
|
|
||||||
+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
|
|
||||||
+ if (ret < 0)
|
|
||||||
+ return ret;
|
|
||||||
|
|
||||||
- if (priv->feat->crit_int)
|
|
||||||
- ret = tsens_register_irq(priv, "critical",
|
|
||||||
- tsens_critical_irq_thread);
|
|
||||||
+ if (priv->feat->crit_int)
|
|
||||||
+ ret = tsens_register_irq(priv, "critical",
|
|
||||||
+ tsens_critical_irq_thread);
|
|
||||||
+ }
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
--- a/drivers/thermal/qcom/tsens.h
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.h
|
|
||||||
@@ -495,6 +495,7 @@ enum regfield_ids {
|
|
||||||
* struct tsens_features - Features supported by the IP
|
|
||||||
* @ver_major: Major number of IP version
|
|
||||||
* @crit_int: does the IP support critical interrupts?
|
|
||||||
+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
|
|
||||||
* @adc: do the sensors only output adc code (instead of temperature)?
|
|
||||||
* @srot_split: does the IP neatly splits the register space into SROT and TM,
|
|
||||||
* with SROT only being available to secure boot firmware?
|
|
||||||
@@ -504,6 +505,7 @@ enum regfield_ids {
|
|
||||||
struct tsens_features {
|
|
||||||
unsigned int ver_major;
|
|
||||||
unsigned int crit_int:1;
|
|
||||||
+ unsigned int combo_int:1;
|
|
||||||
unsigned int adc:1;
|
|
||||||
unsigned int srot_split:1;
|
|
||||||
unsigned int has_watchdog:1;
|
|
||||||
@ -1,100 +0,0 @@
|
|||||||
From f035a370b770831f1c4a5d5b5b4387391ee3f71a Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 28 Apr 2022 19:06:29 +0200
|
|
||||||
Subject: [PATCH 119/137] drivers: thermal: tsens: allow configuring min and
|
|
||||||
max trips
|
|
||||||
|
|
||||||
IPQ8074 and IPQ6018 dont support negative trip temperatures and support
|
|
||||||
up to 204 degrees C as the max trip temperature.
|
|
||||||
|
|
||||||
So, instead of always setting the -40 as min and 120 degrees C as max
|
|
||||||
allow it to be configured as part of the features.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
---
|
|
||||||
drivers/thermal/qcom/tsens-8960.c | 2 ++
|
|
||||||
drivers/thermal/qcom/tsens-v0_1.c | 2 ++
|
|
||||||
drivers/thermal/qcom/tsens-v1.c | 2 ++
|
|
||||||
drivers/thermal/qcom/tsens-v2.c | 2 ++
|
|
||||||
drivers/thermal/qcom/tsens.c | 4 ++--
|
|
||||||
drivers/thermal/qcom/tsens.h | 4 ++++
|
|
||||||
6 files changed, 14 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/thermal/qcom/tsens-8960.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-8960.c
|
|
||||||
@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 0,
|
|
||||||
.max_sensors = 11,
|
|
||||||
+ .trip_min_temp = -40000,
|
|
||||||
+ .trip_max_temp = 120000,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct tsens_plat_data data_8960 = {
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v0_1.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v0_1.c
|
|
||||||
@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 11,
|
|
||||||
+ .trip_min_temp = -40000,
|
|
||||||
+ .trip_max_temp = 120000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v1.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v1.c
|
|
||||||
@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
|
|
||||||
.adc = 1,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 11,
|
|
||||||
+ .trip_min_temp = -40000,
|
|
||||||
+ .trip_max_temp = 120000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
|
|
||||||
.adc = 0,
|
|
||||||
.srot_split = 1,
|
|
||||||
.max_sensors = 16,
|
|
||||||
+ .trip_min_temp = -40000,
|
|
||||||
+ .trip_max_temp = 120000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
|
||||||
--- a/drivers/thermal/qcom/tsens.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.c
|
|
||||||
@@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor
|
|
||||||
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
|
|
||||||
hw_id, __func__, low, high);
|
|
||||||
|
|
||||||
- cl_high = clamp_val(high, -40000, 120000);
|
|
||||||
- cl_low = clamp_val(low, -40000, 120000);
|
|
||||||
+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
|
|
||||||
+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
|
|
||||||
|
|
||||||
high_val = tsens_mC_to_hw(s, cl_high);
|
|
||||||
low_val = tsens_mC_to_hw(s, cl_low);
|
|
||||||
--- a/drivers/thermal/qcom/tsens.h
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.h
|
|
||||||
@@ -501,6 +501,8 @@ enum regfield_ids {
|
|
||||||
* with SROT only being available to secure boot firmware?
|
|
||||||
* @has_watchdog: does this IP support watchdog functionality?
|
|
||||||
* @max_sensors: maximum sensors supported by this version of the IP
|
|
||||||
+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
|
|
||||||
+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
|
|
||||||
*/
|
|
||||||
struct tsens_features {
|
|
||||||
unsigned int ver_major;
|
|
||||||
@@ -510,6 +512,8 @@ struct tsens_features {
|
|
||||||
unsigned int srot_split:1;
|
|
||||||
unsigned int has_watchdog:1;
|
|
||||||
unsigned int max_sensors;
|
|
||||||
+ int trip_min_temp;
|
|
||||||
+ int trip_max_temp;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
@ -1,72 +0,0 @@
|
|||||||
From ffc91d0fc802e58f44c7f888f44643847b6dfa3a Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 28 Apr 2022 20:26:13 +0200
|
|
||||||
Subject: [PATCH 120/137] drivers: thermal: tsens: add IPQ8074 support
|
|
||||||
|
|
||||||
Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
|
|
||||||
it only has one IRQ, that is used for up/low as well as critical.
|
|
||||||
It also does not support negative trip temperatures.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
---
|
|
||||||
drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
|
|
||||||
drivers/thermal/qcom/tsens.c | 3 +++
|
|
||||||
drivers/thermal/qcom/tsens.h | 2 +-
|
|
||||||
3 files changed, 21 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
|
||||||
@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
|
|
||||||
.trip_max_temp = 120000,
|
|
||||||
};
|
|
||||||
|
|
||||||
+static struct tsens_features ipq8074_feat = {
|
|
||||||
+ .ver_major = VER_2_X,
|
|
||||||
+ .crit_int = 1,
|
|
||||||
+ .combo_int = 1,
|
|
||||||
+ .adc = 0,
|
|
||||||
+ .srot_split = 1,
|
|
||||||
+ .max_sensors = 16,
|
|
||||||
+ .trip_min_temp = 0,
|
|
||||||
+ .trip_max_temp = 204000,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
|
||||||
/* ----- SROT ------ */
|
|
||||||
/* VERSION */
|
|
||||||
@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
|
|
||||||
.fields = tsens_v2_regfields,
|
|
||||||
};
|
|
||||||
|
|
||||||
+struct tsens_plat_data data_ipq8074 = {
|
|
||||||
+ .ops = &ops_generic_v2,
|
|
||||||
+ .feat = &ipq8074_feat,
|
|
||||||
+ .fields = tsens_v2_regfields,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
/* Kept around for backward compatibility with old msm8996.dtsi */
|
|
||||||
struct tsens_plat_data data_8996 = {
|
|
||||||
.num_sensors = 13,
|
|
||||||
--- a/drivers/thermal/qcom/tsens.c
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.c
|
|
||||||
@@ -991,6 +991,9 @@ static const struct of_device_id tsens_t
|
|
||||||
.compatible = "qcom,ipq8064-tsens",
|
|
||||||
.data = &data_8960,
|
|
||||||
}, {
|
|
||||||
+ .compatible = "qcom,ipq8074-tsens",
|
|
||||||
+ .data = &data_ipq8074,
|
|
||||||
+ }, {
|
|
||||||
.compatible = "qcom,mdm9607-tsens",
|
|
||||||
.data = &data_9607,
|
|
||||||
}, {
|
|
||||||
--- a/drivers/thermal/qcom/tsens.h
|
|
||||||
+++ b/drivers/thermal/qcom/tsens.h
|
|
||||||
@@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916,
|
|
||||||
extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
|
|
||||||
|
|
||||||
/* TSENS v2 targets */
|
|
||||||
-extern struct tsens_plat_data data_8996, data_tsens_v2;
|
|
||||||
+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
|
|
||||||
|
|
||||||
#endif /* __QCOM_TSENS_H__ */
|
|
||||||
@ -1,131 +0,0 @@
|
|||||||
From 1cdc1eaed3ea5b2cab82dee4c72c3cea23356ca6 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 24 Dec 2021 20:33:59 +0100
|
|
||||||
Subject: [PATCH 121/137] arm64: dts: ipq8074: add thermal nodes
|
|
||||||
|
|
||||||
IPQ8074 has a tsens v2.3.0 peripheral which monitors
|
|
||||||
temperatures around the various subsystems on the
|
|
||||||
die.
|
|
||||||
|
|
||||||
So lets add the tsens and thermal zone nodes, passive
|
|
||||||
CPU cooling will come in later patches after CPU frequency
|
|
||||||
scaling is supported.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
Changes in v5:
|
|
||||||
* Rebase to apply on next-20220708
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
|
|
||||||
1 file changed, 96 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -309,6 +309,16 @@
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
+ tsens: thermal-sensor@4a9000 {
|
|
||||||
+ compatible = "qcom,ipq8074-tsens";
|
|
||||||
+ reg = <0x4a9000 0x1000>, /* TM */
|
|
||||||
+ <0x4a8000 0x1000>; /* SROT */
|
|
||||||
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
+ interrupt-names = "combined";
|
|
||||||
+ #qcom,sensors = <16>;
|
|
||||||
+ #thermal-sensor-cells = <1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
cryptobam: dma-controller@704000 {
|
|
||||||
compatible = "qcom,bam-v1.7.0";
|
|
||||||
reg = <0x00704000 0x20000>;
|
|
||||||
@@ -910,4 +920,90 @@
|
|
||||||
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
||||||
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ thermal-zones {
|
|
||||||
+ nss-top-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 4>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ nss0-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 5>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ nss1-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 6>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ wcss-phya0-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 7>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ wcss-phya1-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 8>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ cpu0_thermal: cpu0-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 9>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ cpu1_thermal: cpu1-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 10>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ cpu2_thermal: cpu2-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 11>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ cpu3_thermal: cpu3-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 12>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ cluster_thermal: cluster-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 13>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ wcss-phyb0-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 14>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ wcss-phyb1-thermal {
|
|
||||||
+ polling-delay-passive = <250>;
|
|
||||||
+ polling-delay = <1000>;
|
|
||||||
+
|
|
||||||
+ thermal-sensors = <&tsens 15>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From 0d176e7d075fb7deeb1b137fec56304a402f2f25 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 19 May 2022 14:51:53 +0200
|
|
||||||
Subject: [PATCH 122/137] mfd: qcom-spmi-pmic: add support for PMP8074
|
|
||||||
|
|
||||||
Add support for PMP8074 PMIC which is a companion PMIC for the Qualcomm
|
|
||||||
IPQ8074 SoC-s.
|
|
||||||
|
|
||||||
It shares the same subtype identifier as PM8901.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
drivers/mfd/qcom-spmi-pmic.c | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
+++ b/drivers/mfd/qcom-spmi-pmic.c
|
|
||||||
@@ -76,6 +76,7 @@ static const struct of_device_id pmic_sp
|
|
||||||
{ .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
|
|
||||||
+ { .compatible = "qcom,pmp8074", .data = (void *)PM8901_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
|
|
||||||
{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
|
|
||||||
{ }
|
|
||||||
@ -1,158 +0,0 @@
|
|||||||
From 2abf33c722b4ade9438dc91a652f294ada68a50e Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Wed, 18 May 2022 16:36:42 +0200
|
|
||||||
Subject: [PATCH 123/137] arm64: dts: qcom: add PMP8074 DTSI
|
|
||||||
|
|
||||||
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
|
|
||||||
controlled via SPMI.
|
|
||||||
|
|
||||||
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
|
|
||||||
|
|
||||||
RTC is disabled by default as there is no built-in battery so it will
|
|
||||||
loose time unless board vendor added a battery, so make it optional.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
Changes in v7:
|
|
||||||
* Dual license with BSD-3-Clause
|
|
||||||
* Use "-" instead of underscores in node names
|
|
||||||
|
|
||||||
Changes in v6:
|
|
||||||
* Add RTC and GPIO nodes
|
|
||||||
|
|
||||||
Changes in v5:
|
|
||||||
* Remove #address-cells and #size-cells as they are not required for
|
|
||||||
regulator subnodes
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
|
|
||||||
1 file changed, 125 insertions(+)
|
|
||||||
create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
|
|
||||||
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
|
|
||||||
@@ -0,0 +1,125 @@
|
|
||||||
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
|
|
||||||
+
|
|
||||||
+#include <dt-bindings/spmi/spmi.h>
|
|
||||||
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
|
|
||||||
+
|
|
||||||
+&spmi_bus {
|
|
||||||
+ pmic@0 {
|
|
||||||
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
|
|
||||||
+ reg = <0x0 SPMI_USID>;
|
|
||||||
+ #address-cells = <1>;
|
|
||||||
+ #size-cells = <0>;
|
|
||||||
+
|
|
||||||
+ pmp8074_adc: adc@3100 {
|
|
||||||
+ compatible = "qcom,spmi-adc-rev2";
|
|
||||||
+ reg = <0x3100>;
|
|
||||||
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
|
||||||
+ #address-cells = <1>;
|
|
||||||
+ #size-cells = <0>;
|
|
||||||
+ #io-channel-cells = <1>;
|
|
||||||
+
|
|
||||||
+ ref-gnd@0 {
|
|
||||||
+ reg = <ADC5_REF_GND>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ vref-1p25@1 {
|
|
||||||
+ reg = <ADC5_1P25VREF>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ vref-vadc@2 {
|
|
||||||
+ reg = <ADC5_VREF_VADC>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pmic_die: die-temp@6 {
|
|
||||||
+ reg = <ADC5_DIE_TEMP>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ xo_therm: xo-temp@76 {
|
|
||||||
+ reg = <ADC5_XO_THERM_100K_PU>;
|
|
||||||
+ qcom,ratiometric;
|
|
||||||
+ qcom,hw-settle-time = <200>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pa_therm1: thermistor1@77 {
|
|
||||||
+ reg = <ADC5_AMUX_THM1_100K_PU>;
|
|
||||||
+ qcom,ratiometric;
|
|
||||||
+ qcom,hw-settle-time = <200>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pa_therm2: thermistor2@78 {
|
|
||||||
+ reg = <ADC5_AMUX_THM2_100K_PU>;
|
|
||||||
+ qcom,ratiometric;
|
|
||||||
+ qcom,hw-settle-time = <200>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pa_therm3: thermistor3@79 {
|
|
||||||
+ reg = <ADC5_AMUX_THM3_100K_PU>;
|
|
||||||
+ qcom,ratiometric;
|
|
||||||
+ qcom,hw-settle-time = <200>;
|
|
||||||
+ qcom,pre-scaling = <1 1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ vph-pwr@131 {
|
|
||||||
+ reg = <ADC5_VPH_PWR>;
|
|
||||||
+ qcom,pre-scaling = <1 3>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pmp8074_rtc: rtc@6000 {
|
|
||||||
+ compatible = "qcom,pm8941-rtc";
|
|
||||||
+ reg = <0x6000>;
|
|
||||||
+ reg-names = "rtc", "alarm";
|
|
||||||
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
|
|
||||||
+ allow-set-time;
|
|
||||||
+ status = "disabled";
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pmp8074_gpios: gpio@c000 {
|
|
||||||
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
|
|
||||||
+ reg = <0xc000>;
|
|
||||||
+ gpio-controller;
|
|
||||||
+ #gpio-cells = <2>;
|
|
||||||
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
|
|
||||||
+ interrupt-controller;
|
|
||||||
+ #interrupt-cells = <2>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pmic@1 {
|
|
||||||
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
|
|
||||||
+ reg = <0x1 SPMI_USID>;
|
|
||||||
+
|
|
||||||
+ regulators {
|
|
||||||
+ compatible = "qcom,pmp8074-regulators";
|
|
||||||
+
|
|
||||||
+ s3: s3 {
|
|
||||||
+ regulator-name = "vdd_s3";
|
|
||||||
+ regulator-min-microvolt = <592000>;
|
|
||||||
+ regulator-max-microvolt = <1064000>;
|
|
||||||
+ regulator-always-on;
|
|
||||||
+ regulator-boot-on;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ s4: s4 {
|
|
||||||
+ regulator-name = "vdd_s4";
|
|
||||||
+ regulator-min-microvolt = <712000>;
|
|
||||||
+ regulator-max-microvolt = <992000>;
|
|
||||||
+ regulator-always-on;
|
|
||||||
+ regulator-boot-on;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ l11: l11 {
|
|
||||||
+ regulator-name = "l11";
|
|
||||||
+ regulator-min-microvolt = <1800000>;
|
|
||||||
+ regulator-max-microvolt = <3300000>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+};
|
|
||||||
@ -1,35 +0,0 @@
|
|||||||
From 89f8d101005ee40b3a6c689ba1765403d3617672 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Thu, 19 May 2022 13:34:03 +0200
|
|
||||||
Subject: [PATCH 124/137] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
|
|
||||||
|
|
||||||
Since now we have control over the PMP8074 PMIC providing various system
|
|
||||||
voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
|
|
||||||
the SDHCI VQMMC supply.
|
|
||||||
|
|
||||||
This allows SDHCI controller to switch to 1.8V I/O mode and support high
|
|
||||||
speed modes like HS200 and HS400.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
|
|
||||||
1 file changed, 2 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
|
||||||
@@ -3,6 +3,7 @@
|
|
||||||
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
|
||||||
*/
|
|
||||||
#include "ipq8074.dtsi"
|
|
||||||
+#include "pmp8074.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
|
|
||||||
@@ -82,6 +83,7 @@
|
|
||||||
|
|
||||||
&sdhc_1 {
|
|
||||||
status = "okay";
|
|
||||||
+ vqmmc-supply = <&l11>;
|
|
||||||
};
|
|
||||||
|
|
||||||
&qusb_phy_0 {
|
|
||||||
@ -1,59 +0,0 @@
|
|||||||
From 7b7941649605363d0eebc9fdfb84a13a95522cfb Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 31 Dec 2021 17:56:14 +0100
|
|
||||||
Subject: [PATCH 125/137] arm64: dts: ipq8074: add CPU clock
|
|
||||||
|
|
||||||
Now that CPU clock is exposed and can be controlled, add the necessary
|
|
||||||
properties to the CPU nodes.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
|
|
||||||
1 file changed, 9 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -5,6 +5,7 @@
|
|
||||||
|
|
||||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
||||||
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
|
|
||||||
+#include <dt-bindings/clock/qcom,apss-ipq.h>
|
|
||||||
|
|
||||||
/ {
|
|
||||||
#address-cells = <2>;
|
|
||||||
@@ -38,6 +39,8 @@
|
|
||||||
reg = <0x0>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
enable-method = "psci";
|
|
||||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
+ clock-names = "cpu";
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU1: cpu@1 {
|
|
||||||
@@ -46,6 +49,8 @@
|
|
||||||
enable-method = "psci";
|
|
||||||
reg = <0x1>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
+ clock-names = "cpu";
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU2: cpu@2 {
|
|
||||||
@@ -54,6 +59,8 @@
|
|
||||||
enable-method = "psci";
|
|
||||||
reg = <0x2>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
+ clock-names = "cpu";
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU3: cpu@3 {
|
|
||||||
@@ -62,6 +69,8 @@
|
|
||||||
enable-method = "psci";
|
|
||||||
reg = <0x3>;
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
+ clock-names = "cpu";
|
|
||||||
};
|
|
||||||
|
|
||||||
L2_0: l2-cache {
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From ff74c990c4b671f17d0dfc2c93bae9e23b017472 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 31 Dec 2021 18:42:53 +0100
|
|
||||||
Subject: [PATCH 126/137] arm64: dts: ipq8074: add label to cpus
|
|
||||||
|
|
||||||
Add label to cpus node as that makes it easy to add OPP table in SoC model
|
|
||||||
specific DTSI as IPQ8074 family has differing clocks and voltages based on
|
|
||||||
the specific model.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -29,7 +29,7 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
- cpus {
|
|
||||||
+ cpus: cpus {
|
|
||||||
#address-cells = <0x1>;
|
|
||||||
#size-cells = <0x0>;
|
|
||||||
|
|
||||||
@ -1,48 +0,0 @@
|
|||||||
From 8ddd2743d7bd30165b0c5e1abb6990da15c181d4 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Fri, 31 Dec 2021 20:38:06 +0100
|
|
||||||
Subject: [PATCH 127/137] arm64: dts: ipq8074: add cooling cells to CPU nodes
|
|
||||||
|
|
||||||
Since there is CPU Freq support as well as thermal sensor support
|
|
||||||
now for the IPQ8074, add cooling cells to CPU nodes so that they can
|
|
||||||
be used as cooling devices using CPU Freq.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
|
|
||||||
1 file changed, 4 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -41,6 +41,7 @@
|
|
||||||
enable-method = "psci";
|
|
||||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
clock-names = "cpu";
|
|
||||||
+ #cooling-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU1: cpu@1 {
|
|
||||||
@@ -51,6 +52,7 @@
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
clock-names = "cpu";
|
|
||||||
+ #cooling-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU2: cpu@2 {
|
|
||||||
@@ -61,6 +63,7 @@
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
clock-names = "cpu";
|
|
||||||
+ #cooling-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
CPU3: cpu@3 {
|
|
||||||
@@ -71,6 +74,7 @@
|
|
||||||
next-level-cache = <&L2_0>;
|
|
||||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
||||||
clock-names = "cpu";
|
|
||||||
+ #cooling-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
L2_0: l2-cache {
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
From aa0c4a764d290cceba0a27fd5d81b30b54c5c81f Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:10 +0530
|
|
||||||
Subject: [PATCH 128/137] dt-bindings: clock: qcom: Add reset for WCSSAON
|
|
||||||
|
|
||||||
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
Acked-by: Rob Herring <robh@kernel.org>
|
|
||||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
|
||||||
---
|
|
||||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
@@ -367,6 +367,7 @@
|
|
||||||
#define GCC_PCIE1_AHB_ARES 129
|
|
||||||
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
|
||||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
|
||||||
+#define GCC_WCSSAON_RESET 132
|
|
||||||
|
|
||||||
#define USB0_GDSC 0
|
|
||||||
#define USB1_GDSC 1
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
From 1377fc72a67c8684237fa9b1f246257fd073b2b1 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:11 +0530
|
|
||||||
Subject: [PATCH 129/137] clk: qcom: Add WCSSAON reset
|
|
||||||
|
|
||||||
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/gcc-ipq8074.c | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
@@ -4820,6 +4820,7 @@ static const struct qcom_reset_map gcc_i
|
|
||||||
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
|
|
||||||
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
|
|
||||||
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
|
|
||||||
+ [GCC_WCSSAON_RESET] = { 0x59010, 0 },
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct gdsc *gcc_ipq8074_gdscs[] = {
|
|
||||||
@ -1,47 +0,0 @@
|
|||||||
From d9965ec6f02f71609d837d33d4bae20fb7dec1fd Mon Sep 17 00:00:00 2001
|
|
||||||
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
|
||||||
Date: Fri, 17 Apr 2020 16:37:10 +0530
|
|
||||||
Subject: [PATCH 130/137] remoteproc: wcss: disable auto boot for IPQ8074
|
|
||||||
|
|
||||||
auto boot is disabled for IPQ8074 the wifi driver brings up the wcss.
|
|
||||||
|
|
||||||
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
|
||||||
Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
|
|
||||||
---
|
|
||||||
drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
|
|
||||||
1 file changed, 4 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
|
||||||
@@ -161,6 +161,7 @@ struct wcss_data {
|
|
||||||
const struct rproc_ops *ops;
|
|
||||||
bool requires_force_stop;
|
|
||||||
bool need_mem_protection;
|
|
||||||
+ bool need_auto_boot;
|
|
||||||
};
|
|
||||||
|
|
||||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
|
||||||
@@ -1151,6 +1152,7 @@ static int q6v5_wcss_probe(struct platfo
|
|
||||||
desc->sysmon_name,
|
|
||||||
desc->ssctl_id);
|
|
||||||
|
|
||||||
+ rproc->auto_boot = desc->need_auto_boot;
|
|
||||||
ret = rproc_add(rproc);
|
|
||||||
if (ret)
|
|
||||||
goto free_rproc;
|
|
||||||
@@ -1187,6 +1189,7 @@ static const struct wcss_data wcss_ipq80
|
|
||||||
.ops = &q6v5_wcss_ipq8074_ops,
|
|
||||||
.requires_force_stop = true,
|
|
||||||
.need_mem_protection = true,
|
|
||||||
+ .need_auto_boot = false,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct wcss_data wcss_qcs404_res_init = {
|
|
||||||
@@ -1203,6 +1206,7 @@ static const struct wcss_data wcss_qcs40
|
|
||||||
.ssctl_id = 0x12,
|
|
||||||
.ops = &q6v5_wcss_qcs404_ops,
|
|
||||||
.requires_force_stop = false,
|
|
||||||
+ .need_auto_boot = true,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct of_device_id q6v5_wcss_of_match[] = {
|
|
||||||
@ -1,120 +0,0 @@
|
|||||||
From 45dfcd1ecf0910e4e45fec5f26f2fc80a47732f9 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Date: Sat, 30 Jan 2021 10:50:13 +0530
|
|
||||||
Subject: [PATCH 131/137] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
|
|
||||||
|
|
||||||
Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
|
|
||||||
Also enables smp2p and mailboxes required for IPC.
|
|
||||||
|
|
||||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
|
||||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
|
||||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
|
|
||||||
1 file changed, 81 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -153,6 +153,32 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
+ wcss: smp2p-wcss {
|
|
||||||
+ compatible = "qcom,smp2p";
|
|
||||||
+ qcom,smem = <435>, <428>;
|
|
||||||
+
|
|
||||||
+ interrupt-parent = <&intc>;
|
|
||||||
+ interrupts = <0 322 1>;
|
|
||||||
+
|
|
||||||
+ mboxes = <&apcs_glb 9>;
|
|
||||||
+
|
|
||||||
+ qcom,local-pid = <0>;
|
|
||||||
+ qcom,remote-pid = <1>;
|
|
||||||
+
|
|
||||||
+ wcss_smp2p_out: master-kernel {
|
|
||||||
+ qcom,entry-name = "master-kernel";
|
|
||||||
+ qcom,smp2p-feature-ssr-ack;
|
|
||||||
+ #qcom,smem-state-cells = <1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ wcss_smp2p_in: slave-kernel {
|
|
||||||
+ qcom,entry-name = "slave-kernel";
|
|
||||||
+
|
|
||||||
+ interrupt-controller;
|
|
||||||
+ #interrupt-cells = <2>;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
soc: soc {
|
|
||||||
#address-cells = <0x1>;
|
|
||||||
#size-cells = <0x1>;
|
|
||||||
@@ -420,6 +446,11 @@
|
|
||||||
#hwlock-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ tcsr_q6: syscon@1945000 {
|
|
||||||
+ compatible = "syscon";
|
|
||||||
+ reg = <0x01945000 0xe000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
spmi_bus: spmi@200f000 {
|
|
||||||
compatible = "qcom,spmi-pmic-arb";
|
|
||||||
reg = <0x0200f000 0x001000>,
|
|
||||||
@@ -924,6 +955,56 @@
|
|
||||||
"axi_s_sticky";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ q6v5_wcss: q6v5_wcss@cd00000 {
|
|
||||||
+ compatible = "qcom,ipq8074-wcss-pil";
|
|
||||||
+ reg = <0x0cd00000 0x4040>,
|
|
||||||
+ <0x004ab000 0x20>;
|
|
||||||
+ reg-names = "qdsp6",
|
|
||||||
+ "rmb";
|
|
||||||
+ qca,auto-restart;
|
|
||||||
+ qca,extended-intc;
|
|
||||||
+ interrupts-extended = <&intc 0 325 1>,
|
|
||||||
+ <&wcss_smp2p_in 0 0>,
|
|
||||||
+ <&wcss_smp2p_in 1 0>,
|
|
||||||
+ <&wcss_smp2p_in 2 0>,
|
|
||||||
+ <&wcss_smp2p_in 3 0>;
|
|
||||||
+ interrupt-names = "wdog",
|
|
||||||
+ "fatal",
|
|
||||||
+ "ready",
|
|
||||||
+ "handover",
|
|
||||||
+ "stop-ack";
|
|
||||||
+
|
|
||||||
+ resets = <&gcc GCC_WCSSAON_RESET>,
|
|
||||||
+ <&gcc GCC_WCSS_BCR>,
|
|
||||||
+ <&gcc GCC_WCSS_Q6_BCR>;
|
|
||||||
+
|
|
||||||
+ reset-names = "wcss_aon_reset",
|
|
||||||
+ "wcss_reset",
|
|
||||||
+ "wcss_q6_reset";
|
|
||||||
+
|
|
||||||
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
||||||
+ clock-names = "prng";
|
|
||||||
+
|
|
||||||
+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
|
|
||||||
+
|
|
||||||
+ qcom,smem-states = <&wcss_smp2p_out 0>,
|
|
||||||
+ <&wcss_smp2p_out 1>;
|
|
||||||
+ qcom,smem-state-names = "shutdown",
|
|
||||||
+ "stop";
|
|
||||||
+
|
|
||||||
+ memory-region = <&q6_region>;
|
|
||||||
+
|
|
||||||
+ glink-edge {
|
|
||||||
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
|
|
||||||
+ qcom,remote-pid = <1>;
|
|
||||||
+ mboxes = <&apcs_glb 8>;
|
|
||||||
+
|
|
||||||
+ rpm_requests {
|
|
||||||
+ qcom,glink-channels = "IPCRTR";
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
@ -1,135 +0,0 @@
|
|||||||
From d8e8adbf99ed4a3b50f87a665661a8cad84918ff Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Tue, 21 Dec 2021 14:49:36 +0100
|
|
||||||
Subject: [PATCH 132/137] arm64: dts: ipq8074: Add WLAN node
|
|
||||||
|
|
||||||
IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
|
|
||||||
by the ath11k.
|
|
||||||
|
|
||||||
Add the required DT node to enable the built-in radios.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
|
|
||||||
1 file changed, 111 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -1005,6 +1005,117 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ wifi: wifi@c0000000 {
|
|
||||||
+ compatible = "qcom,ipq8074-wifi";
|
|
||||||
+ reg = <0xc000000 0x2000000>;
|
|
||||||
+
|
|
||||||
+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
|
|
||||||
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
|
||||||
+
|
|
||||||
+ interrupt-names = "misc-pulse1",
|
|
||||||
+ "misc-latch",
|
|
||||||
+ "sw-exception",
|
|
||||||
+ "ce0",
|
|
||||||
+ "ce1",
|
|
||||||
+ "ce2",
|
|
||||||
+ "ce3",
|
|
||||||
+ "ce4",
|
|
||||||
+ "ce5",
|
|
||||||
+ "ce6",
|
|
||||||
+ "ce7",
|
|
||||||
+ "ce8",
|
|
||||||
+ "ce9",
|
|
||||||
+ "ce10",
|
|
||||||
+ "ce11",
|
|
||||||
+ "host2wbm-desc-feed",
|
|
||||||
+ "host2reo-re-injection",
|
|
||||||
+ "host2reo-command",
|
|
||||||
+ "host2rxdma-monitor-ring3",
|
|
||||||
+ "host2rxdma-monitor-ring2",
|
|
||||||
+ "host2rxdma-monitor-ring1",
|
|
||||||
+ "reo2ost-exception",
|
|
||||||
+ "wbm2host-rx-release",
|
|
||||||
+ "reo2host-status",
|
|
||||||
+ "reo2host-destination-ring4",
|
|
||||||
+ "reo2host-destination-ring3",
|
|
||||||
+ "reo2host-destination-ring2",
|
|
||||||
+ "reo2host-destination-ring1",
|
|
||||||
+ "rxdma2host-monitor-destination-mac3",
|
|
||||||
+ "rxdma2host-monitor-destination-mac2",
|
|
||||||
+ "rxdma2host-monitor-destination-mac1",
|
|
||||||
+ "ppdu-end-interrupts-mac3",
|
|
||||||
+ "ppdu-end-interrupts-mac2",
|
|
||||||
+ "ppdu-end-interrupts-mac1",
|
|
||||||
+ "rxdma2host-monitor-status-ring-mac3",
|
|
||||||
+ "rxdma2host-monitor-status-ring-mac2",
|
|
||||||
+ "rxdma2host-monitor-status-ring-mac1",
|
|
||||||
+ "host2rxdma-host-buf-ring-mac3",
|
|
||||||
+ "host2rxdma-host-buf-ring-mac2",
|
|
||||||
+ "host2rxdma-host-buf-ring-mac1",
|
|
||||||
+ "rxdma2host-destination-ring-mac3",
|
|
||||||
+ "rxdma2host-destination-ring-mac2",
|
|
||||||
+ "rxdma2host-destination-ring-mac1",
|
|
||||||
+ "host2tcl-input-ring4",
|
|
||||||
+ "host2tcl-input-ring3",
|
|
||||||
+ "host2tcl-input-ring2",
|
|
||||||
+ "host2tcl-input-ring1",
|
|
||||||
+ "wbm2host-tx-completions-ring3",
|
|
||||||
+ "wbm2host-tx-completions-ring2",
|
|
||||||
+ "wbm2host-tx-completions-ring1",
|
|
||||||
+ "tcl2host-status-ring";
|
|
||||||
+ qcom,rproc = <&q6v5_wcss>;
|
|
||||||
+ status = "disabled";
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
@ -1,63 +0,0 @@
|
|||||||
From ad08de7cb6308521b4a80c427a7cbec84742a729 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Sat, 1 Jan 2022 18:15:03 +0100
|
|
||||||
Subject: [PATCH 134/137] clk: qcom: ipq8074: add missing networking resets
|
|
||||||
|
|
||||||
Downstream QCA 5.4 kernel defines networking resets which are not present
|
|
||||||
in the mainline kernel but are required for the networking drivers.
|
|
||||||
|
|
||||||
So, port the downstream resets and avoid using magic values for mask,
|
|
||||||
construct mask for resets which require multiple bits to be set/cleared.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
|
|
||||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
|
|
||||||
2 files changed, 28 insertions(+)
|
|
||||||
|
|
||||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
|
||||||
@@ -4821,6 +4821,20 @@ static const struct qcom_reset_map gcc_i
|
|
||||||
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
|
|
||||||
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
|
|
||||||
[GCC_WCSSAON_RESET] = { 0x59010, 0 },
|
|
||||||
+ [GCC_PPE_FULL_RESET] = { 0x68014, 0, GENMASK(19, 16) },
|
|
||||||
+ [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0, GENMASK(13, 4) | BIT(1) },
|
|
||||||
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
|
|
||||||
+ [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0, GENMASK(5, 4) | BIT(1) },
|
|
||||||
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
|
|
||||||
+ [GCC_UNIPHY2_SOFT_RESET] = { 0x56204, 0, GENMASK(5, 4) | BIT(1) },
|
|
||||||
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
|
|
||||||
+ [GCC_EDMA_HW_RESET] = { 0x68014, 0, GENMASK(21, 20) },
|
|
||||||
+ [GCC_NSSPORT1_RESET] = { 0x68014, 0, BIT(24) | GENMASK(1, 0) },
|
|
||||||
+ [GCC_NSSPORT2_RESET] = { 0x68014, 0, BIT(25) | GENMASK(3, 2) },
|
|
||||||
+ [GCC_NSSPORT3_RESET] = { 0x68014, 0, BIT(26) | GENMASK(5, 4) },
|
|
||||||
+ [GCC_NSSPORT4_RESET] = { 0x68014, 0, BIT(27) | GENMASK(9, 8) },
|
|
||||||
+ [GCC_NSSPORT5_RESET] = { 0x68014, 0, BIT(28) | GENMASK(11, 10) },
|
|
||||||
+ [GCC_NSSPORT6_RESET] = { 0x68014, 0, BIT(29) | GENMASK(13, 12) },
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct gdsc *gcc_ipq8074_gdscs[] = {
|
|
||||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
|
||||||
@@ -368,6 +368,20 @@
|
|
||||||
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
|
||||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
|
||||||
#define GCC_WCSSAON_RESET 132
|
|
||||||
+#define GCC_PPE_FULL_RESET 133
|
|
||||||
+#define GCC_UNIPHY0_SOFT_RESET 134
|
|
||||||
+#define GCC_UNIPHY0_XPCS_RESET 135
|
|
||||||
+#define GCC_UNIPHY1_SOFT_RESET 136
|
|
||||||
+#define GCC_UNIPHY1_XPCS_RESET 137
|
|
||||||
+#define GCC_UNIPHY2_SOFT_RESET 138
|
|
||||||
+#define GCC_UNIPHY2_XPCS_RESET 139
|
|
||||||
+#define GCC_EDMA_HW_RESET 140
|
|
||||||
+#define GCC_NSSPORT1_RESET 141
|
|
||||||
+#define GCC_NSSPORT2_RESET 142
|
|
||||||
+#define GCC_NSSPORT3_RESET 143
|
|
||||||
+#define GCC_NSSPORT4_RESET 144
|
|
||||||
+#define GCC_NSSPORT5_RESET 145
|
|
||||||
+#define GCC_NSSPORT6_RESET 146
|
|
||||||
|
|
||||||
#define USB0_GDSC 0
|
|
||||||
#define USB1_GDSC 1
|
|
||||||
@ -1,24 +0,0 @@
|
|||||||
From c7b874696964bab2de6b08a44168c42a556a077c Mon Sep 17 00:00:00 2001
|
|
||||||
From: Robert Marko <robimarko@gmail.com>
|
|
||||||
Date: Wed, 9 Feb 2022 23:13:26 +0100
|
|
||||||
Subject: [PATCH 135/137] arm64: dts: ipq8074: add label to clocks
|
|
||||||
|
|
||||||
Add label to clocks node as that makes it easy to add the NSS fixed
|
|
||||||
clocks that are required in their DTSI.
|
|
||||||
|
|
||||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
||||||
@@ -15,7 +15,7 @@
|
|
||||||
compatible = "qcom,ipq8074";
|
|
||||||
interrupt-parent = <&intc>;
|
|
||||||
|
|
||||||
- clocks {
|
|
||||||
+ clocks: clocks {
|
|
||||||
sleep_clk: sleep_clk {
|
|
||||||
compatible = "fixed-clock";
|
|
||||||
clock-frequency = <32768>;
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,110 +0,0 @@
|
|||||||
From 20bb9e3dd2e4896f1bbaecd952b48bdc3200fc97 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Kathiravan T <kathirav@codeaurora.org>
|
|
||||||
Date: Tue, 31 Aug 2021 08:57:32 +0300
|
|
||||||
Subject: [PATCH] arm64: dts: qcom: ipq6018: add usb3 DT description
|
|
||||||
|
|
||||||
Based on downstream codeaurora code.
|
|
||||||
|
|
||||||
Tested (USB2 only) on IPQ6010 based hardware.
|
|
||||||
|
|
||||||
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
|
|
||||||
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
|
|
||||||
[bjorn: Changed dwc3 node name to usb, per binding]
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389452.git.baruch@tkos.co.il
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 83 +++++++++++++++++++++++++++
|
|
||||||
1 file changed, 83 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
@@ -664,6 +664,89 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
+ ssphy_0: ssphy@78000 {
|
|
||||||
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
|
|
||||||
+ reg = <0x0 0x78000 0x0 0x1C4>;
|
|
||||||
+ #address-cells = <2>;
|
|
||||||
+ #size-cells = <2>;
|
|
||||||
+ #clock-cells = <1>;
|
|
||||||
+ ranges;
|
|
||||||
+
|
|
||||||
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
|
|
||||||
+ clock-names = "aux", "cfg_ahb", "ref";
|
|
||||||
+
|
|
||||||
+ resets = <&gcc GCC_USB0_PHY_BCR>,
|
|
||||||
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
|
|
||||||
+ reset-names = "phy","common";
|
|
||||||
+ status = "disabled";
|
|
||||||
+
|
|
||||||
+ usb0_ssphy: lane@78200 {
|
|
||||||
+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
|
|
||||||
+ <0x0 0x00078400 0x0 0x200>, /* Rx */
|
|
||||||
+ <0x0 0x00078800 0x0 0x1F8>, /* PCS */
|
|
||||||
+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
|
|
||||||
+ #phy-cells = <0>;
|
|
||||||
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
|
|
||||||
+ clock-names = "pipe0";
|
|
||||||
+ clock-output-names = "gcc_usb0_pipe_clk_src";
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ qusb_phy_0: qusb@79000 {
|
|
||||||
+ compatible = "qcom,ipq6018-qusb2-phy";
|
|
||||||
+ reg = <0x0 0x079000 0x0 0x180>;
|
|
||||||
+ #phy-cells = <0>;
|
|
||||||
+
|
|
||||||
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
|
|
||||||
+ <&xo>;
|
|
||||||
+ clock-names = "cfg_ahb", "ref";
|
|
||||||
+
|
|
||||||
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
|
|
||||||
+ status = "disabled";
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ usb3: usb3@8A00000 {
|
|
||||||
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
|
|
||||||
+ reg = <0x0 0x8AF8800 0x0 0x400>;
|
|
||||||
+ #address-cells = <2>;
|
|
||||||
+ #size-cells = <2>;
|
|
||||||
+ ranges;
|
|
||||||
+
|
|
||||||
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_MASTER_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_SLEEP_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
||||||
+ clock-names = "sys_noc_axi",
|
|
||||||
+ "master",
|
|
||||||
+ "sleep",
|
|
||||||
+ "mock_utmi";
|
|
||||||
+
|
|
||||||
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_MASTER_CLK>,
|
|
||||||
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
||||||
+ assigned-clock-rates = <133330000>,
|
|
||||||
+ <133330000>,
|
|
||||||
+ <20000000>;
|
|
||||||
+
|
|
||||||
+ resets = <&gcc GCC_USB0_BCR>;
|
|
||||||
+ status = "disabled";
|
|
||||||
+
|
|
||||||
+ dwc_0: usb@8A00000 {
|
|
||||||
+ compatible = "snps,dwc3";
|
|
||||||
+ reg = <0x0 0x8A00000 0x0 0xcd00>;
|
|
||||||
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
|
|
||||||
+ phy-names = "usb2-phy", "usb3-phy";
|
|
||||||
+ tx-fifo-resize;
|
|
||||||
+ snps,is-utmi-l1-suspend;
|
|
||||||
+ snps,hird-threshold = /bits/ 8 <0x0>;
|
|
||||||
+ snps,dis_u2_susphy_quirk;
|
|
||||||
+ snps,dis_u3_susphy_quirk;
|
|
||||||
+ snps,ref-clock-period-ns = <0x32>;
|
|
||||||
+ dr_mode = "host";
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
wcss: wcss-smp2p {
|
|
||||||
@ -1,42 +0,0 @@
|
|||||||
From 62b177fcdfdfda69f3a0cb740f8b3ac24f95e8c1 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Date: Wed, 13 Oct 2021 16:25:23 +0530
|
|
||||||
Subject: [PATCH] arm64: dts: qcom: ipq6018: Remove unused
|
|
||||||
'qcom,config-pipe-trust-reg' property
|
|
||||||
|
|
||||||
'qcom,config-pipe-trust-reg' property doesn't seem to be
|
|
||||||
used by the qcom, bam_dma driver, so remove the same
|
|
||||||
from 'ipq6018' dts.
|
|
||||||
|
|
||||||
This is a preparatory patch for subsequent patch in
|
|
||||||
this series which converts the qcom_bam_dma device-tree
|
|
||||||
binding into YAML format.
|
|
||||||
|
|
||||||
Without this change, 'make dtbs_check' leads to the following
|
|
||||||
error:
|
|
||||||
$ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml:
|
|
||||||
dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match
|
|
||||||
any of the regexes: 'pinctrl-[0-9]+'
|
|
||||||
|
|
||||||
Fix the same.
|
|
||||||
|
|
||||||
Cc: Thara Gopinath <thara.gopinath@linaro.org>
|
|
||||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Cc: Rob Herring <robh+dt@kernel.org>
|
|
||||||
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211013105541.68045-3-bhupesh.sharma@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 -
|
|
||||||
1 file changed, 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
@@ -195,7 +195,6 @@
|
|
||||||
#dma-cells = <1>;
|
|
||||||
qcom,ee = <1>;
|
|
||||||
qcom,controlled-remotely;
|
|
||||||
- qcom,config-pipe-trust-reg = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
crypto: crypto@73a000 {
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
From 82f07cbd408993551bd3e4cf51da1bb822f61f26 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Date: Wed, 13 Oct 2021 16:25:24 +0530
|
|
||||||
Subject: [PATCH] arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property
|
|
||||||
from dma-controller node
|
|
||||||
|
|
||||||
'iface_clk' clock is not used by the
|
|
||||||
qcom, bam_dma driver, so remove the same from 'ipq6018' dts.
|
|
||||||
|
|
||||||
This is a preparatory patch for subsequent patch in
|
|
||||||
this series which converts the qcom_bam_dma device-tree
|
|
||||||
binding into YAML format.
|
|
||||||
|
|
||||||
Without this change, 'make dtbs_check' leads to the following
|
|
||||||
error:
|
|
||||||
$ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml:
|
|
||||||
dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk']
|
|
||||||
is too long
|
|
||||||
|
|
||||||
Fix the same.
|
|
||||||
|
|
||||||
Cc: Thara Gopinath <thara.gopinath@linaro.org>
|
|
||||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Cc: Rob Herring <robh+dt@kernel.org>
|
|
||||||
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/20211013105541.68045-4-bhupesh.sharma@linaro.org
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 ++---
|
|
||||||
1 file changed, 2 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
@@ -341,9 +341,8 @@
|
|
||||||
compatible = "qcom,bam-v1.7.0";
|
|
||||||
reg = <0x0 0x07984000 0x0 0x1a000>;
|
|
||||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
- clocks = <&gcc GCC_QPIC_CLK>,
|
|
||||||
- <&gcc GCC_QPIC_AHB_CLK>;
|
|
||||||
- clock-names = "iface_clk", "bam_clk";
|
|
||||||
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
|
||||||
+ clock-names = "bam_clk";
|
|
||||||
#dma-cells = <1>;
|
|
||||||
qcom,ee = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
From e3e8a472429923d1c430bf388e9e3df1d9cc63a7 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
Date: Mon, 27 Dec 2021 08:46:03 +0200
|
|
||||||
Subject: [PATCH] arm64: dts: qcom: ipq6018: add pcie max-link-speed
|
|
||||||
|
|
||||||
Add the generic 'max-link-speed' property to describe the IPQ6018 PCIe
|
|
||||||
link generation limit. This allows the generic dwc code to configure the
|
|
||||||
link speed correctly.
|
|
||||||
|
|
||||||
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
|
||||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
||||||
Link: https://lore.kernel.org/r/fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587131.git.baruch@tkos.co.il
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
||||||
@@ -420,6 +420,7 @@
|
|
||||||
linux,pci-domain = <0>;
|
|
||||||
bus-range = <0x00 0xff>;
|
|
||||||
num-lanes = <1>;
|
|
||||||
+ max-link-speed = <3>;
|
|
||||||
#address-cells = <3>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user