mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 14:23:38 +00:00
c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
47 lines
1.7 KiB
Diff
47 lines
1.7 KiB
Diff
From 55299da8c17f23249497ee8868a5a268c6e3fbcc Mon Sep 17 00:00:00 2001
|
|
From: Baruch Siach <baruch.siach@siklu.com>
|
|
Date: Mon, 7 Feb 2022 16:51:25 +0200
|
|
Subject: [PATCH 43/44] PCI: qcom: Define slot capabilities using
|
|
PCI_EXP_SLTCAP_*
|
|
|
|
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
|
|
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
|
|
describe its meaning.
|
|
|
|
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
|
---
|
|
drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
|
|
1 file changed, 13 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
|
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
|
@@ -69,7 +69,18 @@
|
|
#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
|
#define CFG_BRIDGE_SB_INIT BIT(0)
|
|
|
|
-#define PCIE_CAP_LINK1_VAL 0x2FD7F
|
|
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
|
|
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
|
|
+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
|
|
+ PCI_EXP_SLTCAP_PCP | \
|
|
+ PCI_EXP_SLTCAP_MRLSP | \
|
|
+ PCI_EXP_SLTCAP_AIP | \
|
|
+ PCI_EXP_SLTCAP_PIP | \
|
|
+ PCI_EXP_SLTCAP_HPS | \
|
|
+ PCI_EXP_SLTCAP_HPC | \
|
|
+ PCI_EXP_SLTCAP_EIP | \
|
|
+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
|
|
+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
|
|
|
|
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
|
|
|
|
@@ -1125,7 +1136,7 @@ static int qcom_pcie_post_init_2_3_3(str
|
|
|
|
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
|
|
writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
|
|
- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
|
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
|
|
|
val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
|
|
val &= ~PCI_EXP_LNKCAP_ASPMS;
|