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qualcommax: sync upstream label changes

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This commit is contained in:
coolsnowwolf 2025-05-18 23:16:01 +08:00
parent 6c60a311fb
commit 8a383a318f
9 changed files with 1778 additions and 1223 deletions
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48
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
View File

@ -3,22 +3,22 @@
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi" #include "ipq8074-cpr-regulator.dtsi"
&CPU0 { &cpu0 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU1 { &cpu1 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU2 { &cpu2 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU3 { &cpu3 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
@ -35,10 +35,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu0_passive>; trip = <&cpu0_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -55,10 +55,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu1_passive>; trip = <&cpu1_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -75,10 +75,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu2_passive>; trip = <&cpu2_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -95,10 +95,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu3_passive>; trip = <&cpu3_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -115,10 +115,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cluster_passive>; trip = <&cluster_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };

88
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
View File

@ -3,22 +3,22 @@
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi" #include "ipq8074-cpr-regulator.dtsi"
&CPU0 { &cpu0 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU1 { &cpu1 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU2 { &cpu2 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
&CPU3 { &cpu3 {
cpu-supply = <&apc_vreg>; cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>; voltage-tolerance = <1>;
}; };
@ -41,17 +41,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu0_passive_low>; trip = <&cpu0_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cpu0_passive_high>; trip = <&cpu0_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -74,17 +74,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu1_passive_low>; trip = <&cpu1_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cpu1_passive_high>; trip = <&cpu1_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -107,17 +107,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu2_passive_low>; trip = <&cpu2_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cpu2_passive_high>; trip = <&cpu2_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -140,17 +140,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu3_passive_low>; trip = <&cpu3_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cpu3_passive_high>; trip = <&cpu3_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
@ -173,17 +173,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cluster_passive_low>; trip = <&cluster_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cluster_passive_high>; trip = <&cluster_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };

4
target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq50xx-add-dtsi.patch → target/linux/qualcommax/patches-6.1/0030-v6.6-arm64-dts-Add-ipq5018-SoC-and-rdp432-c2-board-suppo.patch
View File

@ -1,6 +1,6 @@
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -0,0 +1,1125 @@ @@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/* +/*
+ * IPQ5018 SoC device tree source + * IPQ5018 SoC device tree source
@ -72,13 +72,11 @@
+ compatible = "operating-points-v2"; + compatible = "operating-points-v2";
+ opp-shared; + opp-shared;
+ +
+ /*
+ opp-800000000 { + opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>; + opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>; + opp-microvolt = <1100000>;
+ clock-latency-ns = <200000>; + clock-latency-ns = <200000>;
+ }; + };
+ */
+ +
+ opp-1008000000 { + opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>; + opp-hz = /bits/ 64 <1008000000>;

176
target/linux/qualcommax/patches-6.1/0055-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch Normal file
View File

@ -0,0 +1,176 @@
From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 22 Oct 2024 17:47:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
5 files changed, 61 insertions(+), 61 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -31,27 +31,27 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -34,12 +34,12 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -47,12 +47,12 @@
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -60,12 +60,12 @@
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -73,12 +73,12 @@
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -86,7 +86,7 @@
#cooling-cells = <2>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,39 +32,39 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

16
target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch
View File

@ -23,37 +23,37 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
#address-cells = <2>; #address-cells = <2>;
@@ -38,6 +39,8 @@ @@ -38,6 +39,8 @@
reg = <0x0>; reg = <0x0>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
enable-method = "psci"; enable-method = "psci";
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU1: cpu@1 { cpu1: cpu@1 {
@@ -46,6 +49,8 @@ @@ -46,6 +49,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x1>; reg = <0x1>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU2: cpu@2 { cpu2: cpu@2 {
@@ -54,6 +59,8 @@ @@ -54,6 +59,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x2>; reg = <0x2>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU3: cpu@3 { cpu3: cpu@3 {
@@ -62,6 +69,8 @@ @@ -62,6 +69,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x3>; reg = <0x3>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
L2_0: l2-cache { l2_0: l2-cache {

381
target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch Normal file
View File

@ -0,0 +1,381 @@
From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 22 Oct 2024 17:47:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
5 files changed, 61 insertions(+), 61 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -31,27 +31,27 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -30,47 +30,47 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -34,12 +34,12 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -47,12 +47,12 @@
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -60,12 +60,12 @@
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -73,12 +73,12 @@
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -86,7 +86,7 @@
#cooling-cells = <2>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -993,10 +993,10 @@
cooling-maps {
map0 {
trip = <&cpu_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,39 +32,39 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -33,12 +33,12 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -46,12 +46,12 @@
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -59,12 +59,12 @@
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x2>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -72,12 +72,12 @@
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x3>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -85,7 +85,7 @@
#cooling-cells = <2>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -845,10 +845,10 @@
cooling-maps {
map0 {
trip = <&cpu0_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -875,10 +875,10 @@
cooling-maps {
map0 {
trip = <&cpu1_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -905,10 +905,10 @@
cooling-maps {
map0 {
trip = <&cpu2_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -935,10 +935,10 @@
cooling-maps {
map0 {
trip = <&cpu3_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

16
target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch
View File

@ -23,37 +23,37 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
#address-cells = <2>; #address-cells = <2>;
@@ -38,6 +39,8 @@ @@ -38,6 +39,8 @@
reg = <0x0>; reg = <0x0>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
enable-method = "psci"; enable-method = "psci";
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU1: cpu@1 { cpu1: cpu@1 {
@@ -46,6 +49,8 @@ @@ -46,6 +49,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x1>; reg = <0x1>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU2: cpu@2 { cpu2: cpu@2 {
@@ -54,6 +59,8 @@ @@ -54,6 +59,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x2>; reg = <0x2>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
CPU3: cpu@3 { cpu3: cpu@3 {
@@ -62,6 +69,8 @@ @@ -62,6 +69,8 @@
enable-method = "psci"; enable-method = "psci";
reg = <0x3>; reg = <0x3>;
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu"; + clock-names = "cpu";
}; };
L2_0: l2-cache { l2_0: l2-cache {

14
target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch
View File

@ -21,28 +21,28 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ #cooling-cells = <2>; + #cooling-cells = <2>;
}; };
CPU1: cpu@1 { cpu1: cpu@1 {
@@ -51,6 +52,7 @@ @@ -51,6 +52,7 @@
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
+ #cooling-cells = <2>; + #cooling-cells = <2>;
}; };
CPU2: cpu@2 { cpu2: cpu@2 {
@@ -61,6 +63,7 @@ @@ -61,6 +63,7 @@
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
+ #cooling-cells = <2>; + #cooling-cells = <2>;
}; };
CPU3: cpu@3 { cpu3: cpu@3 {
@@ -71,6 +74,7 @@ @@ -71,6 +74,7 @@
next-level-cache = <&L2_0>; next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
+ #cooling-cells = <2>; + #cooling-cells = <2>;
}; };
L2_0: l2-cache { l2_0: l2-cache {

8
target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>; + operating-points-v2 = <&cpu_opp_table>;
}; };
CPU1: cpu@1 { cpu1: cpu@1 {
@@ -53,6 +54,7 @@ @@ -53,6 +54,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
@ -28,7 +28,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>; + operating-points-v2 = <&cpu_opp_table>;
}; };
CPU2: cpu@2 { cpu2: cpu@2 {
@@ -64,6 +66,7 @@ @@ -64,6 +66,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
@ -36,7 +36,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>; + operating-points-v2 = <&cpu_opp_table>;
}; };
CPU3: cpu@3 { cpu3: cpu@3 {
@@ -75,6 +78,7 @@ @@ -75,6 +78,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu"; clock-names = "cpu";
@ -44,7 +44,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>; + operating-points-v2 = <&cpu_opp_table>;
}; };
L2_0: l2-cache { l2_0: l2-cache {
@@ -84,6 +88,54 @@ @@ -84,6 +88,54 @@
}; };
}; };