diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi index 6cf8bad5b..a17279f13 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi @@ -3,22 +3,22 @@ #include #include "ipq8074-cpr-regulator.dtsi" -&CPU0 { +&cpu0 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU1 { +&cpu1 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU2 { +&cpu2 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU3 { +&cpu3 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; @@ -35,10 +35,10 @@ cooling-maps { map0 { trip = <&cpu0_passive>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -55,10 +55,10 @@ cooling-maps { map0 { trip = <&cpu1_passive>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -75,10 +75,10 @@ cooling-maps { map0 { trip = <&cpu2_passive>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -95,10 +95,10 @@ cooling-maps { map0 { trip = <&cpu3_passive>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -115,10 +115,10 @@ cooling-maps { map0 { trip = <&cluster_passive>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi index b7d746c44..ec8f5d0aa 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi @@ -3,22 +3,22 @@ #include #include "ipq8074-cpr-regulator.dtsi" -&CPU0 { +&cpu0 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU1 { +&cpu1 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU2 { +&cpu2 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; -&CPU3 { +&cpu3 { cpu-supply = <&apc_vreg>; voltage-tolerance = <1>; }; @@ -41,17 +41,17 @@ cooling-maps { map0 { trip = <&cpu0_passive_low>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu0_passive_high>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -74,17 +74,17 @@ cooling-maps { map0 { trip = <&cpu1_passive_low>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu1_passive_high>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -107,17 +107,17 @@ cooling-maps { map0 { trip = <&cpu2_passive_low>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu2_passive_high>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -140,17 +140,17 @@ cooling-maps { map0 { trip = <&cpu3_passive_low>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu3_passive_high>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -173,17 +173,17 @@ cooling-maps { map0 { trip = <&cluster_passive_low>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cluster_passive_high>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq50xx-add-dtsi.patch b/target/linux/qualcommax/patches-6.1/0030-v6.6-arm64-dts-Add-ipq5018-SoC-and-rdp432-c2-board-suppo.patch similarity index 96% rename from target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq50xx-add-dtsi.patch rename to target/linux/qualcommax/patches-6.1/0030-v6.6-arm64-dts-Add-ipq5018-SoC-and-rdp432-c2-board-suppo.patch index 2dfe4d07f..7c1951b51 100644 --- a/target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq50xx-add-dtsi.patch +++ b/target/linux/qualcommax/patches-6.1/0030-v6.6-arm64-dts-Add-ipq5018-SoC-and-rdp432-c2-board-suppo.patch @@ -1,1128 +1,1126 @@ ---- /dev/null -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -0,0 +1,1125 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * IPQ5018 SoC device tree source -+ * -+ * Copyright (c) 2023 The Linux Foundation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&intc>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ clocks { -+ cmn_pll_ref_clk: cmn-pll-ref-clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <96000000>; -+ #clock-cells = <0>; -+ }; -+ -+ sleep_clk: sleep-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ -+ xo_board_clk: xo-board-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ CPU0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ enable-method = "psci"; -+ next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; -+ }; -+ -+ CPU1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ enable-method = "psci"; -+ next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; -+ }; -+ -+ L2_0: l2-cache { -+ compatible = "cache"; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-unified; -+ }; -+ }; -+ -+ cpu_opp_table: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ /* -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ */ -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ -+ firmware { -+ scm { -+ compatible = "qcom,scm-ipq5018", "qcom,scm"; -+ qcom,sdi-enabled; -+ qcom,dload-mode = <&tcsr 0x6100>; -+ }; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ /* We expect the bootloader to fill in the size */ -+ reg = <0x0 0x40000000 0x0 0x0>; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ tz_apps@4a400000 { -+ reg = <0x0 0x4a400000 0x0 0x400000>; -+ no-map; -+ }; -+ -+ bootloader@4a800000 { -+ reg = <0x0 0x4a800000 0x0 0x200000>; -+ no-map; -+ }; -+ -+ sbl@4aa00000 { -+ reg = <0x0 0x4aa00000 0x0 0x100000>; -+ no-map; -+ }; -+ -+ smem@4ab00000 { -+ compatible = "qcom,smem"; -+ reg = <0x0 0x4ab00000 0x0 0x100000>; -+ no-map; -+ -+ hwlocks = <&tcsr_mutex 3>; -+ }; -+ -+ tz_region: tz@4ac00000 { -+ reg = <0x0 0x4ac00000 0x0 0x200000>; -+ no-map; -+ }; -+ }; -+ -+ soc: soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0 0xffffffff>; -+ -+ usbphy0: phy@5b000 { -+ compatible = "qcom,ipq5018-usb-hsphy"; -+ reg = <0x0005b000 0x120>; -+ -+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; -+ -+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; -+ -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ -+ pcie1_phy: phy@7e000{ -+ compatible = "qcom,ipq5018-uniphy-pcie-phy"; -+ reg = <0x0007e000 0x800>; -+ -+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ -+ resets = <&gcc GCC_PCIE1_PHY_BCR>, -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ -+ #clock-cells = <0>; -+ -+ #phy-cells = <0>; -+ -+ num-lanes = <1>; -+ -+ status = "disabled"; -+ }; -+ -+ pcie0_phy: phy@86000{ -+ compatible = "qcom,ipq5018-uniphy-pcie-phy"; -+ reg = <0x00086000 0x800>; -+ -+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ -+ resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ -+ #clock-cells = <0>; -+ -+ #phy-cells = <0>; -+ -+ num-lanes = <2>; -+ -+ status = "disabled"; -+ }; -+ -+ mdio0: mdio@88000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; -+ reg = <0x88000 0x64>; -+ clocks = <&gcc GCC_MDIO0_AHB_CLK>; -+ clock-names = "gcc_mdio_ahb_clk"; -+ status = "disabled"; -+ -+ ge_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-id004d.d0c0"; -+ reg = <7>; -+ resets = <&gcc GCC_GEPHY_BCR>, -+ <&gcc GCC_GEPHY_MDC_SW_ARES>, -+ <&gcc GCC_GEPHY_DSP_HW_ARES>, -+ <&gcc GCC_GEPHY_RX_ARES>, -+ <&gcc GCC_GEPHY_TX_ARES>; -+ clocks = <&gcc GCC_GEPHY_RX_CLK>, -+ <&gcc GCC_GEPHY_TX_CLK>; -+ }; -+ }; -+ -+ mdio1: mdio@90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "qcom,ipq5018-mdio"; -+ reg = <0x90000 0x64>; -+ clocks = <&gcc GCC_MDIO1_AHB_CLK>; -+ clock-names = "gcc_mdio_ahb_clk"; -+ status = "disabled"; -+ }; -+ -+ cmn_pll: clock-controller@9b000 { -+ compatible = "qcom,ipq9574-cmn-pll"; -+ reg = <0x0009b000 0x800>, -+ <0x19475c4 0x4>; -+ reg-names = "cmn", -+ "tcsr"; -+ clocks = <&cmn_pll_ref_clk>, -+ <&gcc GCC_CMN_BLK_AHB_CLK>, -+ <&gcc GCC_CMN_BLK_SYS_CLK>; -+ clock-names = "ref", "ahb", "sys"; -+ #clock-cells = <1>; -+ }; -+ -+ qfprom: qfprom@a0000 { -+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; -+ reg = <0xa0000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ tsens_mode: mode@249 { -+ reg = <0x249 1>; -+ bits = <0 3>; -+ }; -+ -+ tsens_base1: base1@249 { -+ reg = <0x249 2>; -+ bits = <3 8>; -+ }; -+ -+ tsens_base2: base2@24a { -+ reg = <0x24a 2>; -+ bits = <3 8>; -+ }; -+ -+ tsens_s0_p1: s0-p1@24b { -+ reg = <0x24b 0x2>; -+ bits = <2 6>; -+ }; -+ -+ tsens_s0_p2: s0-p2@24c { -+ reg = <0x24c 0x1>; -+ bits = <1 6>; -+ }; -+ -+ tsens_s1_p1: s1-p1@24c { -+ reg = <0x24c 0x2>; -+ bits = <7 6>; -+ }; -+ -+ tsens_s1_p2: s1-p2@24d { -+ reg = <0x24d 0x2>; -+ bits = <5 6>; -+ }; -+ -+ tsens_s2_p1: s2-p1@24e { -+ reg = <0x24e 0x2>; -+ bits = <3 6>; -+ }; -+ -+ tsens_s2_p2: s2-p2@24f { -+ reg = <0x24f 0x1>; -+ bits = <1 6>; -+ }; -+ -+ tsens_s3_p1: s3-p1@24f { -+ reg = <0x24f 0x2>; -+ bits = <7 6>; -+ }; -+ -+ tsens_s3_p2: s3-p2@250 { -+ reg = <0x250 0x2>; -+ bits = <5 6>; -+ }; -+ -+ tsens_s4_p1: s4-p1@251 { -+ reg = <0x251 0x2>; -+ bits = <3 6>; -+ }; -+ -+ tsens_s4_p2: s4-p2@254 { -+ reg = <0x254 0x1>; -+ bits = <0 6>; -+ }; -+ }; -+ -+ prng: rng@e3000 { -+ compatible = "qcom,prng-ee"; -+ reg = <0x000e3000 0x1000>; -+ clocks = <&gcc GCC_PRNG_AHB_CLK>; -+ clock-names = "core"; -+ status = "disabled"; -+ }; -+ -+ tsens: thermal-sensor@4a9000 { -+ compatible = "qcom,ipq5018-tsens"; -+ reg = <0x4a9000 0x1000>, /* TM */ -+ <0x4a8000 0x1000>; /* SROT */ -+ -+ nvmem-cells = <&tsens_mode>, -+ <&tsens_base1>, -+ <&tsens_base2>, -+ <&tsens_s0_p1>, -+ <&tsens_s0_p2>, -+ <&tsens_s1_p1>, -+ <&tsens_s1_p2>, -+ <&tsens_s2_p1>, -+ <&tsens_s2_p2>, -+ <&tsens_s3_p1>, -+ <&tsens_s3_p2>, -+ <&tsens_s4_p1>, -+ <&tsens_s4_p2>; -+ -+ nvmem-cell-names = "mode", -+ "base1", -+ "base2", -+ "s0_p1", -+ "s0_p2", -+ "s1_p1", -+ "s1_p2", -+ "s2_p1", -+ "s2_p2", -+ "s3_p1", -+ "s3_p2", -+ "s4_p1", -+ "s4_p2"; -+ -+ interrupts = ; -+ interrupt-names = "uplow"; -+ #qcom,sensors = <5>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ cryptobam: dma-controller@704000 { -+ compatible = "qcom,bam-v1.7.0"; -+ reg = <0x00704000 0x20000>; -+ interrupts = ; -+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>; -+ clock-names = "bam_clk"; -+ #dma-cells = <1>; -+ qcom,ee = <1>; -+ qcom,controlled-remotely; -+ status = "disabled"; -+ }; -+ -+ crypto: crypto@73a000 { -+ compatible = "qcom,crypto-v5.1"; -+ reg = <0x0073a000 0x6000>; -+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>, -+ <&gcc GCC_CRYPTO_AXI_CLK>, -+ <&gcc GCC_CRYPTO_CLK>; -+ clock-names = "iface", "bus", "core"; -+ dmas = <&cryptobam 2>, <&cryptobam 3>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ tlmm: pinctrl@1000000 { -+ compatible = "qcom,ipq5018-tlmm"; -+ reg = <0x01000000 0x300000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&tlmm 0 0 47>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ -+ uart1_pins: uart1-state { -+ pins = "gpio31", "gpio32", "gpio33", "gpio34"; -+ function = "blsp1_uart1"; -+ drive-strength = <8>; -+ bias-pull-down; -+ }; -+ }; -+ -+ gcc: clock-controller@1800000 { -+ compatible = "qcom,gcc-ipq5018"; -+ reg = <0x01800000 0x80000>; -+ clocks = <&xo_board_clk>, -+ <&sleep_clk>, -+ <&pcie0_phy>, -+ <&pcie1_phy>, -+ <0>, -+ <&ge_phy 0>, -+ <&ge_phy 1>, -+ <0>, -+ <0>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ #power-domain-cells = <1>; -+ }; -+ -+ tcsr_mutex: hwlock@1905000 { -+ compatible = "qcom,tcsr-mutex"; -+ reg = <0x01905000 0x20000>; -+ #hwlock-cells = <1>; -+ }; -+ -+ tcsr: syscon@1937000 { -+ compatible = "qcom,tcsr-ipq5018", "syscon", "simple-mfd"; -+ reg = <0x01937000 0x21000>; -+ }; -+ -+ pwm: pwm@1941010 { -+ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; -+ reg = <0x01941010 0x20>; -+ clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; -+ assigned-clock-rates = <100000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ sdhc_1: mmc@7804000 { -+ compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; -+ reg = <0x7804000 0x1000>; -+ reg-names = "hc"; -+ -+ interrupts = , -+ ; -+ interrupt-names = "hc_irq", "pwr_irq"; -+ -+ clocks = <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_SDCC1_APPS_CLK>, -+ <&xo_board_clk>; -+ clock-names = "iface", "core", "xo"; -+ non-removable; -+ status = "disabled"; -+ }; -+ -+ blsp_dma: dma-controller@7884000 { -+ compatible = "qcom,bam-v1.7.0"; -+ reg = <0x07884000 0x1d000>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "bam_clk"; -+ #dma-cells = <1>; -+ qcom,ee = <0>; -+ }; -+ -+ blsp1_uart1: serial@78af000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x078af000 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart2: serial@78b0000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x078b0000 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_spi1: spi@78b5000 { -+ compatible = "qcom,spi-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x078b5000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ dmas = <&blsp_dma 4>, <&blsp_dma 5>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ blsp1_i2c3: i2c@78b7000 { -+ compatible = "qcom,i2c-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x078b7000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ clock-frequency = <400000>; -+ dmas = <&blsp_dma 9>, <&blsp_dma 8>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ qpic_bam: dma@7984000 { -+ compatible = "qcom,bam-v1.7.0"; -+ reg = <0x07984000 0x1c000>; -+ interrupts = ; -+ clocks = <&gcc GCC_QPIC_AHB_CLK>; -+ clock-names = "bam_clk"; -+ #dma-cells = <1>; -+ qcom,ee = <0>; -+ status = "disabled"; -+ }; -+ -+ qpic_nand: qpic-nand@79b0000 { -+ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; -+ reg = <0x079b0000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&gcc GCC_QPIC_CLK>, -+ <&gcc GCC_QPIC_AHB_CLK>, -+ <&gcc GCC_QPIC_IO_MACRO_CLK>; -+ clock-names = "core", "aon", "iom"; -+ -+ dmas = <&qpic_bam 0>, -+ <&qpic_bam 1>, -+ <&qpic_bam 2>, -+ <&qpic_bam 3>; -+ dma-names = "tx", "rx", "cmd", "status"; -+ -+ status = "disabled"; -+ }; -+ -+ usb: usb@8af8800 { -+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; -+ reg = <0x08af8800 0x400>; -+ -+ interrupts = ; -+ interrupt-names = "hs_phy_irq"; -+ -+ clocks = <&gcc GCC_USB0_MASTER_CLK>, -+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -+ <&gcc GCC_USB0_SLEEP_CLK>, -+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "core", -+ "iface", -+ "sleep", -+ "mock_utmi"; -+ -+ resets = <&gcc GCC_USB0_BCR>; -+ -+ qcom,select-utmi-as-pipe-clk; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ status = "disabled"; -+ -+ usb_dwc: usb@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x08a00000 0xe000>; -+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "ref"; -+ interrupts = ; -+ phy-names = "usb2-phy"; -+ phys = <&usbphy0>; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ }; -+ }; -+ -+ intc: interrupt-controller@b000000 { -+ compatible = "qcom,msm-qgic2"; -+ reg = <0x0b000000 0x1000>, /* GICD */ -+ <0x0b002000 0x2000>, /* GICC */ -+ <0x0b001000 0x1000>, /* GICH */ -+ <0x0b004000 0x2000>; /* GICV */ -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0b00a000 0x1ffa>; -+ -+ v2m0: v2m@0 { -+ compatible = "arm,gic-v2m-frame"; -+ reg = <0x00000000 0xff8>; -+ msi-controller; -+ }; -+ -+ v2m1: v2m@1000 { -+ compatible = "arm,gic-v2m-frame"; -+ reg = <0x00001000 0xff8>; -+ msi-controller; -+ }; -+ }; -+ -+ watchdog: watchdog@b017000 { -+ compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; -+ reg = <0x0b017000 0x40>; -+ interrupts = ; -+ clocks = <&sleep_clk>; -+ }; -+ -+ apcs_glb: mailbox@b111000 { -+ compatible = "qcom,ipq5018-apcs-apps-global", -+ "qcom,ipq6018-apcs-apps-global"; -+ reg = <0x0b111000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; -+ #mbox-cells = <1>; -+ }; -+ -+ a53pll: clock@b116000 { -+ compatible = "qcom,ipq5018-a53pll"; -+ reg = <0x0b116000 0x40>; -+ #clock-cells = <0>; -+ clocks = <&xo_board_clk>; -+ clock-names = "xo"; -+ }; -+ -+ timer@b120000 { -+ compatible = "arm,armv7-timer-mem"; -+ reg = <0x0b120000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ frame@b120000 { -+ reg = <0x0b121000 0x1000>, -+ <0x0b122000 0x1000>; -+ interrupts = , -+ ; -+ frame-number = <0>; -+ }; -+ -+ frame@b123000 { -+ reg = <0xb123000 0x1000>; -+ interrupts = ; -+ frame-number = <1>; -+ status = "disabled"; -+ }; -+ -+ frame@b124000 { -+ frame-number = <2>; -+ interrupts = ; -+ reg = <0x0b124000 0x1000>; -+ status = "disabled"; -+ }; -+ -+ frame@b125000 { -+ reg = <0x0b125000 0x1000>; -+ interrupts = ; -+ frame-number = <3>; -+ status = "disabled"; -+ }; -+ -+ frame@b126000 { -+ reg = <0x0b126000 0x1000>; -+ interrupts = ; -+ frame-number = <4>; -+ status = "disabled"; -+ }; -+ -+ frame@b127000 { -+ reg = <0x0b127000 0x1000>; -+ interrupts = ; -+ frame-number = <5>; -+ status = "disabled"; -+ }; -+ -+ frame@b128000 { -+ reg = <0x0b128000 0x1000>; -+ interrupts = ; -+ frame-number = <6>; -+ status = "disabled"; -+ }; -+ }; -+ -+ wifi0: wifi@c000000 { -+ compatible = "qcom,ipq5018-wifi"; -+ reg = <0xc000000 0x1000000>; -+ -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ -+ interrupt-names = "misc-pulse1", -+ "misc-latch", -+ "sw-exception", -+ "watchdog", -+ "ce0", -+ "ce1", -+ "ce2", -+ "ce3", -+ "ce4", -+ "ce5", -+ "ce6", -+ "ce7", -+ "ce8", -+ "ce9", -+ "ce10", -+ "ce11", -+ "host2wbm-desc-feed", -+ "host2reo-re-injection", -+ "host2reo-command", -+ "host2rxdma-monitor-ring3", -+ "host2rxdma-monitor-ring2", -+ "host2rxdma-monitor-ring1", -+ "reo2ost-exception", -+ "wbm2host-rx-release", -+ "reo2host-status", -+ "reo2host-destination-ring4", -+ "reo2host-destination-ring3", -+ "reo2host-destination-ring2", -+ "reo2host-destination-ring1", -+ "rxdma2host-monitor-destination-mac3", -+ "rxdma2host-monitor-destination-mac2", -+ "rxdma2host-monitor-destination-mac1", -+ "ppdu-end-interrupts-mac3", -+ "ppdu-end-interrupts-mac2", -+ "ppdu-end-interrupts-mac1", -+ "rxdma2host-monitor-status-ring-mac3", -+ "rxdma2host-monitor-status-ring-mac2", -+ "rxdma2host-monitor-status-ring-mac1", -+ "host2rxdma-host-buf-ring-mac3", -+ "host2rxdma-host-buf-ring-mac2", -+ "host2rxdma-host-buf-ring-mac1", -+ "rxdma2host-destination-ring-mac3", -+ "rxdma2host-destination-ring-mac2", -+ "rxdma2host-destination-ring-mac1", -+ "host2tcl-input-ring4", -+ "host2tcl-input-ring3", -+ "host2tcl-input-ring2", -+ "host2tcl-input-ring1", -+ "wbm2host-tx-completions-ring3", -+ "wbm2host-tx-completions-ring2", -+ "wbm2host-tx-completions-ring1", -+ "tcl2host-status-ring"; -+ -+ status = "disabled"; -+ }; -+ -+ //QCN6102 5G -+ wifi1: wifi1@c000000 { -+ reg = <0x0b00a040 0x0>; -+ compatible = "qcom,qcn6122-wifi"; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ status = "disabled"; -+ }; -+ -+ //QCN6122 5G/6G -+ wifi2: wifi2@c000000 { -+ reg = <0x0b00a040 0x0>; -+ compatible = "qcom,qcn6122-wifi"; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ status = "disabled"; -+ }; -+ -+ q6v5_wcss: remoteproc@cd00000 { -+ compatible = "qcom,ipq5018-q6-mpd"; -+ reg = <0x0cd00000 0x4040>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ clocks = <&gcc GCC_XO_CLK>, -+ <&gcc GCC_SLEEP_CLK_SRC>, -+ <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>; -+ -+ interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, -+ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, -+ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, -+ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, -+ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; -+ interrupt-names = "wdog", -+ "fatal", -+ "ready", -+ "handover", -+ "stop-ack"; -+ -+ qcom,smem-states = <&wcss_smp2p_out 0>, -+ <&wcss_smp2p_out 1>; -+ qcom,smem-state-names = "shutdown", -+ "stop"; -+ -+ status = "disabled"; -+ -+ glink-edge { -+ interrupts = ; -+ label = "rtr"; -+ qcom,remote-pid = <1>; -+ mboxes = <&apcs_glb 8>; -+ -+ qrtr_requests { -+ qcom,glink-channels = "IPCRTR"; -+ }; -+ }; -+ }; -+ -+ wcss: smp2p-wcss { -+ compatible = "qcom,smp2p"; -+ qcom,smem = <435>, <428>; -+ -+ interrupt-parent = <&intc>; -+ interrupts = ; -+ -+ mboxes = <&apcs_glb 9>; -+ -+ qcom,local-pid = <0>; -+ qcom,remote-pid = <1>; -+ -+ wcss_smp2p_out: master-kernel { -+ qcom,entry-name = "master-kernel"; -+ qcom,smp2p-feature-ssr-ack; -+ #qcom,smem-state-cells = <1>; -+ }; -+ -+ wcss_smp2p_in: slave-kernel { -+ qcom,entry-name = "slave-kernel"; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ }; -+ -+ pcie1: pcie@80000000 { -+ compatible = "qcom,pcie-ipq5018"; -+ reg = <0x80000000 0xf1d>, -+ <0x80000f20 0xa8>, -+ <0x80001000 0x1000>, -+ <0x00078000 0x3000>, -+ <0x80100000 0x1000>; -+ reg-names = "dbi", -+ "elbi", -+ "atu", -+ "parf", -+ "config"; -+ device_type = "pci"; -+ linux,pci-domain = <0>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <1>; -+ max-link-speed = <2>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ phys = <&pcie1_phy>; -+ phy-names ="pciephy"; -+ -+ ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */ -+ <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */ -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ -+ -+ interrupts = ; -+ interrupt-names = "global_irq"; -+ -+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, -+ <&gcc GCC_PCIE1_AXI_M_CLK>, -+ <&gcc GCC_PCIE1_AXI_S_CLK>, -+ <&gcc GCC_PCIE1_AHB_CLK>, -+ <&gcc GCC_PCIE1_AUX_CLK>, -+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "aux", -+ "axi_bridge"; -+ -+ resets = <&gcc GCC_PCIE1_PIPE_ARES>, -+ <&gcc GCC_PCIE1_SLEEP_ARES>, -+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE1_AHB_ARES>, -+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, -+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky", -+ "axi_s_sticky"; -+ -+ msi-map = <0x0 &v2m0 0x0 0xff8>; -+ status = "disabled"; -+ }; -+ -+ pcie0: pcie@a0000000 { -+ compatible = "qcom,pcie-ipq5018"; -+ reg = <0xa0000000 0xf1d>, -+ <0xa0000f20 0xa8>, -+ <0xa0001000 0x1000>, -+ <0x00080000 0x3000>, -+ <0xa0100000 0x1000>; -+ reg-names = "dbi", -+ "elbi", -+ "atu", -+ "parf", -+ "config"; -+ device_type = "pci"; -+ linux,pci-domain = <1>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <2>; -+ max-link-speed = <2>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ phys = <&pcie0_phy>; -+ phy-names ="pciephy"; -+ -+ ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>, /* I/O */ -+ <0x82000000 0 0xa0300000 0xa0300000 0 0x10000000>; /* MEM */ -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ -+ -+ interrupts = ; -+ interrupt-names = "global_irq"; -+ -+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -+ <&gcc GCC_PCIE0_AXI_M_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_CLK>, -+ <&gcc GCC_PCIE0_AHB_CLK>, -+ <&gcc GCC_PCIE0_AUX_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "aux", -+ "axi_bridge"; -+ -+ resets = <&gcc GCC_PCIE0_PIPE_ARES>, -+ <&gcc GCC_PCIE0_SLEEP_ARES>, -+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE0_AHB_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky", -+ "axi_s_sticky"; -+ -+ msi-map = <0x0 &v2m0 0x0 0xff8>; -+ status = "disabled"; -+ }; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 2>; -+ -+ trips { -+ cpu-critical { -+ temperature = <120000>; -+ hysteresis = <2>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gephy-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 4>; -+ -+ trips { -+ gephy-critical { -+ temperature = <120000>; -+ hysteresis = <2>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ top-glue-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 3>; -+ -+ trips { -+ top_glue-critical { -+ temperature = <120000>; -+ hysteresis = <2>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ ubi32-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 1>; -+ -+ trips { -+ ubi32-critical { -+ temperature = <120000>; -+ hysteresis = <2>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+}; +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -0,0 +1,1123 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * IPQ5018 SoC device tree source ++ * ++ * Copyright (c) 2023 The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++/ { ++ interrupt-parent = <&intc>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ clocks { ++ cmn_pll_ref_clk: cmn-pll-ref-clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <96000000>; ++ #clock-cells = <0>; ++ }; ++ ++ sleep_clk: sleep-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ ++ xo_board_clk: xo-board-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ CPU0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; ++ }; ++ ++ CPU1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x1>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; ++ }; ++ ++ L2_0: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-unified; ++ }; ++ }; ++ ++ cpu_opp_table: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ ++ firmware { ++ scm { ++ compatible = "qcom,scm-ipq5018", "qcom,scm"; ++ qcom,sdi-enabled; ++ qcom,dload-mode = <&tcsr 0x6100>; ++ }; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ /* We expect the bootloader to fill in the size */ ++ reg = <0x0 0x40000000 0x0 0x0>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = ; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ tz_apps@4a400000 { ++ reg = <0x0 0x4a400000 0x0 0x400000>; ++ no-map; ++ }; ++ ++ bootloader@4a800000 { ++ reg = <0x0 0x4a800000 0x0 0x200000>; ++ no-map; ++ }; ++ ++ sbl@4aa00000 { ++ reg = <0x0 0x4aa00000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ smem@4ab00000 { ++ compatible = "qcom,smem"; ++ reg = <0x0 0x4ab00000 0x0 0x100000>; ++ no-map; ++ ++ hwlocks = <&tcsr_mutex 3>; ++ }; ++ ++ tz_region: tz@4ac00000 { ++ reg = <0x0 0x4ac00000 0x0 0x200000>; ++ no-map; ++ }; ++ }; ++ ++ soc: soc@0 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0xffffffff>; ++ ++ usbphy0: phy@5b000 { ++ compatible = "qcom,ipq5018-usb-hsphy"; ++ reg = <0x0005b000 0x120>; ++ ++ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; ++ ++ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; ++ ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@7e000{ ++ compatible = "qcom,ipq5018-uniphy-pcie-phy"; ++ reg = <0x0007e000 0x800>; ++ ++ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ ++ num-lanes = <1>; ++ ++ status = "disabled"; ++ }; ++ ++ pcie0_phy: phy@86000{ ++ compatible = "qcom,ipq5018-uniphy-pcie-phy"; ++ reg = <0x00086000 0x800>; ++ ++ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ ++ num-lanes = <2>; ++ ++ status = "disabled"; ++ }; ++ ++ mdio0: mdio@88000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; ++ reg = <0x88000 0x64>; ++ clocks = <&gcc GCC_MDIO0_AHB_CLK>; ++ clock-names = "gcc_mdio_ahb_clk"; ++ status = "disabled"; ++ ++ ge_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-id004d.d0c0"; ++ reg = <7>; ++ resets = <&gcc GCC_GEPHY_BCR>, ++ <&gcc GCC_GEPHY_MDC_SW_ARES>, ++ <&gcc GCC_GEPHY_DSP_HW_ARES>, ++ <&gcc GCC_GEPHY_RX_ARES>, ++ <&gcc GCC_GEPHY_TX_ARES>; ++ clocks = <&gcc GCC_GEPHY_RX_CLK>, ++ <&gcc GCC_GEPHY_TX_CLK>; ++ }; ++ }; ++ ++ mdio1: mdio@90000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "qcom,ipq5018-mdio"; ++ reg = <0x90000 0x64>; ++ clocks = <&gcc GCC_MDIO1_AHB_CLK>; ++ clock-names = "gcc_mdio_ahb_clk"; ++ status = "disabled"; ++ }; ++ ++ cmn_pll: clock-controller@9b000 { ++ compatible = "qcom,ipq9574-cmn-pll"; ++ reg = <0x0009b000 0x800>, ++ <0x19475c4 0x4>; ++ reg-names = "cmn", ++ "tcsr"; ++ clocks = <&cmn_pll_ref_clk>, ++ <&gcc GCC_CMN_BLK_AHB_CLK>, ++ <&gcc GCC_CMN_BLK_SYS_CLK>; ++ clock-names = "ref", "ahb", "sys"; ++ #clock-cells = <1>; ++ }; ++ ++ qfprom: qfprom@a0000 { ++ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; ++ reg = <0xa0000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ tsens_mode: mode@249 { ++ reg = <0x249 1>; ++ bits = <0 3>; ++ }; ++ ++ tsens_base1: base1@249 { ++ reg = <0x249 2>; ++ bits = <3 8>; ++ }; ++ ++ tsens_base2: base2@24a { ++ reg = <0x24a 2>; ++ bits = <3 8>; ++ }; ++ ++ tsens_s0_p1: s0-p1@24b { ++ reg = <0x24b 0x2>; ++ bits = <2 6>; ++ }; ++ ++ tsens_s0_p2: s0-p2@24c { ++ reg = <0x24c 0x1>; ++ bits = <1 6>; ++ }; ++ ++ tsens_s1_p1: s1-p1@24c { ++ reg = <0x24c 0x2>; ++ bits = <7 6>; ++ }; ++ ++ tsens_s1_p2: s1-p2@24d { ++ reg = <0x24d 0x2>; ++ bits = <5 6>; ++ }; ++ ++ tsens_s2_p1: s2-p1@24e { ++ reg = <0x24e 0x2>; ++ bits = <3 6>; ++ }; ++ ++ tsens_s2_p2: s2-p2@24f { ++ reg = <0x24f 0x1>; ++ bits = <1 6>; ++ }; ++ ++ tsens_s3_p1: s3-p1@24f { ++ reg = <0x24f 0x2>; ++ bits = <7 6>; ++ }; ++ ++ tsens_s3_p2: s3-p2@250 { ++ reg = <0x250 0x2>; ++ bits = <5 6>; ++ }; ++ ++ tsens_s4_p1: s4-p1@251 { ++ reg = <0x251 0x2>; ++ bits = <3 6>; ++ }; ++ ++ tsens_s4_p2: s4-p2@254 { ++ reg = <0x254 0x1>; ++ bits = <0 6>; ++ }; ++ }; ++ ++ prng: rng@e3000 { ++ compatible = "qcom,prng-ee"; ++ reg = <0x000e3000 0x1000>; ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "core"; ++ status = "disabled"; ++ }; ++ ++ tsens: thermal-sensor@4a9000 { ++ compatible = "qcom,ipq5018-tsens"; ++ reg = <0x4a9000 0x1000>, /* TM */ ++ <0x4a8000 0x1000>; /* SROT */ ++ ++ nvmem-cells = <&tsens_mode>, ++ <&tsens_base1>, ++ <&tsens_base2>, ++ <&tsens_s0_p1>, ++ <&tsens_s0_p2>, ++ <&tsens_s1_p1>, ++ <&tsens_s1_p2>, ++ <&tsens_s2_p1>, ++ <&tsens_s2_p2>, ++ <&tsens_s3_p1>, ++ <&tsens_s3_p2>, ++ <&tsens_s4_p1>, ++ <&tsens_s4_p2>; ++ ++ nvmem-cell-names = "mode", ++ "base1", ++ "base2", ++ "s0_p1", ++ "s0_p2", ++ "s1_p1", ++ "s1_p2", ++ "s2_p1", ++ "s2_p2", ++ "s3_p1", ++ "s3_p2", ++ "s4_p1", ++ "s4_p2"; ++ ++ interrupts = ; ++ interrupt-names = "uplow"; ++ #qcom,sensors = <5>; ++ #thermal-sensor-cells = <1>; ++ }; ++ ++ cryptobam: dma-controller@704000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x00704000 0x20000>; ++ interrupts = ; ++ clocks = <&gcc GCC_CRYPTO_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <1>; ++ qcom,controlled-remotely; ++ status = "disabled"; ++ }; ++ ++ crypto: crypto@73a000 { ++ compatible = "qcom,crypto-v5.1"; ++ reg = <0x0073a000 0x6000>; ++ clocks = <&gcc GCC_CRYPTO_AHB_CLK>, ++ <&gcc GCC_CRYPTO_AXI_CLK>, ++ <&gcc GCC_CRYPTO_CLK>; ++ clock-names = "iface", "bus", "core"; ++ dmas = <&cryptobam 2>, <&cryptobam 3>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ tlmm: pinctrl@1000000 { ++ compatible = "qcom,ipq5018-tlmm"; ++ reg = <0x01000000 0x300000>; ++ interrupts = ; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&tlmm 0 0 47>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ uart1_pins: uart1-state { ++ pins = "gpio31", "gpio32", "gpio33", "gpio34"; ++ function = "blsp1_uart1"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ gcc: clock-controller@1800000 { ++ compatible = "qcom,gcc-ipq5018"; ++ reg = <0x01800000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&sleep_clk>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, ++ <0>, ++ <&ge_phy 0>, ++ <&ge_phy 1>, ++ <0>, ++ <0>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ #power-domain-cells = <1>; ++ }; ++ ++ tcsr_mutex: hwlock@1905000 { ++ compatible = "qcom,tcsr-mutex"; ++ reg = <0x01905000 0x20000>; ++ #hwlock-cells = <1>; ++ }; ++ ++ tcsr: syscon@1937000 { ++ compatible = "qcom,tcsr-ipq5018", "syscon", "simple-mfd"; ++ reg = <0x01937000 0x21000>; ++ }; ++ ++ pwm: pwm@1941010 { ++ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; ++ reg = <0x01941010 0x20>; ++ clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; ++ assigned-clock-rates = <100000000>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ sdhc_1: mmc@7804000 { ++ compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; ++ reg = <0x7804000 0x1000>; ++ reg-names = "hc"; ++ ++ interrupts = , ++ ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ ++ clocks = <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_SDCC1_APPS_CLK>, ++ <&xo_board_clk>; ++ clock-names = "iface", "core", "xo"; ++ non-removable; ++ status = "disabled"; ++ }; ++ ++ blsp_dma: dma-controller@7884000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x07884000 0x1d000>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ }; ++ ++ blsp1_uart1: serial@78af000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078af000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart2: serial@78b0000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b0000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi1: spi@78b5000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x078b5000 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 4>, <&blsp_dma 5>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_i2c3: i2c@78b7000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x078b7000 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ clock-frequency = <400000>; ++ dmas = <&blsp_dma 9>, <&blsp_dma 8>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ qpic_bam: dma@7984000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x07984000 0x1c000>; ++ interrupts = ; ++ clocks = <&gcc GCC_QPIC_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ status = "disabled"; ++ }; ++ ++ qpic_nand: qpic-nand@79b0000 { ++ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; ++ reg = <0x079b0000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "iom"; ++ ++ dmas = <&qpic_bam 0>, ++ <&qpic_bam 1>, ++ <&qpic_bam 2>, ++ <&qpic_bam 3>; ++ dma-names = "tx", "rx", "cmd", "status"; ++ ++ status = "disabled"; ++ }; ++ ++ usb: usb@8af8800 { ++ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; ++ reg = <0x08af8800 0x400>; ++ ++ interrupts = ; ++ interrupt-names = "hs_phy_irq"; ++ ++ clocks = <&gcc GCC_USB0_MASTER_CLK>, ++ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, ++ <&gcc GCC_USB0_SLEEP_CLK>, ++ <&gcc GCC_USB0_MOCK_UTMI_CLK>; ++ clock-names = "core", ++ "iface", ++ "sleep", ++ "mock_utmi"; ++ ++ resets = <&gcc GCC_USB0_BCR>; ++ ++ qcom,select-utmi-as-pipe-clk; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ status = "disabled"; ++ ++ usb_dwc: usb@8a00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x08a00000 0xe000>; ++ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; ++ clock-names = "ref"; ++ interrupts = ; ++ phy-names = "usb2-phy"; ++ phys = <&usbphy0>; ++ tx-fifo-resize; ++ snps,is-utmi-l1-suspend; ++ snps,hird-threshold = /bits/ 8 <0x0>; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ }; ++ }; ++ ++ intc: interrupt-controller@b000000 { ++ compatible = "qcom,msm-qgic2"; ++ reg = <0x0b000000 0x1000>, /* GICD */ ++ <0x0b002000 0x2000>, /* GICC */ ++ <0x0b001000 0x1000>, /* GICH */ ++ <0x0b004000 0x2000>; /* GICV */ ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x0b00a000 0x1ffa>; ++ ++ v2m0: v2m@0 { ++ compatible = "arm,gic-v2m-frame"; ++ reg = <0x00000000 0xff8>; ++ msi-controller; ++ }; ++ ++ v2m1: v2m@1000 { ++ compatible = "arm,gic-v2m-frame"; ++ reg = <0x00001000 0xff8>; ++ msi-controller; ++ }; ++ }; ++ ++ watchdog: watchdog@b017000 { ++ compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; ++ reg = <0x0b017000 0x40>; ++ interrupts = ; ++ clocks = <&sleep_clk>; ++ }; ++ ++ apcs_glb: mailbox@b111000 { ++ compatible = "qcom,ipq5018-apcs-apps-global", ++ "qcom,ipq6018-apcs-apps-global"; ++ reg = <0x0b111000 0x1000>; ++ #clock-cells = <1>; ++ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; ++ #mbox-cells = <1>; ++ }; ++ ++ a53pll: clock@b116000 { ++ compatible = "qcom,ipq5018-a53pll"; ++ reg = <0x0b116000 0x40>; ++ #clock-cells = <0>; ++ clocks = <&xo_board_clk>; ++ clock-names = "xo"; ++ }; ++ ++ timer@b120000 { ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x0b120000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ frame@b120000 { ++ reg = <0x0b121000 0x1000>, ++ <0x0b122000 0x1000>; ++ interrupts = , ++ ; ++ frame-number = <0>; ++ }; ++ ++ frame@b123000 { ++ reg = <0xb123000 0x1000>; ++ interrupts = ; ++ frame-number = <1>; ++ status = "disabled"; ++ }; ++ ++ frame@b124000 { ++ frame-number = <2>; ++ interrupts = ; ++ reg = <0x0b124000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b125000 { ++ reg = <0x0b125000 0x1000>; ++ interrupts = ; ++ frame-number = <3>; ++ status = "disabled"; ++ }; ++ ++ frame@b126000 { ++ reg = <0x0b126000 0x1000>; ++ interrupts = ; ++ frame-number = <4>; ++ status = "disabled"; ++ }; ++ ++ frame@b127000 { ++ reg = <0x0b127000 0x1000>; ++ interrupts = ; ++ frame-number = <5>; ++ status = "disabled"; ++ }; ++ ++ frame@b128000 { ++ reg = <0x0b128000 0x1000>; ++ interrupts = ; ++ frame-number = <6>; ++ status = "disabled"; ++ }; ++ }; ++ ++ wifi0: wifi@c000000 { ++ compatible = "qcom,ipq5018-wifi"; ++ reg = <0xc000000 0x1000000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ ++ interrupt-names = "misc-pulse1", ++ "misc-latch", ++ "sw-exception", ++ "watchdog", ++ "ce0", ++ "ce1", ++ "ce2", ++ "ce3", ++ "ce4", ++ "ce5", ++ "ce6", ++ "ce7", ++ "ce8", ++ "ce9", ++ "ce10", ++ "ce11", ++ "host2wbm-desc-feed", ++ "host2reo-re-injection", ++ "host2reo-command", ++ "host2rxdma-monitor-ring3", ++ "host2rxdma-monitor-ring2", ++ "host2rxdma-monitor-ring1", ++ "reo2ost-exception", ++ "wbm2host-rx-release", ++ "reo2host-status", ++ "reo2host-destination-ring4", ++ "reo2host-destination-ring3", ++ "reo2host-destination-ring2", ++ "reo2host-destination-ring1", ++ "rxdma2host-monitor-destination-mac3", ++ "rxdma2host-monitor-destination-mac2", ++ "rxdma2host-monitor-destination-mac1", ++ "ppdu-end-interrupts-mac3", ++ "ppdu-end-interrupts-mac2", ++ "ppdu-end-interrupts-mac1", ++ "rxdma2host-monitor-status-ring-mac3", ++ "rxdma2host-monitor-status-ring-mac2", ++ "rxdma2host-monitor-status-ring-mac1", ++ "host2rxdma-host-buf-ring-mac3", ++ "host2rxdma-host-buf-ring-mac2", ++ "host2rxdma-host-buf-ring-mac1", ++ "rxdma2host-destination-ring-mac3", ++ "rxdma2host-destination-ring-mac2", ++ "rxdma2host-destination-ring-mac1", ++ "host2tcl-input-ring4", ++ "host2tcl-input-ring3", ++ "host2tcl-input-ring2", ++ "host2tcl-input-ring1", ++ "wbm2host-tx-completions-ring3", ++ "wbm2host-tx-completions-ring2", ++ "wbm2host-tx-completions-ring1", ++ "tcl2host-status-ring"; ++ ++ status = "disabled"; ++ }; ++ ++ //QCN6102 5G ++ wifi1: wifi1@c000000 { ++ reg = <0x0b00a040 0x0>; ++ compatible = "qcom,qcn6122-wifi"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ status = "disabled"; ++ }; ++ ++ //QCN6122 5G/6G ++ wifi2: wifi2@c000000 { ++ reg = <0x0b00a040 0x0>; ++ compatible = "qcom,qcn6122-wifi"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ status = "disabled"; ++ }; ++ ++ q6v5_wcss: remoteproc@cd00000 { ++ compatible = "qcom,ipq5018-q6-mpd"; ++ reg = <0x0cd00000 0x4040>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_XO_CLK>, ++ <&gcc GCC_SLEEP_CLK_SRC>, ++ <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>; ++ ++ interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, ++ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; ++ interrupt-names = "wdog", ++ "fatal", ++ "ready", ++ "handover", ++ "stop-ack"; ++ ++ qcom,smem-states = <&wcss_smp2p_out 0>, ++ <&wcss_smp2p_out 1>; ++ qcom,smem-state-names = "shutdown", ++ "stop"; ++ ++ status = "disabled"; ++ ++ glink-edge { ++ interrupts = ; ++ label = "rtr"; ++ qcom,remote-pid = <1>; ++ mboxes = <&apcs_glb 8>; ++ ++ qrtr_requests { ++ qcom,glink-channels = "IPCRTR"; ++ }; ++ }; ++ }; ++ ++ wcss: smp2p-wcss { ++ compatible = "qcom,smp2p"; ++ qcom,smem = <435>, <428>; ++ ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ ++ mboxes = <&apcs_glb 9>; ++ ++ qcom,local-pid = <0>; ++ qcom,remote-pid = <1>; ++ ++ wcss_smp2p_out: master-kernel { ++ qcom,entry-name = "master-kernel"; ++ qcom,smp2p-feature-ssr-ack; ++ #qcom,smem-state-cells = <1>; ++ }; ++ ++ wcss_smp2p_in: slave-kernel { ++ qcom,entry-name = "slave-kernel"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ }; ++ ++ pcie1: pcie@80000000 { ++ compatible = "qcom,pcie-ipq5018"; ++ reg = <0x80000000 0xf1d>, ++ <0x80000f20 0xa8>, ++ <0x80001000 0x1000>, ++ <0x00078000 0x3000>, ++ <0x80100000 0x1000>; ++ reg-names = "dbi", ++ "elbi", ++ "atu", ++ "parf", ++ "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ max-link-speed = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ phys = <&pcie1_phy>; ++ phy-names ="pciephy"; ++ ++ ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */ ++ <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */ ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ interrupts = ; ++ interrupt-names = "global_irq"; ++ ++ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, ++ <&gcc GCC_PCIE1_AXI_M_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; ++ clock-names = "iface", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "aux", ++ "axi_bridge"; ++ ++ resets = <&gcc GCC_PCIE1_PIPE_ARES>, ++ <&gcc GCC_PCIE1_SLEEP_ARES>, ++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_MASTER_ARES>, ++ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, ++ <&gcc GCC_PCIE1_AHB_ARES>, ++ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; ++ reset-names = "pipe", ++ "sleep", ++ "sticky", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "axi_m_sticky", ++ "axi_s_sticky"; ++ ++ msi-map = <0x0 &v2m0 0x0 0xff8>; ++ status = "disabled"; ++ }; ++ ++ pcie0: pcie@a0000000 { ++ compatible = "qcom,pcie-ipq5018"; ++ reg = <0xa0000000 0xf1d>, ++ <0xa0000f20 0xa8>, ++ <0xa0001000 0x1000>, ++ <0x00080000 0x3000>, ++ <0xa0100000 0x1000>; ++ reg-names = "dbi", ++ "elbi", ++ "atu", ++ "parf", ++ "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ max-link-speed = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ phys = <&pcie0_phy>; ++ phy-names ="pciephy"; ++ ++ ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>, /* I/O */ ++ <0x82000000 0 0xa0300000 0xa0300000 0 0x10000000>; /* MEM */ ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ interrupts = ; ++ interrupt-names = "global_irq"; ++ ++ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, ++ <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; ++ clock-names = "iface", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "aux", ++ "axi_bridge"; ++ ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_SLEEP_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, ++ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>, ++ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; ++ reset-names = "pipe", ++ "sleep", ++ "sticky", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "axi_m_sticky", ++ "axi_s_sticky"; ++ ++ msi-map = <0x0 &v2m0 0x0 0xff8>; ++ status = "disabled"; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 2>; ++ ++ trips { ++ cpu-critical { ++ temperature = <120000>; ++ hysteresis = <2>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gephy-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 4>; ++ ++ trips { ++ gephy-critical { ++ temperature = <120000>; ++ hysteresis = <2>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ top-glue-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 3>; ++ ++ trips { ++ top_glue-critical { ++ temperature = <120000>; ++ hysteresis = <2>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ ubi32-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 1>; ++ ++ trips { ++ ubi32-critical { ++ temperature = <120000>; ++ hysteresis = <2>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++}; diff --git a/target/linux/qualcommax/patches-6.1/0055-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.1/0055-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch new file mode 100644 index 000000000..07ab74186 --- /dev/null +++ b/target/linux/qualcommax/patches-6.1/0055-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch @@ -0,0 +1,176 @@ +From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 22 Oct 2024 17:47:26 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case + +DTS coding style expects labels to be lowercase. No functional impact. +Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++--- + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++------- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++-------------- + 5 files changed, 61 insertions(+), 61 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -31,27 +31,27 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -34,12 +34,12 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -47,12 +47,12 @@ + #cooling-cells = <2>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -60,12 +60,12 @@ + #cooling-cells = <2>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -73,12 +73,12 @@ + #cooling-cells = <2>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -86,7 +86,7 @@ + #cooling-cells = <2>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -32,39 +32,39 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; diff --git a/target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch b/target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch index a3c5f344a..a6265ff00 100644 --- a/target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch +++ b/target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch @@ -23,37 +23,37 @@ Signed-off-by: Robert Marko #address-cells = <2>; @@ -38,6 +39,8 @@ reg = <0x0>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; enable-method = "psci"; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU1: cpu@1 { + cpu1: cpu@1 { @@ -46,6 +49,8 @@ enable-method = "psci"; reg = <0x1>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU2: cpu@2 { + cpu2: cpu@2 { @@ -54,6 +59,8 @@ enable-method = "psci"; reg = <0x2>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU3: cpu@3 { + cpu3: cpu@3 { @@ -62,6 +69,8 @@ enable-method = "psci"; reg = <0x3>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - L2_0: l2-cache { + l2_0: l2-cache { diff --git a/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch new file mode 100644 index 000000000..6a1c93b86 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch @@ -0,0 +1,381 @@ +From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 22 Oct 2024 17:47:26 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case + +DTS coding style expects labels to be lowercase. No functional impact. +Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++--- + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++------- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++-------------- + 5 files changed, 61 insertions(+), 61 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -31,27 +31,27 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; +--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi +@@ -30,47 +30,47 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -34,12 +34,12 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -47,12 +47,12 @@ + #cooling-cells = <2>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -60,12 +60,12 @@ + #cooling-cells = <2>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -73,12 +73,12 @@ + #cooling-cells = <2>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -86,7 +86,7 @@ + #cooling-cells = <2>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +@@ -993,10 +993,10 @@ + cooling-maps { + map0 { + trip = <&cpu_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -32,39 +32,39 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -33,12 +33,12 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -46,12 +46,12 @@ + #cooling-cells = <2>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -59,12 +59,12 @@ + #cooling-cells = <2>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x2>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -72,12 +72,12 @@ + #cooling-cells = <2>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x3>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -85,7 +85,7 @@ + #cooling-cells = <2>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +@@ -845,10 +845,10 @@ + cooling-maps { + map0 { + trip = <&cpu0_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -875,10 +875,10 @@ + cooling-maps { + map0 { + trip = <&cpu1_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -905,10 +905,10 @@ + cooling-maps { + map0 { + trip = <&cpu2_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -935,10 +935,10 @@ + cooling-maps { + map0 { + trip = <&cpu3_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; diff --git a/target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch b/target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch index a3c5f344a..a6265ff00 100644 --- a/target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch +++ b/target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch @@ -23,37 +23,37 @@ Signed-off-by: Robert Marko #address-cells = <2>; @@ -38,6 +39,8 @@ reg = <0x0>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; enable-method = "psci"; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU1: cpu@1 { + cpu1: cpu@1 { @@ -46,6 +49,8 @@ enable-method = "psci"; reg = <0x1>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU2: cpu@2 { + cpu2: cpu@2 { @@ -54,6 +59,8 @@ enable-method = "psci"; reg = <0x2>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - CPU3: cpu@3 { + cpu3: cpu@3 { @@ -62,6 +69,8 @@ enable-method = "psci"; reg = <0x3>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; }; - L2_0: l2-cache { + l2_0: l2-cache { diff --git a/target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch b/target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch index 3520b3813..bea358045 100644 --- a/target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch +++ b/target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch @@ -21,28 +21,28 @@ Signed-off-by: Robert Marko + #cooling-cells = <2>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { @@ -51,6 +52,7 @@ - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + #cooling-cells = <2>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { @@ -61,6 +63,7 @@ - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + #cooling-cells = <2>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { @@ -71,6 +74,7 @@ - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; + #cooling-cells = <2>; }; - L2_0: l2-cache { + l2_0: l2-cache { diff --git a/target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch b/target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch index a89e50f52..9de502c4c 100644 --- a/target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch +++ b/target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch @@ -20,7 +20,7 @@ Signed-off-by: Robert Marko + operating-points-v2 = <&cpu_opp_table>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { @@ -53,6 +54,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; @@ -28,7 +28,7 @@ Signed-off-by: Robert Marko + operating-points-v2 = <&cpu_opp_table>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { @@ -64,6 +66,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; @@ -36,7 +36,7 @@ Signed-off-by: Robert Marko + operating-points-v2 = <&cpu_opp_table>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { @@ -75,6 +78,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; @@ -44,7 +44,7 @@ Signed-off-by: Robert Marko + operating-points-v2 = <&cpu_opp_table>; }; - L2_0: l2-cache { + l2_0: l2-cache { @@ -84,6 +88,54 @@ }; };