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generic: 6.1: drop outdated patches
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lunatickochiya
parent
61e557fee9
commit
5a0e9d95e4
@ -16,10 +16,10 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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select HAVE_UID16
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select HAVE_UID16
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select IRQ_FORCED_THREADING
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select IRQ_FORCED_THREADING
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select LOCK_MM_AND_FIND_VMA
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+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
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+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
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select MODULES_USE_ELF_REL
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select MODULES_USE_ELF_REL
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select NEED_DMA_MAP_STATE
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select NEED_DMA_MAP_STATE
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select OF_EARLY_FLATTREE if OF
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--- a/arch/arm/boot/compressed/Makefile
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--- a/arch/arm/boot/compressed/Makefile
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+++ b/arch/arm/boot/compressed/Makefile
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+++ b/arch/arm/boot/compressed/Makefile
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@@ -91,6 +91,7 @@ endif
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@@ -91,6 +91,7 @@ endif
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@ -1,54 +0,0 @@
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From 3b6c472822f8bdeaa3cea8290f5b4a210dca5585 Mon Sep 17 00:00:00 2001
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From: Ulf Hansson <ulf.hansson@linaro.org>
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Date: Thu, 3 Mar 2022 17:45:22 +0100
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Subject: [PATCH] mmc: core: Improve fallback to speed modes if eMMC HS200
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fails
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In the error path of mmc_select_hs200() we are trying our best to restore
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the card/host into a valid state. This makes sense, especially if we
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encounter a simple switch error (-EBADMSG). However, rather than then
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continue with using the legacy speed mode, let's try the other better speed
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modes first. Additionally, let's update the card->mmc_avail_type to avoid
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us from trying a broken HS200 mode again.
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In an Amlogic S905W based TV box where the switch to HS200 mode fails for
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the eMMC, this allows us to use the eMMC in DDR mode in favor of the legacy
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mode, which greatly improves the performance.
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Suggested-by: Heiner Kallweit <hkallweit1@gmail.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Tested-by: Heiner Kallweit <hkallweit1@gmail.com>
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Link: https://lore.kernel.org/r/20220303164522.129583-1-ulf.hansson@linaro.org
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---
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drivers/mmc/core/mmc.c | 16 +++++++++++++---
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1 file changed, 13 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/core/mmc.c
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+++ b/drivers/mmc/core/mmc.c
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@@ -1530,13 +1530,23 @@ static int mmc_select_timing(struct mmc_
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if (!mmc_can_ext_csd(card))
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goto bus_speed;
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- if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES)
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+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES) {
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err = mmc_select_hs400es(card);
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- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)
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+ goto out;
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+ }
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+
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+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) {
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err = mmc_select_hs200(card);
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- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
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+ if (err == -EBADMSG)
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+ card->mmc_avail_type &= ~EXT_CSD_CARD_TYPE_HS200;
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+ else
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+ goto out;
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+ }
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+
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+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
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err = mmc_select_hs(card);
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+out:
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if (err && err != -EBADMSG)
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return err;
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@ -1,40 +0,0 @@
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From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
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From: Andrew Powers-Holmes <aholmes@omnom.net>
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Date: Sat, 12 Nov 2022 22:41:26 +1100
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Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
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range mappings
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The register and range mappings for the PCIe controller in Rockchip's
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RK356x SoCs are incorrect. Replace them with corrected values from the
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vendor BSP sources, updated to match current DT schema.
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Tested-by: Ondrej Jirman <megi@xff.cz>
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Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
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2 files changed, 12 insertions(+), 9 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -708,7 +708,7 @@
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0000000 0x0 0x00400000>,
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<0x0 0xfe260000 0x0 0x00010000>,
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- <0x3 0x3f000000 0x0 0x01000000>;
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+ <0x0 0xf4000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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@@ -738,8 +738,9 @@
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
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- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
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+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
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+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
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resets = <&cru SRST_PCIE20_POWERUP>;
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reset-names = "pipe";
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#address-cells = <3>;
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@ -1,40 +0,0 @@
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From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
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From: Andrew Powers-Holmes <aholmes@omnom.net>
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Date: Sat, 12 Nov 2022 22:41:26 +1100
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Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
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range mappings
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The register and range mappings for the PCIe controller in Rockchip's
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RK356x SoCs are incorrect. Replace them with corrected values from the
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vendor BSP sources, updated to match current DT schema.
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Tested-by: Ondrej Jirman <megi@xff.cz>
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Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
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2 files changed, 12 insertions(+), 9 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -952,7 +952,7 @@
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0000000 0x0 0x00400000>,
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<0x0 0xfe260000 0x0 0x00010000>,
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- <0x3 0x3f000000 0x0 0x01000000>;
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+ <0x0 0xf4000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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@@ -982,8 +982,9 @@
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
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- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
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+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
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+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
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resets = <&cru SRST_PCIE20_POWERUP>;
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reset-names = "pipe";
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#address-cells = <3>;
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