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rockchip: add FastRhino R66S support in kernel 5.19

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This commit is contained in:
coolsnowwolf 2022-08-10 04:19:14 +00:00
parent 27befb47d9
commit 595bf71b39
7 changed files with 837 additions and 68 deletions
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2
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -10,6 +10,7 @@ rockchip_setup_interfaces()
case "$board" in
embedfire,doornet1|\
embedfire,doornet2|\
fastrhino,r66s|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
friendlyarm,nanopi-r4s|\
@ -45,6 +46,7 @@ rockchip_setup_macs()
case "$board" in
embedfire,doornet1|\
embedfire,doornet2|\
fastrhino,r66s|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
sharevdi,guangmiao-g4c)

531
target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts Normal file
View File

@ -0,0 +1,531 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568.dtsi"
/ {
model = "FastRhino R66S";
compatible = "fastrhino,r66s", "rockchip,rk3568";
aliases {
ethernet0 = &rtl8125_1;
ethernet1 = &rtl8125_2;
led-boot = &power_led;
led-failsafe = &power_led;
led-running = &power_led;
led-upgrade = &power_led;
mmc0 = &sdmmc0;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&power_led_pin>;
power_led: led-power {
label = "green:power";
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&reset_button_pin>;
reset {
debounce-interval = <50>;
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_pcie: gpio-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_sys";
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
regulator-always-on;
regulator-boot-on;
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-init-microvolt = <950000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@10 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
};
};
};
&pcie3x2 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@20 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
};
};
};
&pinctrl {
gpio-leds {
power_led_pin: power-led-pin {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rockchip-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdmmc0 {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
dr_mode = "host";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};

45
target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt Normal file
View File

@ -0,0 +1,45 @@
Rockchip Hardware Random Number Generator
Required properties:
- compatible : should be one of the following.
"rockchip,cryptov1-rng" for crypto v1
"rockchip,cryptov2-rng" for crypto v2
"rockchip,trngv1" for independent trng, such as rk3588.
- reg : Specifies base physical address and size of the registers map.
- clocks : Phandle to clock-controller plus clock-specifier pair.
- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.
- assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>
- assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
<200000000>, <100000000>
- resets : Used for module reset
- reset-names : Reset names, should be "reset"
Example:
rng: rng@100fc000 {
compatible = "rockchip,cryptov1-rng";
reg = <0x100fc000 0x4000>;
clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
clock-names = "clk_crypto", "hclk_crypto";
assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
assigned-clock-rates = <150000000>, <100000000>;
resets = <&cru SRST_CRYPTO>;
reset-names = "reset";
status = "disabled";
};
rng: rng@ff2f0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff2f0000 0x0 0x4000>;
clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
clock-names = "clk_crypto", "clk_crypto_apk",
"aclk_crypto", "hclk_crypto";
assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
assigned-clock-rates = <150000000>, <150000000>,
<200000000>, <100000000>;
resets = <&cru SRST_CRYPTO>;
reset-names = "reset";
};

283
target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c
View File

@ -21,7 +21,7 @@
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
#define ROCKCHIP_POLL_PERIOD_US 100
#define ROCKCHIP_POLL_TIMEOUT_US 10000
#define ROCKCHIP_POLL_TIMEOUT_US 50000
#define RK_MAX_RNG_BYTE (32)
/* start of CRYPTO V1 register define */
@ -37,7 +37,8 @@
/* end of CRYPTO V1 register define */
/* start of CRYPTO V2 register define */
#define CRYPTO_V2_RNG_CTL 0x0400
#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400
#define CRYPTO_V2_RNG_CTL 0x0
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
@ -48,13 +49,48 @@
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
#define CRYPTO_V2_RNG_ENABLE BIT(1)
#define CRYPTO_V2_RNG_START BIT(0)
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
#define CRYPTO_V2_RNG_DOUT_0 0x0410
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004
#define CRYPTO_V2_RNG_DOUT_0 0x0010
/* end of CRYPTO V2 register define */
/* start of TRNG_V1 register define */
/* TRNG is no longer subordinate to the Crypto module */
#define TRNG_V1_CTRL 0x0000
#define TRNG_V1_CTRL_NOP _SBF(0, 0x00)
#define TRNG_V1_CTRL_RAND _SBF(0, 0x01)
#define TRNG_V1_CTRL_SEED _SBF(0, 0x02)
#define TRNG_V1_STAT 0x0004
#define TRNG_V1_STAT_SEEDED BIT(9)
#define TRNG_V1_STAT_GENERATING BIT(30)
#define TRNG_V1_STAT_RESEEDING BIT(31)
#define TRNG_V1_MODE 0x0008
#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00)
#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01)
#define TRNG_V1_IE 0x0010
#define TRNG_V1_IE_GLBL_EN BIT(31)
#define TRNG_V1_IE_SEED_DONE_EN BIT(1)
#define TRNG_V1_IE_RAND_RDY_EN BIT(0)
#define TRNG_V1_ISTAT 0x0014
#define TRNG_V1_ISTAT_RAND_RDY BIT(0)
/* RAND0 ~ RAND7 */
#define TRNG_V1_RAND0 0x0020
#define TRNG_V1_RAND7 0x003C
#define TRNG_V1_AUTO_RQSTS 0x0060
#define TRNG_V1_VERSION 0x00F0
#define TRNG_v1_VERSION_CODE 0x46bc
/* end of TRNG_V1 register define */
struct rk_rng_soc_data {
const char * const *clks;
int clks_num;
u32 default_offset;
int (*rk_rng_init)(struct hwrng *rng);
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
};
@ -63,22 +99,10 @@ struct rk_rng {
struct hwrng rng;
void __iomem *mem;
struct rk_rng_soc_data *soc_data;
u32 clk_num;
int clk_num;
struct clk_bulk_data *clk_bulks;
};
static const char * const rk_rng_v1_clks[] = {
"hclk_crypto",
"clk_crypto",
};
static const char * const rk_rng_v2_clks[] = {
"hclk_crypto",
"aclk_crypto",
"clk_crypto",
"clk_crypto_apk",
};
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
{
__raw_writel(val, rng->mem + offset);
@ -113,6 +137,38 @@ static void rk_rng_cleanup(struct hwrng *rng)
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
}
static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret;
int read_len = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
if (!rk_rng->soc_data->rk_rng_read)
return -EFAULT;
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
ret = 0;
while (max > ret) {
read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
max - ret, wait);
if (read_len < 0) {
ret = read_len;
break;
}
ret += read_len;
}
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
size_t size)
{
@ -122,18 +178,12 @@ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
}
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
/* enable osc_ring to get entropy, sample period is set as 100 */
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
@ -158,24 +208,15 @@ out:
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
CRYPTO_V1_CTRL);
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
/* enable osc_ring to get entropy, sample period is set as 100 */
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
@ -202,32 +243,139 @@ out:
/* close TRNG */
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
return ret;
}
static int rk_trng_v1_init(struct hwrng *rng)
{
int ret;
uint32_t auto_reseed_cnt = 1000;
uint32_t reg_ctrl, status, version;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
ret = pm_runtime_get_sync(rk_rng->dev);
if (ret < 0) {
pm_runtime_put_noidle(rk_rng->dev);
return ret;
}
version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
if (version != TRNG_v1_VERSION_CODE) {
dev_err(rk_rng->dev,
"wrong trng version, expected = %08x, actual = %08x\n",
TRNG_V1_VERSION, version);
ret = -EFAULT;
goto exit;
}
status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
if (!(status & TRNG_V1_STAT_SEEDED) ||
(status & TRNG_V1_STAT_GENERATING) ||
(status & TRNG_V1_STAT_RESEEDING)) {
uint32_t mask = TRNG_V1_STAT_SEEDED |
TRNG_V1_STAT_GENERATING |
TRNG_V1_STAT_RESEEDING;
udelay(10);
/* wait for GENERATING and RESEEDING flag to clear */
readl_poll_timeout(rk_rng->mem + TRNG_V1_STAT, reg_ctrl,
(reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US);
}
/* clear ISTAT flag because trng may auto reseeding when power on */
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
ret = 0;
exit:
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
.clks_num = ARRAY_SIZE(rk_rng_v1_clks),
.clks = rk_rng_v1_clks,
.rk_rng_read = rk_rng_v1_read,
static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
/* clear ISTAT anyway */
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
/* generate 256bit random */
rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
/*
* Generate2 56 bit random data will cost 1024 clock cycles.
* Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
*/
udelay(10);
reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
/* wait RAND_RDY triggered */
ret = readl_poll_timeout(rk_rng->mem + TRNG_V1_ISTAT, reg_ctrl,
(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
ROCKCHIP_POLL_PERIOD_US,
ROCKCHIP_POLL_TIMEOUT_US);
if (ret < 0)
goto out;
}
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
/* clear all status flag */
rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
out:
/* close TRNG */
rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
return ret;
}
static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
.default_offset = 0,
.rk_rng_read = rk_crypto_v1_read,
};
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
.clks_num = ARRAY_SIZE(rk_rng_v2_clks),
.clks = rk_rng_v2_clks,
.rk_rng_read = rk_rng_v2_read,
static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
.rk_rng_read = rk_crypto_v2_read,
};
static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
.default_offset = 0,
.rk_rng_init = rk_trng_v1_init,
.rk_rng_read = rk_trng_v1_read,
};
static const struct of_device_id rk_rng_dt_match[] = {
{
.compatible = "rockchip,cryptov1-rng",
.data = (void *)&rk_rng_v1_soc_data,
.data = (void *)&rk_crypto_v1_soc_data,
},
{
.compatible = "rockchip,cryptov2-rng",
.data = (void *)&rk_rng_v2_soc_data,
.data = (void *)&rk_crypto_v2_soc_data,
},
{
.compatible = "rockchip,trngv1",
.data = (void *)&rk_trng_v1_soc_data,
},
{ },
};
@ -236,11 +384,11 @@ MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
static int rk_rng_probe(struct platform_device *pdev)
{
int i;
int ret;
struct rk_rng *rk_rng;
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
resource_size_t map_size;
dev_dbg(&pdev->dev, "probing...\n");
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
@ -256,27 +404,31 @@ static int rk_rng_probe(struct platform_device *pdev)
rk_rng->rng.init = rk_rng_init;
rk_rng->rng.cleanup = rk_rng_cleanup,
#endif
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
rk_rng->rng.quality = 1000;
rk_rng->rng.read = rk_rng_read;
rk_rng->rng.quality = 999;
rk_rng->clk_bulks =
devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
rk_rng->soc_data->clks_num, GFP_KERNEL);
rk_rng->clk_num = rk_rng->soc_data->clks_num;
for (i = 0; i < rk_rng->soc_data->clks_num; i++)
rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
if (IS_ERR(rk_rng->mem))
return PTR_ERR(rk_rng->mem);
ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
rk_rng->clk_bulks);
if (ret) {
/* compatible with crypto v2 module */
/*
* With old dtsi configurations, the RNG base was equal to the crypto
* base, so both drivers could not be enabled at the same time.
* RNG base = CRYPTO base + RNG offset
* (Since RK356X, RNG module is no longer belongs to CRYPTO module)
*
* With new dtsi configurations, CRYPTO regs is divided into two parts
* |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
* RNG driver and CRYPTO driver could be enabled at the same time.
*/
if (map_size > rk_rng->soc_data->default_offset)
rk_rng->mem += rk_rng->soc_data->default_offset;
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
if (rk_rng->clk_num < 0) {
dev_err(&pdev->dev, "failed to get clks property\n");
return ret;
return -ENODEV;
}
platform_set_drvdata(pdev, rk_rng);
@ -292,6 +444,10 @@ static int rk_rng_probe(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
}
/* for some platform need hardware operation when probe */
if (rk_rng->soc_data->rk_rng_init)
ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
return ret;
}
@ -337,4 +493,3 @@ module_platform_driver(rk_rng_driver);
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
MODULE_LICENSE("GPL v2");

11
target/linux/rockchip/image/armv8.mk
View File

@ -22,6 +22,17 @@ define Device/embedfire_doornet2
endef
TARGET_DEVICES += embedfire_doornet2
define Device/fastrhino-r66s
DEVICE_VENDOR := FastRhino
DEVICE_MODEL := R66S
SOC := rk3568
UBOOT_DEVICE_NAME := fastrhino-r66s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8125
SUPPORTED_DEVICES := fastrhino,r66s
endef
TARGET_DEVICES += fastrhino-r66s
define Device/friendlyarm_nanopi-neo3
DEVICE_VENDOR := FriendlyARM
DEVICE_MODEL := NanoPi NEO3

21
target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
reg = <0x0 0xff100000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2042,6 +2042,16 @@
@@ -1937,6 +1937,16 @@
};
};
@ -48,3 +48,22 @@ Signed-off-by: wevsty <ty@wevs.org>
gpu: gpu@ff9a0000 {
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
reg = <0x0 0xff9a0000 0x0 0x10000>;
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi 2022-08-09 00:09:02.289032224 +0800
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi 2022-08-09 00:11:01.829992919 +0800
@@ -89,6 +89,16 @@
};
};
+ rng: rng@fe388000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xfe388000 0x0 0x2000>;
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+ clock-names = "clk_trng", "hclk_trng";
+ resets = <&cru SRST_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
combphy0: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;

6
target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
View File

@ -32,3 +32,9 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
@@ -65,4 +65,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb