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https://github.com/coolsnowwolf/lede.git
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update ath10k firmware
This commit is contained in:
coolsnowwolf
parent
ad7e29070e
commit
246241f742
@ -8,9 +8,9 @@
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include $(TOPDIR)/rules.mk
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PKG_NAME:=ath10k-firmware
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PKG_SOURCE_DATE:=2018-02-09
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PKG_SOURCE_VERSION:=8f4bafdd400d21a65966004d0ce6e0686ef4d9bc
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PKG_MIRROR_HASH:=4f4f0678b9d07c0282f18c69bd63a5e2a2ae015b9ce7298cedb88a60be87ed3a
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PKG_SOURCE_DATE:=2018-04-19
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PKG_SOURCE_VERSION:=71e50312b54cc972657a7b08c470088447cb9676
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PKG_MIRROR_HASH:=726e7bce9917532e3b39ced6a17ca2d4c39fdf4c9bec4a3f8f2ea3e5defa6a54
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PKG_RELEASE:=1
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PKG_SOURCE_PROTO:=git
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@ -0,0 +1,41 @@
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From 7eb6313910023f1be6015a8cd9e1b380ae01af64 Mon Sep 17 00:00:00 2001
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From: Chen Minqiang <ptpt52@gmail.com>
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Date: Sun, 7 Jan 2018 14:38:36 +0800
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Subject: [PATCH] custom fix txpower and dfs
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---
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db.txt | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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diff --git a/db.txt b/db.txt
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index 75dc0a3..24989ad 100644
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--- a/db.txt
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+++ b/db.txt
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@@ -277,9 +277,9 @@ country CL: DFS-JP
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(5735 - 5835 @ 80), (20)
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country CN: DFS-FCC
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- (2402 - 2482 @ 40), (20)
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- (5170 - 5250 @ 80), (23), AUTO-BW
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- (5250 - 5330 @ 80), (23), DFS, AUTO-BW
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+ (2402 - 2482 @ 40), (30)
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+ (5170 - 5250 @ 80), (30), AUTO-BW
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+ (5250 - 5330 @ 80), (30), AUTO-BW
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(5735 - 5835 @ 80), (30)
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# 60 GHz band channels 1,4: 28dBm, channels 2,3: 44dBm
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# ref: http://www.miit.gov.cn/n11293472/n11505629/n11506593/n11960250/n11960606/n11960700/n12330791.files/n12330790.pdf
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@@ -1238,9 +1238,9 @@ country UG: DFS-FCC
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country US: DFS-FCC
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(2402 - 2472 @ 40), (30)
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# 5.15 ~ 5.25 GHz: 30 dBm for master mode, 23 dBm for clients
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- (5170 - 5250 @ 80), (23), AUTO-BW
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- (5250 - 5330 @ 80), (23), DFS, AUTO-BW
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- (5490 - 5730 @ 160), (23), DFS
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+ (5170 - 5250 @ 80), (30), AUTO-BW
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+ (5250 - 5330 @ 80), (30), AUTO-BW
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+ (5490 - 5730 @ 160), (30)
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(5735 - 5835 @ 80), (30)
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# 60g band
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# reference: http://cfr.regstoday.com/47cfr15.aspx#47_CFR_15p255
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--
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2.7.4
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@ -0,0 +1,240 @@
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "qcom-ipq4019.dtsi"
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#include "qcom-ipq4019-bus.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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model = "OpenMesh A62";
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compatible = "openmesh,a62", "qcom,ipq4019";
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soc {
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mdio@90000 {
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status = "okay";
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};
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ess-psgmii@98000 {
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status = "okay";
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};
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tcsr@194b000 {
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/* select hostmode */
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compatible = "qcom,tcsr";
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reg = <0x194b000 0x100>;
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qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
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status = "okay";
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};
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tcsr@1949000 {
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compatible = "qcom,tcsr";
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reg = <0x1949000 0x100>;
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
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};
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ess_tcsr@1953000 {
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compatible = "qcom,tcsr";
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reg = <0x1953000 0x1000>;
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
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};
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tcsr@1957000 {
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compatible = "qcom,tcsr";
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reg = <0x1957000 0x100>;
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
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};
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usb2: usb2@60f8800 {
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status = "okay";
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};
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serial@78af000 {
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pinctrl-0 = <&serial_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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crypto@8e3a000 {
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status = "okay";
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};
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watchdog@b017000 {
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status = "okay";
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};
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ess-switch@c000000 {
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switch_lan_bmp = <0x10>;
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switch_wan_bmp = <0x20>;
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status = "okay";
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};
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edma@c080000 {
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status = "okay";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART >;
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};
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};
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aliases {
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led-boot = &power;
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led-failsafe = &power;
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led-running = &power;
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led-upgrade = &power;
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};
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gpio-leds {
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compatible = "gpio-leds";
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red {
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label = "a62:red:status";
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gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-off";
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};
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power: green {
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label = "a62:green:status";
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gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
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};
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blue {
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label = "a62:blue:status";
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gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-off";
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};
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};
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watchdog {
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compatible = "linux,wdt-gpio";
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gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
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hw_algo = "toggle";
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/* hw_margin_ms is actually 300s but driver limits it to 60s */
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hw_margin_ms = <60000>;
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always-running;
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};
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};
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&tlmm {
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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spi_0_pins: spi_0_pinmux {
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pin {
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function = "blsp_spi0";
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pins = "gpio13", "gpio14", "gpio15";
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drive-strength = <12>;
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bias-disable;
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};
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pin_cs {
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function = "gpio";
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pins = "gpio12";
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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enable-usb-power {
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gpio-hog;
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gpios = <58 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "enable USB2 power";
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};
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};
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&blsp_dma {
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status = "okay";
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};
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&spi_0 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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/* partitions are passed via bootloader */
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};
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};
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&cryptobam {
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status = "okay";
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};
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&gmac0 {
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qcom,phy_mdio_addr = <3>;
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qcom,poll_required = <1>;
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qcom,forced_speed = <1000>;
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qcom,forced_duplex = <1>;
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vlan_tag = <1 0x10>;
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};
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&usb2_hs_phy {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
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wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ath10k@0,0 {
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compatible = "qcom,ath10k";
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status = "okay";
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reg = <0 0 0 0 0>;
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device_type = "pci";
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qcom,ath10k-calibration-variant = "OM-A62";
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};
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};
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};
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&wifi0 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A62";
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};
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&wifi1 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A62";
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};
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@ -0,0 +1,103 @@
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Thu, 12 Apr 2018 21:01:38 +0200
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Subject: [PATCH] pinctrl: msm: fix gpio-hog related boot issues
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Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
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Setting up any gpio-hog in the device-tree for his device would
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"kill the bootup completely":
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| [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
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| [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
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| [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
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| [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
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| [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
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| [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
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| [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
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This was also verified on a RT-AC58U (IPQ4018) which would
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no longer boot, if a gpio-hog was specified. (Tried forcing
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the USB LED PIN (GPIO0) to high.).
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The problem is that Pinctrl+GPIO registration is currently
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peformed in the following order in pinctrl-msm.c:
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1. pinctrl_register()
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2. gpiochip_add()
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3. gpiochip_add_pin_range()
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The actual error code -517 == -EPROBE_DEFER is coming from
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pinctrl_get_device_gpio_range(), which is called through:
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gpiochip_add
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of_gpiochip_add
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of_gpiochip_scan_gpios
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gpiod_hog
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gpiochip_request_own_desc
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__gpiod_request
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chip->request
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gpiochip_generic_request
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pinctrl_gpio_request
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pinctrl_get_device_gpio_range
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pinctrl_get_device_gpio_range() is unable to find any valid
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pin ranges, since nothing has been added to the pinctrldev_list yet.
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so the range can't be found, and the operation fails with -EPROBE_DEFER.
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This patch fixes the issue by adding the "gpio-ranges" property to
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the pinctrl device node of all upstream Qcom SoC. The pin ranges are
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then added by the gpio core.
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In order to remain compatible with older, existing DTs (and ACPI)
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a check for the "gpio-ranges" property has been added to
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msm_gpio_init(). This prevents the driver of adding the same entry
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to the pinctrldev_list twice.
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Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Origin: other, https://patchwork.kernel.org/patch/10339127/
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
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drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++-----
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14 files changed, 32 insertions(+), 6 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -166,6 +166,7 @@
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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+ gpio-ranges = <&tlmm 0 0 100>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -831,11 +831,24 @@ static int msm_gpio_init(struct msm_pinc
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return ret;
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}
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- ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
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- if (ret) {
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- dev_err(pctrl->dev, "Failed to add pin range\n");
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- gpiochip_remove(&pctrl->chip);
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- return ret;
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+ /*
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+ * For DeviceTree-supported systems, the gpio core checks the
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+ * pinctrl's device node for the "gpio-ranges" property.
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+ * If it is present, it takes care of adding the pin ranges
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+ * for the driver. In this case the driver can skip ahead.
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+ *
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+ * In order to remain compatible with older, existing DeviceTree
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+ * files which don't set the "gpio-ranges" property or systems that
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+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
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+ */
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+ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
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+ ret = gpiochip_add_pin_range(&pctrl->chip,
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+ dev_name(pctrl->dev), 0, 0, chip->ngpio);
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+ if (ret) {
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+ dev_err(pctrl->dev, "Failed to add pin range\n");
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+ gpiochip_remove(&pctrl->chip);
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+ return ret;
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+ }
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}
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ret = gpiochip_irqchip_add(chip,
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