rockchip: revert to origin defaults

The current target code is too chaotic, the patches are
messy and disorderly, and there are still many duplicate
code. Pack it back to half a year ago.

package/boot/uboot-rockchip/Makefile

@@ -1,6 +1,6 @@
 #
 # This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information. 
+# See /LICENSE for more information.
 #
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
@@ -69,36 +69,14 @@ define U-Boot/orangepi-r1-plus-lts-rk3328
   USE_RKBIN:=1
 endef
 
-define U-Boot/doornet1-rk3328
-  BUILD_SUBTARGET:=armv8
-  NAME:=DoorNet1
-  BUILD_DEVICES:= \
-    embedfire_doornet1
-  DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328
-  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
-  ATF:=rk322xh_bl31_v1.49.elf
-  USE_RKBIN:=1
-endef
 
 # RK3399 boards
 
-define U-Boot/doornet2-rk3399
-  BUILD_SUBTARGET:=armv8
-  NAME:=DoorNet2
-  BUILD_DEVICES:= \
-    embedfire_doornet2
-  DEPENDS:=+PACKAGE_u-boot-doornet2-rk3399:arm-trusted-firmware-rk3399
-  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
-  ATF:=rk3399_bl31_v1.35.elf
-  USE_RKBIN:=1
-endef
-
 define U-Boot/guangmiao-g4c-rk3399
   BUILD_SUBTARGET:=armv8
   NAME:=GuangMiao G4C
   BUILD_DEVICES:= \
-    sharevdi_guangmiao-g4c \
+    sharevdi_guangmiao-g4c
-    embedfire_doornet2-4gb
   DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip
   PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
   ATF:=rk3399_bl31.elf
@@ -126,39 +104,17 @@ define U-Boot/nanopi-r4se-rk3399
   USE_RKBIN:=1
 endef
 
-define U-Boot/fastrhino-r66s-rk3568
-  BUILD_SUBTARGET:=armv8
-  NAME:=FastRhin-R66S
-  BUILD_DEVICES:= \
-    fastrhino_r66s
-  DEPENDS:=+PACKAGE_u-boot-fastrhino-r66s-rk3568:arm-trusted-firmware-rk3568
-  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
-  ATF:=rk3568_bl31_v1.28.elf
-  DDR:=rk3568_ddr_1560MHz_v1.13.bin
-endef
-
 define U-Boot/nanopi-r5s-rk3568
   BUILD_SUBTARGET:=armv8
-  NAME:=NANOPI-R5S
+  NAME:=NanoPi R5S
   BUILD_DEVICES:= \
-    friendlyelec_nanopi-r5s
+    friendlyarm_nanopi-r5s
   DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
   PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
   ATF:=rk3568_bl31_v1.28.elf
   DDR:=rk3568_ddr_1560MHz_v1.13.bin
 endef
 
-define U-Boot/rock-3a-rk3568
-  BUILD_SUBTARGET:=armv8
-  NAME:=ROCK-3A
-  BUILD_DEVICES:= \
-    radxa_rock-3a
-  DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568
-  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
-  ATF:=rk3568_bl31_v1.28.elf
-  DDR:=rk3568_ddr_1560MHz_v1.13.bin
-endef
-
 define U-Boot/rock-pi-4-rk3399
   BUILD_SUBTARGET:=armv8
   NAME:=Rock Pi 4
@@ -179,33 +135,17 @@ define U-Boot/rockpro64-rk3399
   ATF:=rk3399_bl31.elf
 endef
 
-define U-Boot/station-p2-rk3568
-  BUILD_SUBTARGET:=armv8
-  NAME:=StationP2
-  BUILD_DEVICES:= \
-       firefly_station-p2
-  DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568
-  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
-  ATF:=rk3568_bl31_v1.28.elf
-  DDR:=rk3568_ddr_1560MHz_v1.13.bin
-endef
-
 UBOOT_TARGETS := \
-  doornet2-rk3399 \
-  fastrhino-r66s-rk3568 \
   guangmiao-g4c-rk3399 \
   nanopi-r4s-rk3399 \
   nanopi-r4se-rk3399 \
   nanopi-r5s-rk3568 \
-  rock-3a-rk3568 \
   rock-pi-4-rk3399 \
   rockpro64-rk3399 \
-  doornet1-rk3328 \
   nanopi-r2c-rk3328 \
   nanopi-r2s-rk3328 \
   orangepi-r1-plus-rk3328 \
-  orangepi-r1-plus-lts-rk3328 \
+  orangepi-r1-plus-lts-rk3328
-  station-p2-rk3568
 
 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
 

package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch

@@ -1,92 +0,0 @@
---- /dev/null
-+++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
-+ */
-+
-+#include "rk3568-u-boot.dtsi"
-+
-+/ {
-+	chosen {
-+		stdout-path = &uart2;
-+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
-+	};
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	u-boot,dm-spl;
-+	u-boot,spl-fifo-mode;
-+};
-+
-+&uart2 {
-+	clock-frequency = <24000000>;
-+	u-boot,dm-spl;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/arch/arm/dts/rk3568-fastrhino-r66s.dts
-@@ -0,0 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3568-evb.dts"
-+
-+/ {
-+	model = "FastRhino R66S";
-+	compatible = "fastrhino,r66s", "rockchip,rk3568";
-+};
---- /dev/null
-+++ b/board/fastrhino/fastrhino-r66s-rk3568/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_FASTRHINO_R66S_RK3568
-+
-+config SYS_BOARD
-+	default "fastrhino-r66s-rk3568"
-+
-+config SYS_VENDOR
-+	default "fastrhino"
-+
-+config SYS_CONFIG_NAME
-+	default "fastrhino-r66s-rk3568"
-+
-+config BOARD_SPECIFIC_OPTIONS # dummy
-+	def_bool y
-+
-+endif
---- /dev/null
-+++ b/board/fastrhino/fastrhino-r66s-rk3568/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier:     GPL-2.0+
-+#
-+
-+obj-y	+= fastrhino-r66s-rk3568.o
---- /dev/null
-+++ b/board/fastrhino/fastrhino-r66s-rk3568/fastrhino-r66s-rk3568.c
-@@ -0,0 +1,4 @@
-+ // SPDX-License-Identifier: GPL-2.0+
-+/*
-+ *
-+ */
---- /dev/null
-+++ b/include/configs/fastrhino-r66s-rk3568.h
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+
-+#ifndef __FASTRHINO_R66S_RK3568_H
-+#define __FASTRHINO_R66S_RK3568_H
-+
-+#include <configs/rk3568_common.h>
-+
-+#define CONFIG_SUPPORT_EMMC_RPMB
-+
-+#define ROCKCHIP_DEVICE_SETTINGS \
-+			"stdout=serial,vidconsole\0" \
-+			"stderr=serial,vidconsole\0"
-+
-+#define CONFIG_USB_OHCI_NEW
-+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
-+
-+#endif

package/boot/uboot-rockchip/patches/017-rockchip-rk3568-Add-support-for-Station-P2.patch

@@ -1,78 +0,0 @@
-From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001
-From: huangjf <hjf@t-chip.com.cn>
-Date: Thu, 7 Apr 2022 16:22:56 +0800
-Subject: [PATCH] rockchip: rk3568: Add support for Station P2
-
----
- configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++
- 1 file changed, 59 insertions(+)
- create mode 100644 configs/station-p2-rk3568_defconfig
-
-diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig
-new file mode 100644
-index 0000000000..435be99edf
---- /dev/null
-+++ b/configs/station-p2-rk3568_defconfig
-@@ -0,0 +1,59 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00a00000
-+CONFIG_SPL_LIBCOMMON_SUPPORT=y
-+CONFIG_SPL_LIBGENERIC_SUPPORT=y
-+CONFIG_NR_DRAM_BANKS=2
-+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
-+CONFIG_ROCKCHIP_RK3568=y
-+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_SPL_MMC=y
-+CONFIG_SPL_SERIAL=y
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_TARGET_EVB_RK3568=y
-+CONFIG_DEBUG_UART_BASE=0xFE660000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEBUG_UART=y
-+CONFIG_SYS_LOAD_ADDR=0xc00800
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_SEPARATE_BSS=y
-+CONFIG_SPL_ATF=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+# CONFIG_CMD_SETEXPR is not set
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_OF_LIVE=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_SPL_CLK=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MISC=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_SDMA=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_SPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSRESET=y
-+CONFIG_ERRNO_STR=y
--- 
-2.20.1
-

package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch

@@ -1,549 +0,0 @@
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- 	rk3308-roc-cc.dtb
- 
- dtb-$(CONFIG_ROCKCHIP_RK3328) += \
-+	rk3328-doornet1.dtb \
- 	rk3328-evb.dtb \
- 	rk3328-nanopi-r2s.dtb \
- 	rk3328-roc-cc.dtb \
---- /dev/null
-+++ b/arch/arm/dts/rk3328-doornet1-u-boot.dtsi
-@@ -0,0 +1,46 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
-+ * Copyright (c) 2021 EmbedFire <embedfire@embedfire.com>
-+ */
-+
-+#include "rk3328-u-boot.dtsi"
-+#include "rk3328-sdram-ddr4-666.dtsi"
-+/ {
-+	aliases {
-+		mmc0 = &sdmmc;
-+		mmc1 = &emmc;
-+	};
-+
-+	chosen {
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
-+	};
-+};
-+
-+&gpio0 {
-+	u-boot,dm-spl;
-+};
-+
-+&pinctrl {
-+	u-boot,dm-spl;
-+};
-+
-+&sdmmc0m1_pin {
-+	u-boot,dm-spl;
-+};
-+
-+&pcfg_pull_up_4ma {
-+	u-boot,dm-spl;
-+};
-+
-+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
-+&vcc_sd {
-+	u-boot,dm-spl;
-+};
-+
-+&gmac2io {
-+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	snps,reset-delays-us = <0 10000 50000>;
-+};
-+
---- /dev/null
-+++ b/arch/arm/dts/rk3328-doornet1.dts
-@@ -0,0 +1,385 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/gpio/gpio.h>
-+#include "rk3328.dtsi"
-+
-+/ {
-+	model = "EmbedFire DoorNet1";
-+	compatible = "embedfire,doornet1", "rockchip,rk3328";
-+
-+	chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac_clk: gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	keys {
-+		compatible = "gpio-keys";
-+		pinctrl-0 = <&reset_button_pin>;
-+		pinctrl-names = "default";
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <50>;
-+		};
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+		pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
-+		pinctrl-names = "default";
-+
-+		lan_led: led-0 {
-+			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:green:lan";
-+		};
-+
-+		sys_led: led-1 {
-+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:red:sys";
-+		};
-+
-+		wan_led: led-2 {
-+			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:green:wan";
-+		};
-+	};
-+
-+	vcc_io_sdio: sdmmcio-regulator {
-+		compatible = "regulator-gpio";
-+		enable-active-high;
-+		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
-+		pinctrl-0 = <&sdio_vcc_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vcc_io_sdio";
-+		regulator-always-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-settling-time-us = <5000>;
-+		regulator-type = "voltage";
-+		startup-delay-us = <2000>;
-+		states = <1800000 0x1
-+			  3300000 0x0>;
-+		vin-supply = <&vcc_io_33>;
-+	};
-+
-+	vcc_sd: sdmmc-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+		pinctrl-0 = <&sdmmc0m1_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vcc_sd";
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc_io_33>;
-+	};
-+
-+	vdd_5v: vdd-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&gmac2io {
-+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+	clock_in_out = "input";
-+	phy-handle = <&rtl8211f>;
-+	phy-mode = "rgmii";
-+	phy-supply = <&vcc_io_33>;
-+	pinctrl-0 = <&rgmiim1_pins>;
-+	pinctrl-names = "default";
-+	rx_delay = <0x54>;
-+	snps,aal;
-+	tx_delay = <0x20>;
-+	status = "okay";
-+
-+	mdio {
-+		compatible = "snps,dwmac-mdio";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		rtl8211f: ethernet-phy@1 {
-+			compatible = "ethernet-phy-id001c.c916",
-+				     "ethernet-phy-ieee802.3-c22";
-+			reg = <1>;
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	status = "okay";
-+
-+	rk805: pmic@18 {
-+		compatible = "rockchip,rk805";
-+		reg = <0x18>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		clock-output-names = "xin32k", "rk805-clkout2";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		pinctrl-0 = <&pmic_int_l>;
-+		pinctrl-names = "default";
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vdd_5v>;
-+		vcc2-supply = <&vdd_5v>;
-+		vcc3-supply = <&vdd_5v>;
-+		vcc4-supply = <&vdd_5v>;
-+		vcc5-supply = <&vcc_io_33>;
-+		vcc6-supply = <&vdd_5v>;
-+
-+		regulators {
-+			vdd_log: DCDC_REG1 {
-+				regulator-name = "vdd_log";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vdd_arm: DCDC_REG2 {
-+				regulator-name = "vdd_arm";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <950000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_io_33: DCDC_REG4 {
-+				regulator-name = "vcc_io_33";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc_18: LDO_REG1 {
-+				regulator-name = "vcc_18";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc18_emmc: LDO_REG2 {
-+				regulator-name = "vcc18_emmc";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdd_10: LDO_REG3 {
-+				regulator-name = "vdd_10";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1000000>;
-+				regulator-max-microvolt = <1000000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&io_domains {
-+	pmuio-supply = <&vcc_io_33>;
-+	vccio1-supply = <&vcc_io_33>;
-+	vccio2-supply = <&vcc18_emmc>;
-+	vccio3-supply = <&vcc_io_sdio>;
-+	vccio4-supply = <&vcc_18>;
-+	vccio5-supply = <&vcc_io_33>;
-+	vccio6-supply = <&vcc_io_33>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	button {
-+		reset_button_pin: reset-button-pin {
-+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	ethernet-phy {
-+		eth_phy_reset_pin: eth-phy-reset-pin {
-+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+	};
-+
-+	leds {
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		sys_led_pin: sys-led-pin {
-+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sd {
-+		sdio_vcc_pin: sdio-vcc-pin {
-+			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&pwm2 {
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+	pinctrl-names = "default";
-+	sd-uhs-sdr12;
-+	sd-uhs-sdr25;
-+	sd-uhs-sdr50;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc_sd>;
-+	vqmmc-supply = <&vcc_io_sdio>;
-+	status = "okay";
-+};
-+
-+&emmc {
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	max-frequency = <150000000>;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+	vmmc-supply = <&vcc_io_33>;
-+	vqmmc-supply = <&vcc18_emmc>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <0>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&u2phy {
-+	status = "okay";
-+};
-+
-+&u2phy_host {
-+	status = "okay";
-+};
-+
-+&u2phy_otg {
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb20_otg {
-+	status = "okay";
-+	dr_mode = "host";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
---- /dev/null
-+++ b/configs/doornet1-rk3328_defconfig
-@@ -0,0 +1,99 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_SPL_GPIO_SUPPORT=y
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SYSINFO=y
-+CONFIG_SYS_LOAD_ADDR=0x800800
-+CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-doornet1.dtb"
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_SPL_POWER_SUPPORT=y
-+CONFIG_SPL_ATF=y
-+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-doornet1"
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_SPL_DM_REGULATOR=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_SPL_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSRESET=y
-+# CONFIG_TPL_SYSRESET is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_DWC3=y
-+# CONFIG_USB_DWC3_GADGET is not set
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_TPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y

package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch

@@ -1,984 +0,0 @@
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -121,6 +121,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
- 	rk3368-px5-evb.dtb \
- 
- dtb-$(CONFIG_ROCKCHIP_RK3399) += \
-+	rk3399-doornet2.dtb \
- 	rk3399-evb.dtb \
- 	rk3399-ficus.dtb \
- 	rk3399-firefly.dtb \
---- /dev/null
-+++ b/arch/arm/dts/rk3399-doornet2-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
-+ */
-+
-+#include "rk3399-u-boot.dtsi"
-+#include "rk3399-sdram-lpddr4-100.dtsi"
-+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
-+#include "rk3399-sdram-ddr3-1866.dtsi"
-+
-+/{
-+	aliases {
-+		mmc0 = &sdmmc;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen {
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
-+	};
-+};
-+
-+&sdmmc {
-+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
-+};
-+
---- /dev/null
-+++ b/arch/arm/dts/rk3399-doornet2.dts
-@@ -0,0 +1,122 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3399-doornet2.dtsi"
-+
-+/ {
-+	model = "EmbedFire DoorNet2";
-+	compatible = "embedfire,doornet2", "rockchip,rk3399";
-+
-+	/delete-node/ display-subsystem;
-+
-+	gpio-leds {
-+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+
-+		/delete-node/ status;
-+
-+		lan_led: led-lan {
-+			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-+			label = "green:lan";
-+		};
-+
-+		sys_led: led-sys {
-+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-+			label = "red:sys";
-+			default-state = "on";
-+		};
-+
-+		wan_led: led-wan {
-+			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+			label = "green:wan";
-+		};
-+	};
-+
-+	gpio-keys {
-+		pinctrl-0 = <&reset_button_pin>;
-+
-+		/delete-node/ power;
-+
-+		reset {
-+			debounce-interval = <50>;
-+			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
-+		};
-+	};
-+
-+	vdd_5v: vdd-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+	};
-+};
-+
-+&emmc_phy {
-+	status = "okay";
-+};
-+
-+&i2c4 {
-+	status = "disabled";
-+};
-+
-+&pcie0 {
-+	max-link-speed = <1>;
-+	num-lanes = <1>;
-+	vpcie3v3-supply = <&vcc3v3_sys>;
-+};
-+
-+&pinctrl {
-+	gpio-leds {
-+		/delete-node/ leds-gpio;
-+
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		sys_led_pin: sys-led-pin {
-+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		/delete-node/ power-key;
-+
-+		reset_button_pin: reset-button-pin {
-+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&sdhci {
-+	status = "okay";
-+};
-+
-+&sdio0 {
-+	status = "disabled";
-+};
-+
-+&u2phy0_host {
-+	phy-supply = <&vdd_5v>;
-+};
-+
-+&u2phy1_host {
-+	status = "disabled";
-+};
-+
-+&uart0 {
-+	status = "disabled";
-+};
-+
-+&usbdrd_dwc3_0 {
-+	dr_mode = "host";
-+};
-+
-+&vcc3v3_sys {
-+	vin-supply = <&vcc5v0_sys>;
-+};
-+
---- /dev/null
-+++ b/arch/arm/dts/rk3399-doornet2.dtsi
-@@ -0,0 +1,750 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+
-+/dts-v1/;
-+#include <dt-bindings/input/linux-event-codes.h>
-+#include "rk3399.dtsi"
-+#include "rk3399-opp.dtsi"
-+
-+/ {
-+	chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	clkin_gmac: external-gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "clkin_gmac";
-+		#clock-cells = <0>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-name = "vcc3v3_sys";
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-name = "vcc5v0_sys";
-+		vin-supply = <&vdd_5v>;
-+	};
-+
-+	/* switched by pmic_sleep */
-+	vcc1v8_s3: vcc1v8-s3 {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-name = "vcc1v8_s3";
-+		vin-supply = <&vcc_1v8>;
-+	};
-+
-+	vcc3v0_sd: vcc3v0-sd {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&sdmmc0_pwr_h>;
-+		regulator-always-on;
-+		regulator-min-microvolt = <3000000>;
-+		regulator-max-microvolt = <3000000>;
-+		regulator-name = "vcc3v0_sd";
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	/*
-+	 * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
-+	 * drives the enable pin, but we can't quite model that.
-+	 */
-+	vcca0v9_s3: vcca0v9-s3 {
-+		compatible = "regulator-fixed";
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		regulator-name = "vcca0v9_s3";
-+		vin-supply = <&vcc1v8_s3>;
-+	};
-+
-+	/* As above, actually supplied by vcc3v3_sys */
-+	vcca1v8_s3: vcca1v8-s3 {
-+		compatible = "regulator-fixed";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-name = "vcca1v8_s3";
-+		vin-supply = <&vcc1v8_s3>;
-+	};
-+
-+	vbus_typec: vbus-typec {
-+		compatible = "regulator-fixed";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-name = "vbus_typec";
-+	};
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+		autorepeat;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&power_key>;
-+
-+		power {
-+			debounce-interval = <100>;
-+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
-+			label = "GPIO Key Power";
-+			linux,code = <KEY_POWER>;
-+			wakeup-source;
-+		};
-+	};
-+
-+	leds: gpio-leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&leds_gpio>;
-+
-+		status {
-+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-+			label = "status_led";
-+			linux,default-trigger = "heartbeat";
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk808 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_reg_on_h>;
-+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-+	};
-+};
-+
-+&cpu_b0 {
-+	cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_b1 {
-+	cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_l0 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l1 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l2 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l3 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&emmc_phy {
-+	status = "okay";
-+};
-+
-+&gmac {
-+	assigned-clock-parents = <&clkin_gmac>;
-+	assigned-clocks = <&cru SCLK_RMII_SRC>;
-+	clock_in_out = "input";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
-+	phy-handle = <&rtl8211f>;
-+	phy-mode = "rgmii";
-+	phy-supply = <&vcc3v3_s3>;
-+	tx_delay = <0x28>;
-+	rx_delay = <0x11>;
-+	status = "okay";
-+
-+	mdio {
-+		compatible = "snps,dwmac-mdio";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		rtl8211f: ethernet-phy@1 {
-+			compatible = "ethernet-phy-id001c.c916",
-+				     "ethernet-phy-ieee802.3-c22";
-+			reg = <1>;
-+			interrupt-parent = <&gpio3>;
-+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <30000>;
-+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	ddc-i2c-bus = <&i2c7>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&hdmi_cec>;
-+	status = "okay";
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	clock-frequency = <400000>;
-+	i2c-scl-rising-time-ns = <160>;
-+	i2c-scl-falling-time-ns = <30>;
-+	status = "okay";
-+
-+	vdd_cpu_b: regulator@40 {
-+		compatible = "silergy,syr827";
-+		reg = <0x40>;
-+		fcs,suspend-voltage-selector = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&cpu_b_sleep>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-name = "vdd_cpu_b";
-+		regulator-ramp-delay = <1000>;
-+		vin-supply = <&vcc3v3_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	vdd_gpu: regulator@41 {
-+		compatible = "silergy,syr828";
-+		reg = <0x41>;
-+		fcs,suspend-voltage-selector = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&gpu_sleep>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-name = "vdd_gpu";
-+		regulator-ramp-delay = <1000>;
-+		vin-supply = <&vcc3v3_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk808: pmic@1b {
-+		compatible = "rockchip,rk808";
-+		reg = <0x1b>;
-+		clock-output-names = "xin32k", "rtc_clko_wifi";
-+		#clock-cells = <1>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int_l>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		vcc10-supply = <&vcc3v3_sys>;
-+		vcc11-supply = <&vcc3v3_sys>;
-+		vcc12-supply = <&vcc3v3_sys>;
-+		vddio-supply = <&vcc_3v0>;
-+
-+		regulators {
-+			vdd_center: DCDC_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <750000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-name = "vdd_center";
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_cpu_l: DCDC_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <750000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-name = "vdd_cpu_l";
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc_ddr";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG4 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc_1v8";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc1v8_cam: LDO_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc1v8_cam";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v0_touch: LDO_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcc3v0_touch";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc1v8_pmupll: LDO_REG3 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc1v8_pmupll";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc_sdio: LDO_REG4 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <3000000>;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc_sdio";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3000000>;
-+				};
-+			};
-+
-+			vcca3v0_codec: LDO_REG5 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcca3v0_codec";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v5: LDO_REG6 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1500000>;
-+				regulator-max-microvolt = <1500000>;
-+				regulator-name = "vcc_1v5";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1500000>;
-+				};
-+			};
-+
-+			vcca1v8_codec: LDO_REG7 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcca1v8_codec";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v0: LDO_REG8 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcc_3v0";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3000000>;
-+				};
-+			};
-+
-+			vcc3v3_s3: SWITCH_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc3v3_s3";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_s0: SWITCH_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc3v3_s0";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	clock-frequency = <200000>;
-+	i2c-scl-rising-time-ns = <150>;
-+	i2c-scl-falling-time-ns = <30>;
-+	status = "okay";
-+};
-+
-+&i2c2 {
-+	status = "okay";
-+};
-+
-+&i2c4 {
-+	clock-frequency = <400000>;
-+	i2c-scl-rising-time-ns = <160>;
-+	i2c-scl-falling-time-ns = <30>;
-+	status = "okay";
-+
-+	fusb0: typec-portc@22 {
-+		compatible = "fcs,fusb302";
-+		reg = <0x22>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&fusb0_int>;
-+		vbus-supply = <&vbus_typec>;
-+	};
-+};
-+
-+&i2c7 {
-+	status = "okay";
-+};
-+
-+&i2s2 {
-+	status = "okay";
-+};
-+
-+&io_domains {
-+	bt656-supply = <&vcc_1v8>;
-+	audio-supply = <&vcca1v8_codec>;
-+	sdmmc-supply = <&vcc_sdio>;
-+	gpio1830-supply = <&vcc_3v0>;
-+	status = "okay";
-+};
-+
-+&pcie_phy {
-+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
-+	assigned-clock-rates = <100000000>;
-+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
-+	status = "okay";
-+};
-+
-+&pcie0 {
-+	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-+	max-link-speed = <2>;
-+	num-lanes = <2>;
-+	vpcie0v9-supply = <&vcca0v9_s3>;
-+	vpcie1v8-supply = <&vcca1v8_s3>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	fusb30x {
-+		fusb0_int: fusb0-int {
-+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		leds_gpio: leds-gpio {
-+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	phy {
-+		phy_intb: phy-intb {
-+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
-+		phy_rstb: phy-rstb {
-+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		cpu_b_sleep: cpu-b-sleep {
-+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+
-+		gpu_sleep: gpu-sleep {
-+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		power_key: power-key {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sdio {
-+		bt_host_wake_l: bt-host-wake-l {
-+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_reg_on_h: bt-reg-on-h {
-+			/* external pullup to VCC1V8_PMUPLL */
-+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_wake_l: bt-wake-l {
-+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wifi_reg_on_h: wifi-reg_on-h {
-+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdmmc {
-+		sdmmc0_det_l: sdmmc0-det-l {
-+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
-+		sdmmc0_pwr_h: sdmmc0-pwr-h {
-+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmu1830-supply = <&vcc_3v0>;
-+	status = "okay";
-+};
-+
-+&pwm0 {
-+	status = "okay";
-+};
-+
-+&pwm1 {
-+	status = "okay";
-+};
-+
-+&pwm2 {
-+	pinctrl-names = "active";
-+	pinctrl-0 = <&pwm2_pin_pull_down>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca1v8_s3>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	status = "okay";
-+};
-+
-+&sdio0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
-+	sd-uhs-sdr104;
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-mmc-highspeed;
-+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v0_sd>;
-+	vqmmc-supply = <&vcc_sdio>;
-+	status = "okay";
-+};
-+
-+&tcphy0 {
-+	status = "okay";
-+};
-+
-+&tcphy1 {
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	/* tshut mode 0:CRU 1:GPIO */
-+	rockchip,hw-tshut-mode = <1>;
-+	/* tshut polarity 0:LOW 1:HIGH */
-+	rockchip,hw-tshut-polarity = <1>;
-+	status = "okay";
-+};
-+
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_host {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&u2phy1_host {
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		clocks = <&rk808 1>;
-+		clock-names = "lpo";
-+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
-+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
-+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-+		max-speed = <4000000>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
-+		vbat-supply = <&vcc3v3_sys>;
-+		vddio-supply = <&vcc_1v8>;
-+	};
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usbdrd3_0 {
-+	status = "okay";
-+};
-+
-+&usbdrd3_1 {
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3_0 {
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3_1 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&vopb {
-+	status = "okay";
-+};
-+
-+&vopb_mmu {
-+	status = "okay";
-+};
-+
-+&vopl {
-+	status = "okay";
-+};
-+
-+&vopl_mmu {
-+	status = "okay";
-+};
-+
---- /dev/null
-+++ b/configs/doornet2-rk3399_defconfig
-@@ -0,0 +1,65 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_ROCKCHIP_RK3399=y
-+CONFIG_TARGET_EVB_RK3399=y
-+CONFIG_DEBUG_UART_BASE=0xFF1A0000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEFAULT_DEVICE_TREE="rk3399-doornet2"
-+CONFIG_SYS_LOAD_ADDR=0x800800
-+CONFIG_DEBUG_UART=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-doornet2.dtb"
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-+CONFIG_TPL=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_SYS_MMC_ENV_DEV=1
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM_RK3399_LPDDR4=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSRESET=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_KEYBOARD=y
-+CONFIG_USB_HOST_ETHER=y
-+CONFIG_USB_ETHER_ASIX=y
-+CONFIG_USB_ETHER_ASIX88179=y
-+CONFIG_USB_ETHER_MCS7830=y
-+CONFIG_USB_ETHER_RTL8152=y
-+CONFIG_USB_ETHER_SMSC95XX=y
-+CONFIG_DM_VIDEO=y
-+CONFIG_DISPLAY=y
-+CONFIG_VIDEO_ROCKCHIP=y
-+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
-+

package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch

@@ -0,0 +1,110 @@
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -157,6 +157,7 @@
+ 	rk3399-nanopi-m4b.dtb \
+ 	rk3399-nanopi-neo4.dtb \
+ 	rk3399-nanopi-r4s.dtb \
++	rk3399-nanopi-r4se.dtb \
+ 	rk3399-orangepi.dtb \
+ 	rk3399-pinebook-pro.dtb \
+ 	rk3399-puma-haikou.dtb \
+--- /dev/null
++++ b/arch/arm/dts/rk3399-nanopi-r4se.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * FriendlyElec NanoPC-T4 board device tree source
++ *
++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2018 Collabora Ltd.
++ *
++ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
++ */
++
++/dts-v1/;
++#include "rk3399-nanopi-r4s.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R4SE";
++	compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
+--- /dev/null
++++ b/configs/nanopi-r4se-rk3399_defconfig
+@@ -0,0 +1,65 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
++CONFIG_ROCKCHIP_RK3399=y
++CONFIG_TARGET_EVB_RK3399=y
++CONFIG_DEBUG_UART_BASE=0xFF1A0000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SYS_LOAD_ADDR=0x800800
++CONFIG_DEBUG_UART=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
++CONFIG_TPL=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ROCKCHIP=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM_RK3399_LPDDR4=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_KEYBOARD=y
++CONFIG_USB_HOST_ETHER=y
++CONFIG_USB_ETHER_ASIX=y
++CONFIG_USB_ETHER_ASIX88179=y
++CONFIG_USB_ETHER_MCS7830=y
++CONFIG_USB_ETHER_RTL8152=y
++CONFIG_USB_ETHER_SMSC95XX=y
++CONFIG_DM_VIDEO=y
++CONFIG_DISPLAY=y
++CONFIG_VIDEO_ROCKCHIP=y
++CONFIG_DISPLAY_ROCKCHIP_HDMI=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y

package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch

@@ -1,11 +0,0 @@
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -157,6 +157,8 @@
- 	rk3399-nanopi-m4b.dtb \
- 	rk3399-nanopi-neo4.dtb \
- 	rk3399-nanopi-r4s.dtb \
-+	rk3399-nanopi-r4se.dtb \
-+	rk3568-fastrhino-r66s.dtb \
- 	rk3399-orangepi.dtb \
- 	rk3399-pinebook-pro.dtb \
- 	rk3399-puma-haikou.dtb \

package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts

@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * FriendlyElec NanoPC-T4 board device tree source
- *
- * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2018 Collabora Ltd.
- *
- * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
- * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
- * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
-	model = "FriendlyElec NanoPi R4SE";
-	compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
-
-	/delete-node/ display-subsystem;
-
-	gpio-leds {
-		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-
-		/delete-node/ led-0;
-
-		lan_led: led-lan {
-			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-			label = "green:lan";
-		};
-
-		sys_led: led-sys {
-			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
-			default-state = "on";
-		};
-
-		wan_led: led-wan {
-			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-			label = "green:wan";
-		};
-	};
-
-	gpio-keys {
-		pinctrl-0 = <&reset_button_pin>;
-
-		/delete-node/ power;
-
-		reset {
-			debounce-interval = <50>;
-			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	vdd_5v: vdd-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_5v";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&i2c4 {
-	status = "disabled";
-};
-
-&pcie0 {
-	max-link-speed = <1>;
-	num-lanes = <1>;
-	vpcie3v3-supply = <&vcc3v3_sys>;
-};
-
-&pinctrl {
-	gpio-leds {
-		/delete-node/ status-led-pin;
-
-		lan_led_pin: lan-led-pin {
-			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	rockchip-key {
-		/delete-node/ power-key;
-
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&sdio0 {
-	status = "disabled";
-};
-
-&u2phy0_host {
-	phy-supply = <&vdd_5v>;
-};
-
-&u2phy1_host {
-	status = "disabled";
-};
-
-&uart0 {
-	status = "disabled";
-};
-
-&usbdrd_dwc3_0 {
-	dr_mode = "host";
-};
-
-&vcc3v3_sys {
-	vin-supply = <&vcc5v0_sys>;
-};

package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig

@@ -1,97 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-fastrhino-r66s"
-CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_TARGET_FASTRHINO_R66S_RK3568=y
-CONFIG_DEBUG_UART_BASE=0xFE660000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0xc00800
-CONFIG_API=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
-# CONFIG_SYS_DEVICE_NULLDEV is not set
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
-CONFIG_CMD_BIND=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM_WARN=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_CLK=y
-CONFIG_ROCKCHIP_GPIO=y
-CONFIG_ROCKCHIP_GPIO_V2=y
-CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_SPL_MMC_HS200_SUPPORT=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_SPL_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_REGULATOR_RK8XX=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_SPL_RAM=y
-CONFIG_DM_RESET=y
-CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_ERRNO_STR=y

package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig

@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=24000000
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
-CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
-CONFIG_DEBUG_UART_BASE=0xFF1A0000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_DEBUG_UART=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-CONFIG_TPL=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ROCKCHIP_GPIO=y
-CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_RK8XX=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM_RK3399_LPDDR4=y
-CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYSRESET=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_ASIX88179=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_USB_ETHER_RTL8152=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_DM_VIDEO=y
-CONFIG_DISPLAY=y
-CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y

target/linux/rockchip/Makefile

@@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
 SUBTARGETS:=armv8
 
 KERNEL_PATCHVER=5.15
-KERNEL_TESTING_PATCHVER=5.19
+KERNEL_TESTING_PATCHVER=5.10
 
 define Target/Description
 	Build firmware image for Rockchip SoC devices.
@@ -17,8 +17,7 @@ endef
 include $(INCLUDE_DIR)/target.mk
 
 DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \
-		    automount autocore-arm autosamba fdisk cfdisk e2fsprogs ethtool haveged htop \
+		    automount autocore-arm e2fsprogs ethtool haveged htop usb-modeswitch
-		    luci-app-zerotier luci-app-ipsec-vpnd luci-app-diskman usbutils usb-modeswitch
 
 KERNELNAME:=Image dtbs
 

target/linux/rockchip/armv8/base-files/etc/board.d/01_leds

@@ -9,7 +9,6 @@ boardname="${board##*,}"
 board_config_update
 
 case $board in
-embedfire,doornet1|\
 friendlyarm,nanopi-r2c|\
 friendlyarm,nanopi-r2s|\
 xunlong,orangepi-r1-plus|\
@@ -17,24 +16,17 @@ xunlong,orangepi-r1-plus-lts)
 	ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
 	ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
 	;;
-embedfire,doornet2|\
 friendlyarm,nanopi-r4s|\
 friendlyarm,nanopi-r4se|\
 sharevdi,guangmiao-g4c)
 	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
 	ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1"
 	;;
-firefly,rk3568-roc-pc)
+friendlyarm,nanopi-r5s)
-	ucidef_set_led_timer "health" "health" "firefly:yellow:user" "200" "800"
-	;;
-friendlyelec,nanopi-r5s)
 	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
 	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
 	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2"
 	;;
-radxa,rock3a)
-	ucidef_set_led_netdev "lan" "LAN" "user-led" "br-lan"
-	;;
 esac
 
 board_config_flush

target/linux/rockchip/armv8/base-files/etc/board.d/02_network

@@ -8,8 +8,6 @@ rockchip_setup_interfaces()
 	local board="$1"
 
 	case "$board" in
-	embedfire,doornet1|\
-	embedfire,doornet2|\
 	friendlyarm,nanopi-r2c|\
 	friendlyarm,nanopi-r2s|\
 	friendlyarm,nanopi-r4s|\
@@ -19,11 +17,7 @@ rockchip_setup_interfaces()
 	xunlong,orangepi-r1-plus-lts)
 		ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
 		;;
-	fastrhino,r66s|\
+	friendlyarm,nanopi-r5s)
-	firefly,rk3568-roc-pc)
-		ucidef_set_interfaces_lan_wan "eth0" "eth1"
-		;;
-	friendlyelec,nanopi-r5s)
 		ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
 		;;
 	*)
@@ -34,7 +28,7 @@ rockchip_setup_interfaces()
 
 nanopi_r2s_generate_mac()
 {
-	local sd_hash=$(sha256sum /sys/class/block/mmcblk*/device/cid | head -n 1)
+	local sd_hash=$(sha256sum /sys/class/block/mmcblk0/device/cid)
 	local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)")
 	echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")"
 }
@@ -47,24 +41,16 @@ rockchip_setup_macs()
 	local label_mac=""
 
 	case "$board" in
-	embedfire,doornet1|\
-	embedfire,doornet2|\
-	fastrhino,r66s|\
 	friendlyarm,nanopi-r2c|\
 	friendlyarm,nanopi-r2s|\
-	sharevdi,guangmiao-g4c|\
+	friendlyarm,nanopi-r5s|\
-	friendlyelec,nanopi-r5s|\
+	sharevdi,guangmiao-g4c)
-	firefly,rk3568-roc-pc)
 		wan_mac=$(nanopi_r2s_generate_mac)
 		lan_mac=$(macaddr_add "$wan_mac" +1)
 		;;
-	friendlyarm,nanopi-r4se|\
+	friendlyarm,nanopi-r4s|\
-	friendlyarm,nanopi-r4s)
+	friendlyarm,nanopi-r4se)
-		if [ -f /sys/bus/i2c/devices/2-0051/eeprom ]; then
+		wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa)
-			wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa)
-		else
-			wan_mac=$(nanopi_r2s_generate_mac)
-		fi
 		lan_mac=$(macaddr_setbit_la "$wan_mac")
 		;;
 	xunlong,orangepi-r1-plus|\

target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity

@@ -5,13 +5,12 @@
 get_device_irq() {
 	local device="$1"
 	local line
-	local seconds="0"
+	local seconds
 
 	# wait up to 10 seconds for the irq/device to appear
-	while [ "${seconds}" -le 10 ]; do
+	for seconds in $(seq 0 9); do
 		line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
-		seconds="$(( seconds + 2 ))"
+		sleep 1
-		sleep 2
 	done
 	echo ${line} | sed 's/:.*//'
 }
@@ -29,7 +28,10 @@ set_interface_core() {
 }
 
 case "$(board_name)" in
-embedfire,doornet1|\
+fastrhino,r66s)
+	set_interface_core 2 "eth0"
+	set_interface_core 4 "eth1"
+	;;
 friendlyarm,nanopi-r2c|\
 friendlyarm,nanopi-r2s|\
 xunlong,orangepi-r1-plus|\
@@ -37,18 +39,13 @@ xunlong,orangepi-r1-plus-lts)
 	set_interface_core 2 "eth0"
 	set_interface_core 4 "eth1" "xhci-hcd:usb3"
 	;;
-embedfire,doornet2|\
 friendlyarm,nanopi-r4s|\
+friendlyarm,nanopi-r4se|\
 sharevdi,guangmiao-g4c)
 	set_interface_core 10 "eth0"
 	set_interface_core 20 "eth1"
 	;;
-fastrhino,r66s|\
+friendlyarm,nanopi-r5s)
-firefly,rk3568-roc-pc)
-	set_interface_core 2 "eth0"
-	set_interface_core 4 "eth1"
-	;;
-friendlyelec,nanopi-r5s)
 	set_interface_core 0 "eth0"
 	set_interface_core 2 "eth1"
 	set_interface_core 4 "eth2"

target/linux/rockchip/armv8/config-5.10

@@ -448,7 +448,6 @@ CONFIG_PHY_ROCKCHIP_EMMC=y
 # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
 # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set
 CONFIG_PHY_ROCKCHIP_PCIE=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PHY_ROCKCHIP_USB=y

target/linux/rockchip/armv8/config-5.19

@@ -1,841 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_AF_UNIX_OOB=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_ARM64=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_1024718=y
-CONFIG_ARM64_ERRATUM_1530923=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_MODULE_PLTS=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=48
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-# CONFIG_ARMV8_DEPRECATED is not set
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_FFA_SMCCC=y
-CONFIG_ARM_FFA_TRANSPORT=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MHU=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_RK3399_DMC_DEVFREQ=y
-CONFIG_ARM_SCMI_CPUFREQ=y
-CONFIG_ARM_SCMI_HAVE_SHMEM=y
-CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=y
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_ARM_SCPI_CPUFREQ=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-CONFIG_ARM_SMMU=y
-CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINARY_PRINTF=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BLOCK_LEGACY_AUTOLOAD=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CHARGER_GPIO=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=5
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-# CONFIG_COMMON_CLK_RS9_PCIE is not set
-CONFIG_COMMON_CLK_SCMI=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC64=y
-CONFIG_CRC64_ROCKSOFT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC64_ROCKSOFT=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_RNG2=y
-# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
-# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVPORT is not set
-# CONFIG_DM9051 is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DRM=y
-# CONFIG_DRM_ANALOGIX_ANX7625 is not set
-CONFIG_DRM_BRIDGE=y
-# CONFIG_DRM_CHIPONE_ICN6211 is not set
-CONFIG_DRM_DEBUG_MODESET_LOCK=y
-CONFIG_DRM_DISPLAY_HDMI_HELPER=y
-CONFIG_DRM_DISPLAY_HELPER=y
-CONFIG_DRM_DW_HDMI=y
-CONFIG_DRM_DW_MIPI_DSI=y
-# CONFIG_DRM_FSL_LDB is not set
-CONFIG_DRM_GEM_CMA_HELPER=y
-# CONFIG_DRM_ITE_IT6505 is not set
-# CONFIG_DRM_ITE_IT66121 is not set
-CONFIG_DRM_KMS_HELPER=y
-# CONFIG_DRM_LONTIUM_LT8912B is not set
-# CONFIG_DRM_LONTIUM_LT9211 is not set
-# CONFIG_DRM_LONTIUM_LT9611UXC is not set
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_NOMODESET=y
-CONFIG_DRM_PANEL=y
-# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
-# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
-CONFIG_DRM_PANEL_BRIDGE=y
-# CONFIG_DRM_PANEL_DSI_CM is not set
-# CONFIG_DRM_PANEL_EDP is not set
-# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
-# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
-# CONFIG_DRM_PANEL_JDI_R63452 is not set
-# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
-# CONFIG_DRM_PANEL_MIPI_DBI is not set
-# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
-# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
-# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
-# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
-# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
-# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
-# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
-# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
-# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
-# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
-# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
-# CONFIG_DRM_RCAR_MIPI_DSI is not set
-# CONFIG_DRM_RCAR_USE_LVDS is not set
-CONFIG_DRM_ROCKCHIP=y
-# CONFIG_DRM_SIMPLEDRM is not set
-# CONFIG_DRM_SSD130X is not set
-# CONFIG_DRM_TI_SN65DSI83 is not set
-CONFIG_DTC=y
-CONFIG_DT_IDLE_GENPD=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_DWC_QOS_ETH=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EMAC_ROCKCHIP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FORTIFY_SOURCE is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_FUN_ETH is not set
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC12_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PHY_MIPI_DPHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_GPIO_CASCADE is not set
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_ROCKCHIP=y
-# CONFIG_GPIO_SIM is not set
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDENED_USERCOPY is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
-# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_RK3X=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INDIRECT_PIO=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_MATRIXKMAP=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_RK805_PWRKEY=y
-CONFIG_INPUT_SPARSEKMAP=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEXEC_FILE=y
-# CONFIG_KEXEC_SIG is not set
-CONFIG_KSM=y
-# CONFIG_LAN966X_SWITCH is not set
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-# CONFIG_LEDS_PWM_MULTICOLOR is not set
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_LTO_NONE=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_KHADAS_MCU is not set
-# CONFIG_MFD_MAX77714 is not set
-CONFIG_MFD_RK808=y
-# CONFIG_MFD_SIMPLE_MFD_I2C is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MOTORCOMM_PHY=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-CONFIG_MQ_IOSCHED_DEADLINE=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-# CONFIG_NET_DSA_REALTEK is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_NLS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-# CONFIG_NVME_VERBOSE_ERRORS is not set
-# CONFIG_OCTEON_EP is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGSUSPEND3=y
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_SPLIT_BTF=y
-CONFIG_PAHOLE_VERSION=121
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PATA_SIS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_STUB=y
-CONFIG_PCS_XPCS=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_ROCKCHIP_DP=y
-CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
-CONFIG_PHY_ROCKCHIP_EMMC=y
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
-CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
-CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RK805=y
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PL330_DMA=y
-CONFIG_PLATFORM_MHU=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_XILINX is not set
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-CONFIG_RAID_ATTRS=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_ARM_SCMI is not set
-CONFIG_REGULATOR_FAN53555=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_RK808=y
-# CONFIG_REGULATOR_RT5190A is not set
-# CONFIG_REGULATOR_RT5759 is not set
-# CONFIG_REGULATOR_SY7636A is not set
-# CONFIG_REGULATOR_TPS6286X is not set
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SCMI=y
-CONFIG_RFS_ACCEL=y
-# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
-# CONFIG_ROCKCHIP_CDN_DP is not set
-CONFIG_ROCKCHIP_DW_HDMI=y
-CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_EFUSE=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_INNO_HDMI=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-# CONFIG_ROCKCHIP_LVDS is not set
-CONFIG_ROCKCHIP_MBOX=y
-# CONFIG_ROCKCHIP_OTP is not set
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_RGB is not set
-CONFIG_ROCKCHIP_RK3066_HDMI=y
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_ROCKCHIP_VOP=y
-CONFIG_ROCKCHIP_VOP2=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RK808=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_NVMEM=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_PMP=y
-CONFIG_SATA_SIS=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SCSI_SAS_ATA is not set
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SAS_LIBSAS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SENSORS_ARM_SCMI is not set
-CONFIG_SENSORS_ARM_SCPI=y
-# CONFIG_SENSORS_NCT6775_I2C is not set
-# CONFIG_SENSORS_SY7636A is not set
-# CONFIG_SENSORS_TMP464 is not set
-CONFIG_SERIAL_8250_ASPEED_VUART=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_PCIPS2=y
-CONFIG_SERIO_RAW=y
-# CONFIG_SFC_SIENA is not set
-CONFIG_SG_POOL=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ROCKCHIP=y
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_PER_TASK=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_SWAP is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYSVIPC_COMPAT=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-# CONFIG_TINYDRM_ILI9163 is not set
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_TRANS_TABLE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_DP_ALTMODE is not set
-CONFIG_TYPEC_FUSB302=y
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_FSA4480 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_RT1719 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-# CONFIG_TYPEC_TCPCI is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_TYPEC_WUSB3801 is not set
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HOST=y
-CONFIG_USB_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USERIO=y
-CONFIG_VIDEOMODE_HELPERS=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-# CONFIG_VMWARE_VMCI is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WATCHDOG is not set
-CONFIG_XARRAY_MULTI=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y

target/linux/rockchip/armv8/config-5.4

@@ -427,7 +427,6 @@ CONFIG_PHY_ROCKCHIP_DP=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
 # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set
 CONFIG_PHY_ROCKCHIP_PCIE=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PHY_ROCKCHIP_USB=y

target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3566.dtsi

@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include "rk356x.dtsi"
-
-/ {
-	compatible = "rockchip,rk3566";
-};
-
-&pipegrf {
-	compatible = "rockchip,rk3566-pipe-grf", "syscon";
-};
-
-&power {
-	power-domain@RK3568_PD_PIPE {
-		reg = <RK3568_PD_PIPE>;
-		clocks = <&cru PCLK_PIPE>;
-		pm_qos = <&qos_pcie2x1>,
-			 <&qos_sata1>,
-			 <&qos_sata2>,
-			 <&qos_usb3_0>,
-			 <&qos_usb3_1>;
-		#power-domain-cells = <0>;
-	};
-};
-
-&usb_host0_xhci {
-	phys = <&usb2phy0_otg>;
-	phy-names = "usb2-phy";
-	extcon = <&usb2phy0>;
-	maximum-speed = "high-speed";
-};
-
-&vop {
-	compatible = "rockchip,rk3566-vop";
-};

target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

@@ -1,70 +1,72 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2022 Marty Jones <mj8263788@gmail.com>
+ * Copyright (c) 2022 Tianling Shen <cnsztl@gmail.com>
+ */
 
 /dts-v1/;
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
-	model = "Radxa ROCK3 Model A";
+	model = "FriendlyElec NanoPi R5S";
-	compatible = "radxa,rock3a", "rockchip,rk3568";
+	compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568";
 
 	aliases {
-		ethernet0 = &gmac1;
+		ethernet0 = &gmac0;
 		mmc0 = &sdmmc0;
 		mmc1 = &sdhci;
+
+		led-boot = &sys_led;
+		led-failsafe = &sys_led;
+		led-running = &sys_led;
+		led-upgrade = &sys_led;
 	};
 
 	chosen: chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>,
+			    <&sys_led_pin>, <&wan_led_pin>;
+		pinctrl-names = "default";
 
-		led_user: led-0 {
+		lan1_led: led-0 {
-			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_HEARTBEAT;
+			label = "lan1_led";
-			color = <LED_COLOR_ID_BLUE>;
+		};
-			linux,default-trigger = "heartbeat";
+
-			pinctrl-names = "default";
+		lan2_led: led-1 {
-			pinctrl-0 = <&led_user_en>;
+			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
+			label = "lan2_led";
+		};
+
+		sys_led: led-2 {
+			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+			label = "sys_led";
+		};
+
+		wan_led: led-3 {
+			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+			label = "wan_led";
 		};
 	};
 
-	rk809-sound {
+	vdd_5v: vdd-5v {
-		compatible = "simple-audio-card";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,name = "Analog RK809";
-		simple-audio-card,mclk-fs = <256>;
-
-		simple-audio-card,cpu {
-			sound-dai = <&i2s1_8ch>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&rk809>;
-		};
-	};
-
-	vcc12v_dcin: vcc12v-dcin {
 		compatible = "regulator-fixed";
-		regulator-name = "vcc12v_dcin";
+		regulator-name = "vdd_5v";
 		regulator-always-on;
 		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
 	};
 
 	vcc3v3_sys: vcc3v3-sys {
@@ -74,27 +76,27 @@
 		regulator-boot-on;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc12v_dcin>;
+		vin-supply = <&vdd_5v>;
 	};
 
-	vcc5v0_sys: vcc5v0-sys {
+	vcc3v3_sysp: vcc3v3-sysp {
 		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
+		regulator-name = "vcc3v3_sysp";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_5v>;
+	};
+
+	vcc5v0_sysp: vcc5v0-sysp {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sysp";
 		regulator-always-on;
 		regulator-boot-on;
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
+		vin-supply = <&vcc3v3_sysp>;
-	};
-
-	vcc5v0_usb: vcc5v0-usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
 	};
 
 	vcc5v0_usb_host: vcc5v0-usb-host {
@@ -106,30 +108,18 @@
 		regulator-name = "vcc5v0_usb_host";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
+		vin-supply = <&vcc5v0_sysp>;
 	};
 
-	vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
+	vcc3v3_pcie: vcc3v3-pcie {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
+		regulator-name = "vcc3v3_pcie";
-		pinctrl-0 = <&vcc5v0_usb_hub_en>;
+		regulator-min-microvolt = <3300000>;
-		regulator-name = "vcc5v0_usb_hub";
+		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		startup-delay-us = <5000>;
-		vin-supply = <&vcc5v0_usb>;
+		vin-supply = <&vcc3v3_sysp>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
 	};
 };
 
@@ -141,6 +131,10 @@
 	status = "okay";
 };
 
+&combphy2 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -157,50 +151,32 @@
 	cpu-supply = <&vdd_cpu>;
 };
 
-&gmac1 {
+&gmac0 {
-	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
-	assigned-clock-rates = <0>, <125000000>;
 	clock_in_out = "output";
-	phy-handle = <&rgmii_phy1>;
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac1m1_miim
+	pinctrl-0 = <&gmac0_miim
-		     &gmac1m1_tx_bus2
+		     &gmac0_tx_bus2
-		     &gmac1m1_rx_bus2
+		     &gmac0_rx_bus2
-		     &gmac1m1_rgmii_clk
+		     &gmac0_rgmii_clk
-		     &gmac1m1_rgmii_bus>;
+		     &gmac0_rgmii_bus>;
-	status = "okay";
+	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-};
+	snps,reset-active-low;
-
+	/* Reset time is 15ms, 50ms for rtl8211f */
-&gpu {
+	snps,reset-delays-us = <0 15000 50000>;
-	mali-supply = <&vdd_gpu>;
+	tx_delay = <0x3c>;
-	status = "okay";
+	rx_delay = <0x2f>;
-};
+	phy-handle = <&rgmii_phy0>;
-
-&hdmi {
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint {
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
 	status = "okay";
 };
 
 &i2c0 {
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
 	status = "okay";
 
 	vdd_cpu: regulator@1c {
@@ -210,10 +186,11 @@
 		regulator-name = "vdd_cpu";
 		regulator-always-on;
 		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
+		regulator-min-microvolt = <712500>;
-		regulator-max-microvolt = <1150000>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
 		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
+		vin-supply = <&vcc3v3_sys>;
 
 		regulator-state-mem {
 			regulator-off-in-suspend;
@@ -225,15 +202,12 @@
 		reg = <0x20>;
 		interrupt-parent = <&gpio0>;
 		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
 		#clock-cells = <1>;
-		clock-names = "mclk";
-		clocks = <&cru I2S1_MCLKOUT_TX>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		pinctrl-0 = <&pmic_int>;
 		rockchip,system-power-controller;
-		#sound-dai-cells = <0>;
+		wakeup-source;
+
 		vcc1-supply = <&vcc3v3_sys>;
 		vcc2-supply = <&vcc3v3_sys>;
 		vcc3-supply = <&vcc3v3_sys>;
@@ -243,7 +217,6 @@
 		vcc7-supply = <&vcc3v3_sys>;
 		vcc8-supply = <&vcc3v3_sys>;
 		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
 
 		regulators {
 			vdd_logic: DCDC_REG1 {
@@ -427,57 +400,132 @@
 
 			vcc3v3_sd: SWITCH_REG2 {
 				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
 
 				regulator-state-mem {
 					regulator-off-in-suspend;
 				};
 			};
 		};
+	};
+};
 
-		codec {
+&i2c5 {
-			mic-in-differential;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gmac_int>;
+	};
+};
+
+&pcie2x1 {
+	num-lanes = <1>;
+	num-viewport = <4>;
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pcie@00 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		r8125_1: pcie@01,0 {
+			reg = <0x000000 0 0 0 0>;
 		};
 	};
 };
 
-&i2s0_8ch {
+&pcie30phy {
+	data-lanes = <1 2>;
 	status = "okay";
 };
 
-&i2s1_8ch {
+&pcie3x1 {
-	rockchip,trcm-sync-tx-only;
+	num-lanes = <1>;
+	num-viewport = <4>;
+	rockchip,init-delay-ms = <100>;
+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
-};
 
-&mdio1 {
+	pcie@10 {
-	rgmii_phy1: ethernet-phy@0 {
+		reg = <0x00100000 0 0 0 0>;
-		compatible = "ethernet-phy-ieee802.3-c22";
+		#address-cells = <3>;
-		reg = <0x0>;
+		#size-cells = <2>;
-		pinctrl-names = "default";
+
-		pinctrl-0 = <&eth_phy_rst>;
+		r8125_2: pcie@10,0 {
-		reset-assert-us = <20000>;
+			reg = <0x000000 0 0 0 0>;
-		reset-deassert-us = <100000>;
+		};
-		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
 	};
 };
 
+&pcie3x2 {
+	num-lanes = <1>;
+	max-link-speed = <2>;
+	num-ib-windows = <8>;
+	num-ob-windows = <8>;
+	num-viewport = <4>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
 &pinctrl {
-	ethernet {
+	leds {
-		eth_phy_rst: eth_phy_rst {
+		lan1_led_pin: lan1-led-pin {
-			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan2_led_pin: lan2-led-pin {
+			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 
-	leds {
+	eth_phy {
-		led_user_en: led_user_en {
+		gmac_int: gmac-int {
-			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
 
 	pmic {
 		pmic_int: pmic_int {
-			rockchip,pins =
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
 
@@ -485,20 +533,12 @@
 		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
-		vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
-			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
 	};
 };
 
 &pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
 	pmuio2-supply = <&vcc3v3_pmu>;
 	vccio1-supply = <&vccio_acodec>;
-	vccio2-supply = <&vcc_1v8>;
 	vccio3-supply = <&vccio_sd>;
 	vccio4-supply = <&vcc_1v8>;
 	vccio5-supply = <&vcc_3v3>;
@@ -507,6 +547,10 @@
 	status = "okay";
 };
 
+&pwm0 {
+	status = "okay";
+};
+
 &saradc {
 	vref-supply = <&vcca_1v8>;
 	status = "okay";
@@ -517,9 +561,7 @@
 	max-frequency = <200000000>;
 	non-removable;
 	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vcc_1v8>;
 	status = "okay";
 };
 
@@ -581,7 +623,6 @@
 };
 
 &usb2phy0_otg {
-	vbus-supply = <&vcc5v0_usb_otg>;
 	status = "okay";
 };
 
@@ -590,28 +631,9 @@
 };
 
 &usb2phy1_host {
-	phy-supply = <&vcc5v0_usb_host>;
 	status = "okay";
 };
 
 &usb2phy1_otg {
-	phy-supply = <&vcc5v0_usb_host>;
 	status = "okay";
 };
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&vp0 {
-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-		remote-endpoint = <&hdmi_in_vp0>;
-	};
-};

target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi

@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include "rk356x.dtsi"
-
-/ {
-	compatible = "rockchip,rk3568";
-
-	sata0: sata@fc000000 {
-		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
-		reg = <0 0xfc000000 0 0x1000>;
-		clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
-			 <&cru CLK_SATA0_RXOOB>;
-		clock-names = "sata", "pmalive", "rxoob";
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		phys = <&combphy0 PHY_TYPE_SATA>;
-		phy-names = "sata-phy";
-		ports-implemented = <0x1>;
-		power-domains = <&power RK3568_PD_PIPE>;
-		status = "disabled";
-	};
-
-	pipe_phy_grf0: syscon@fdc70000 {
-		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
-		reg = <0x0 0xfdc70000 0x0 0x1000>;
-	};
-
-	qos_pcie3x1: qos@fe190080 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190080 0x0 0x20>;
-	};
-
-	qos_pcie3x2: qos@fe190100 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190100 0x0 0x20>;
-	};
-
-	qos_sata0: qos@fe190200 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190200 0x0 0x20>;
-	};
-
-	gmac0: ethernet@fe2a0000 {
-		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
-		reg = <0x0 0xfe2a0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "macirq", "eth_wake_irq";
-		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
-			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
-			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
-			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
-		clock-names = "stmmaceth", "mac_clk_rx",
-			      "mac_clk_tx", "clk_mac_refout",
-			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref";
-		resets = <&cru SRST_A_GMAC0>;
-		reset-names = "stmmaceth";
-		rockchip,grf = <&grf>;
-		snps,axi-config = <&gmac0_stmmac_axi_setup>;
-		snps,mixed-burst;
-		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
-		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
-		snps,tso;
-		status = "disabled";
-
-		mdio0: mdio {
-			compatible = "snps,dwmac-mdio";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-		};
-
-		gmac0_stmmac_axi_setup: stmmac-axi-config {
-			snps,blen = <0 0 0 0 16 8 4>;
-			snps,rd_osr_lmt = <8>;
-			snps,wr_osr_lmt = <4>;
-		};
-
-		gmac0_mtl_rx_setup: rx-queues-config {
-			snps,rx-queues-to-use = <1>;
-			queue0 {};
-		};
-
-		gmac0_mtl_tx_setup: tx-queues-config {
-			snps,tx-queues-to-use = <1>;
-			queue0 {};
-		};
-	};
-
-	combphy0: phy@fe820000 {
-		compatible = "rockchip,rk3568-naneng-combphy";
-		reg = <0x0 0xfe820000 0x0 0x100>;
-		clocks = <&pmucru CLK_PCIEPHY0_REF>,
-			 <&cru PCLK_PIPEPHY0>,
-			 <&cru PCLK_PIPE>;
-		clock-names = "ref", "apb", "pipe";
-		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
-		assigned-clock-rates = <100000000>;
-		resets = <&cru SRST_PIPEPHY0>;
-		rockchip,pipe-grf = <&pipegrf>;
-		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
-		#phy-cells = <1>;
-		status = "disabled";
-	};
-};
-
-&cpu0_opp_table {
-	opp-1992000000 {
-		opp-hz = /bits/ 64 <1992000000>;
-		opp-microvolt = <1150000 1150000 1150000>;
-	};
-};
-
-&pipegrf {
-	compatible = "rockchip,rk3568-pipe-grf", "syscon";
-};
-
-&power {
-	power-domain@RK3568_PD_PIPE {
-		reg = <RK3568_PD_PIPE>;
-		clocks = <&cru PCLK_PIPE>;
-		pm_qos = <&qos_pcie2x1>,
-			 <&qos_pcie3x1>,
-			 <&qos_pcie3x2>,
-			 <&qos_sata0>,
-			 <&qos_sata1>,
-			 <&qos_sata2>,
-			 <&qos_usb3_0>,
-			 <&qos_usb3_1>;
-		#power-domain-cells = <0>;
-	};
-};
-
-&usb_host0_xhci {
-	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
-	phy-names = "usb2-phy", "usb3-phy";
-};
-
-&vop {
-	compatible = "rockchip,rk3568-vop";
-};

target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

@@ -1,477 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Author:Mark Yao <mark.yao@rock-chips.com>
- */
-
-#ifndef _ROCKCHIP_DRM_VOP2_H
-#define _ROCKCHIP_DRM_VOP2_H
-
-#include "rockchip_drm_vop.h"
-
-#include <linux/regmap.h>
-#include <drm/drm_modes.h>
-
-#define VOP_FEATURE_OUTPUT_10BIT        BIT(0)
-
-#define WIN_FEATURE_AFBDC		BIT(0)
-#define WIN_FEATURE_CLUSTER		BIT(1)
-
-/*
- *  the delay number of a window in different mode.
- */
-enum win_dly_mode {
-	VOP2_DLY_MODE_DEFAULT,   /**< default mode */
-	VOP2_DLY_MODE_HISO_S,    /** HDR in SDR out mode, as a SDR window */
-	VOP2_DLY_MODE_HIHO_H,    /** HDR in HDR out mode, as a HDR window */
-	VOP2_DLY_MODE_MAX,
-};
-
-struct vop_rect {
-	int width;
-	int height;
-};
-
-enum vop2_scale_up_mode {
-	VOP2_SCALE_UP_NRST_NBOR,
-	VOP2_SCALE_UP_BIL,
-	VOP2_SCALE_UP_BIC,
-};
-
-enum vop2_scale_down_mode {
-	VOP2_SCALE_DOWN_NRST_NBOR,
-	VOP2_SCALE_DOWN_BIL,
-	VOP2_SCALE_DOWN_AVG,
-};
-
-enum vop2_win_regs {
-	VOP2_WIN_ENABLE,
-	VOP2_WIN_FORMAT,
-	VOP2_WIN_CSC_MODE,
-	VOP2_WIN_XMIRROR,
-	VOP2_WIN_YMIRROR,
-	VOP2_WIN_RB_SWAP,
-	VOP2_WIN_UV_SWAP,
-	VOP2_WIN_ACT_INFO,
-	VOP2_WIN_DSP_INFO,
-	VOP2_WIN_DSP_ST,
-	VOP2_WIN_YRGB_MST,
-	VOP2_WIN_UV_MST,
-	VOP2_WIN_YRGB_VIR,
-	VOP2_WIN_UV_VIR,
-	VOP2_WIN_YUV_CLIP,
-	VOP2_WIN_Y2R_EN,
-	VOP2_WIN_R2Y_EN,
-	VOP2_WIN_COLOR_KEY,
-	VOP2_WIN_COLOR_KEY_EN,
-	VOP2_WIN_DITHER_UP,
-
-	/* scale regs */
-	VOP2_WIN_SCALE_YRGB_X,
-	VOP2_WIN_SCALE_YRGB_Y,
-	VOP2_WIN_SCALE_CBCR_X,
-	VOP2_WIN_SCALE_CBCR_Y,
-	VOP2_WIN_YRGB_HOR_SCL_MODE,
-	VOP2_WIN_YRGB_HSCL_FILTER_MODE,
-	VOP2_WIN_YRGB_VER_SCL_MODE,
-	VOP2_WIN_YRGB_VSCL_FILTER_MODE,
-	VOP2_WIN_CBCR_VER_SCL_MODE,
-	VOP2_WIN_CBCR_HSCL_FILTER_MODE,
-	VOP2_WIN_CBCR_HOR_SCL_MODE,
-	VOP2_WIN_CBCR_VSCL_FILTER_MODE,
-	VOP2_WIN_VSD_CBCR_GT2,
-	VOP2_WIN_VSD_CBCR_GT4,
-	VOP2_WIN_VSD_YRGB_GT2,
-	VOP2_WIN_VSD_YRGB_GT4,
-	VOP2_WIN_BIC_COE_SEL,
-
-	/* cluster regs */
-	VOP2_WIN_CLUSTER_ENABLE,
-	VOP2_WIN_AFBC_ENABLE,
-	VOP2_WIN_CLUSTER_LB_MODE,
-
-	/* afbc regs */
-	VOP2_WIN_AFBC_FORMAT,
-	VOP2_WIN_AFBC_RB_SWAP,
-	VOP2_WIN_AFBC_UV_SWAP,
-	VOP2_WIN_AFBC_AUTO_GATING_EN,
-	VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
-	VOP2_WIN_AFBC_PIC_VIR_WIDTH,
-	VOP2_WIN_AFBC_TILE_NUM,
-	VOP2_WIN_AFBC_PIC_OFFSET,
-	VOP2_WIN_AFBC_PIC_SIZE,
-	VOP2_WIN_AFBC_DSP_OFFSET,
-	VOP2_WIN_AFBC_TRANSFORM_OFFSET,
-	VOP2_WIN_AFBC_HDR_PTR,
-	VOP2_WIN_AFBC_HALF_BLOCK_EN,
-	VOP2_WIN_AFBC_ROTATE_270,
-	VOP2_WIN_AFBC_ROTATE_90,
-	VOP2_WIN_MAX_REG,
-};
-
-struct vop2_win_data {
-	const char *name;
-	unsigned int phys_id;
-
-	u32 base;
-	enum drm_plane_type type;
-
-	u32 nformats;
-	const u32 *formats;
-	const uint64_t *format_modifiers;
-	const unsigned int supported_rotations;
-
-	/**
-	 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
-	 */
-	unsigned int layer_sel_id;
-	uint64_t feature;
-
-	unsigned int max_upscale_factor;
-	unsigned int max_downscale_factor;
-	const u8 dly[VOP2_DLY_MODE_MAX];
-};
-
-struct vop2_video_port_data {
-	unsigned int id;
-	u32 feature;
-	u16 gamma_lut_len;
-	u16 cubic_lut_len;
-	struct vop_rect max_output;
-	const u8 pre_scan_max_dly[4];
-	const struct vop2_video_port_regs *regs;
-	unsigned int offset;
-};
-
-struct vop2_data {
-	u8 nr_vps;
-	const struct vop2_ctrl *ctrl;
-	const struct vop2_win_data *win;
-	const struct vop2_video_port_data *vp;
-	const struct vop_csc_table *csc_table;
-	struct vop_rect max_input;
-	struct vop_rect max_output;
-
-	unsigned int win_size;
-	unsigned int soc_id;
-};
-
-/* interrupt define */
-#define FS_NEW_INTR			BIT(4)
-#define ADDR_SAME_INTR			BIT(5)
-#define LINE_FLAG1_INTR			BIT(6)
-#define WIN0_EMPTY_INTR			BIT(7)
-#define WIN1_EMPTY_INTR			BIT(8)
-#define WIN2_EMPTY_INTR			BIT(9)
-#define WIN3_EMPTY_INTR			BIT(10)
-#define HWC_EMPTY_INTR			BIT(11)
-#define POST_BUF_EMPTY_INTR		BIT(12)
-#define PWM_GEN_INTR			BIT(13)
-#define DMA_FINISH_INTR			BIT(14)
-#define FS_FIELD_INTR			BIT(15)
-#define FE_INTR				BIT(16)
-#define WB_UV_FIFO_FULL_INTR		BIT(17)
-#define WB_YRGB_FIFO_FULL_INTR		BIT(18)
-#define WB_COMPLETE_INTR		BIT(19)
-
-/*
- * display output interface supported by rockchip lcdc
- */
-#define ROCKCHIP_OUT_MODE_P888		0
-#define ROCKCHIP_OUT_MODE_BT1120	0
-#define ROCKCHIP_OUT_MODE_P666		1
-#define ROCKCHIP_OUT_MODE_P565		2
-#define ROCKCHIP_OUT_MODE_BT656		5
-#define ROCKCHIP_OUT_MODE_S888		8
-#define ROCKCHIP_OUT_MODE_S888_DUMMY	12
-#define ROCKCHIP_OUT_MODE_YUV420	14
-/* for use special outface */
-#define ROCKCHIP_OUT_MODE_AAAA		15
-
-enum vop_csc_format {
-	CSC_BT601L,
-	CSC_BT709L,
-	CSC_BT601F,
-	CSC_BT2020,
-};
-
-enum src_factor_mode {
-	SRC_FAC_ALPHA_ZERO,
-	SRC_FAC_ALPHA_ONE,
-	SRC_FAC_ALPHA_DST,
-	SRC_FAC_ALPHA_DST_INVERSE,
-	SRC_FAC_ALPHA_SRC,
-	SRC_FAC_ALPHA_SRC_GLOBAL,
-};
-
-enum dst_factor_mode {
-	DST_FAC_ALPHA_ZERO,
-	DST_FAC_ALPHA_ONE,
-	DST_FAC_ALPHA_SRC,
-	DST_FAC_ALPHA_SRC_INVERSE,
-	DST_FAC_ALPHA_DST,
-	DST_FAC_ALPHA_DST_GLOBAL,
-};
-
-#define RK3568_GRF_VO_CON1			0x0364
-/* System registers definition */
-#define RK3568_REG_CFG_DONE			0x000
-#define RK3568_VERSION_INFO			0x004
-#define RK3568_SYS_AUTO_GATING_CTRL		0x008
-#define RK3568_SYS_AXI_LUT_CTRL			0x024
-#define RK3568_DSP_IF_EN			0x028
-#define RK3568_DSP_IF_CTRL			0x02c
-#define RK3568_DSP_IF_POL			0x030
-#define RK3568_WB_CTRL				0x40
-#define RK3568_WB_XSCAL_FACTOR			0x44
-#define RK3568_WB_YRGB_MST			0x48
-#define RK3568_WB_CBR_MST			0x4C
-#define RK3568_OTP_WIN_EN			0x050
-#define RK3568_LUT_PORT_SEL			0x058
-#define RK3568_SYS_STATUS0			0x060
-#define RK3568_VP_LINE_FLAG(vp)			(0x70 + (vp) * 0x4)
-#define RK3568_SYS0_INT_EN			0x80
-#define RK3568_SYS0_INT_CLR			0x84
-#define RK3568_SYS0_INT_STATUS			0x88
-#define RK3568_SYS1_INT_EN			0x90
-#define RK3568_SYS1_INT_CLR			0x94
-#define RK3568_SYS1_INT_STATUS			0x98
-#define RK3568_VP_INT_EN(vp)			(0xA0 + (vp) * 0x10)
-#define RK3568_VP_INT_CLR(vp)			(0xA4 + (vp) * 0x10)
-#define RK3568_VP_INT_STATUS(vp)		(0xA8 + (vp) * 0x10)
-#define RK3568_VP_INT_RAW_STATUS(vp)		(0xAC + (vp) * 0x10)
-
-/* Video Port registers definition */
-#define RK3568_VP_DSP_CTRL			0x00
-#define RK3568_VP_MIPI_CTRL			0x04
-#define RK3568_VP_COLOR_BAR_CTRL		0x08
-#define RK3568_VP_3D_LUT_CTRL			0x10
-#define RK3568_VP_3D_LUT_MST			0x20
-#define RK3568_VP_DSP_BG			0x2C
-#define RK3568_VP_PRE_SCAN_HTIMING		0x30
-#define RK3568_VP_POST_DSP_HACT_INFO		0x34
-#define RK3568_VP_POST_DSP_VACT_INFO		0x38
-#define RK3568_VP_POST_SCL_FACTOR_YRGB		0x3C
-#define RK3568_VP_POST_SCL_CTRL			0x40
-#define RK3568_VP_POST_DSP_VACT_INFO_F1		0x44
-#define RK3568_VP_DSP_HTOTAL_HS_END		0x48
-#define RK3568_VP_DSP_HACT_ST_END		0x4C
-#define RK3568_VP_DSP_VTOTAL_VS_END		0x50
-#define RK3568_VP_DSP_VACT_ST_END		0x54
-#define RK3568_VP_DSP_VS_ST_END_F1		0x58
-#define RK3568_VP_DSP_VACT_ST_END_F1		0x5C
-#define RK3568_VP_BCSH_CTRL			0x60
-#define RK3568_VP_BCSH_BCS			0x64
-#define RK3568_VP_BCSH_H			0x68
-#define RK3568_VP_BCSH_COLOR_BAR		0x6C
-
-/* Overlay registers definition    */
-#define RK3568_OVL_CTRL				0x600
-#define RK3568_OVL_LAYER_SEL			0x604
-#define RK3568_OVL_PORT_SEL			0x608
-#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL	0x610
-#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL	0x614
-#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x618
-#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL	0x61C
-#define RK3568_MIX0_SRC_COLOR_CTRL		0x650
-#define RK3568_MIX0_DST_COLOR_CTRL		0x654
-#define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
-#define RK3568_MIX0_DST_ALPHA_CTRL		0x65C
-#define RK3568_HDR0_SRC_COLOR_CTRL		0x6C0
-#define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
-#define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
-#define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
-#define RK3568_VP_BG_MIX_CTRL(vp)		(0x6E0 + (vp) * 4)
-#define RK3568_CLUSTER_DLY_NUM			0x6F0
-#define RK3568_SMART_DLY_NUM			0x6F8
-
-/* Cluster register definition, offset relative to window base */
-#define RK3568_CLUSTER_WIN_CTRL0		0x00
-#define RK3568_CLUSTER_WIN_CTRL1		0x04
-#define RK3568_CLUSTER_WIN_YRGB_MST		0x10
-#define RK3568_CLUSTER_WIN_CBR_MST		0x14
-#define RK3568_CLUSTER_WIN_VIR			0x18
-#define RK3568_CLUSTER_WIN_ACT_INFO		0x20
-#define RK3568_CLUSTER_WIN_DSP_INFO		0x24
-#define RK3568_CLUSTER_WIN_DSP_ST		0x28
-#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB	0x30
-#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET	0x3C
-#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL	0x50
-#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE	0x54
-#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR	0x58
-#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH	0x5C
-#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE	0x60
-#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET	0x64
-#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET	0x68
-#define RK3568_CLUSTER_WIN_AFBCD_CTRL		0x6C
-
-#define RK3568_CLUSTER_CTRL			0x100
-
-/* (E)smart register definition, offset relative to window base */
-#define RK3568_SMART_CTRL0			0x00
-#define RK3568_SMART_CTRL1			0x04
-#define RK3568_SMART_REGION0_CTRL		0x10
-#define RK3568_SMART_REGION0_YRGB_MST		0x14
-#define RK3568_SMART_REGION0_CBR_MST		0x18
-#define RK3568_SMART_REGION0_VIR		0x1C
-#define RK3568_SMART_REGION0_ACT_INFO		0x20
-#define RK3568_SMART_REGION0_DSP_INFO		0x24
-#define RK3568_SMART_REGION0_DSP_ST		0x28
-#define RK3568_SMART_REGION0_SCL_CTRL		0x30
-#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB	0x34
-#define RK3568_SMART_REGION0_SCL_FACTOR_CBR	0x38
-#define RK3568_SMART_REGION0_SCL_OFFSET		0x3C
-#define RK3568_SMART_REGION1_CTRL		0x40
-#define RK3568_SMART_REGION1_YRGB_MST		0x44
-#define RK3568_SMART_REGION1_CBR_MST		0x48
-#define RK3568_SMART_REGION1_VIR		0x4C
-#define RK3568_SMART_REGION1_ACT_INFO		0x50
-#define RK3568_SMART_REGION1_DSP_INFO		0x54
-#define RK3568_SMART_REGION1_DSP_ST		0x58
-#define RK3568_SMART_REGION1_SCL_CTRL		0x60
-#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB	0x64
-#define RK3568_SMART_REGION1_SCL_FACTOR_CBR	0x68
-#define RK3568_SMART_REGION1_SCL_OFFSET		0x6C
-#define RK3568_SMART_REGION2_CTRL		0x70
-#define RK3568_SMART_REGION2_YRGB_MST		0x74
-#define RK3568_SMART_REGION2_CBR_MST		0x78
-#define RK3568_SMART_REGION2_VIR		0x7C
-#define RK3568_SMART_REGION2_ACT_INFO		0x80
-#define RK3568_SMART_REGION2_DSP_INFO		0x84
-#define RK3568_SMART_REGION2_DSP_ST		0x88
-#define RK3568_SMART_REGION2_SCL_CTRL		0x90
-#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB	0x94
-#define RK3568_SMART_REGION2_SCL_FACTOR_CBR	0x98
-#define RK3568_SMART_REGION2_SCL_OFFSET		0x9C
-#define RK3568_SMART_REGION3_CTRL		0xA0
-#define RK3568_SMART_REGION3_YRGB_MST		0xA4
-#define RK3568_SMART_REGION3_CBR_MST		0xA8
-#define RK3568_SMART_REGION3_VIR		0xAC
-#define RK3568_SMART_REGION3_ACT_INFO		0xB0
-#define RK3568_SMART_REGION3_DSP_INFO		0xB4
-#define RK3568_SMART_REGION3_DSP_ST		0xB8
-#define RK3568_SMART_REGION3_SCL_CTRL		0xC0
-#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB	0xC4
-#define RK3568_SMART_REGION3_SCL_FACTOR_CBR	0xC8
-#define RK3568_SMART_REGION3_SCL_OFFSET		0xCC
-#define RK3568_SMART_COLOR_KEY_CTRL		0xD0
-
-/* HDR register definition */
-#define RK3568_HDR_LUT_CTRL			0x2000
-#define RK3568_HDR_LUT_MST			0x2004
-#define RK3568_SDR2HDR_CTRL			0x2010
-#define RK3568_HDR2SDR_CTRL			0x2020
-#define RK3568_HDR2SDR_SRC_RANGE		0x2024
-#define RK3568_HDR2SDR_NORMFACEETF		0x2028
-#define RK3568_HDR2SDR_DST_RANGE		0x202C
-#define RK3568_HDR2SDR_NORMFACCGAMMA		0x2030
-#define RK3568_HDR_EETF_OETF_Y0			0x203C
-#define RK3568_HDR_SAT_Y0			0x20C0
-#define RK3568_HDR_EOTF_OETF_Y0			0x20F0
-#define RK3568_HDR_OETF_DX_POW1			0x2200
-#define RK3568_HDR_OETF_XN1			0x2300
-
-#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN		BIT(15)
-
-#define RK3568_VP_DSP_CTRL__STANDBY			BIT(31)
-#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE		BIT(20)
-#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL		GENMASK(19, 18)
-#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN		BIT(17)
-#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN		BIT(16)
-#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y		BIT(15)
-#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP			BIT(9)
-#define RK3568_VP_DSP_CTRL__DSP_INTERLACE		BIT(7)
-#define RK3568_VP_DSP_CTRL__DSP_FILED_POL		BIT(6)
-#define RK3568_VP_DSP_CTRL__P2I_EN			BIT(5)
-#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV		BIT(4)
-#define RK3568_VP_DSP_CTRL__OUT_MODE			GENMASK(3, 0)
-
-#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN		BIT(1)
-#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN		BIT(0)
-
-#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX		GENMASK(26, 25)
-#define RK3568_SYS_DSP_INFACE_EN_LVDS1			BIT(24)
-#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX		GENMASK(22, 21)
-#define RK3568_SYS_DSP_INFACE_EN_MIPI1			BIT(20)
-#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX		GENMASK(19, 18)
-#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX		GENMASK(17, 16)
-#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX		GENMASK(15, 14)
-#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX		GENMASK(11, 10)
-#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX		GENMASK(9, 8)
-#define RK3568_SYS_DSP_INFACE_EN_LVDS0			BIT(5)
-#define RK3568_SYS_DSP_INFACE_EN_MIPI0			BIT(4)
-#define RK3568_SYS_DSP_INFACE_EN_EDP			BIT(3)
-#define RK3568_SYS_DSP_INFACE_EN_HDMI			BIT(1)
-#define RK3568_SYS_DSP_INFACE_EN_RGB			BIT(0)
-
-#define RK3568_DSP_IF_POL__MIPI_PIN_POL			GENMASK(19, 16)
-#define RK3568_DSP_IF_POL__EDP_PIN_POL			GENMASK(15, 12)
-#define RK3568_DSP_IF_POL__HDMI_PIN_POL			GENMASK(7, 4)
-#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL		GENMASK(3, 0)
-
-#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK	BIT(5)
-#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2			BIT(4)
-
-#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN	BIT(31)
-
-#define RK3568_DSP_IF_POL__CFG_DONE_IMD			BIT(28)
-
-#define VOP2_SYS_AXI_BUS_NUM				2
-
-#define VOP2_CLUSTER_YUV444_10				0x12
-
-#define VOP2_COLOR_KEY_MASK				BIT(31)
-
-#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD		BIT(28)
-
-#define RK3568_VP_BG_MIX_CTRL__BG_DLY			GENMASK(31, 24)
-
-#define RK3568_OVL_PORT_SEL__SEL_PORT			GENMASK(31, 16)
-#define RK3568_OVL_PORT_SEL__SMART1			GENMASK(31, 30)
-#define RK3568_OVL_PORT_SEL__SMART0			GENMASK(29, 28)
-#define RK3568_OVL_PORT_SEL__ESMART1			GENMASK(27, 26)
-#define RK3568_OVL_PORT_SEL__ESMART0			GENMASK(25, 24)
-#define RK3568_OVL_PORT_SEL__CLUSTER1			GENMASK(19, 18)
-#define RK3568_OVL_PORT_SEL__CLUSTER0			GENMASK(17, 16)
-#define RK3568_OVL_PORT_SET__PORT2_MUX			GENMASK(11, 8)
-#define RK3568_OVL_PORT_SET__PORT1_MUX			GENMASK(7, 4)
-#define RK3568_OVL_PORT_SET__PORT0_MUX			GENMASK(3, 0)
-#define RK3568_OVL_LAYER_SEL__LAYER(layer, x)		((x) << ((layer) * 4))
-
-#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1		GENMASK(31, 24)
-#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0		GENMASK(23, 16)
-#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1		GENMASK(15, 8)
-#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0		GENMASK(7, 0)
-
-#define RK3568_SMART_DLY_NUM__SMART1			GENMASK(31, 24)
-#define RK3568_SMART_DLY_NUM__SMART0			GENMASK(23, 16)
-#define RK3568_SMART_DLY_NUM__ESMART1			GENMASK(15, 8)
-#define RK3568_SMART_DLY_NUM__ESMART0			GENMASK(7, 0)
-
-#define VP_INT_DSP_HOLD_VALID	BIT(6)
-#define VP_INT_FS_FIELD		BIT(5)
-#define VP_INT_POST_BUF_EMPTY	BIT(4)
-#define VP_INT_LINE_FLAG1	BIT(3)
-#define VP_INT_LINE_FLAG0	BIT(2)
-#define VOP2_INT_BUS_ERRPR	BIT(1)
-#define VP_INT_FS		BIT(0)
-
-#define POLFLAG_DCLK_INV	BIT(3)
-
-enum vop2_layer_phy_id {
-	ROCKCHIP_VOP2_CLUSTER0 = 0,
-	ROCKCHIP_VOP2_CLUSTER1,
-	ROCKCHIP_VOP2_ESMART0,
-	ROCKCHIP_VOP2_ESMART1,
-	ROCKCHIP_VOP2_SMART0,
-	ROCKCHIP_VOP2_SMART1,
-	ROCKCHIP_VOP2_CLUSTER2,
-	ROCKCHIP_VOP2_CLUSTER3,
-	ROCKCHIP_VOP2_ESMART2,
-	ROCKCHIP_VOP2_ESMART3,
-	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
-};
-
-extern const struct component_ops vop2_component_ops;
-
-#endif /* _ROCKCHIP_DRM_VOP2_H */

target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

@@ -1,281 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) Rockchip Electronics Co.Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/component.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <drm/drm_fourcc.h>
-#include <drm/drm_plane.h>
-#include <drm/drm_print.h>
-
-#include "rockchip_drm_vop2.h"
-
-static const uint32_t formats_win_full_10bit[] = {
-	DRM_FORMAT_XRGB8888,
-	DRM_FORMAT_ARGB8888,
-	DRM_FORMAT_XBGR8888,
-	DRM_FORMAT_ABGR8888,
-	DRM_FORMAT_RGB888,
-	DRM_FORMAT_BGR888,
-	DRM_FORMAT_RGB565,
-	DRM_FORMAT_BGR565,
-	DRM_FORMAT_NV12,
-	DRM_FORMAT_NV16,
-	DRM_FORMAT_NV24,
-};
-
-static const uint32_t formats_win_full_10bit_yuyv[] = {
-	DRM_FORMAT_XRGB8888,
-	DRM_FORMAT_ARGB8888,
-	DRM_FORMAT_XBGR8888,
-	DRM_FORMAT_ABGR8888,
-	DRM_FORMAT_RGB888,
-	DRM_FORMAT_BGR888,
-	DRM_FORMAT_RGB565,
-	DRM_FORMAT_BGR565,
-	DRM_FORMAT_NV12,
-	DRM_FORMAT_NV16,
-	DRM_FORMAT_NV24,
-	DRM_FORMAT_YVYU,
-	DRM_FORMAT_VYUY,
-};
-
-static const uint32_t formats_win_lite[] = {
-	DRM_FORMAT_XRGB8888,
-	DRM_FORMAT_ARGB8888,
-	DRM_FORMAT_XBGR8888,
-	DRM_FORMAT_ABGR8888,
-	DRM_FORMAT_RGB888,
-	DRM_FORMAT_BGR888,
-	DRM_FORMAT_RGB565,
-	DRM_FORMAT_BGR565,
-};
-
-static const uint64_t format_modifiers[] = {
-	DRM_FORMAT_MOD_LINEAR,
-	DRM_FORMAT_MOD_INVALID,
-};
-
-static const uint64_t format_modifiers_afbc[] = {
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_SPARSE),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_YTR),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_CBR),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_YTR |
-				AFBC_FORMAT_MOD_SPARSE),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_CBR |
-				AFBC_FORMAT_MOD_SPARSE),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_YTR |
-				AFBC_FORMAT_MOD_CBR),
-
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_YTR |
-				AFBC_FORMAT_MOD_CBR |
-				AFBC_FORMAT_MOD_SPARSE),
-
-	/* SPLIT mandates SPARSE, RGB modes mandates YTR */
-	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
-				AFBC_FORMAT_MOD_YTR |
-				AFBC_FORMAT_MOD_SPARSE |
-				AFBC_FORMAT_MOD_SPLIT),
-	DRM_FORMAT_MOD_INVALID,
-};
-
-static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
-	{
-		.id = 0,
-		.feature = VOP_FEATURE_OUTPUT_10BIT,
-		.gamma_lut_len = 1024,
-		.cubic_lut_len = 9 * 9 * 9,
-		.max_output = { 4096, 2304 },
-		.pre_scan_max_dly = { 69, 53, 53, 42 },
-		.offset = 0xc00,
-	}, {
-		.id = 1,
-		.gamma_lut_len = 1024,
-		.max_output = { 2048, 1536 },
-		.pre_scan_max_dly = { 40, 40, 40, 40 },
-		.offset = 0xd00,
-	}, {
-		.id = 2,
-		.gamma_lut_len = 1024,
-		.max_output = { 1920, 1080 },
-		.pre_scan_max_dly = { 40, 40, 40, 40 },
-		.offset = 0xe00,
-	},
-};
-
-/*
- * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
- * Every cluster can work as 4K win or split into two win.
- * All win in cluster support AFBCD.
- *
- * Every esmart win and smart win support 4 Multi-region.
- *
- * Scale filter mode:
- *
- * * Cluster:  bicubic for horizontal scale up, others use bilinear
- * * ESmart:
- *    * nearest-neighbor/bilinear/bicubic for scale up
- *    * nearest-neighbor/bilinear/average for scale down
- *
- *
- * @TODO describe the wind like cpu-map dt nodes;
- */
-static const struct vop2_win_data rk3568_vop_win_data[] = {
-	{
-		.name = "Smart0-win0",
-		.phys_id = ROCKCHIP_VOP2_SMART0,
-		.base = 0x1c00,
-		.formats = formats_win_lite,
-		.nformats = ARRAY_SIZE(formats_win_lite),
-		.format_modifiers = format_modifiers,
-		.layer_sel_id = 3,
-		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_PRIMARY,
-		.max_upscale_factor = 8,
-		.max_downscale_factor = 8,
-		.dly = { 20, 47, 41 },
-	}, {
-		.name = "Smart1-win0",
-		.phys_id = ROCKCHIP_VOP2_SMART1,
-		.formats = formats_win_lite,
-		.nformats = ARRAY_SIZE(formats_win_lite),
-		.format_modifiers = format_modifiers,
-		.base = 0x1e00,
-		.layer_sel_id = 7,
-		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_PRIMARY,
-		.max_upscale_factor = 8,
-		.max_downscale_factor = 8,
-		.dly = { 20, 47, 41 },
-	}, {
-		.name = "Esmart1-win0",
-		.phys_id = ROCKCHIP_VOP2_ESMART1,
-		.formats = formats_win_full_10bit_yuyv,
-		.nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv),
-		.format_modifiers = format_modifiers,
-		.base = 0x1a00,
-		.layer_sel_id = 6,
-		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_PRIMARY,
-		.max_upscale_factor = 8,
-		.max_downscale_factor = 8,
-		.dly = { 20, 47, 41 },
-	}, {
-		.name = "Esmart0-win0",
-		.phys_id = ROCKCHIP_VOP2_ESMART0,
-		.formats = formats_win_full_10bit_yuyv,
-		.nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv),
-		.format_modifiers = format_modifiers,
-		.base = 0x1800,
-		.layer_sel_id = 2,
-		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_OVERLAY,
-		.max_upscale_factor = 8,
-		.max_downscale_factor = 8,
-		.dly = { 20, 47, 41 },
-	}, {
-		.name = "Cluster0-win0",
-		.phys_id = ROCKCHIP_VOP2_CLUSTER0,
-		.base = 0x1000,
-		.formats = formats_win_full_10bit,
-		.nformats = ARRAY_SIZE(formats_win_full_10bit),
-		.format_modifiers = format_modifiers_afbc,
-		.layer_sel_id = 0,
-		.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
-					DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
-		.max_upscale_factor = 4,
-		.max_downscale_factor = 4,
-		.dly = { 0, 27, 21 },
-		.type = DRM_PLANE_TYPE_OVERLAY,
-		.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER,
-	}, {
-		.name = "Cluster1-win0",
-		.phys_id = ROCKCHIP_VOP2_CLUSTER1,
-		.base = 0x1200,
-		.formats = formats_win_full_10bit,
-		.nformats = ARRAY_SIZE(formats_win_full_10bit),
-		.format_modifiers = format_modifiers_afbc,
-		.layer_sel_id = 1,
-		.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
-					DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_OVERLAY,
-		.max_upscale_factor = 4,
-		.max_downscale_factor = 4,
-		.dly = { 0, 27, 21 },
-		.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER,
-	},
-};
-
-static const struct vop2_data rk3566_vop = {
-	.nr_vps = 3,
-	.max_input = { 4096, 2304 },
-	.max_output = { 4096, 2304 },
-	.vp = rk3568_vop_video_ports,
-	.win = rk3568_vop_win_data,
-	.win_size = ARRAY_SIZE(rk3568_vop_win_data),
-	.soc_id = 3566,
-};
-
-static const struct vop2_data rk3568_vop = {
-	.nr_vps = 3,
-	.max_input = { 4096, 2304 },
-	.max_output = { 4096, 2304 },
-	.vp = rk3568_vop_video_ports,
-	.win = rk3568_vop_win_data,
-	.win_size = ARRAY_SIZE(rk3568_vop_win_data),
-	.soc_id = 3568,
-};
-
-static const struct of_device_id vop2_dt_match[] = {
-	{
-		.compatible = "rockchip,rk3566-vop",
-		.data = &rk3566_vop,
-	}, {
-		.compatible = "rockchip,rk3568-vop",
-		.data = &rk3568_vop,
-	}, {
-	},
-};
-MODULE_DEVICE_TABLE(of, vop2_dt_match);
-
-static int vop2_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-
-	return component_add(dev, &vop2_component_ops);
-}
-
-static int vop2_remove(struct platform_device *pdev)
-{
-	component_del(&pdev->dev, &vop2_component_ops);
-
-	return 0;
-}
-
-struct platform_driver vop2_platform_driver = {
-	.probe = vop2_probe,
-	.remove = vop2_remove,
-	.driver = {
-		.name = "rockchip-vop2",
-		.of_match_table = of_match_ptr(vop2_dt_match),
-	},
-};

target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

@@ -1,581 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
- *
- * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <linux/clk.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of_device.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/units.h>
-
-#define BIT_WRITEABLE_SHIFT		16
-#define REF_CLOCK_24MHz			(24 * HZ_PER_MHZ)
-#define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
-#define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
-
-/* COMBO PHY REG */
-#define PHYREG6				0x14
-#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
-#define PHYREG6_PLL_DIV_SHIFT		6
-#define PHYREG6_PLL_DIV_2		1
-
-#define PHYREG7				0x18
-#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
-#define PHYREG7_TX_RTERM_SHIFT		4
-#define PHYREG7_TX_RTERM_50OHM		8
-#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
-#define PHYREG7_RX_RTERM_SHIFT		0
-#define PHYREG7_RX_RTERM_44OHM		15
-
-#define PHYREG8				0x1C
-#define PHYREG8_SSC_EN			BIT(4)
-
-#define PHYREG11			0x28
-#define PHYREG11_SU_TRIM_0_7		0xF0
-
-#define PHYREG12			0x2C
-#define PHYREG12_PLL_LPF_ADJ_VALUE	4
-
-#define PHYREG13			0x30
-#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
-#define PHYREG13_RESISTER_SHIFT		0x4
-#define PHYREG13_RESISTER_HIGH_Z	3
-#define PHYREG13_CKRCV_AMP0		BIT(7)
-
-#define PHYREG14			0x34
-#define PHYREG14_CKRCV_AMP1		BIT(0)
-
-#define PHYREG15			0x38
-#define PHYREG15_CTLE_EN		BIT(0)
-#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
-#define PHYREG15_SSC_CNT_SHIFT		6
-#define PHYREG15_SSC_CNT_VALUE		1
-
-#define PHYREG16			0x3C
-#define PHYREG16_SSC_CNT_VALUE		0x5f
-
-#define PHYREG18			0x44
-#define PHYREG18_PLL_LOOP		0x32
-
-#define PHYREG32			0x7C
-#define PHYREG32_SSC_MASK		GENMASK(7, 4)
-#define PHYREG32_SSC_DIR_SHIFT		4
-#define PHYREG32_SSC_UPWARD		0
-#define PHYREG32_SSC_DOWNWARD		1
-#define PHYREG32_SSC_OFFSET_SHIFT	6
-#define PHYREG32_SSC_OFFSET_500PPM	1
-
-#define PHYREG33			0x80
-#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
-#define PHYREG33_PLL_KVCO_SHIFT		2
-#define PHYREG33_PLL_KVCO_VALUE		2
-
-struct rockchip_combphy_priv;
-
-struct combphy_reg {
-	u16 offset;
-	u16 bitend;
-	u16 bitstart;
-	u16 disable;
-	u16 enable;
-};
-
-struct rockchip_combphy_grfcfg {
-	struct combphy_reg pcie_mode_set;
-	struct combphy_reg usb_mode_set;
-	struct combphy_reg sgmii_mode_set;
-	struct combphy_reg qsgmii_mode_set;
-	struct combphy_reg pipe_rxterm_set;
-	struct combphy_reg pipe_txelec_set;
-	struct combphy_reg pipe_txcomp_set;
-	struct combphy_reg pipe_clk_25m;
-	struct combphy_reg pipe_clk_100m;
-	struct combphy_reg pipe_phymode_sel;
-	struct combphy_reg pipe_rate_sel;
-	struct combphy_reg pipe_rxterm_sel;
-	struct combphy_reg pipe_txelec_sel;
-	struct combphy_reg pipe_txcomp_sel;
-	struct combphy_reg pipe_clk_ext;
-	struct combphy_reg pipe_sel_usb;
-	struct combphy_reg pipe_sel_qsgmii;
-	struct combphy_reg pipe_phy_status;
-	struct combphy_reg con0_for_pcie;
-	struct combphy_reg con1_for_pcie;
-	struct combphy_reg con2_for_pcie;
-	struct combphy_reg con3_for_pcie;
-	struct combphy_reg con0_for_sata;
-	struct combphy_reg con1_for_sata;
-	struct combphy_reg con2_for_sata;
-	struct combphy_reg con3_for_sata;
-	struct combphy_reg pipe_con0_for_sata;
-	struct combphy_reg pipe_xpcs_phy_ready;
-};
-
-struct rockchip_combphy_cfg {
-	const struct rockchip_combphy_grfcfg *grfcfg;
-	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
-};
-
-struct rockchip_combphy_priv {
-	u8 type;
-	void __iomem *mmio;
-	int num_clks;
-	struct clk_bulk_data *clks;
-	struct device *dev;
-	struct regmap *pipe_grf;
-	struct regmap *phy_grf;
-	struct phy *phy;
-	struct reset_control *phy_rst;
-	const struct rockchip_combphy_cfg *cfg;
-	bool enable_ssc;
-	bool ext_refclk;
-	struct clk *refclk;
-};
-
-static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
-				     int mask, int val, int reg)
-{
-	unsigned int temp;
-
-	temp = readl(priv->mmio + reg);
-	temp = (temp & ~(mask)) | val;
-	writel(temp, priv->mmio + reg);
-}
-
-static int rockchip_combphy_param_write(struct regmap *base,
-					const struct combphy_reg *reg, bool en)
-{
-	u32 val, mask, tmp;
-
-	tmp = en ? reg->enable : reg->disable;
-	mask = GENMASK(reg->bitend, reg->bitstart);
-	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
-
-	return regmap_write(base, reg->offset, val);
-}
-
-static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
-{
-	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-	u32 mask, val;
-
-	mask = GENMASK(cfg->pipe_phy_status.bitend,
-		       cfg->pipe_phy_status.bitstart);
-
-	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
-	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
-
-	return val;
-}
-
-static int rockchip_combphy_init(struct phy *phy)
-{
-	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
-	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-	u32 val;
-	int ret;
-
-	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
-	if (ret) {
-		dev_err(priv->dev, "failed to enable clks\n");
-		return ret;
-	}
-
-	switch (priv->type) {
-	case PHY_TYPE_PCIE:
-	case PHY_TYPE_USB3:
-	case PHY_TYPE_SATA:
-	case PHY_TYPE_SGMII:
-	case PHY_TYPE_QSGMII:
-		if (priv->cfg->combphy_cfg)
-			ret = priv->cfg->combphy_cfg(priv);
-		break;
-	default:
-		dev_err(priv->dev, "incompatible PHY type\n");
-		ret = -EINVAL;
-		break;
-	}
-
-	if (ret) {
-		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
-		goto err_clk;
-	}
-
-	ret = reset_control_deassert(priv->phy_rst);
-	if (ret)
-		goto err_clk;
-
-	if (priv->type == PHY_TYPE_USB3) {
-		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
-						priv, val,
-						val == cfg->pipe_phy_status.enable,
-						10, 1000);
-		if (ret)
-			dev_warn(priv->dev, "wait phy status ready timeout\n");
-	}
-
-	return 0;
-
-err_clk:
-	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-
-	return ret;
-}
-
-static int rockchip_combphy_exit(struct phy *phy)
-{
-	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
-
-	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-	reset_control_assert(priv->phy_rst);
-
-	return 0;
-}
-
-static const struct phy_ops rochchip_combphy_ops = {
-	.init = rockchip_combphy_init,
-	.exit = rockchip_combphy_exit,
-	.owner = THIS_MODULE,
-};
-
-static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
-{
-	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
-
-	if (args->args_count != 1) {
-		dev_err(dev, "invalid number of arguments\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (priv->type != PHY_NONE && priv->type != args->args[0])
-		dev_warn(dev, "phy type select %d overwriting type %d\n",
-			 args->args[0], priv->type);
-
-	priv->type = args->args[0];
-
-	return priv->phy;
-}
-
-static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
-{
-	int i;
-
-	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
-	if (priv->num_clks < 1)
-		return -EINVAL;
-
-	priv->refclk = NULL;
-	for (i = 0; i < priv->num_clks; i++) {
-		if (!strncmp(priv->clks[i].id, "ref", 3)) {
-			priv->refclk = priv->clks[i].clk;
-			break;
-		}
-	}
-
-	if (!priv->refclk) {
-		dev_err(dev, "no refclk found\n");
-		return -EINVAL;
-	}
-
-	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
-	if (IS_ERR(priv->pipe_grf)) {
-		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
-		return PTR_ERR(priv->pipe_grf);
-	}
-
-	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
-	if (IS_ERR(priv->phy_grf)) {
-		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
-		return PTR_ERR(priv->phy_grf);
-	}
-
-	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
-
-	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
-
-	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
-	if (IS_ERR(priv->phy_rst))
-		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
-
-	return 0;
-}
-
-static int rockchip_combphy_probe(struct platform_device *pdev)
-{
-	struct phy_provider *phy_provider;
-	struct device *dev = &pdev->dev;
-	struct rockchip_combphy_priv *priv;
-	const struct rockchip_combphy_cfg *phy_cfg;
-	struct resource *res;
-	int ret;
-
-	phy_cfg = of_device_get_match_data(dev);
-	if (!phy_cfg) {
-		dev_err(dev, "no OF match data provided\n");
-		return -EINVAL;
-	}
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-	if (IS_ERR(priv->mmio)) {
-		ret = PTR_ERR(priv->mmio);
-		return ret;
-	}
-
-	priv->dev = dev;
-	priv->type = PHY_NONE;
-	priv->cfg = phy_cfg;
-
-	ret = rockchip_combphy_parse_dt(dev, priv);
-	if (ret)
-		return ret;
-
-	ret = reset_control_assert(priv->phy_rst);
-	if (ret) {
-		dev_err(dev, "failed to reset phy\n");
-		return ret;
-	}
-
-	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
-	if (IS_ERR(priv->phy)) {
-		dev_err(dev, "failed to create combphy\n");
-		return PTR_ERR(priv->phy);
-	}
-
-	dev_set_drvdata(dev, priv);
-	phy_set_drvdata(priv->phy, priv);
-
-	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
-
-	return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
-{
-	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-	unsigned long rate;
-	u32 val;
-
-	switch (priv->type) {
-	case PHY_TYPE_PCIE:
-		/* Set SSC downward spread spectrum. */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
-
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
-		break;
-
-	case PHY_TYPE_USB3:
-		/* Set SSC downward spread spectrum. */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
-
-		/* Enable adaptive CTLE for USB3.0 Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
-
-		/* Set PLL KVCO fine tuning signals. */
-		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
-					 PHYREG33);
-
-		/* Enable controlling random jitter. */
-		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
-
-		/* Set PLL input clock divider 1/2. */
-		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
-					 PHYREG6);
-
-		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
-		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
-
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
-		break;
-
-	case PHY_TYPE_SATA:
-		/* Enable adaptive CTLE for SATA Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
-		/*
-		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
-		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
-		 */
-		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
-		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
-		writel(val, priv->mmio + PHYREG7);
-
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
-		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
-		break;
-
-	case PHY_TYPE_SGMII:
-		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
-		break;
-
-	case PHY_TYPE_QSGMII:
-		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
-		break;
-
-	default:
-		dev_err(priv->dev, "incompatible PHY type\n");
-		return -EINVAL;
-	}
-
-	rate = clk_get_rate(priv->refclk);
-
-	switch (rate) {
-	case REF_CLOCK_24MHz:
-		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
-			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
-			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
-						 val, PHYREG15);
-
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
-		}
-		break;
-
-	case REF_CLOCK_25MHz:
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
-		break;
-
-	case REF_CLOCK_100MHz:
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
-		if (priv->type == PHY_TYPE_PCIE) {
-			/* PLL KVCO  fine tuning. */
-			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
-
-			/* Enable controlling random jitter. */
-			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
-
-			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-						 val, PHYREG6);
-
-			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
-			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
-		} else if (priv->type == PHY_TYPE_SATA) {
-			/* downward spread spectrum +500ppm */
-			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
-			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
-		}
-		break;
-
-	default:
-		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
-		return -EINVAL;
-	}
-
-	if (priv->ext_refclk) {
-		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
-		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
-			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
-			val |= PHYREG13_CKRCV_AMP0;
-			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
-
-			val = readl(priv->mmio + PHYREG14);
-			val |= PHYREG14_CKRCV_AMP1;
-			writel(val, priv->mmio + PHYREG14);
-		}
-	}
-
-	if (priv->enable_ssc) {
-		val = readl(priv->mmio + PHYREG8);
-		val |= PHYREG8_SSC_EN;
-		writel(val, priv->mmio + PHYREG8);
-	}
-
-	return 0;
-}
-
-static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
-	/* pipe-phy-grf */
-	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
-	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
-	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
-	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
-	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
-	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
-	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
-	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
-	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
-	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
-	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
-	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
-	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
-	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
-	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
-	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
-	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
-	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
-	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
-	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
-	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
-	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
-	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
-	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
-	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
-	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
-	/* pipe-grf */
-	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
-	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
-};
-
-static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
-	.grfcfg		= &rk3568_combphy_grfcfgs,
-	.combphy_cfg	= rk3568_combphy_cfg,
-};
-
-static const struct of_device_id rockchip_combphy_of_match[] = {
-	{
-		.compatible = "rockchip,rk3568-naneng-combphy",
-		.data = &rk3568_combphy_cfgs,
-	},
-	{ },
-};
-MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
-
-static struct platform_driver rockchip_combphy_driver = {
-	.probe	= rockchip_combphy_probe,
-	.driver = {
-		.name = "rockchip-naneng-combphy",
-		.of_match_table = rockchip_combphy_of_match,
-	},
-};
-module_platform_driver(rockchip_combphy_driver);
-
-MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
-MODULE_LICENSE("GPL v2");

target/linux/rockchip/files-5.15/include/dt-bindings/soc/rockchip,vop2.h

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
-
-#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
-#define __DT_BINDINGS_ROCKCHIP_VOP2_H
-
-#define ROCKCHIP_VOP2_EP_RGB0	1
-#define ROCKCHIP_VOP2_EP_HDMI0	2
-#define ROCKCHIP_VOP2_EP_EDP0	3
-#define ROCKCHIP_VOP2_EP_MIPI0	4
-#define ROCKCHIP_VOP2_EP_LVDS0	5
-#define ROCKCHIP_VOP2_EP_MIPI1	6
-#define ROCKCHIP_VOP2_EP_LVDS1	7
-
-#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts

@@ -1,495 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 EmbedFire <embedfire@embedfire.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "rk3328-dram-nanopi2-timing.dtsi"
-#include "rk3328.dtsi"
-
-/ {
-	model = "EmbedFire DoorNet1";
-	compatible = "embedfire,doornet1", "rockchip,rk3328";
-	
-	aliases {
-		led-boot = &sys_led;
-		led-failsafe = &sys_led;
-		led-running = &sys_led;
-		led-upgrade = &sys_led;
-		// mmc1 = &sdmmc;
-		// mmc0 = &emmc;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	gmac_clk: gmac-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "gmac_clkin";
-		#clock-cells = <0>;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&reset_button_pin>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <50>;
-		};
-	};
-
-	vcc_rtl8153: vcc-rtl8153-regulator {
-		compatible = "regulator-fixed";
-		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&rtl8153_en_drv>;
-		regulator-always-on;
-		regulator-name = "vcc_rtl8153";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-	};
-
-	dmc: dmc {
-		  	compatible = "rockchip,rk3328-dmc";
-		   	devfreq-events = <&dfi>;
-			center-supply = <&vdd_log>;
-			clocks = <&cru SCLK_DDRCLK>;
-			clock-names = "dmc_clk";
-			operating-points-v2 = <&dmc_opp_table>;
-	    	ddr_timing = <&ddr_timing>;
-			upthreshold = <40>;
-			downdifferential = <20>;
-			auto-min-freq = <786000>;
-			auto-freq-en = <1>;
-			#cooling-cells = <2>;
-			status = "okay";
-
-		ddr_power_model: ddr_power_model {
-			compatible = "ddr_power_model";
-			dynamic-power-coefficient = <120>;
-			static-power-coefficient = <200>;
-			ts = <32000 4700 (-80) 2>;
-			thermal-zone = "soc-thermal";
-		};
-	};
-
-	dmc_opp_table: dmc-opp-table {
-		compatible = "operating-points-v2";
-
-		rockchip,leakage-voltage-sel = <
-			1   10    0
-			11  254   1
-		>;
-		nvmem-cells = <&logic_leakage>;
-		nvmem-cell-names = "ddr_leakage";
-
-		opp-786000000 {
-			opp-hz = /bits/ 64 <786000000>;
-			opp-microvolt = <1075000>;
-			opp-microvolt-L0 = <1075000>;
-			opp-microvolt-L1 = <1050000>;
-		};
-		opp-798000000 {
-			opp-hz = /bits/ 64 <798000000>;
-			opp-microvolt = <1075000>;
-			opp-microvolt-L0 = <1075000>;
-			opp-microvolt-L1 = <1050000>;
-		};
-		opp-840000000 {
-			opp-hz = /bits/ 64 <840000000>;
-			opp-microvolt = <1075000>;
-			opp-microvolt-L0 = <1075000>;
-			opp-microvolt-L1 = <1050000>;
-		};
-		opp-924000000 {
-			opp-hz = /bits/ 64 <924000000>;
-			opp-microvolt = <1100000>;
-			opp-microvolt-L0 = <1100000>;
-			opp-microvolt-L1 = <1075000>;
-		};
-		opp-1056000000 {
-			opp-hz = /bits/ 64 <1056000000>;
-			opp-microvolt = <1175000>;
-			opp-microvolt-L0 = <1175000>;
-			opp-microvolt-L1 = <1150000>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
-		pinctrl-names = "default";
-
-		lan_led: led-0 {
-			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-			label = "doornet1:green:lan";
-		};
-
-		sys_led: led-1 {
-			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-			label = "doornet1:red:sys";
-		};
-
-		wan_led: led-2 {
-			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-			label = "doornet1:green:wan";
-		};
-		
-		wifi_enable: wifi_enable {
-			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-			label = "wifi-enable";
-		};	
-	};
-
-	vcc_io_sdio: sdmmcio-regulator {
-		compatible = "regulator-gpio";
-		enable-active-high;
-		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
-		pinctrl-0 = <&sdio_vcc_pin>;
-		pinctrl-names = "default";
-		regulator-name = "vcc_io_sdio";
-		regulator-always-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-settling-time-us = <5000>;
-		regulator-type = "voltage";
-		startup-delay-us = <2000>;
-		states = <1800000 0x1
-			  3300000 0x0>;
-		vin-supply = <&vcc_io_33>;
-	};
-
-	vcc_sd: sdmmc-regulator {
-		compatible = "regulator-fixed";
-		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-		pinctrl-0 = <&sdmmc0m1_pin>;
-		pinctrl-names = "default";
-		regulator-name = "vcc_sd";
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc_io_33>;
-	};
-
-	vdd_5v: vdd-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_5v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&dfi {
-	status = "okay";
-};
-
-&gmac2io {
-	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-	clock_in_out = "input";
-	phy-mode = "rgmii";
-	phy-supply = <&vcc_io_33>;
-	pinctrl-0 = <&rgmiim1_pins>;
-	pinctrl-names = "default";
-	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-	snps,reset-delays-us = <0 1000000 50000>;
-	snps,reset-active-low;
-	tx_delay = <0x18>;
-	rx_delay = <0x24>;
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-
-	rk805: pmic@18 {
-		compatible = "rockchip,rk805";
-		reg = <0x18>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "xin32k", "rk805-clkout2";
-		gpio-controller;
-		#gpio-cells = <2>;
-		pinctrl-0 = <&pmic_int_l>;
-		pinctrl-names = "default";
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vdd_5v>;
-		vcc2-supply = <&vdd_5v>;
-		vcc3-supply = <&vdd_5v>;
-		vcc4-supply = <&vdd_5v>;
-		vcc5-supply = <&vcc_io_33>;
-		vcc6-supply = <&vdd_5v>;
-
-		regulators {
-			vdd_log: DCDC_REG1 {
-				regulator-name = "vdd_log";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <1075000>;
-				regulator-min-microvolt = <712500>;
-				regulator-max-microvolt = <1450000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vdd_arm: DCDC_REG2 {
-				regulator-name = "vdd_arm";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <1225000>;				
-				regulator-min-microvolt = <712500>;
-				regulator-max-microvolt = <1450000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <950000>;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_io_33: DCDC_REG4 {
-				regulator-name = "vcc_io_33";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcc_18: LDO_REG1 {
-				regulator-name = "vcc_18";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc18_emmc: LDO_REG2 {
-				regulator-name = "vcc18_emmc";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd_10: LDO_REG3 {
-				regulator-name = "vdd_10";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-		};
-	};
-        usb {
-                rtl8153_en_drv: rtl8153-en-drv {
-                        rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-};
-
-&io_domains {
-	pmuio-supply = <&vcc_io_33>;
-	vccio1-supply = <&vcc_io_33>;
-	vccio2-supply = <&vcc18_emmc>;
-	vccio3-supply = <&vcc_io_sdio>;
-	vccio4-supply = <&vcc_18>;
-	vccio5-supply = <&vcc_io_33>;
-	vccio6-supply = <&vcc_io_33>;
-	status = "okay";
-};
-
-&pinctrl {
-	button {
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	ethernet-phy {
-		eth_phy_reset_pin: eth-phy-reset-pin {
-			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-
-	leds {
-		lan_led_pin: lan-led-pin {
-			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wifi_pin: wifi_pin{
-			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	sd {
-		sdio_vcc_pin: sdio-vcc-pin {
-			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&pwm2 {
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	disable-wp;
-	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-	pinctrl-names = "default";
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc_sd>;
-	vqmmc-supply = <&vcc_io_sdio>;
-	status = "okay";
-};
-
-&emmc {
-	bus-width = <8>;
-	cap-mmc-highspeed;
-	max-frequency = <150000000>;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-	vmmc-supply = <&vcc_io_33>;
-	vqmmc-supply = <&vcc18_emmc>;
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <0>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&u2phy {
-	status = "okay";
-};
-
-&u2phy_host {
-	status = "okay";
-};
-
-&u2phy_otg {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb20_otg {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usbdrd3 {
-	status = "okay";
-};
-
-&usbdrd3 {
-	dr_mode = "host";
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	/* Second port is for USB 3.0 */
-	rtl8153: device@2 {
-		compatible = "usbbda,8153";
-		reg = <2>;
-
-		realtek,led-data = <0x87>;
-	};
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts

@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
- */
-
-/dts-v1/;
-
-#include "rk3328-nanopi-r2s.dts"
-
-/ {
-	model = "FriendlyElec NanoPi R2C";
-	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-};
-
-&gmac2io {
-	phy-handle = <&yt8521s>;
-
-	mdio {
-		/delete-node/ ethernet-phy@1;
-
-		yt8521s: ethernet-phy@3 {
-			compatible = "ethernet-phy-id0000.011a",
-				     "ethernet-phy-ieee802.3-c22";
-			reg = <3>;
-			pinctrl-0 = <&eth_phy_reset_pin>;
-			pinctrl-names = "default";
-			reset-assert-us = <10000>;
-			reset-deassert-us = <50000>;
-			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&lan_led {
-	label = "nanopi-r2c:green:lan";
-};
-
-&sys_led {
-	label = "nanopi-r2c:red:sys";
-};
-
-&wan_led {
-	label = "nanopi-r2c:green:wan";
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-#include "rk3328-orangepi-r1-plus.dts"
-
-/ {
-	model = "Xunlong Orange Pi R1 Plus LTS";
-	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-};
-
-/delete-node/ &rtl8211e;
-&gmac2io {
-        phy-handle = <&ethphy3>;
-        snps,reset-delays-us = <0 15000 50000>;
-        tx_delay = <0x19>;
-        rx_delay = <0x05>;
-        status = "okay";
-
-        mdio {
-                compatible = "snps,dwmac-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                ethphy3: ethernet-phy@0 {
-                        reg = <0x0>;
-                        keep-clkout-on;
-                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-                };
-        };
-};
-
-&sdmmc {
-      bus-width = <4>;
-      cap-sd-highspeed;
-      disable-wp;
-      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-      pinctrl-names = "default";
-      sd-uhs-sdr12;
-      sd-uhs-sdr25;
-      sd-uhs-sdr50;
-      sd-uhs-sdr104;
-      vmmc-supply = <&vcc_sd>;
-      vqmmc-supply = <&vcc_io_sdio>;
-      status = "okay";
-};
-
-&dmc_opp_table {
-        opp-1056000000 {
-                status = "disabled";
-        };
-        opp-924000000 {
-                status = "disabled";
-        };
-        opp-840000000 {
-                status = "disabled";
-        };
-        opp-798000000 {
-                status = "disabled";
-        };
-};
-
-&sys_led {
-       label = "orangepi-r1-plus-lts:red:sys";
-};
-
-&wan_led {
-       label = "orangepi-r1-plus-lts:green:wan";
-};
-
-&lan_led {
-       label = "orangepi-r1-plus-lts:green:lan";
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-#include "rk3328-nanopi-r2s.dts"
-
-/ {
-	model = "Xunlong Orange Pi R1 Plus";
-	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-};
-
-&lan_led {
-	label = "orangepi-r1-plus:green:lan";
-};
-
-&spi0 {
-	max-freq = <48000000>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-	};
-};
-
-&sys_led {
-	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-	label = "orangepi-r1-plus:red:sys";
-};
-
-&sys_led_pin {
-	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&wan_led {
-	label = "orangepi-r1-plus:green:wan";
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts

@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include "rk3399-doornet2.dtsi"
-
-/ {
-	model = "EmbedFire DoorNet2 1GB";
-	compatible = "embedfire,doornet2", "rockchip,rk3399";
-
-	aliases {
-		led-boot = &sys_led;
-		led-failsafe = &sys_led;
-		led-running = &sys_led;
-		led-upgrade = &sys_led;
-	};
-
-	/delete-node/ display-subsystem;
-
-	gpio-leds {
-		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-
-		/delete-node/ status;
-
-		lan_led: led-lan {
-			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-			label = "green:lan";
-		};
-
-		sys_led: led-sys {
-			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-			label = "red:sys";
-			default-state = "on";
-		};
-
-		wan_led: led-wan {
-			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-			label = "green:wan";
-		};
-	};
-
-	gpio-keys {
-		pinctrl-0 = <&reset_button_pin>;
-
-		/delete-node/ power;
-
-		reset {
-			debounce-interval = <50>;
-			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	vdd_5v: vdd-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_5v";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&pcie0 {
-	max-link-speed = <1>;
-	num-lanes = <1>;
-	vpcie3v3-supply = <&vcc3v3_sys>;
-
-	pcie@0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		pcie-eth@0,0 {
-			compatible = "realtek,r8168";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x870>;
-		};
-	};
-};
-
-&pinctrl {
-	gpio-leds {
-		/delete-node/ leds-gpio;
-
-		lan_led_pin: lan-led-pin {
-			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	rockchip-key {
-		/delete-node/ power-key;
-
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&u2phy0_host {
-	phy-supply = <&vdd_5v>;
-};
-
-&vcc3v3_sys {
-	vin-supply = <&vcc5v0_sys>;
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi

@@ -1,636 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include "rk3399.dtsi"
-
-/ {
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	clkin_gmac: external-gmac-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "clkin_gmac";
-		#clock-cells = <0>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-name = "vcc3v3_sys";
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-name = "vcc5v0_sys";
-		vin-supply = <&vdd_5v>;
-	};
-
-	/* switched by pmic_sleep */
-	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-name = "vcc1v8_s3";
-		vin-supply = <&vcc_1v8>;
-	};
-
-	vcc3v0_sd: vcc3v0-sd {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc0_pwr_h>;
-		regulator-always-on;
-		regulator-min-microvolt = <3000000>;
-		regulator-max-microvolt = <3000000>;
-		regulator-name = "vcc3v0_sd";
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vbus_typec: vbus-typec {
-		compatible = "regulator-fixed";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-name = "vbus_typec";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		pinctrl-names = "default";
-		pinctrl-0 = <&power_key>;
-
-		power {
-			debounce-interval = <100>;
-			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
-			label = "GPIO Key Power";
-			linux,code = <KEY_POWER>;
-			wakeup-source;
-		};
-	};
-
-	leds: gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_gpio>;
-
-		status {
-			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-			label = "status_led";
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-	sdio_pwrseq: sdio-pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk808 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_reg_on_h>;
-		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&cpu_b0 {
-	cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
-	cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_l0 {
-	cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
-	cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
-	cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
-	cpu-supply = <&vdd_cpu_l>;
-};
-
-&emmc_phy {
-	status = "okay";
-};
-
-&gmac {
-	assigned-clocks = <&cru SCLK_RMII_SRC>;
-	assigned-clock-parents = <&clkin_gmac>;
-	clock_in_out = "input";
-	phy-supply = <&vcc3v3_s3>;
-	phy-mode = "rgmii";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 100000 50000>;
-	tx_delay = <0x28>;
-	rx_delay = <0x11>;
-	status = "okay";
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	ddc-i2c-bus = <&i2c7>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&hdmi_cec>;
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	i2c-scl-rising-time-ns = <160>;
-	i2c-scl-falling-time-ns = <30>;
-	status = "okay";
-
-	vdd_cpu_b: regulator@40 {
-		compatible = "silergy,syr827";
-		reg = <0x40>;
-		fcs,suspend-voltage-selector = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&cpu_b_sleep>;
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <712500>;
-		regulator-max-microvolt = <1500000>;
-		regulator-name = "vdd_cpu_b";
-		regulator-ramp-delay = <1000>;
-		vin-supply = <&vcc3v3_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vdd_gpu: regulator@41 {
-		compatible = "silergy,syr828";
-		reg = <0x41>;
-		fcs,suspend-voltage-selector = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&gpu_sleep>;
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <712500>;
-		regulator-max-microvolt = <1500000>;
-		regulator-name = "vdd_gpu";
-		regulator-ramp-delay = <1000>;
-		vin-supply = <&vcc3v3_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk808: pmic@1b {
-		compatible = "rockchip,rk808";
-		reg = <0x1b>;
-		clock-output-names = "xin32k", "rtc_clko_wifi";
-		#clock-cells = <1>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		vcc10-supply = <&vcc3v3_sys>;
-		vcc11-supply = <&vcc3v3_sys>;
-		vcc12-supply = <&vcc3v3_sys>;
-		vddio-supply = <&vcc_3v0>;
-
-		regulators {
-			vdd_center: DCDC_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-name = "vdd_center";
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_cpu_l: DCDC_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-name = "vdd_cpu_l";
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_ddr";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_1v8";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc1v8_cam: LDO_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc1v8_cam";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v0_touch: LDO_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-name = "vcc3v0_touch";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_pmupll: LDO_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc1v8_pmupll";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_sdio: LDO_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <3000000>;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc_sdio";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3000000>;
-				};
-			};
-
-			vcca3v0_codec: LDO_REG5 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-name = "vcca3v0_codec";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v5: LDO_REG6 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1500000>;
-				regulator-max-microvolt = <1500000>;
-				regulator-name = "vcc_1v5";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1500000>;
-				};
-			};
-
-			vcca1v8_codec: LDO_REG7 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcca1v8_codec";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v0: LDO_REG8 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-name = "vcc_3v0";
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3000000>;
-				};
-			};
-
-			vcc3v3_s3: SWITCH_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc3v3_s3";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_s0: SWITCH_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc3v3_s0";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <200000>;
-	i2c-scl-rising-time-ns = <150>;
-	i2c-scl-falling-time-ns = <30>;
-	status = "okay";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c7 {
-	status = "okay";
-};
-
-&io_domains {
-	bt656-supply = <&vcc_1v8>;
-	audio-supply = <&vcca1v8_codec>;
-	sdmmc-supply = <&vcc_sdio>;
-	gpio1830-supply = <&vcc_3v0>;
-	status = "okay";
-};
-
-&pcie_phy {
-	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
-	assigned-clock-rates = <100000000>;
-	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
-	status = "okay";
-};
-
-&pcie0 {
-	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-	max-link-speed = <2>;
-	num-lanes = <4>;
-	status = "okay";
-};
-
-&pinctrl {
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	gpio-leds {
-		leds_gpio: leds-gpio {
-			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	ethernet-phy {
-		eth_phy_reset_pin: eth-phy-reset-pin {
-			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-
-	pmic {
-		cpu_b_sleep: cpu-b-sleep {
-			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-
-		gpu_sleep: gpu-sleep {
-			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	rockchip-key {
-		power_key: power-key {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	sdio {
-		bt_host_wake_l: bt-host-wake-l {
-			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_reg_on_h: bt-reg-on-h {
-			/* external pullup to VCC1V8_PMUPLL */
-			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_wake_l: bt-wake-l {
-			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wifi_reg_on_h: wifi-reg_on-h {
-			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	sdmmc {
-		sdmmc0_det_l: sdmmc0-det-l {
-			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		sdmmc0_pwr_h: sdmmc0-pwr-h {
-			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmu1830-supply = <&vcc_3v0>;
-	status = "okay";
-};
-
-&pwm1 {
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca1v8_s3>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	non-removable;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-mmc-highspeed;
-	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v0_sd>;
-	vqmmc-supply = <&vcc_sdio>;
-	status = "okay";
-};
-
-&tcphy0 {
-	status = "okay";
-};
-
-&tcphy1 {
-	status = "okay";
-};
-
-&tsadc {
-	/* tshut mode 0:CRU 1:GPIO */
-	rockchip,hw-tshut-mode = <1>;
-	/* tshut polarity 0:LOW 1:HIGH */
-	rockchip,hw-tshut-polarity = <1>;
-	status = "okay";
-};
-
-&u2phy0 {
-	status = "okay";
-};
-
-&u2phy0_host {
-	status = "okay";
-};
-
-&u2phy0_otg {
-	status = "okay";
-};
-
-&u2phy1 {
-	status = "okay";
-};
-
-&u2phy1_otg {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usbdrd3_0 {
-	status = "okay";
-};
-
-&usbdrd3_1 {
-	status = "okay";
-};
-
-&usbdrd_dwc3_0 {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usbdrd_dwc3_1 {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&vopb {
-	status = "okay";
-};
-
-&vopb_mmu {
-	status = "okay";
-};
-
-&vopl {
-	status = "okay";
-};
-
-&vopl_mmu {
-	status = "okay";
-};
-

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi

@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
- *
- * Copyright (c) 2020 Tianling Shen <cnsztl@gmail.com>
- * Copyright (c) 2020 gzelvis <gzelvis@gmail.com>
- */
-
-/ {
-	cluster0_opp: opp-table-0 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <408000000>;
-			opp-microvolt = <800000>;
-			clock-latency-ns = <40000>;
-		};
-		opp01 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <800000>;
-		};
-		opp02 {
-			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <850000>;
-		};
-		opp03 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <925000>;
-		};
-		opp04 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1000000>;
-		};
-		opp05 {
-			opp-hz = /bits/ 64 <1416000000>;
-			opp-microvolt = <1125000>;
-		};
-		opp06 {
-			opp-hz = /bits/ 64 <1608000000>;
-			opp-microvolt = <1225000>;
-		};
-		opp07 {
-			opp-hz = /bits/ 64 <1800000000>;
-			opp-microvolt = <1275000>;
-		};
-	};
-
-	cluster1_opp: opp-table-1 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <408000000>;
-			opp-microvolt = <800000>;
-			clock-latency-ns = <40000>;
-		};
-		opp01 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <800000>;
-		};
-		opp02 {
-			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <825000>;
-		};
-		opp03 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <875000>;
-		};
-		opp04 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <950000>;
-		};
-		opp05 {
-			opp-hz = /bits/ 64 <1416000000>;
-			opp-microvolt = <1025000>;
-		};
-		opp06 {
-			opp-hz = /bits/ 64 <1608000000>;
-			opp-microvolt = <1100000>;
-		};
-		opp07 {
-			opp-hz = /bits/ 64 <1800000000>;
-			opp-microvolt = <1200000>;
-		};
-		opp08 {
-			opp-hz = /bits/ 64 <2016000000>;
-			opp-microvolt = <1250000>;
-		};
-		opp09 {
-			opp-hz = /bits/ 64 <2208000000>;
-			opp-microvolt = <1325000>;
-		};
-	};
-
-	gpu_opp_table: opp-table-2 {
-		compatible = "operating-points-v2";
-
-		opp00 {
-			opp-hz = /bits/ 64 <200000000>;
-			opp-microvolt = <800000>;
-		};
-		opp01 {
-			opp-hz = /bits/ 64 <297000000>;
-			opp-microvolt = <800000>;
-		};
-		opp02 {
-			opp-hz = /bits/ 64 <400000000>;
-			opp-microvolt = <825000>;
-		};
-		opp03 {
-			opp-hz = /bits/ 64 <500000000>;
-			opp-microvolt = <875000>;
-		};
-		opp04 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <925000>;
-		};
-		opp05 {
-			opp-hz = /bits/ 64 <800000000>;
-			opp-microvolt = <1100000>;
-		};
-	};
-};
-
-&cpu_l0 {
-	operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l1 {
-	operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l2 {
-	operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l3 {
-	operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_b0 {
-	operating-points-v2 = <&cluster1_opp>;
-};
-
-&cpu_b1 {
-	operating-points-v2 = <&cluster1_opp>;
-};
-
-&gpu {
-	operating-points-v2 = <&gpu_opp_table>;
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts

@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
- */
-
-/* TODO
- * Delete this file and migrate RockPi 4 to RockPi 4A after
- * removing Kernel 5.4.
- */
-
-
-/dts-v1/;
-#include "rk3399-rock-pi-4.dtsi"
-
-/ {
-	model = "Radxa ROCK Pi 4";
-	compatible = "radxa,rockpi4", "rockchip,rk3399";
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

@@ -1,825 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "FriendlyElec NanoPi R5S";
-	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &gmac0;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
-		led-boot = &sys_led;
-		led-failsafe = &sys_led;
-		led-running = &sys_led;
-		led-upgrade = &sys_led;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		cooling-levels = <0 18 102 170 255>;
-		#cooling-cells = <2>;
-		fan-supply = <&vcc5v0_sysp>;
-		pwms = <&pwm0 0 50000 0>;
-	};
-
-	firmware {
-		optee: optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-
-	cspmu: cspmu@fd90c000 {
-		compatible = "rockchip,cspmu";
-		reg = <0x0 0xfd90c000 0x0 0x1000>,
-			<0x0 0xfd90d000 0x0 0x1000>,
-			<0x0 0xfd90e000 0x0 0x1000>,
-			<0x0 0xfd90f000 0x0 0x1000>;
-	};
-
-	gpio-key {
-		compatible = "gpio-key";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key1_pin>;
-
-		button@1 {
-			debounce-interval = <50>;
-			gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
-			wakeup-source;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		sys_led: led-sys {
-			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
-			linux,default-trigger = "heartbeat";
-			pinctrl-names = "default";
-			pinctrl-0 = <&sys_led_pin>;
-		};
-
-		wan_led: led-wan {
-			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-			label = "green:wan";
-			pinctrl-names = "default";
-			pinctrl-0 = <&wan_led_pin>;
-		};
-
-		lan1_led: led-lan1 {
-			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-			label = "green:lan1";
-			pinctrl-names = "default";
-			pinctrl-0 = <&lan1_led_pin>;
-		};
-
-		lan2_led: led-lan2 {
-			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
-			label = "green:lan2";
-			pinctrl-names = "default";
-			pinctrl-0 = <&lan2_led_pin>;
-		};
-	};
-
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	vdd_usbc: vdd-usbc {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_usbc";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	pcie30_avdd0v9: pcie30-avdd0v9 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd0v9";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <900000>;
-		regulator-max-microvolt = <900000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	pcie30_avdd1v8: pcie30-avdd1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <200000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc3v3_pcie>;
-	};
-
-	vcc3v3_ngff: vcc3v3-ngff-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_ngff";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc3v3_pcie>;
-	};
-
-	vcc5v0_usb: vcc5v0_usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	vcc5v0_usb_host: vcc5v0-usb-host {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_host_en>;
-		regulator-name = "vcc5v0_usb_host";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_sysp: vcc5v0-sysp {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sysp";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&combphy2 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gmac0 {
-	phy-mode = "rgmii";
-	clock_in_out = "output";
-
-	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac0_miim
-		     &gmac0_tx_bus2
-		     &gmac0_rx_bus2
-		     &gmac0_rgmii_clk
-		     &gmac0_rgmii_bus>;
-
-	tx_delay = <0x3c>;
-	rx_delay = <0x2f>;
-
-	phy-handle = <&rgmii_phy0>;
-	status = "okay";
-};
-
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint {
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-always-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-
-&i2c5 {
-	status = "okay";
-
-	hym8563: hym8563@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&rtc_int>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-		wakeup-source;
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&i2s1_8ch {
-	rockchip,trcm-sync-tx-only;
-	status = "okay";
-};
-
-
-&mdio0 {
-	rgmii_phy0: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_int>;
-	};
-};
-
-&pcie30phy {
-	data-lanes = <1 2>;
-	status = "okay";
-};
-
-&pcie3x1 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_ngff>;
-	status = "okay";
-};
-
-&pcie3x2 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-};
-
-&pcie2x1 {
-	num-viewport = <4>;
-	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&pinctrl {
-	gpio-leds {
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		lan1_led_pin: lan1-led-pin {
-			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		lan2_led_pin: lan2-led-pin {
-			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	gmac {
-		gmac_int: gmac-int {
-			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	gpio-key {
-		key1_pin: key1-pin {
-			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	rtc {
-		rtc_int: rtc-int {
-			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&pwm0 {
-	status = "okay";
-};
-
-&pwm4 {
-	status = "disabled";
-};
-
-&pwm5 {
-	status = "disabled";
-};
-
-&pwm7 {
-	status = "disabled";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sata2 {
-	status = "disabled";
-};
-
-&sdhci {
-	bus-width = <8>;
-	non-removable;
-	max-frequency = <200000000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	status = "okay";
-};
-
-&spi3 {
-	pinctrl-0 = <&spi3m1_pins>;
-	status = "disabled";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "disabled";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart7 {
-	pinctrl-0 = <&uart7m1_xfer>;
-	status = "disabled";
-};
-
-&uart9 {
-	pinctrl-0 = <&uart9m1_xfer>;
-	status = "disabled";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	phy-supply = <&vcc5v0_usb_otg>;
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb2phy1_host {
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&vp0 {
-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-		remote-endpoint = <&hdmi_in_vp0>;
-	};
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts

@@ -1,541 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "FastRhino R66S";
-	compatible = "fastrhino,r66s", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &rtl8125_1;
-		ethernet1 = &rtl8125_2;
-		led-boot = &power_led;
-		led-failsafe = &power_led;
-		led-running = &power_led;
-		led-upgrade = &power_led;
-		mmc0 = &sdmmc0;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&power_led_pin>;
-
-		power_led: led-power {
-			label = "green:power";
-			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&reset_button_pin>;
-
-		reset {
-			debounce-interval = <50>;
-			gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	dc_12v: dc-12v {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-name = "vcc5v0_sys";
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_usb_host: vcc5v0-usb-host {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb_host";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-min-microvolt = <950000>;
-				regulator-max-microvolt = <950000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-init-microvolt = <950000>;
-				regulator-min-microvolt = <950000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <950000>;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-
-	};
-};
-
-&pcie30phy {
-	data-lanes = <1 2>;
-	status = "okay";
-};
-
-&pcie3x1 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-
-	pcie@10 {
-		reg = <0x00100000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		rtl8125_1: pcie-eth@10,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
-};
-
-&pcie3x2 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-
-	pcie@20 {
-		reg = <0x00200000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		rtl8125_2: pcie-eth@20,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
-};
-
-&pinctrl {
-	gpio-leds {
-		power_led_pin: power-led-pin {
-			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	rockchip-key {
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&rng {
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	disable-wp;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	extcon = <&usb2phy0>;
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	phy-supply = <&vcc5v0_usb_otg>;
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts

@@ -1,617 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "Radxa ROCK3 Model A";
-	compatible = "radxa,rock3a", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &gmac1;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_user: led-0 {
-			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_HEARTBEAT;
-			color = <LED_COLOR_ID_BLUE>;
-			linux,default-trigger = "heartbeat";
-			pinctrl-names = "default";
-			pinctrl-0 = <&led_user_en>;
-		};
-	};
-
-	rk809-sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,name = "Analog RK809";
-		simple-audio-card,mclk-fs = <256>;
-
-		simple-audio-card,cpu {
-			sound-dai = <&i2s1_8ch>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&rk809>;
-		};
-	};
-
-	vcc12v_dcin: vcc12v-dcin {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc12v_dcin";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	vcc5v0_usb: vcc5v0-usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	vcc5v0_usb_host: vcc5v0-usb-host {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_host_en>;
-		regulator-name = "vcc5v0_usb_host";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_hub_en>;
-		regulator-name = "vcc5v0_usb_hub";
-		regulator-always-on;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gmac1 {
-	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
-	assigned-clock-rates = <0>, <125000000>;
-	clock_in_out = "output";
-	phy-handle = <&rgmii_phy1>;
-	phy-mode = "rgmii-id";
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac1m1_miim
-		     &gmac1m1_tx_bus2
-		     &gmac1m1_rx_bus2
-		     &gmac1m1_rgmii_clk
-		     &gmac1m1_rgmii_bus>;
-	status = "okay";
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint {
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-		#clock-cells = <1>;
-		clock-names = "mclk";
-		clocks = <&cru I2S1_MCLKOUT_TX>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
-		rockchip,system-power-controller;
-		#sound-dai-cells = <0>;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-
-		codec {
-			mic-in-differential;
-		};
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&i2s1_8ch {
-	rockchip,trcm-sync-tx-only;
-	status = "okay";
-};
-
-&mdio1 {
-	rgmii_phy1: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eth_phy_rst>;
-		reset-assert-us = <20000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	ethernet {
-		eth_phy_rst: eth_phy_rst {
-			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	leds {
-		led_user_en: led_user_en {
-			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins =
-				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
-			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio2-supply = <&vcc_1v8>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	extcon = <&usb2phy0>;
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	vbus-supply = <&vcc5v0_usb_otg>;
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb2phy1_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&vp0 {
-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-		remote-endpoint = <&hdmi_in_vp0>;
-	};
-};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts

@@ -1,787 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "Firefly Station P2";
-	compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	gmac0_clkin: external-gmac0-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "gmac0_clkin";
-		#clock-cells = <0>;
-	};
-
-	gmac1_clkin: external-gmac1-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "gmac1_clkin";
-		#clock-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_led: power {
-			label = "firefly:blue:power";
-			linux,default-trigger = "ir-power-click";
-			default-state = "on";
-			gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&led_power>;
-		};
-
-		user_led: user {
-			label = "firefly:yellow:user";
-			linux,default-trigger = "ir-user-click";
-			default-state = "off";
-			gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&led_user>;
-		};
-	};
-
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	sdio_pwrseq: sdio-pwrseq {
-		status = "okay";
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
-		post-power-on-delay-ms = <100>;
-	};
-
-	dc_12v: dc-12v {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_usb: vcc5v0-usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	pcie30_avdd0v9: pcie30-avdd0v9 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd0v9";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <900000>;
-		regulator-max-microvolt = <900000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	pcie30_avdd1v8: pcie30-avdd1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		enable-active-high;
-		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_enable_h>;
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc5v0_host: vcc5v0-host {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_host";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_host_en>;
-		regulator-always-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_otg: vcc5v0-otg {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_otg";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_otg_en>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-	
-	vcc_hub_reset: vcc-hub-reset {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_hub_reset";
-		enable-active-high;
-		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc_hub_reset_en>;
-		regulator-always-on;
-	};
-
-	pcie_pi6c_oe: pcie-pi6c-oe {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie_pi6c_oe_en";
-		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_pi6c_oe_en>;
-		regulator-always-on;
-	};
-
-	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_lcd0_n";
-		regulator-boot-on;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_lcd1_n";
-		regulator-boot-on;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-};
-
-&gmac0 {
-	phy-mode = "rgmii";
-	clock_in_out = "input";
-
-	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac0_miim
-		     &gmac0_tx_bus2
-		     &gmac0_rx_bus2
-		     &gmac0_rgmii_clk
-		     &gmac0_rgmii_bus
-		     &gmac0_clkinout>;
-
-	tx_delay = <0x3c>;
-	rx_delay = <0x2f>;
-
-	phy-handle = <&rgmii_phy0>;
-	status = "okay";
-};
-
-&gmac1 {
-	phy-mode = "rgmii";
-	clock_in_out = "input";
-
-	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac1m1_miim
-		     &gmac1m1_tx_bus2
-		     &gmac1m1_rx_bus2
-		     &gmac1m1_rgmii_clk
-		     &gmac1m1_rgmii_bus
-		     &gmac1m1_clkinout>;
-
-	tx_delay = <0x4f>;
-	rx_delay = <0x26>;
-
-	phy-handle = <&rgmii_phy1>;
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-		#clock-cells = <1>;
-		clock-names = "mclk";
-		clocks = <&cru I2S1_MCLKOUT_TX>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		#sound-dai-cells = <0>;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&mdio0 {
-	rgmii_phy0: phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-	};
-};
-
-&mdio1 {
-	rgmii_phy1: phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-	};
-};
-
-&pinctrl {
-	leds {
-		led_power: led-power {
-			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		led_user: led-user {
-			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	sdio-pwrseq {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usb {
-		vcc5v0_host_en: vcc5v0-host-en {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc5v0_otg_en: vcc5v0-otg-en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc_hub_reset_en: vcc-hub-reset-en {
-			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	fusb0_int {
-		fusb0_int: fusb0-int {
-			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-
-	pcie {
-		pcie_enable_h: pcie-enable-h {
-			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		pcie_reset_h: pcie-reset-h {
-			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		pcie_pi6c_oe_en: pcie-pi6c-oe-en {
-			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins =
-				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio2-supply = <&vcc_1v8>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&sdmmc2 {
-	max-frequency = <150000000>;
-	supports-sdio;
-	bus-width = <4>;
-	disable-wp;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
-	sd-uhs-sdr104;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	status = "okay";
-};
-
-&tsadc {
-        status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&vop {
-	status = "okay";
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint@0 {
-		reg = <0>;
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&vp0 {
-        vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-                reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-                remote-endpoint = <&hdmi_in_vp0>;
-        };
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&combphy2 {
-	status = "okay";
-};
-
-&sata2 {
-	status = "okay";
-};
-
-&pcie30phy {
-	status = "okay";
-};
-
-&pcie3x2{
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_h>;
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy1_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	extcon = <&usb2phy0>;
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};

target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml

@@ -1,157 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: "http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-
-title: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK
-
-maintainers:
-
-properties:
-  compatible:
-    enum:
-      - rockchip,rk3328-u3phy
-
-  reg:
-    - description: the base address of the USB 3.0 PHY
-
-  interrupts:
-    maxItems: 1
-
-  interrupt-names:
-    items:
-      - const: linestate
-        description: host/otg linestate interrupt
-
-  clocks:
-    maxItems: 2
-
-  clock-names:
-    items:
-      - const: u3phy-otg
-        description: USB 3.0 PHY UTMI
-      - const: u3phy-pipe
-        description: USB 3.0 PHY Pipe
-
-  resets:
-    maxItems: 6
-
-  reset-names:
-    items:
-      - const: u3phy-u2-por
-      description: USB 2.0 logic of USB 3.0 PHY
-      - const: u3phy-u3-por
-      description: USB 3.0 logic of USB 3.0 PHY
-      - const: u3phy-pipe-mac
-      description: USB 3.0 PHY pipe MAC
-      - const: u3phy-utmi-mac
-      description: USB 3.0 PHY utmi MAC
-      - const: u3phy-utmi-apb
-      description: USB 3.0 PHY utmi apb
-      - const: u3phy-pipe-apb
-      description: USB 3.0 PHY pipe apb
-
-  "#phy-cells":
-    const: 1
-
-  rockchip,u3phygrf:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    type: array
-    - description: phandle to the syscon managing the
-                   "USB 3.0 PHY general register files".
-
-  vbus-drv-gpios:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    type: array
-    - description: phandle for gpio vbus supply
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - interrupt-names
-  - clocks
-  - clock-names
-  - resets
-  - reset-names
-  - "#phy-cells"
-  - rockchip,u3phygrf
-
-patternProperties:
-  "^u3phy_utmi@[0-9a-f]+$":
-    type: object
-
-    properties:
-      - description: USB 2.0 utmi phy.
-
-      rockchip,odt-val-tuning:
-        type: boolean
-        - description: specify 45ohm ODT tuning value.
-
-      "phy-cells":
-        const: 0
-
-    required:
-      - reg
-      - "#phy-cells"
-
-patternProperties:
-  "^u3phy_pipe@[0-9a-f]+$":
-    type: object
-
-    properties:
-      - description: USB 3.0 pipe phy.
-
-      rockchip,refclk-25m-quirk :
-
-        - description: phy reference clock changed to 25m quirk.
-
-      "phy-cells":
-        const: 0
-
-    required:
-      - reg
-      - "#phy-cells"
-
-examples:
-
-usb3phy_grf: syscon@ff460000 {
-	compatible = "rockchip,usb3phy-grf", "syscon";
-	reg = <0x0 0xff460000 0x0 0x1000>;
-};
-
-...
-
-u3phy: usb3-phy@ff470000 {
-	compatible = "rockchip,rk3328-u3phy";
-	reg = <0x0 0xff470000 0x0 0x0>;
-	rockchip,u3phygrf = <&usb3phy_grf>;
-	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-names = "linestate";
-	clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
-	clock-names = "u3phy-otg", "u3phy-pipe";
-	resets = <&cru SRST_USB3PHY_U2>,
-		 <&cru SRST_USB3PHY_U3>,
-		 <&cru SRST_USB3PHY_PIPE>,
-		 <&cru SRST_USB3OTG_UTMI>,
-		 <&cru SRST_USB3PHY_OTG_P>,
-		 <&cru SRST_USB3PHY_PIPE_P>;
-	reset-names = "u3phy-u2-por", "u3phy-u3-por",
-		      "u3phy-pipe-mac", "u3phy-utmi-mac",
-		      "u3phy-utmi-apb", "u3phy-pipe-apb";
-	vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-	ranges;
-
-	u3phy_utmi: utmi@ff470000 {
-		reg = <0x0 0xff470000 0x0 0x8000>;
-		#phy-cells = <0>;
-	};
-
-	u3phy_pipe: pipe@ff478000 {
-		reg = <0x0 0xff478000 0x0 0x8000>;
-		#phy-cells = <0>;
-	};
-};

target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt

@@ -1,45 +0,0 @@
-Rockchip Hardware Random Number Generator
-
-Required properties:
-
-- compatible  : should be one of the following.
-		"rockchip,cryptov1-rng" for crypto v1
-		"rockchip,cryptov2-rng" for crypto v2
-		"rockchip,trngv1" for independent trng, such as rk3588.
-- reg         : Specifies base physical address and size of the registers map.
-- clocks      : Phandle to clock-controller plus clock-specifier pair.
-- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.
-- assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
-		<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>
-- assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
-		<200000000>, <100000000>
-- resets      : Used for module reset
-- reset-names : Reset names, should be "reset"
-Example:
-
-	rng: rng@100fc000 {
-		compatible = "rockchip,cryptov1-rng";
-		reg = <0x100fc000 0x4000>;
-		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-		clock-names = "clk_crypto", "hclk_crypto";
-		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-		assigned-clock-rates = <150000000>, <100000000>;
-		resets = <&cru SRST_CRYPTO>;
-		reset-names = "reset";
-		status = "disabled";
-	};
-
-	rng: rng@ff2f0000 {
-		compatible = "rockchip,cryptov2-rng";
-		reg = <0x0 0xff2f0000 0x0 0x4000>;
-		clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
-			<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-		clock-names = "clk_crypto", "clk_crypto_apk",
-			"aclk_crypto", "hclk_crypto";
-		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
-				<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-		assigned-clock-rates = <150000000>, <150000000>,
-					<200000000>, <100000000>;
-		resets = <&cru SRST_CRYPTO>;
-		reset-names = "reset";
-	};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts

@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
- */
-
-#include "rk3328-nanopi-r2s.dts"
-
-/ {
-	model = "FriendlyElec NanoPi R2C";
-	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-};
-
-&gmac2io {
-	phy-handle = <&yt8521s>;
-
-	mdio {
-		/delete-node/ ethernet-phy@1;
-
-		yt8521s: ethernet-phy@3 {
-			compatible = "ethernet-phy-id0000.011a",
-				     "ethernet-phy-ieee802.3-c22";
-			reg = <3>;
-			pinctrl-0 = <&eth_phy_reset_pin>;
-			pinctrl-names = "default";
-			reset-assert-us = <10000>;
-			reset-deassert-us = <50000>;
-			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&lan_led {
-	label = "nanopi-r2c:green:lan";
-};
-
-&rtl8153 {
-	realtek,led-data = <0x78>;
-};
-
-&sys_led {
-	label = "nanopi-r2c:red:sys";
-};
-
-&wan_led {
-	label = "nanopi-r2c:green:wan";
-};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Xunlong Software. Co., Ltd.
- * (http://www.orangepi.org)
- *
- * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
- */
-
-#include "rk3328-orangepi-r1-plus.dts"
-
-/ {
-	model = "Xunlong Orange Pi R1 Plus LTS";
-	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-};
-
-&dmc_opp_table {
-	opp-798000000 {
-		status = "disabled";
-	};
-	opp-840000000 {
-		status = "disabled";
-	};
-	opp-924000000 {
-		status = "disabled";
-	};
-	opp-1056000000 {
-		status = "disabled";
-	};
-};
-
-&gmac2io {
-	phy-handle = <&yt8531c>;
-	tx_delay = <0x19>;
-	rx_delay = <0x05>;
-
-	mdio {
-		/delete-node/ ethernet-phy@1;
-
-		yt8531c: ethernet-phy@0 {
-			compatible = "ethernet-phy-id4f51.e91b",
-				     "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			pinctrl-0 = <&eth_phy_reset_pin>;
-			pinctrl-names = "default";
-			reset-assert-us = <15000>;
-			reset-deassert-us = <50000>;
-			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&lan_led {
-	label = "orangepi-r1-plus-lts:green:lan";
-};
-
-&rtl8153 {
-	realtek,led-data = <0x78>;
-};
-
-&sys_led {
-	label = "orangepi-r1-plus-lts:red:sys";
-};
-
-&wan_led {
-	label = "orangepi-r1-plus-lts:green:wan";
-};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-#include "rk3328-nanopi-r2s.dts"
-
-/ {
-	model = "Xunlong Orange Pi R1 Plus";
-	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-};
-
-&lan_led {
-	label = "orangepi-r1-plus:green:lan";
-};
-
-&spi0 {
-	max-freq = <48000000>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-	};
-};
-
-&sys_led {
-	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-	label = "orangepi-r1-plus:red:sys";
-};
-
-&sys_led_pin {
-	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&wan_led {
-	label = "orangepi-r1-plus:green:wan";
-};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-doornet2-4gb.dts

@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include "rk3399-doornet2.dtsi"
-
-/ {
-	model = "EmbedFire DoorNet2-4GB";
-	compatible = "embedfire,doornet2", "rockchip,rk3399";
-
-	aliases {
-		led-boot = &sys_led;
-		led-failsafe = &sys_led;
-		led-running = &sys_led;
-		led-upgrade = &sys_led;
-	};
-
-	/delete-node/ display-subsystem;
-
-	gpio-leds {
-		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-
-		/delete-node/ status;
-
-		lan_led: led-lan {
-			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-			label = "green:lan";
-		};
-
-		sys_led: led-sys {
-			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-			label = "red:sys";
-			default-state = "on";
-		};
-
-		wan_led: led-wan {
-			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-			label = "green:wan";
-		};
-	};
-
-	gpio-keys {
-		pinctrl-0 = <&reset_button_pin>;
-
-		/delete-node/ power;
-
-		reset {
-			debounce-interval = <50>;
-			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	vdd_5v: vdd-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_5v";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&pcie0 {
-	max-link-speed = <1>;
-	num-lanes = <1>;
-	vpcie3v3-supply = <&vcc3v3_sys>;
-
-	pcie@0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		pcie-eth@0,0 {
-			compatible = "realtek,r8168";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x870>;
-		};
-	};
-};
-
-&pinctrl {
-	gpio-leds {
-		/delete-node/ leds-gpio;
-
-		lan_led_pin: lan-led-pin {
-			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	rockchip-key {
-		/delete-node/ power-key;
-
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&u2phy0_host {
-	phy-supply = <&vdd_5v>;
-};
-
-&vcc3v3_sys {
-	vin-supply = <&vcc5v0_sys>;
-};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

@@ -1,825 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "FriendlyElec NanoPi R5S";
-	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &gmac0;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
-		led-boot = &sys_led;
-		led-failsafe = &sys_led;
-		led-running = &sys_led;
-		led-upgrade = &sys_led;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		cooling-levels = <0 18 102 170 255>;
-		#cooling-cells = <2>;
-		fan-supply = <&vcc5v0_sysp>;
-		pwms = <&pwm0 0 50000 0>;
-	};
-
-	firmware {
-		optee: optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-
-	cspmu: cspmu@fd90c000 {
-		compatible = "rockchip,cspmu";
-		reg = <0x0 0xfd90c000 0x0 0x1000>,
-			<0x0 0xfd90d000 0x0 0x1000>,
-			<0x0 0xfd90e000 0x0 0x1000>,
-			<0x0 0xfd90f000 0x0 0x1000>;
-	};
-
-	gpio-key {
-		compatible = "gpio-key";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key1_pin>;
-
-		button@1 {
-			debounce-interval = <50>;
-			gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
-			wakeup-source;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		sys_led: led-sys {
-			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
-			linux,default-trigger = "heartbeat";
-			pinctrl-names = "default";
-			pinctrl-0 = <&sys_led_pin>;
-		};
-
-		wan_led: led-wan {
-			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-			label = "green:wan";
-			pinctrl-names = "default";
-			pinctrl-0 = <&wan_led_pin>;
-		};
-
-		lan1_led: led-lan1 {
-			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-			label = "green:lan1";
-			pinctrl-names = "default";
-			pinctrl-0 = <&lan1_led_pin>;
-		};
-
-		lan2_led: led-lan2 {
-			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
-			label = "green:lan2";
-			pinctrl-names = "default";
-			pinctrl-0 = <&lan2_led_pin>;
-		};
-	};
-
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	vdd_usbc: vdd-usbc {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_usbc";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	pcie30_avdd0v9: pcie30-avdd0v9 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd0v9";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <900000>;
-		regulator-max-microvolt = <900000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	pcie30_avdd1v8: pcie30-avdd1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <200000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc3v3_pcie>;
-	};
-
-	vcc3v3_ngff: vcc3v3-ngff-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_ngff";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc3v3_pcie>;
-	};
-
-	vcc5v0_usb: vcc5v0_usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vdd_usbc>;
-	};
-
-	vcc5v0_usb_host: vcc5v0-usb-host {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_host_en>;
-		regulator-name = "vcc5v0_usb_host";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_sysp: vcc5v0-sysp {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sysp";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&combphy2 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gmac0 {
-	phy-mode = "rgmii";
-	clock_in_out = "output";
-
-	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac0_miim
-		     &gmac0_tx_bus2
-		     &gmac0_rx_bus2
-		     &gmac0_rgmii_clk
-		     &gmac0_rgmii_bus>;
-
-	tx_delay = <0x3c>;
-	rx_delay = <0x2f>;
-
-	phy-handle = <&rgmii_phy0>;
-	status = "okay";
-};
-
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint {
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-always-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-
-&i2c5 {
-	status = "okay";
-
-	hym8563: hym8563@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&rtc_int>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-		wakeup-source;
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&i2s1_8ch {
-	rockchip,trcm-sync-tx-only;
-	status = "okay";
-};
-
-
-&mdio0 {
-	rgmii_phy0: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_int>;
-	};
-};
-
-&pcie30phy {
-	data-lanes = <1 2>;
-	status = "okay";
-};
-
-&pcie3x1 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_ngff>;
-	status = "okay";
-};
-
-&pcie3x2 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-};
-
-&pcie2x1 {
-	num-viewport = <4>;
-	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&pinctrl {
-	gpio-leds {
-
-		sys_led_pin: sys-led-pin {
-			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wan_led_pin: wan-led-pin {
-			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		lan1_led_pin: lan1-led-pin {
-			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		lan2_led_pin: lan2-led-pin {
-			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	gmac {
-		gmac_int: gmac-int {
-			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	gpio-key {
-		key1_pin: key1-pin {
-			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	rtc {
-		rtc_int: rtc-int {
-			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&pwm0 {
-	status = "okay";
-};
-
-&pwm4 {
-	status = "disabled";
-};
-
-&pwm5 {
-	status = "disabled";
-};
-
-&pwm7 {
-	status = "disabled";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sata2 {
-	status = "disabled";
-};
-
-&sdhci {
-	bus-width = <8>;
-	non-removable;
-	max-frequency = <200000000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	status = "okay";
-};
-
-&spi3 {
-	pinctrl-0 = <&spi3m1_pins>;
-	status = "disabled";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "disabled";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart7 {
-	pinctrl-0 = <&uart7m1_xfer>;
-	status = "disabled";
-};
-
-&uart9 {
-	pinctrl-0 = <&uart9m1_xfer>;
-	status = "disabled";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	phy-supply = <&vcc5v0_usb_otg>;
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb2phy1_host {
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&vp0 {
-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-		remote-endpoint = <&hdmi_in_vp0>;
-	};
-};

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts

@@ -1,542 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "FastRhino R66S";
-	compatible = "fastrhino,r66s", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &rtl8125_1;
-		ethernet1 = &rtl8125_2;
-		led-boot = &power_led;
-		led-failsafe = &power_led;
-		led-running = &power_led;
-		led-upgrade = &power_led;
-		mmc0 = &sdmmc0;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&reset_button_pin>;
-
-		reset {
-			debounce-interval = <50>;
-			gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&power_led_pin>;
-
-		power_led: led-power {
-			label = "green:power";
-			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	dc_12v: dc-12v {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc3v3_pcie: vcc3v3-pcie-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_pcie";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_usb_host: vcc5v0-usb-host {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb_host";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_usb_otg: vcc5v0-usb-otg {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-		regulator-name = "vcc5v0_usb_otg";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-min-microvolt = <950000>;
-				regulator-max-microvolt = <950000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-init-microvolt = <950000>;
-				regulator-min-microvolt = <950000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <950000>;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-
-	};
-};
-
-&pcie30phy {
-	data-lanes = <1 2>;
-	status = "okay";
-};
-
-&pcie3x1 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-
-	pcie@10 {
-		reg = <0x00100000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		rtl8125_1: pcie-eth@10,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
-};
-
-&pcie3x2 {
-	num-lanes = <1>;
-	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-
-	pcie@20 {
-		reg = <0x00200000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		rtl8125_2: pcie-eth@20,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
-};
-
-&pinctrl {
-	gpio-leds {
-		power_led_pin: power-led-pin {
-			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	rockchip-key {
-		reset_button_pin: reset-button-pin {
-			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&rng {
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	disable-wp;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	extcon = <&usb2phy0>;
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	phy-supply = <&vcc5v0_usb_otg>;
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts

@@ -1,787 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
-	model = "Firefly Station P2";
-	compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
-
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	gmac0_clkin: external-gmac0-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "gmac0_clkin";
-		#clock-cells = <0>;
-	};
-
-	gmac1_clkin: external-gmac1-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "gmac1_clkin";
-		#clock-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_led: power {
-			label = "firefly:blue:power";
-			linux,default-trigger = "ir-power-click";
-			default-state = "on";
-			gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&led_power>;
-		};
-
-		user_led: user {
-			label = "firefly:yellow:user";
-			linux,default-trigger = "ir-user-click";
-			default-state = "off";
-			gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&led_user>;
-		};
-	};
-
-	hdmi-con {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	sdio_pwrseq: sdio-pwrseq {
-		status = "okay";
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
-		post-power-on-delay-ms = <100>;
-	};
-
-	dc_12v: dc-12v {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc3v3_sys: vcc3v3-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vcc5v0_usb: vcc5v0-usb {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	pcie30_avdd0v9: pcie30-avdd0v9 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd0v9";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <900000>;
-		regulator-max-microvolt = <900000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	pcie30_avdd1v8: pcie30-avdd1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		enable-active-high;
-		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_enable_h>;
-		regulator-name = "vcc3v3_pcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc5v0_host: vcc5v0-host {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_host";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_host_en>;
-		regulator-always-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_otg: vcc5v0-otg {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_otg";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_otg_en>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-	
-	vcc_hub_reset: vcc-hub-reset {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_hub_reset";
-		enable-active-high;
-		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc_hub_reset_en>;
-		regulator-always-on;
-	};
-
-	pcie_pi6c_oe: pcie-pi6c-oe {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie_pi6c_oe_en";
-		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_pi6c_oe_en>;
-		regulator-always-on;
-	};
-
-	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_lcd0_n";
-		regulator-boot-on;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_lcd1_n";
-		regulator-boot-on;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-};
-
-&gmac0 {
-	phy-mode = "rgmii";
-	clock_in_out = "input";
-
-	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac0_miim
-		     &gmac0_tx_bus2
-		     &gmac0_rx_bus2
-		     &gmac0_rgmii_clk
-		     &gmac0_rgmii_bus
-		     &gmac0_clkinout>;
-
-	tx_delay = <0x3c>;
-	rx_delay = <0x2f>;
-
-	phy-handle = <&rgmii_phy0>;
-	status = "okay";
-};
-
-&gmac1 {
-	phy-mode = "rgmii";
-	clock_in_out = "input";
-
-	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
-
-	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac1m1_miim
-		     &gmac1m1_tx_bus2
-		     &gmac1m1_rx_bus2
-		     &gmac1m1_rgmii_clk
-		     &gmac1m1_rgmii_bus
-		     &gmac1m1_clkinout>;
-
-	tx_delay = <0x4f>;
-	rx_delay = <0x26>;
-
-	phy-handle = <&rgmii_phy1>;
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-	avdd-0v9-supply = <&vdda0v9_image>;
-	avdd-1v8-supply = <&vcca1v8_image>;
-};
-
-&i2c0 {
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-		#clock-cells = <1>;
-		clock-names = "mclk";
-		clocks = <&cru I2S1_MCLKOUT_TX>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int>;
-		rockchip,system-power-controller;
-		#sound-dai-cells = <0>;
-		vcc1-supply = <&vcc3v3_sys>;
-		vcc2-supply = <&vcc3v3_sys>;
-		vcc3-supply = <&vcc3v3_sys>;
-		vcc4-supply = <&vcc3v3_sys>;
-		vcc5-supply = <&vcc3v3_sys>;
-		vcc6-supply = <&vcc3v3_sys>;
-		vcc7-supply = <&vcc3v3_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc3v3_sys>;
-		wakeup-source;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-name = "vdd_logic";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-name = "vdd_gpu";
-				regulator-always-on;
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdd_npu: DCDC_REG4 {
-				regulator-name = "vdd_npu";
-				regulator-init-microvolt = <900000>;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8: DCDC_REG5 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_image: LDO_REG1 {
-				regulator-name = "vdda0v9_image";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda_0v9: LDO_REG2 {
-				regulator-name = "vdda_0v9";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-name = "vdda0v9_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <900000>;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-name = "vccio_acodec";
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-name = "vccio_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-name = "vcc3v3_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_1v8: LDO_REG7 {
-				regulator-name = "vcca_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG8 {
-				regulator-name = "vcca1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcca1v8_image: LDO_REG9 {
-				regulator-name = "vcca1v8_image";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3: SWITCH_REG1 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: SWITCH_REG2 {
-				regulator-name = "vcc3v3_sd";
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&mdio0 {
-	rgmii_phy0: phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-	};
-};
-
-&mdio1 {
-	rgmii_phy1: phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-	};
-};
-
-&pinctrl {
-	leds {
-		led_power: led-power {
-			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		led_user: led-user {
-			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	sdio-pwrseq {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usb {
-		vcc5v0_host_en: vcc5v0-host-en {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc5v0_otg_en: vcc5v0-otg-en {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-		vcc_hub_reset_en: vcc-hub-reset-en {
-			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	fusb0_int {
-		fusb0_int: fusb0-int {
-			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-
-	pcie {
-		pcie_enable_h: pcie-enable-h {
-			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		pcie_reset_h: pcie-reset-h {
-			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		pcie_pi6c_oe_en: pcie-pi6c-oe-en {
-			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic_int {
-			rockchip,pins =
-				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcc3v3_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio2-supply = <&vcc_1v8>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_3v3>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcca_1v8>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&sdmmc2 {
-	max-frequency = <150000000>;
-	supports-sdio;
-	bus-width = <4>;
-	disable-wp;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
-	sd-uhs-sdr104;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	status = "okay";
-};
-
-&tsadc {
-        status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&vop {
-	status = "okay";
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint@0 {
-		reg = <0>;
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&vp0 {
-        vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-                reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-                remote-endpoint = <&hdmi_in_vp0>;
-        };
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&combphy0 {
-	status = "okay";
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&combphy2 {
-	status = "okay";
-};
-
-&sata2 {
-	status = "okay";
-};
-
-&pcie30phy {
-	status = "okay";
-};
-
-&pcie3x2{
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_h>;
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie>;
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy1_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	extcon = <&usb2phy0>;
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};

target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c

@@ -21,7 +21,7 @@
 
 #define ROCKCHIP_AUTOSUSPEND_DELAY		100
 #define ROCKCHIP_POLL_PERIOD_US			100
-#define ROCKCHIP_POLL_TIMEOUT_US		50000
+#define ROCKCHIP_POLL_TIMEOUT_US		10000
 #define RK_MAX_RNG_BYTE				(32)
 
 /* start of CRYPTO V1 register define */
@@ -37,8 +37,7 @@
 /* end of CRYPTO V1 register define */
 
 /* start of CRYPTO V2 register define */
-#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
+#define CRYPTO_V2_RNG_CTL			0x0400
-#define CRYPTO_V2_RNG_CTL			0x0
 #define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
 #define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
 #define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
@@ -49,48 +48,11 @@
 #define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
 #define CRYPTO_V2_RNG_ENABLE			BIT(1)
 #define CRYPTO_V2_RNG_START			BIT(0)
-#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
-#define CRYPTO_V2_RNG_DOUT_0			0x0010
+#define CRYPTO_V2_RNG_DOUT_0			0x0410
 /* end of CRYPTO V2 register define */
 
-/* start of TRNG_V1 register define */
-/* TRNG is no longer subordinate to the Crypto module */
-#define TRNG_V1_CTRL				0x0000
-#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
-#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
-#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
-
-#define TRNG_V1_STAT				0x0004
-#define TRNG_V1_STAT_SEEDED			BIT(9)
-#define TRNG_V1_STAT_GENERATING			BIT(30)
-#define TRNG_V1_STAT_RESEEDING			BIT(31)
-
-#define TRNG_V1_MODE				0x0008
-#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
-#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
-
-#define TRNG_V1_IE				0x0010
-#define TRNG_V1_IE_GLBL_EN			BIT(31)
-#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
-#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
-
-#define TRNG_V1_ISTAT				0x0014
-#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
-
-/* RAND0 ~ RAND7 */
-#define TRNG_V1_RAND0				0x0020
-#define TRNG_V1_RAND7				0x003C
-
-#define TRNG_V1_AUTO_RQSTS			0x0060
-
-#define TRNG_V1_VERSION				0x00F0
-#define TRNG_v1_VERSION_CODE			0x46bc
-/* end of TRNG_V1 register define */
-
 struct rk_rng_soc_data {
-	u32 default_offset;
-
-	int (*rk_rng_init)(struct hwrng *rng);
 	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
 };
 
@@ -137,38 +99,6 @@ static void rk_rng_cleanup(struct hwrng *rng)
 	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
 }
 
-static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-{
-	int ret;
-	int read_len = 0;
-	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-
-	if (!rk_rng->soc_data->rk_rng_read)
-		return -EFAULT;
-
-	ret = pm_runtime_get_sync(rk_rng->dev);
-	if (ret < 0) {
-		pm_runtime_put_noidle(rk_rng->dev);
-		return ret;
-	}
-
-	ret = 0;
-	while (max > ret) {
-		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
-							 max - ret, wait);
-		if (read_len < 0) {
-			ret = read_len;
-			break;
-		}
-		ret += read_len;
-	}
-
-	pm_runtime_mark_last_busy(rk_rng->dev);
-	pm_runtime_put_sync_autosuspend(rk_rng->dev);
-
-	return ret;
-}
-
 static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
 			     size_t size)
 {
@@ -178,12 +108,18 @@ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
 		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
 }
 
-static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 {
 	int ret = 0;
 	u32 reg_ctrl = 0;
 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 
+	ret = pm_runtime_get_sync(rk_rng->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(rk_rng->dev);
+		return ret;
+	}
+
 	/* enable osc_ring to get entropy, sample period is set as 100 */
 	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
 	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
@@ -208,15 +144,24 @@ out:
 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
 		      CRYPTO_V1_CTRL);
 
+	pm_runtime_mark_last_busy(rk_rng->dev);
+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
+
 	return ret;
 }
 
-static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 {
 	int ret = 0;
 	u32 reg_ctrl = 0;
 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 
+	ret = pm_runtime_get_sync(rk_rng->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(rk_rng->dev);
+		return ret;
+	}
+
 	/* enable osc_ring to get entropy, sample period is set as 100 */
 	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
 
@@ -226,7 +171,7 @@ static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait
 	reg_ctrl |= CRYPTO_V2_RNG_START;
 
 	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
-		      CRYPTO_V2_RNG_CTL);
+			CRYPTO_V2_RNG_CTL);
 
 	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
 				 !(reg_ctrl & CRYPTO_V2_RNG_START),
@@ -243,139 +188,28 @@ out:
 	/* close TRNG */
 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
 
-	return ret;
-}
-
-static int rk_trng_v1_init(struct hwrng *rng)
-{
-	int ret;
-	uint32_t auto_reseed_cnt = 1000;
-	uint32_t reg_ctrl, status, version;
-	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-
-	ret = pm_runtime_get_sync(rk_rng->dev);
-	if (ret < 0) {
-		pm_runtime_put_noidle(rk_rng->dev);
-		return ret;
-	}
-
-	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
-	if (version != TRNG_v1_VERSION_CODE) {
-		dev_err(rk_rng->dev,
-			"wrong trng version, expected = %08x, actual = %08x\n",
-			TRNG_V1_VERSION, version);
-		ret = -EFAULT;
-		goto exit;
-	}
-
-	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
-
-	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
-	if (!(status & TRNG_V1_STAT_SEEDED) ||
-	    (status & TRNG_V1_STAT_GENERATING) ||
-	    (status & TRNG_V1_STAT_RESEEDING)) {
-		uint32_t mask = TRNG_V1_STAT_SEEDED |
-				TRNG_V1_STAT_GENERATING |
-				TRNG_V1_STAT_RESEEDING;
-
-		udelay(10);
-
-		/* wait for GENERATING and RESEEDING flag to clear */
-		readl_poll_timeout(rk_rng->mem + TRNG_V1_STAT, reg_ctrl,
-				   (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
-				   ROCKCHIP_POLL_PERIOD_US,
-				   ROCKCHIP_POLL_TIMEOUT_US);
-	}
-
-	/* clear ISTAT flag because trng may auto reseeding when power on */
-	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-
-	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
-	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
-
-	ret = 0;
-exit:
 	pm_runtime_mark_last_busy(rk_rng->dev);
 	pm_runtime_put_sync_autosuspend(rk_rng->dev);
 
 	return ret;
 }
 
-static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
-{
+	.rk_rng_read = rk_rng_v1_read,
-	int ret = 0;
-	u32 reg_ctrl = 0;
-	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-
-	/* clear ISTAT anyway */
-	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-
-	/* generate 256bit random */
-	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
-	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
-
-	/*
-	 * Generate2 56 bit random data will cost 1024 clock cycles.
-	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
-	 */
-	udelay(10);
-	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
-		/* wait RAND_RDY triggered */
-		ret = readl_poll_timeout(rk_rng->mem + TRNG_V1_ISTAT, reg_ctrl,
-					 (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
-					 ROCKCHIP_POLL_PERIOD_US,
-					 ROCKCHIP_POLL_TIMEOUT_US);
-		if (ret < 0)
-			goto out;
-	}
-
-	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-
-	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
-
-	/* clear all status flag */
-	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-out:
-	/* close TRNG */
-	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
-
-	return ret;
-}
-
-static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
-	.default_offset = 0,
-
-	.rk_rng_read = rk_crypto_v1_read,
 };
 
-static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
-	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
+	.rk_rng_read = rk_rng_v2_read,
-
-	.rk_rng_read = rk_crypto_v2_read,
-};
-
-static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
-	.default_offset = 0,
-
-	.rk_rng_init = rk_trng_v1_init,
-	.rk_rng_read = rk_trng_v1_read,
 };
 
 static const struct of_device_id rk_rng_dt_match[] = {
 	{
 		.compatible = "rockchip,cryptov1-rng",
-		.data = (void *)&rk_crypto_v1_soc_data,
+		.data = (void *)&rk_rng_v1_soc_data,
 	},
 	{
 		.compatible = "rockchip,cryptov2-rng",
-		.data = (void *)&rk_crypto_v2_soc_data,
+		.data = (void *)&rk_rng_v2_soc_data,
-	},
-	{
-		.compatible = "rockchip,trngv1",
-		.data = (void *)&rk_trng_v1_soc_data,
 	},
 	{ },
 };
@@ -388,7 +222,6 @@ static int rk_rng_probe(struct platform_device *pdev)
 	struct rk_rng *rk_rng;
 	struct device_node *np = pdev->dev.of_node;
 	const struct of_device_id *match;
-	resource_size_t map_size;
 
 	dev_dbg(&pdev->dev, "probing...\n");
 	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
@@ -404,27 +237,13 @@ static int rk_rng_probe(struct platform_device *pdev)
 	rk_rng->rng.init    = rk_rng_init;
 	rk_rng->rng.cleanup = rk_rng_cleanup,
 #endif
-	rk_rng->rng.read    = rk_rng_read;
+	rk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;
 	rk_rng->rng.quality = 999;
 
-	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
+	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
 	if (IS_ERR(rk_rng->mem))
 		return PTR_ERR(rk_rng->mem);
 
-	/* compatible with crypto v2 module */
-	/*
-	 * With old dtsi configurations, the RNG base was equal to the crypto
-	 * base, so both drivers could not be enabled at the same time.
-	 * RNG base = CRYPTO base + RNG offset
-	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
-	 *
-	 * With new dtsi configurations, CRYPTO regs is divided into two parts
-	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
-	 * RNG driver and CRYPTO driver could be enabled at the same time.
-	 */
-	if (map_size > rk_rng->soc_data->default_offset)
-		rk_rng->mem += rk_rng->soc_data->default_offset;
-
 	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
 	if (rk_rng->clk_num < 0) {
 		dev_err(&pdev->dev, "failed to get clks property\n");
@@ -434,7 +253,7 @@ static int rk_rng_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, rk_rng);
 
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
-					 ROCKCHIP_AUTOSUSPEND_DELAY);
+					ROCKCHIP_AUTOSUSPEND_DELAY);
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 
@@ -444,10 +263,6 @@ static int rk_rng_probe(struct platform_device *pdev)
 		pm_runtime_disable(&pdev->dev);
 	}
 
-	/* for some platform need hardware operation when probe */
-	if (rk_rng->soc_data->rk_rng_init)
-		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
-
 	return ret;
 }
 
@@ -470,7 +285,7 @@ static int rk_rng_runtime_resume(struct device *dev)
 
 static const struct dev_pm_ops rk_rng_pm_ops = {
 	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-			   rk_rng_runtime_resume, NULL)
+				rk_rng_runtime_resume, NULL)
 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 				pm_runtime_force_resume)
 };

target/linux/rockchip/files/drivers/net/phy/motorcomm.c

@@ -0,0 +1,414 @@
+/*
+ * drivers/net/phy/motorcomm.c
+ *
+ * Driver for Motorcomm PHYs
+ *
+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
+ *
+ * Copyright (c) 2019 Motorcomm, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Support : Motorcomm Phys:
+ *		Giga phys: yt8511, yt8521
+ *		100/10 Phys : yt8512, yt8512b, yt8510
+ *		Automotive 100Mb Phys : yt8010
+ *		Automotive 100/10 hyper range Phys: yt8510
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/motorcomm_phy.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
+{
+	int ret;
+	int val;
+
+	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		return ret;
+
+	val = phy_read(phydev, REG_DEBUG_DATA);
+
+	return val;
+}
+
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
+{
+	int ret;
+
+	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		return ret;
+
+	ret = phy_write(phydev, REG_DEBUG_DATA, val);
+
+	return ret;
+}
+
+static int yt8010_config_aneg(struct phy_device *phydev)
+{
+	phydev->speed = SPEED_100;
+	return 0;
+}
+
+static int yt8511_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8511_EN_SLEEP_SW_BIT));
+	ret = ytphy_write_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	/* output SyncE clock (125mhz) even link is down */
+	ret = ytphy_write_ext(phydev, 0xa012, 0xd0);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_read_ext(phydev, 0xc);
+	if (val < 0)
+		return val;
+
+	/* ext reg 0xc.b[2:1]
+	00-----25M from pll;
+	01---- 25M from xtl;(default)
+	10-----62.5M from pll;
+	11----125M from pll(here set to this value)
+	*/
+	val |= (3 << 1);
+	ret = ytphy_write_ext(phydev, 0xc, val);
+	if (ret < 0)
+		return ret;
+
+	/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
+	ytphy_write_ext(phydev, 0xa00b, 0xe004);
+	ytphy_write_ext(phydev, 0xa00c, 0);
+	ytphy_write_ext(phydev, 0xa00d, 0x2600);
+	ytphy_write_ext(phydev, 0xa00e, 0x0070);
+	ytphy_write_ext(phydev, 0xa00f, 0x000a);
+
+	return 0;
+}
+
+static int yt8512_clk_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
+	if (ret < 0)
+		return ret;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_CONTROL1_RMII_EN;
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
+	if (ret < 0)
+		return ret;
+
+	val = phy_read(phydev, MII_BMCR);
+	if (val < 0)
+		return val;
+
+	val |= YT_SOFTWARE_RESET;
+	ret = phy_write(phydev, MII_BMCR, val);
+
+	return ret;
+}
+
+static int yt8512_led_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int mask;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_LED0_ACT_BLK_IND;
+
+	mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
+		YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
+		YT8512_LED0_BT_ON_EN;
+	val &= ~mask;
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
+	if (ret < 0)
+		return ret;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_LED1_BT_ON_EN;
+
+	mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
+	val &= ~mask;
+
+	ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
+
+	return ret;
+}
+
+static int yt8512_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+
+	ret = yt8512_clk_init(phydev);
+	if (ret < 0)
+		return ret;
+
+	ret = yt8512_led_init(phydev);
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int yt8512_read_status(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int speed, speed_mode, duplex;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+	if (val < 0)
+		return val;
+
+	duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
+	speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
+	switch (speed_mode) {
+	case 0:
+		speed = SPEED_10;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	case 2:
+	case 3:
+	default:
+		speed = SPEED_UNKNOWN;
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+static int yt8521_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	/* switch to access UTP */
+	ret = ytphy_write_ext(phydev, 0xa000, 0);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_read_ext(phydev, 0xc);
+	if (val < 0)
+		return val;
+
+	val &= ~(1 << 12);
+	ret = ytphy_write_ext(phydev, 0xc, val);
+	if (ret < 0)
+		return ret;
+
+	/* output SyncE clock (125mhz) even link is down */
+	ret = ytphy_write_ext(phydev, 0xa012, 0x38);
+	if (ret < 0)
+		return ret;
+
+	/* disable rgmii clk 2ns delay */
+	val = ytphy_read_ext(phydev, 0xa001);
+	if (val < 0)
+		return val;
+
+	val &= ~(1 << 8);
+	ret = ytphy_write_ext(phydev, 0xa001, val);
+	if (ret < 0)
+		return ret;
+
+	/* setup delay */
+	val = (1 << 10) | (0xf << 4) | 5;
+	ret = ytphy_write_ext(phydev, 0xa003, val);
+	if (ret < 0)
+		return ret;
+
+	/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
+	ytphy_write_ext(phydev, 0xa00b, 0xe004);
+	ytphy_write_ext(phydev, 0xa00c, 0);
+	ytphy_write_ext(phydev, 0xa00d, 0x2600);
+	ytphy_write_ext(phydev, 0xa00e, 0x0070);
+	ytphy_write_ext(phydev, 0xa00f, 0x000a);
+
+	return 0;
+}
+
+static int yt8521_config_intr(struct phy_device *phydev)
+{
+	int val;
+
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+		val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
+	else
+		val = 0;
+
+	return phy_write(phydev, REG_INT_MASK, val);
+}
+
+static int yt8521_ack_interrupt(struct phy_device *phydev)
+{
+	int val;
+
+	val = phy_read(phydev, REG_INT_STATUS);
+	phydev_dbg(phydev, "intr status 0x04%x\n", val);
+
+	return (val < 0) ? val : 0;
+}
+
+static struct phy_driver ytphy_drvs[] = {
+	{
+		.phy_id		= PHY_ID_YT8010,
+		.name		= "YT8010 Automotive Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_BASIC_FEATURES,
+		.config_aneg	= yt8010_config_aneg,
+		.read_status	= genphy_read_status,
+	}, {
+		.phy_id		= PHY_ID_YT8510,
+		.name		= "YT8510 100/10Mb Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_BASIC_FEATURES,
+		.read_status	= genphy_read_status,
+	}, {
+		.phy_id		= PHY_ID_YT8511,
+		.name		= "YT8511 Gigabit Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_GBIT_FEATURES,
+		.read_status	= genphy_read_status,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	}, {
+		.phy_id		= PHY_ID_YT8512,
+		.name		= "YT8512 Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_BASIC_FEATURES,
+		.config_init	= yt8512_config_init,
+		.read_status	= yt8512_read_status,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	}, {
+		.phy_id		= PHY_ID_YT8512B,
+		.name		= "YT8512B Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_BASIC_FEATURES,
+		.config_init	= yt8512_config_init,
+		.read_status	= yt8512_read_status,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	}, {
+		.phy_id		= PHY_ID_YT8521,
+		.name		= "YT8521 Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		/* PHY_GBIT_FEATURES */
+		.config_init	= yt8521_config_init,
+		.ack_interrupt	= yt8521_ack_interrupt,
+		.config_intr	= yt8521_config_intr,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	}, {
+		/* same as 8521 */
+		.phy_id		= PHY_ID_YT8531S,
+		.name		= "YT8531S Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		/* PHY_GBIT_FEATURES */
+		.config_init	= yt8521_config_init,
+		.ack_interrupt	= yt8521_ack_interrupt,
+		.config_intr	= yt8521_config_intr,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	}, {
+		/* same as 8511 */
+		.phy_id		= PHY_ID_YT8531,
+		.name		= "YT8531 Gigabit Ethernet",
+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
+		.features	= PHY_GBIT_FEATURES,
+		.config_init	= yt8511_config_init,
+		.read_status	= genphy_read_status,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+	},
+};
+
+module_phy_driver(ytphy_drvs);
+
+MODULE_DESCRIPTION("Motorcomm PHY driver");
+MODULE_AUTHOR("Leilei Zhao");
+MODULE_LICENSE("GPL");
+
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+	{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
+	{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);

target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c

@@ -1,343 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Rockchip PCIE3.0 phy driver
- *
- * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/kernel.h>
-#include <linux/mfd/syscon.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/phy/pcie.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-/* Register for RK3568 */
-#define GRF_PCIE30PHY_CON1			0x4
-#define GRF_PCIE30PHY_CON4			0x10
-#define GRF_PCIE30PHY_CON6			0x18
-#define GRF_PCIE30PHY_CON9			0x24
-#define GRF_PCIE30PHY_STATUS0			0x80
-#define SRAM_INIT_DONE(reg)			(reg & BIT(14))
-
-#define RK3568_BIFURCATION_LANE_0_1		BIT(0)
-
-/* Register for RK3588 */
-#define PHP_GRF_PCIESEL_CON			0x100
-#define RK3588_PCIE3PHY_GRF_CMN_CON0		0x0
-#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1	0x904
-#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1	0xa04
-#define RK3588_SRAM_INIT_DONE(reg)		(reg & BIT(0))
-
-#define RK3588_BIFURCATION_LANE_0_1		BIT(0)
-#define RK3588_BIFURCATION_LANE_2_3		BIT(1)
-#define RK3588_LANE_AGGREGATION		BIT(2)
-
-struct rockchip_p3phy_ops;
-
-struct rockchip_p3phy_priv {
-	const struct rockchip_p3phy_ops *ops;
-	void __iomem *mmio;
-	/* mode: RC, EP */
-	int mode;
-	/* pcie30_phymode: Aggregation, Bifurcation */
-	int pcie30_phymode;
-	struct regmap *phy_grf;
-	struct regmap *pipe_grf;
-	struct reset_control *p30phy;
-	struct phy *phy;
-	struct clk_bulk_data *clks;
-	int num_clks;
-	int num_lanes;
-	u32 lanes[4];
-};
-
-struct rockchip_p3phy_ops {
-	int (*phy_init)(struct rockchip_p3phy_priv *priv);
-};
-
-static u16 phy_fw[] = {
-	#include "p3phy.fw"
-};
-
-static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
-{
-	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-
-	/* Actually We don't care EP/RC mode, but just record it */
-	switch (submode) {
-	case PHY_MODE_PCIE_RC:
-		priv->mode = PHY_MODE_PCIE_RC;
-		break;
-	case PHY_MODE_PCIE_EP:
-		priv->mode = PHY_MODE_PCIE_EP;
-		break;
-	default:
-		dev_err(&phy->dev, "%s, invalid mode\n", __func__);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
-{
-	struct phy *phy = priv->phy;
-	bool bifurcation = false;
-	int ret;
-	int i;
-	u32 reg;
-
-	/* Deassert PCIe PMA output clamp mode */
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31));
-
-	for (i = 0; i < priv->num_lanes; i++) {
-		dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
-		if (priv->lanes[i] > 1)
-			bifurcation = true;
-	}
-
-	/* Set bifurcation if needed, and it doesn't care RC/EP */
-	if (bifurcation) {
-		dev_info(&phy->dev, "bifurcation enabled\n");
-		regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
-			     (0xf << 16) | RK3568_BIFURCATION_LANE_0_1);
-		regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
-			     BIT(15) | BIT(31));
-	} else {
-		dev_info(&phy->dev, "bifurcation disabled\n");
-		regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
-			     (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1);
-	}
-
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
-		     (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
-		     (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
-
-	reset_control_deassert(priv->p30phy);
-
-	ret = regmap_read_poll_timeout(priv->phy_grf,
-				       GRF_PCIE30PHY_STATUS0,
-				       reg, SRAM_INIT_DONE(reg),
-				       0, 500);
-	if (ret) {
-		dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
-		       __func__, reg);
-		return ret;
-	}
-
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
-		     (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
-	for (i = 0; i < 8192; i++)
-		writel(phy_fw[i], priv->mmio + (i<<2));
-
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
-		     (0x0 << 8) | (0x3 << (8 + 16)));
-	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
-		     (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
-
-	dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
-	return 0;
-}
-
-static const struct rockchip_p3phy_ops rk3568_ops = {
-	.phy_init = rockchip_p3phy_rk3568_init,
-};
-
-static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
-{
-	u32 reg = 0;
-	u8 mode = 0;
-	int ret;
-	int i;
-
-	/* Deassert PCIe PMA output clamp mode */
-	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
-
-	/* Set bifurcation if needed */
-	for (i = 0; i < priv->num_lanes; i++) {
-		if (!priv->lanes[i])
-			mode |= (BIT(i) << 3);
-
-		if (priv->lanes[i] > 1)
-			mode |= (BIT(i) >> 1);
-	}
-
-	if (!mode)
-		reg = RK3588_LANE_AGGREGATION;
-	else {
-		if (mode & (BIT(0) | BIT(1)))
-			reg |= RK3588_BIFURCATION_LANE_0_1;
-
-		if (mode & (BIT(2) | BIT(3)))
-			reg |= RK3588_BIFURCATION_LANE_2_3;
-	}
-
-	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
-
-	/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
-	if (!IS_ERR(priv->pipe_grf)) {
-		reg = (mode & (BIT(6) | BIT(7))) >> 6;
-		if (reg)
-			regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
-				     (reg << 16) | reg);
-	}
-
-	reset_control_deassert(priv->p30phy);
-
-	ret = regmap_read_poll_timeout(priv->phy_grf,
-				       RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
-				       reg, RK3588_SRAM_INIT_DONE(reg),
-				       0, 500);
-	ret |= regmap_read_poll_timeout(priv->phy_grf,
-					RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
-					reg, RK3588_SRAM_INIT_DONE(reg),
-					0, 500);
-	if (ret)
-		pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
-		       __func__, reg);
-	return ret;
-}
-
-static const struct rockchip_p3phy_ops rk3588_ops = {
-	.phy_init = rockchip_p3phy_rk3588_init,
-};
-
-static int rochchip_p3phy_init(struct phy *phy)
-{
-	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-	int ret;
-
-	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
-	if (ret) {
-		pr_err("failed to enable PCIe bulk clks %d\n", ret);
-		return ret;
-	}
-
-	reset_control_assert(priv->p30phy);
-	udelay(1);
-
-	if (priv->ops->phy_init) {
-		ret = priv->ops->phy_init(priv);
-		if (ret)
-			clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-	}
-
-	return ret;
-}
-
-static int rochchip_p3phy_exit(struct phy *phy)
-{
-	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-
-	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-	reset_control_assert(priv->p30phy);
-	return 0;
-}
-
-static const struct phy_ops rochchip_p3phy_ops = {
-	.init = rochchip_p3phy_init,
-	.exit = rochchip_p3phy_exit,
-	.set_mode = rockchip_p3phy_set_mode,
-	.owner = THIS_MODULE,
-};
-
-static int rockchip_p3phy_probe(struct platform_device *pdev)
-{
-	struct phy_provider *phy_provider;
-	struct device *dev = &pdev->dev;
-	struct rockchip_p3phy_priv *priv;
-	struct device_node *np = dev->of_node;
-	struct resource *res;
-	int ret;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	priv->mmio = devm_ioremap_resource(dev, res);
-	if (IS_ERR(priv->mmio)) {
-		ret = PTR_ERR(priv->mmio);
-		return ret;
-	}
-
-	priv->ops = of_device_get_match_data(&pdev->dev);
-	if (!priv->ops) {
-		dev_err(&pdev->dev, "no of match data provided\n");
-		return -EINVAL;
-	}
-
-	priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
-	if (IS_ERR(priv->phy_grf)) {
-		dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
-		return PTR_ERR(priv->phy_grf);
-	}
-
-	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
-							 "rockchip,pipe-grf");
-	if (IS_ERR(priv->pipe_grf))
-		dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
-
-	priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
-							     priv->lanes, 2,
-							     ARRAY_SIZE(priv->lanes));
-
-	/* if no data-lanes assume aggregation */
-	if (priv->num_lanes == -EINVAL) {
-		dev_dbg(dev, "no data-lanes property found\n");
-		priv->num_lanes = 1;
-		priv->lanes[0] = 1;
-	} else if (priv->num_lanes < 0) {
-		dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
-		return priv->num_lanes;
-	}
-
-	priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
-	if (IS_ERR(priv->phy)) {
-		dev_err(dev, "failed to create combphy\n");
-		return PTR_ERR(priv->phy);
-	}
-
-	priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
-	if (IS_ERR(priv->p30phy)) {
-		return dev_err_probe(dev, PTR_ERR(priv->p30phy),
-				     "failed to get phy reset control\n");
-	}
-	if (!priv->p30phy)
-		dev_info(dev, "no phy reset control specified\n");
-
-	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
-	if (priv->num_clks < 1)
-		return -ENODEV;
-
-	dev_set_drvdata(dev, priv);
-	phy_set_drvdata(priv->phy, priv);
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static const struct of_device_id rockchip_p3phy_of_match[] = {
-	{ .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
-	{ .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
-
-static struct platform_driver rockchip_p3phy_driver = {
-	.probe	= rockchip_p3phy_probe,
-	.driver = {
-		.name = "rockchip-snps-pcie3-phy",
-		.of_match_table = rockchip_p3phy_of_match,
-	},
-};
-module_platform_driver(rockchip_p3phy_driver);
-MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
-MODULE_LICENSE("GPL");

target/linux/rockchip/files/include/linux/motorcomm_phy.h

@@ -0,0 +1,73 @@
+/*
+ * include/linux/motorcomm_phy.h
+ *
+ * Motorcomm PHY IDs
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _MOTORCOMM_PHY_H
+#define _MOTORCOMM_PHY_H
+
+#define MOTORCOMM_PHY_ID_MASK	0x00000fff
+#define MOTORCOMM_PHY_ID_8531_MASK	0xffffffff
+
+#define PHY_ID_YT8010		0x00000309
+#define PHY_ID_YT8510		0x00000109
+#define PHY_ID_YT8511		0x0000010a
+#define PHY_ID_YT8512		0x00000118
+#define PHY_ID_YT8512B		0x00000128
+#define PHY_ID_YT8521		0x0000011a
+#define PHY_ID_YT8531S		0x4f51e91a
+#define PHY_ID_YT8531		0x4f51e91b
+
+#define REG_PHY_SPEC_STATUS		0x11
+#define REG_INT_MASK			0x12
+#define REG_INT_STATUS			0x13
+#define REG_DEBUG_ADDR_OFFSET		0x1e
+#define REG_DEBUG_DATA			0x1f
+
+#define YT8511_EXTREG_SLEEP_CONTROL1	0x27
+#define YT8511_EN_SLEEP_SW_BIT		15
+
+#define YT8512_EXTREG_AFE_PLL		0x50
+#define YT8512_EXTREG_EXTEND_COMBO	0x4000
+#define YT8512_EXTREG_LED0		0x40c0
+#define YT8512_EXTREG_LED1		0x40c3
+
+#define YT8512_EXTREG_SLEEP_CONTROL1	0x2027
+
+#define YT_SOFTWARE_RESET		0x8000
+
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN	0x0040
+#define YT8512_CONTROL1_RMII_EN		0x0001
+#define YT8512_LED0_ACT_BLK_IND		0x1000
+#define YT8512_LED0_DIS_LED_AN_TRY	0x0001
+#define YT8512_LED0_BT_BLK_EN		0x0002
+#define YT8512_LED0_HT_BLK_EN		0x0004
+#define YT8512_LED0_COL_BLK_EN		0x0008
+#define YT8512_LED0_BT_ON_EN		0x0010
+#define YT8512_LED1_BT_ON_EN		0x0010
+#define YT8512_LED1_TXACT_BLK_EN	0x0100
+#define YT8512_LED1_RXACT_BLK_EN	0x0200
+#define YT8512_SPEED_MODE		0xc000
+#define YT8512_DUPLEX			0x2000
+
+#define YT8512_SPEED_MODE_BIT		14
+#define YT8512_DUPLEX_BIT		13
+#define YT8512_EN_SLEEP_SW_BIT		15
+
+#define YT8521_EXTREG_SLEEP_CONTROL1	0x27
+#define YT8521_EN_SLEEP_SW_BIT		15
+
+#define YT8521_SPEED_MODE		0xc000
+#define YT8521_DUPLEX			0x2000
+#define YT8521_SPEED_MODE_BIT		14
+#define YT8521_DUPLEX_BIT		13
+#define YT8521_LINK_STATUS_BIT		10
+
+#endif /* _MOTORCOMM_PHY_H */

target/linux/rockchip/files/include/linux/phy/pcie.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-#ifndef __PHY_PCIE_H
-#define __PHY_PCIE_H
-
-#define PHY_MODE_PCIE_RC 20
-#define PHY_MODE_PCIE_EP 21
-#define PHY_MODE_PCIE_BIFURCATION 22
-
-#endif

target/linux/rockchip/image/armv8.mk

@@ -2,46 +2,6 @@
 #
 # Copyright (C) 2020 Tobias Maedel
 
-define Device/embedfire_doornet1
-  DEVICE_VENDOR := EmbedFire
-  DEVICE_MODEL := DoorNet1
-  SOC := rk3328
-  UBOOT_DEVICE_NAME := doornet1-rk3328
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
-  DEVICE_PACKAGES := kmod-usb-net-rtl8152 kmod-rtl8821cu
-endef
-TARGET_DEVICES += embedfire_doornet1
-
-define Device/embedfire_doornet2
-  DEVICE_VENDOR := EmbedFire
-  DEVICE_MODEL := DoorNet2 1GB
-  SOC := rk3399
-  UBOOT_DEVICE_NAME := doornet2-rk3399
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
-  DEVICE_PACKAGES := kmod-r8168 -urngd
-endef
-TARGET_DEVICES += embedfire_doornet2
-
-define Device/fastrhino_r66s
-  DEVICE_VENDOR := FastRhino
-  DEVICE_MODEL := R66S
-  SOC := rk3568
-  UBOOT_DEVICE_NAME := fastrhino-r66s-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
-  DEVICE_PACKAGES := kmod-r8125
-endef
-TARGET_DEVICES += fastrhino_r66s
-
-define Device/firefly_station-p2
-  DEVICE_VENDOR := Firefly
-  DEVICE_MODEL := Station P2
-  SOC := rk3568
-  UBOOT_DEVICE_NAME := station-p2-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
-  DEVICE_PACKAGES := kmod-brcmfmac kmod-ikconfig kmod-ata-ahci-platform station-p2-firmware wpad-openssl
-endef
-TARGET_DEVICES += firefly_station-p2
-
 define Device/friendlyarm_nanopi-neo3
   DEVICE_VENDOR := FriendlyARM
   DEVICE_MODEL := NanoPi NEO3
@@ -91,7 +51,7 @@ define Device/friendlyarm_nanopi-r4se
 endef
 TARGET_DEVICES += friendlyarm_nanopi-r4se
 
-define Device/friendlyelec_nanopi-r5s
+define Device/friendlyarm_nanopi-r5s
   DEVICE_VENDOR := FriendlyARM
   DEVICE_MODEL := NanoPi R5S
   SOC := rk3568
@@ -99,7 +59,7 @@ define Device/friendlyelec_nanopi-r5s
   IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
   DEVICE_PACKAGES := kmod-r8125
 endef
-TARGET_DEVICES += friendlyelec_nanopi-r5s
+TARGET_DEVICES += friendlyarm_nanopi-r5s
 
 define Device/pine64_rockpro64
   DEVICE_VENDOR := Pine64
@@ -111,16 +71,6 @@ define Device/pine64_rockpro64
 endef
 TARGET_DEVICES += pine64_rockpro64
 
-define Device/radxa_rock-3a
-  DEVICE_VENDOR := Radxa
-  DEVICE_MODEL := ROCK3 Model A
-  SOC := rk3568
-  SUPPORTED_DEVICES := radxa,rock3a
-  UBOOT_DEVICE_NAME := rock-3a-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
-endef
-TARGET_DEVICES += radxa_rock-3a
-
 define Device/radxa_rock-pi-4
   DEVICE_VENDOR := Radxa
   DEVICE_MODEL := ROCK Pi 4

target/linux/rockchip/modules.mk

@@ -16,8 +16,6 @@ define KernelPackage/drm-rockchip
 	CONFIG_PHY_ROCKCHIP_INNO_HDMI \
 	CONFIG_DRM_DW_HDMI \
 	CONFIG_DRM_DW_HDMI_CEC \
-	CONFIG_ROCKCHIP_VOP=y \
-	CONFIG_ROCKCHIP_VOP2=y
 	CONFIG_ROCKCHIP_ANALOGIX_DP=n \
 	CONFIG_ROCKCHIP_CDN_DP=n \
 	CONFIG_ROCKCHIP_DW_HDMI=y \
@@ -34,7 +32,8 @@ define KernelPackage/drm-rockchip
 	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \
 	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.ko \
 	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \
-	$(LINUX_DIR)/drivers/media/cec/core/cec.ko \
+	$(LINUX_DIR)/drivers/media/cec/cec.ko@lt5.10 \
+	$(LINUX_DIR)/drivers/media/cec/core/cec.ko@ge5.10 \
 	$(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \
 	$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@ge5.15 \
 	$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
@@ -48,23 +47,20 @@ endef
 
 $(eval $(call KernelPackage,drm-rockchip))
 
-define KernelPackage/gpu-lima
+define KernelPackage/saradc-rockchip
-  SUBMENU:=$(VIDEO_MENU)
+  SUBMENU:=$(IIO_MENU)
-  TITLE:=Mali-4xx GPU support
+  TITLE:=Rockchip SARADC support
-  DEPENDS:=@TARGET_rockchip +kmod-drm
+  DEPENDS:=@TARGET_rockchip +kmod-industrialio-triggered-buffer
   KCONFIG:= \
-	CONFIG_DRM_VGEM \
+	CONFIG_RESET_CONTROLLER=y \
-	CONFIG_DRM_GEM_CMA_HELPER=y \
+	CONFIG_ROCKCHIP_SARADC
-	CONFIG_DRM_LIMA
   FILES:= \
-	$(LINUX_DIR)/drivers/gpu/drm/vgem/vgem.ko \
+	$(LINUX_DIR)/drivers/iio/adc/rockchip_saradc.ko
-	$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko \
+  AUTOLOAD:=$(call AutoProbe,rockchip_saradc)
-	$(LINUX_DIR)/drivers/gpu/drm/lima/lima.ko
-  AUTOLOAD:=$(call AutoProbe,lima vgem)
 endef
 
-define KernelPackage/gpu-lima/description
+define KernelPackage/saradc-rockchip/description
-  Open-source reverse-engineered driver for Mali-4xx GPUs
+  Support for the SARADC found in SoCs from Rockchip
 endef
 
-$(eval $(call KernelPackage,gpu-lima))
+$(eval $(call KernelPackage,saradc-rockchip))

target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch

@@ -8,15 +8,20 @@ stores the MAC address.
 
 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
 ---
- .../boot/dts/rockchip/rk3399-nanopi-r4s.dts    | 13 +++++++++++++
+ .../boot/dts/rockchip/rk3399-nanopi-r4s.dts    | 18 ++++++++++++++++++
-1 file changed, 13 insertions(+)
+ 1 file changed, 18 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -75,6 +75,19 @@ &emmc_phy {
+@@ -68,6 +68,24 @@
  	status = "disabled";
  };
  
++&gmac {
++	nvmem-cells = <&mac_address>;
++	nvmem-cell-names = "mac-address";
++};
++
 +&i2c2 {
 +	eeprom@51 {
 +		compatible = "microchip,24c02", "atmel,24c02";

target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch

@@ -19,7 +19,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	dr_mode = "host";
  	status = "okay";
 +
-+	usb-eth@2 {
++	usb_eth: usb-eth@2 {
 +		compatible = "realtek,rtl8153";
 +		reg = <2>;
 +

target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch

@@ -11,7 +11,7 @@
 +		#size-cells = <2>;
 +
 +		pcie-eth@0,0 {
-+			compatible = "realtek,r8168";
++			compatible = "pci10ec,8168";
 +			reg = <0x000000 0 0 0 0>;
 +
 +			realtek,led-data = <0x870>;

target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch

@@ -32,4 +32,4 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
 +
  	host->ios.clock = 0;
  	host->ios.vdd = 0;
- 
+ 

target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch

@@ -1,434 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
-@@ -0,0 +1,419 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 EmbedFire <embedfire@embedfire.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/gpio/gpio.h>
-+#include "rk3328.dtsi"
-+
-+/ {
-+	model = "EmbedFire DoorNet1";
-+	compatible = "embedfire,doornet1", "rockchip,rk3328";
-+	
-+	aliases {
-+		led-boot = &sys_led;
-+		led-failsafe = &sys_led;
-+		led-running = &sys_led;
-+		led-upgrade = &sys_led;
-+		// mmc1 = &sdmmc;
-+		// mmc0 = &emmc;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac_clk: gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	keys {
-+		compatible = "gpio-keys";
-+		pinctrl-0 = <&reset_button_pin>;
-+		pinctrl-names = "default";
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <50>;
-+		};
-+	};
-+
-+	vcc_rtl8153: vcc-rtl8153-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&rtl8153_en_drv>;
-+		regulator-always-on;
-+		regulator-name = "vcc_rtl8153";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		enable-active-high;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+		pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
-+		pinctrl-names = "default";
-+
-+		lan_led: led-0 {
-+			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:green:lan";
-+		};
-+
-+		sys_led: led-1 {
-+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:red:sys";
-+		};
-+
-+		wan_led: led-2 {
-+			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+			label = "doornet1:green:wan";
-+		};
-+		
-+		wifi_enable: wifi_enable {
-+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-+			label = "wifi-enable";
-+		};	
-+	};
-+
-+	vcc_io_sdio: sdmmcio-regulator {
-+		compatible = "regulator-gpio";
-+		enable-active-high;
-+		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
-+		pinctrl-0 = <&sdio_vcc_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vcc_io_sdio";
-+		regulator-always-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-settling-time-us = <5000>;
-+		regulator-type = "voltage";
-+		startup-delay-us = <2000>;
-+		states = <1800000 0x1
-+			  3300000 0x0>;
-+		vin-supply = <&vcc_io_33>;
-+	};
-+
-+	vcc_sd: sdmmc-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+		pinctrl-0 = <&sdmmc0m1_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vcc_sd";
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc_io_33>;
-+	};
-+
-+	vdd_5v: vdd-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&gmac2io {
-+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+	clock_in_out = "input";
-+	phy-mode = "rgmii";
-+	phy-supply = <&vcc_io_33>;
-+	pinctrl-0 = <&rgmiim1_pins>;
-+	pinctrl-names = "default";
-+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+	snps,reset-delays-us = <0 1000000 50000>;
-+	snps,reset-active-low;
-+	tx_delay = <0x18>;
-+	rx_delay = <0x24>;
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	status = "okay";
-+
-+	rk805: pmic@18 {
-+		compatible = "rockchip,rk805";
-+		reg = <0x18>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		clock-output-names = "xin32k", "rk805-clkout2";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		pinctrl-0 = <&pmic_int_l>;
-+		pinctrl-names = "default";
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vdd_5v>;
-+		vcc2-supply = <&vdd_5v>;
-+		vcc3-supply = <&vdd_5v>;
-+		vcc4-supply = <&vdd_5v>;
-+		vcc5-supply = <&vcc_io_33>;
-+		vcc6-supply = <&vdd_5v>;
-+
-+		regulators {
-+			vdd_log: DCDC_REG1 {
-+				regulator-name = "vdd_log";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vdd_arm: DCDC_REG2 {
-+				regulator-name = "vdd_arm";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <950000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_io_33: DCDC_REG4 {
-+				regulator-name = "vcc_io_33";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc_18: LDO_REG1 {
-+				regulator-name = "vcc_18";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc18_emmc: LDO_REG2 {
-+				regulator-name = "vcc18_emmc";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdd_10: LDO_REG3 {
-+				regulator-name = "vdd_10";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1000000>;
-+				regulator-max-microvolt = <1000000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+		};
-+	};
-+        usb {
-+                rtl8153_en_drv: rtl8153-en-drv {
-+                        rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+                };
-+        };
-+};
-+
-+&io_domains {
-+	pmuio-supply = <&vcc_io_33>;
-+	vccio1-supply = <&vcc_io_33>;
-+	vccio2-supply = <&vcc18_emmc>;
-+	vccio3-supply = <&vcc_io_sdio>;
-+	vccio4-supply = <&vcc_18>;
-+	vccio5-supply = <&vcc_io_33>;
-+	vccio6-supply = <&vcc_io_33>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	button {
-+		reset_button_pin: reset-button-pin {
-+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	ethernet-phy {
-+		eth_phy_reset_pin: eth-phy-reset-pin {
-+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+	};
-+
-+	leds {
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		sys_led_pin: sys-led-pin {
-+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wifi_pin: wifi_pin{
-+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sd {
-+		sdio_vcc_pin: sdio-vcc-pin {
-+			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&pwm2 {
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+	pinctrl-names = "default";
-+	sd-uhs-sdr12;
-+	sd-uhs-sdr25;
-+	sd-uhs-sdr50;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc_sd>;
-+	vqmmc-supply = <&vcc_io_sdio>;
-+	status = "okay";
-+};
-+
-+&emmc {
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	max-frequency = <150000000>;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+	vmmc-supply = <&vcc_io_33>;
-+	vqmmc-supply = <&vcc18_emmc>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <0>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&u2phy {
-+	status = "okay";
-+};
-+
-+&u2phy_host {
-+	status = "okay";
-+};
-+
-+&u2phy_otg {
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb20_otg {
-+	status = "okay";
-+	dr_mode = "host";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usbdrd3 {
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3 {
-+	dr_mode = "host";
-+	status = "okay";
-+
-+	usb-eth@2 {
-+		compatible = "realtek,rtl8153";
-+		reg = <2>;
-+
-+		realtek,led-data = <0x87>;
-+	};
-+};
--- 
-2.25.1

target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch

@@ -0,0 +1,79 @@
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+@@ -0,0 +1,66 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
++ * (http://www.orangepi.org)
++ *
++ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
++ */
++
++#include "rk3328-orangepi-r1-plus.dts"
++
++/ {
++	model = "Xunlong Orange Pi R1 Plus LTS";
++	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
++};
++
++&dmc_opp_table {
++	opp-798000000 {
++		status = "disabled";
++	};
++	opp-840000000 {
++		status = "disabled";
++	};
++	opp-924000000 {
++		status = "disabled";
++	};
++	opp-1056000000 {
++		status = "disabled";
++	};
++};
++
++&gmac2io {
++	phy-handle = <&yt8531c>;
++	tx_delay = <0x19>;
++	rx_delay = <0x05>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8531c: ethernet-phy@0 {
++			compatible = "ethernet-phy-id4f51.e91b",
++				     "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <15000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
++
++&lan_led {
++	label = "orangepi-r1-plus-lts:green:lan";
++};
++
++&sys_led {
++	label = "orangepi-r1-plus-lts:red:sys";
++};
++
++&usb_eth {
++	realtek,led-data = <0x78>;
++};
++
++&wan_led {
++	label = "orangepi-r1-plus-lts:green:wan";
++};

target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch

@@ -1,8 +1,8 @@
 --- a/arch/arm64/boot/dts/rockchip/Makefile
 +++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
+@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
@@ -10,7 +10,7 @@
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,47 @@
+@@ -0,0 +1,51 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@@ -55,6 +55,10 @@
 +	label = "nanopi-r2c:red:sys";
 +};
 +
++&usb_eth {
++      realtek,led-data = <0x78>;
++};
++
 +&wan_led {
 +	label = "nanopi-r2c:green:wan";
 +};

target/linux/rockchip/patches-5.10/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch

@@ -37,15 +37,11 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
 index 479906f3a..5f6ffb496 100644
 --- a/arch/arm64/boot/dts/rockchip/Makefile
 +++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -3,6 +3,11 @@
+@@ -3,6 +3,7 @@
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-station-p2.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb

target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch

@@ -1,768 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts
-@@ -0,0 +1,115 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3399-doornet2.dtsi"
-+
-+/ {
-+	model = "EmbedFire DoorNet2 1GB";
-+	compatible = "embedfire,doornet2", "rockchip,rk3399";
-+
-+	aliases {
-+		led-boot = &sys_led;
-+		led-failsafe = &sys_led;
-+		led-running = &sys_led;
-+		led-upgrade = &sys_led;
-+	};
-+
-+	/delete-node/ display-subsystem;
-+
-+	gpio-leds {
-+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+
-+		/delete-node/ status;
-+
-+		lan_led: led-lan {
-+			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-+			label = "green:lan";
-+		};
-+
-+		sys_led: led-sys {
-+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-+			label = "red:sys";
-+			default-state = "on";
-+		};
-+
-+		wan_led: led-wan {
-+			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+			label = "green:wan";
-+		};
-+	};
-+
-+	gpio-keys {
-+		pinctrl-0 = <&reset_button_pin>;
-+
-+		/delete-node/ power;
-+
-+		reset {
-+			debounce-interval = <50>;
-+			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
-+		};
-+	};
-+
-+	vdd_5v: vdd-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+	};
-+};
-+
-+&pcie0 {
-+	max-link-speed = <1>;
-+	num-lanes = <1>;
-+	vpcie3v3-supply = <&vcc3v3_sys>;
-+
-+	pcie@0 {
-+		reg = <0x00000000 0 0 0 0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+
-+		pcie-eth@0,0 {
-+			compatible = "realtek,r8168";
-+			reg = <0x000000 0 0 0 0>;
-+
-+			realtek,led-data = <0x870>;
-+		};
-+	};
-+};
-+
-+&pinctrl {
-+	gpio-leds {
-+		/delete-node/ leds-gpio;
-+
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		sys_led_pin: sys-led-pin {
-+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		/delete-node/ power-key;
-+
-+		reset_button_pin: reset-button-pin {
-+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&u2phy0_host {
-+	phy-supply = <&vdd_5v>;
-+};
-+
-+&vcc3v3_sys {
-+	vin-supply = <&vcc5v0_sys>;
-+};
-+
-+
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
-@@ -0,0 +1,637 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include <dt-bindings/input/linux-event-codes.h>
-+#include "rk3399.dtsi"
-+#include "rk3399-opp.dtsi"
-+
-+/ {
-+	chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	clkin_gmac: external-gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "clkin_gmac";
-+		#clock-cells = <0>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-name = "vcc3v3_sys";
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-name = "vcc5v0_sys";
-+		vin-supply = <&vdd_5v>;
-+	};
-+
-+	/* switched by pmic_sleep */
-+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
-+		compatible = "regulator-fixed";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-name = "vcc1v8_s3";
-+		vin-supply = <&vcc_1v8>;
-+	};
-+
-+	vcc3v0_sd: vcc3v0-sd {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&sdmmc0_pwr_h>;
-+		regulator-always-on;
-+		regulator-min-microvolt = <3000000>;
-+		regulator-max-microvolt = <3000000>;
-+		regulator-name = "vcc3v0_sd";
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	vbus_typec: vbus-typec {
-+		compatible = "regulator-fixed";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-name = "vbus_typec";
-+	};
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+		autorepeat;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&power_key>;
-+
-+		power {
-+			debounce-interval = <100>;
-+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
-+			label = "GPIO Key Power";
-+			linux,code = <KEY_POWER>;
-+			wakeup-source;
-+		};
-+	};
-+
-+	leds: gpio-leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&leds_gpio>;
-+
-+		status {
-+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-+			label = "status_led";
-+			linux,default-trigger = "heartbeat";
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk808 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_reg_on_h>;
-+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-+	};
-+};
-+
-+&cpu_b0 {
-+	cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_b1 {
-+	cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_l0 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l1 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l2 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l3 {
-+	cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&emmc_phy {
-+	status = "okay";
-+};
-+
-+&gmac {
-+	assigned-clocks = <&cru SCLK_RMII_SRC>;
-+	assigned-clock-parents = <&clkin_gmac>;
-+	clock_in_out = "input";
-+	phy-supply = <&vcc3v3_s3>;
-+	phy-mode = "rgmii";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&rgmii_pins>;
-+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	snps,reset-delays-us = <0 100000 50000>;
-+	tx_delay = <0x28>;
-+	rx_delay = <0x11>;
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	ddc-i2c-bus = <&i2c7>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&hdmi_cec>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	clock-frequency = <400000>;
-+	i2c-scl-rising-time-ns = <160>;
-+	i2c-scl-falling-time-ns = <30>;
-+	status = "okay";
-+
-+	vdd_cpu_b: regulator@40 {
-+		compatible = "silergy,syr827";
-+		reg = <0x40>;
-+		fcs,suspend-voltage-selector = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&cpu_b_sleep>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-name = "vdd_cpu_b";
-+		regulator-ramp-delay = <1000>;
-+		vin-supply = <&vcc3v3_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	vdd_gpu: regulator@41 {
-+		compatible = "silergy,syr828";
-+		reg = <0x41>;
-+		fcs,suspend-voltage-selector = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&gpu_sleep>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-name = "vdd_gpu";
-+		regulator-ramp-delay = <1000>;
-+		vin-supply = <&vcc3v3_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk808: pmic@1b {
-+		compatible = "rockchip,rk808";
-+		reg = <0x1b>;
-+		clock-output-names = "xin32k", "rtc_clko_wifi";
-+		#clock-cells = <1>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int_l>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		vcc10-supply = <&vcc3v3_sys>;
-+		vcc11-supply = <&vcc3v3_sys>;
-+		vcc12-supply = <&vcc3v3_sys>;
-+		vddio-supply = <&vcc_3v0>;
-+
-+		regulators {
-+			vdd_center: DCDC_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <750000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-name = "vdd_center";
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_cpu_l: DCDC_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <750000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-name = "vdd_cpu_l";
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc_ddr";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG4 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc_1v8";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc1v8_cam: LDO_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc1v8_cam";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v0_touch: LDO_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcc3v0_touch";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc1v8_pmupll: LDO_REG3 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc1v8_pmupll";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc_sdio: LDO_REG4 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <3000000>;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc_sdio";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3000000>;
-+				};
-+			};
-+
-+			vcca3v0_codec: LDO_REG5 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcca3v0_codec";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v5: LDO_REG6 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1500000>;
-+				regulator-max-microvolt = <1500000>;
-+				regulator-name = "vcc_1v5";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1500000>;
-+				};
-+			};
-+
-+			vcca1v8_codec: LDO_REG7 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcca1v8_codec";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v0: LDO_REG8 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-name = "vcc_3v0";
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3000000>;
-+				};
-+			};
-+
-+			vcc3v3_s3: SWITCH_REG1 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc3v3_s3";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_s0: SWITCH_REG2 {
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-name = "vcc3v3_s0";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	clock-frequency = <200000>;
-+	i2c-scl-rising-time-ns = <150>;
-+	i2c-scl-falling-time-ns = <30>;
-+	status = "okay";
-+};
-+
-+&i2c2 {
-+	status = "okay";
-+};
-+
-+&i2c7 {
-+	status = "okay";
-+};
-+
-+&io_domains {
-+	bt656-supply = <&vcc_1v8>;
-+	audio-supply = <&vcca1v8_codec>;
-+	sdmmc-supply = <&vcc_sdio>;
-+	gpio1830-supply = <&vcc_3v0>;
-+	status = "okay";
-+};
-+
-+&pcie_phy {
-+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
-+	assigned-clock-rates = <100000000>;
-+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
-+	status = "okay";
-+};
-+
-+&pcie0 {
-+	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-+	max-link-speed = <2>;
-+	num-lanes = <4>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	fusb30x {
-+		fusb0_int: fusb0-int {
-+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		leds_gpio: leds-gpio {
-+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	ethernet-phy {
-+		eth_phy_reset_pin: eth-phy-reset-pin {
-+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+	};
-+
-+	pmic {
-+		cpu_b_sleep: cpu-b-sleep {
-+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+
-+		gpu_sleep: gpu-sleep {
-+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		power_key: power-key {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sdio {
-+		bt_host_wake_l: bt-host-wake-l {
-+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_reg_on_h: bt-reg-on-h {
-+			/* external pullup to VCC1V8_PMUPLL */
-+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_wake_l: bt-wake-l {
-+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wifi_reg_on_h: wifi-reg_on-h {
-+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdmmc {
-+		sdmmc0_det_l: sdmmc0-det-l {
-+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
-+		sdmmc0_pwr_h: sdmmc0-pwr-h {
-+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmu1830-supply = <&vcc_3v0>;
-+	status = "okay";
-+};
-+
-+&pwm1 {
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca1v8_s3>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-mmc-highspeed;
-+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v0_sd>;
-+	vqmmc-supply = <&vcc_sdio>;
-+	status = "okay";
-+};
-+
-+&tcphy0 {
-+	status = "okay";
-+};
-+
-+&tcphy1 {
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	/* tshut mode 0:CRU 1:GPIO */
-+	rockchip,hw-tshut-mode = <1>;
-+	/* tshut polarity 0:LOW 1:HIGH */
-+	rockchip,hw-tshut-polarity = <1>;
-+	status = "okay";
-+};
-+
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_host {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usbdrd3_0 {
-+	status = "okay";
-+};
-+
-+&usbdrd3_1 {
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3_0 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3_1 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&vopb {
-+	status = "okay";
-+};
-+
-+&vopb_mmu {
-+	status = "okay";
-+};
-+
-+&vopl {
-+	status = "okay";
-+};
-+
-+&vopl_mmu {
-+	status = "okay";
-+};
-+

target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch

@@ -1,101 +0,0 @@
-From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001
-From: baiywt <baiywt_gj@163.com>
-Date: Mon, 15 Nov 2021 16:51:43 +0800
-Subject: [PATCH] Add support for OrangePi R1 Plus LTS
-
----
- arch/arm64/boot/dts/rockchip/Makefile         |  1 +
- .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 44 +++++++++++++++++++
- 2 files changed, 45 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index 23373c752..552d97555 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -5,6 +5,7 @@
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-new file mode 100644
-index 000000000..c65f7c417
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,70 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus LTS";
-+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+/delete-node/ &rtl8211e;
-+&gmac2io {
-+        phy-handle = <&ethphy3>;
-+        snps,reset-delays-us = <0 15000 50000>;
-+        tx_delay = <0x19>;
-+        rx_delay = <0x05>;
-+        status = "okay";
-+
-+        mdio {
-+                compatible = "snps,dwmac-mdio";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                ethphy3: ethernet-phy@0 {
-+                        reg = <0x0>;
-+                        keep-clkout-on;
-+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+                };
-+        };
-+};
-+
-+&sdmmc {
-+      bus-width = <4>;
-+      cap-sd-highspeed;
-+      disable-wp;
-+      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+      pinctrl-names = "default";
-+      sd-uhs-sdr12;
-+      sd-uhs-sdr25;
-+      sd-uhs-sdr50;
-+      sd-uhs-sdr104;
-+      vmmc-supply = <&vcc_sd>;
-+      vqmmc-supply = <&vcc_io_sdio>;
-+      status = "okay";
-+};
-+
-+&dmc_opp_table {
-+        opp-1056000000 {
-+                status = "disabled";
-+        };
-+        opp-924000000 {
-+                status = "disabled";
-+        };
-+        opp-840000000 {
-+                status = "disabled";
-+        };
-+        opp-798000000 {
-+                status = "disabled";
-+        };
-+};
-+
-+&sys_led {
-+       label = "orangepi-r1-plus-lts:red:sys";
-+};
-+
-+&wan_led {
-+       label = "orangepi-r1-plus-lts:green:wan";
-+};
-+
-+&lan_led {
-+       label = "orangepi-r1-plus-lts:green:lan";
-+};
--- 
-2.25.1

target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch

@@ -37,421 +37,3 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  obj-$(CONFIG_NATIONAL_PHY)	+= national.o
  obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
  obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
---- /dev/null
-+++ b/drivers/net/phy/motorcomm.c
-@@ -0,0 +1,345 @@
-+/*
-+ * drivers/net/phy/motorcomm.c
-+ *
-+ * Driver for Motorcomm PHYs
-+ *
-+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
-+ *
-+ * Copyright (c) 2019 Motorcomm, Inc.
-+ *
-+ * This program is free software; you can redistribute  it and/or modify it
-+ * under  the terms of  the GNU General  Public License as published by the
-+ * Free Software Foundation;  either version 2 of the  License, or (at your
-+ * option) any later version.
-+ *
-+ * Support : Motorcomm Phys:
-+ *		Giga phys: yt8511, yt8521
-+ *		100/10 Phys : yt8512, yt8512b, yt8510
-+ *		Automotive 100Mb Phys : yt8010
-+ *		Automotive 100/10 hyper range Phys: yt8510
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+#include <linux/motorcomm_phy.h>
-+#include <linux/of.h>
-+#include <linux/clk.h>
-+
-+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
-+{
-+	int ret;
-+	int val;
-+
-+	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = phy_read(phydev, REG_DEBUG_DATA);
-+
-+	return val;
-+}
-+
-+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
-+{
-+	int ret;
-+
-+	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = phy_write(phydev, REG_DEBUG_DATA, val);
-+
-+	return ret;
-+}
-+
-+static int yt8010_config_aneg(struct phy_device *phydev)
-+{
-+	phydev->speed = SPEED_100;
-+	return 0;
-+}
-+
-+static int yt8512_clk_init(struct phy_device *phydev)
-+{
-+	int ret;
-+	int val;
-+
-+	val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
-+	if (val < 0)
-+		return val;
-+
-+	val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
-+
-+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
-+	if (val < 0)
-+		return val;
-+
-+	val |= YT8512_CONTROL1_RMII_EN;
-+
-+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = phy_read(phydev, MII_BMCR);
-+	if (val < 0)
-+		return val;
-+
-+	val |= YT_SOFTWARE_RESET;
-+	ret = phy_write(phydev, MII_BMCR, val);
-+
-+	return ret;
-+}
-+
-+static int yt8512_led_init(struct phy_device *phydev)
-+{
-+	int ret;
-+	int val;
-+	int mask;
-+
-+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
-+	if (val < 0)
-+		return val;
-+
-+	val |= YT8512_LED0_ACT_BLK_IND;
-+
-+	mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
-+		YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
-+		YT8512_LED0_BT_ON_EN;
-+	val &= ~mask;
-+
-+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
-+	if (val < 0)
-+		return val;
-+
-+	val |= YT8512_LED1_BT_ON_EN;
-+
-+	mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
-+	val &= ~mask;
-+
-+	ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
-+
-+	return ret;
-+}
-+
-+static int yt8512_config_init(struct phy_device *phydev)
-+{
-+	int ret;
-+	int val;
-+
-+	ret = yt8512_clk_init(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = yt8512_led_init(phydev);
-+
-+	/* disable auto sleep */
-+	val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
-+	if (val < 0)
-+		return val;
-+
-+	val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
-+
-+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	return ret;
-+}
-+
-+static int yt8512_read_status(struct phy_device *phydev)
-+{
-+	int ret;
-+	int val;
-+	int speed, speed_mode, duplex;
-+
-+	ret = genphy_update_link(phydev);
-+	if (ret)
-+		return ret;
-+
-+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
-+	if (val < 0)
-+		return val;
-+
-+	duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
-+	speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
-+	switch (speed_mode) {
-+	case 0:
-+		speed = SPEED_10;
-+		break;
-+	case 1:
-+		speed = SPEED_100;
-+		break;
-+	case 2:
-+	case 3:
-+	default:
-+		speed = SPEED_UNKNOWN;
-+		break;
-+	}
-+
-+	phydev->speed = speed;
-+	phydev->duplex = duplex;
-+
-+	return 0;
-+}
-+
-+static int yt8521_config_init(struct phy_device *phydev)
-+{
-+	int ret;
-+	int val;
-+
-+	/* disable auto sleep */
-+	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
-+	if (val < 0)
-+		return val;
-+
-+	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
-+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* switch to access UTP */
-+	ret = ytphy_write_ext(phydev, 0xa000, 0);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* enable RXC clock when no wire plug */
-+	val = ytphy_read_ext(phydev, 0xc);
-+	if (val < 0)
-+		return val;
-+
-+	val &= ~(1 << 12);
-+	ret = ytphy_write_ext(phydev, 0xc, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* output SyncE clock (125mhz) even link is down */
-+	ret = ytphy_write_ext(phydev, 0xa012, 0x38);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* disable rgmii clk 2ns delay */
-+	val = ytphy_read_ext(phydev, 0xa001);
-+	if (val < 0)
-+		return val;
-+
-+	val &= ~(1 << 8);
-+	ret = ytphy_write_ext(phydev, 0xa001, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* setup delay */
-+	val = (1 << 10) | (0xf << 4) | 5;
-+	ret = ytphy_write_ext(phydev, 0xa003, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
-+	ytphy_write_ext(phydev, 0xa00b, 0xe004);
-+	ytphy_write_ext(phydev, 0xa00c, 0);
-+	ytphy_write_ext(phydev, 0xa00d, 0x2600);
-+	ytphy_write_ext(phydev, 0xa00e, 0x0070);
-+	ytphy_write_ext(phydev, 0xa00f, 0x000a);
-+
-+	return 0;
-+}
-+
-+static int yt8521_config_intr(struct phy_device *phydev)
-+{
-+	int val;
-+
-+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
-+		val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
-+	else
-+		val = 0;
-+
-+	return phy_write(phydev, REG_INT_MASK, val);
-+}
-+
-+static int yt8521_ack_interrupt(struct phy_device *phydev)
-+{
-+	int val;
-+
-+	val = phy_read(phydev, REG_INT_STATUS);
-+	phydev_dbg(phydev, "intr status 0x04%x\n", val);
-+
-+	return (val < 0) ? val : 0;
-+}
-+
-+static struct phy_driver ytphy_drvs[] = {
-+	{
-+		.phy_id		= PHY_ID_YT8010,
-+		.name		= "YT8010 Automotive Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		.features	= PHY_BASIC_FEATURES,
-+		.config_aneg	= yt8010_config_aneg,
-+		.read_status	= genphy_read_status,
-+	}, {
-+		.phy_id		= PHY_ID_YT8510,
-+		.name		= "YT8510 100/10Mb Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		.features	= PHY_BASIC_FEATURES,
-+		.read_status	= genphy_read_status,
-+	}, {
-+		.phy_id		= PHY_ID_YT8511,
-+		.name		= "YT8511 Gigabit Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		.features	= PHY_GBIT_FEATURES,
-+		.read_status	= genphy_read_status,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+	}, {
-+		.phy_id		= PHY_ID_YT8512,
-+		.name		= "YT8512 Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		.features	= PHY_BASIC_FEATURES,
-+		.config_init	= yt8512_config_init,
-+		.read_status	= yt8512_read_status,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+	}, {
-+		.phy_id		= PHY_ID_YT8512B,
-+		.name		= "YT8512B Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		.features	= PHY_BASIC_FEATURES,
-+		.config_init	= yt8512_config_init,
-+		.read_status	= yt8512_read_status,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+	}, {
-+		.phy_id		= PHY_ID_YT8521,
-+		.name		= "YT8521 Ethernet",
-+		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-+		/* PHY_GBIT_FEATURES */
-+		.config_init	= yt8521_config_init,
-+		.ack_interrupt	= yt8521_ack_interrupt,
-+		.config_intr	= yt8521_config_intr,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+	},
-+};
-+
-+module_phy_driver(ytphy_drvs);
-+
-+MODULE_DESCRIPTION("Motorcomm PHY driver");
-+MODULE_AUTHOR("Leilei Zhao");
-+MODULE_LICENSE("GPL");
-+
-+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
-+	{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
---- /dev/null
-+++ b/include/linux/motorcomm_phy.h
-@@ -0,0 +1,67 @@
-+/*
-+ * include/linux/motorcomm_phy.h
-+ *
-+ * Motorcomm PHY IDs
-+ *
-+ * This program is free software; you can redistribute  it and/or modify it
-+ * under  the terms of  the GNU General  Public License as published by the
-+ * Free Software Foundation;  either version 2 of the  License, or (at your
-+ * option) any later version.
-+ *
-+ */
-+
-+#ifndef _MOTORCOMM_PHY_H
-+#define _MOTORCOMM_PHY_H
-+
-+#define MOTORCOMM_PHY_ID_MASK	0x00000fff
-+
-+#define PHY_ID_YT8010		0x00000309
-+#define PHY_ID_YT8510		0x00000109
-+#define PHY_ID_YT8511		0x0000010a
-+#define PHY_ID_YT8512		0x00000118
-+#define PHY_ID_YT8512B		0x00000128
-+#define PHY_ID_YT8521		0x0000011a
-+
-+#define REG_PHY_SPEC_STATUS		0x11
-+#define REG_INT_MASK			0x12
-+#define REG_INT_STATUS			0x13
-+#define REG_DEBUG_ADDR_OFFSET		0x1e
-+#define REG_DEBUG_DATA			0x1f
-+
-+#define YT8512_EXTREG_AFE_PLL		0x50
-+#define YT8512_EXTREG_EXTEND_COMBO	0x4000
-+#define YT8512_EXTREG_LED0		0x40c0
-+#define YT8512_EXTREG_LED1		0x40c3
-+
-+#define YT8512_EXTREG_SLEEP_CONTROL1	0x2027
-+
-+#define YT_SOFTWARE_RESET		0x8000
-+
-+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN	0x0040
-+#define YT8512_CONTROL1_RMII_EN		0x0001
-+#define YT8512_LED0_ACT_BLK_IND		0x1000
-+#define YT8512_LED0_DIS_LED_AN_TRY	0x0001
-+#define YT8512_LED0_BT_BLK_EN		0x0002
-+#define YT8512_LED0_HT_BLK_EN		0x0004
-+#define YT8512_LED0_COL_BLK_EN		0x0008
-+#define YT8512_LED0_BT_ON_EN		0x0010
-+#define YT8512_LED1_BT_ON_EN		0x0010
-+#define YT8512_LED1_TXACT_BLK_EN	0x0100
-+#define YT8512_LED1_RXACT_BLK_EN	0x0200
-+#define YT8512_SPEED_MODE		0xc000
-+#define YT8512_DUPLEX			0x2000
-+
-+#define YT8512_SPEED_MODE_BIT		14
-+#define YT8512_DUPLEX_BIT		13
-+#define YT8512_EN_SLEEP_SW_BIT		15
-+
-+#define YT8521_EXTREG_SLEEP_CONTROL1	0x27
-+#define YT8521_EN_SLEEP_SW_BIT		15
-+
-+#define YT8521_SPEED_MODE		0xc000
-+#define YT8521_DUPLEX			0x2000
-+#define YT8521_SPEED_MODE_BIT		14
-+#define YT8521_DUPLEX_BIT		13
-+#define YT8521_LINK_STATUS_BIT		10
-+
-+#endif /* _MOTORCOMM_PHY_H */

target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch

@@ -1,475 +0,0 @@
-From abf36eb72942657cef05ebcb2897eaea9064ad06 Mon Sep 17 00:00:00 2001
-From: From: fengying0347 <fengying0347@163.com>
-Date: Thu, 13 Jan 2022 12:59:36 +0800
-Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs
-
----
- .../net/ethernet/stmicro/stmmac/stmmac_main.c |  82 ++++++++
- drivers/net/phy/motorcomm.c                   | 181 +++++++++++++++++-
- drivers/net/phy/phy_device.c                  |  83 ++++++++
- include/linux/motorcomm_phy.h                 |   5 +
- 4 files changed, 350 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 8dc4def..bcd46ca 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -121,6 +121,10 @@ static void stmmac_exit_fs(struct net_device *dev);
- 
- #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
- 
-+#define RTL_8211E_PHY_ID  0x001cc915
-+#define RTL_8211F_PHY_ID  0x001cc916
-+#define YT_8531C_PHY_ID   0x4f51e91b
-+
- int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
- {
- 	int ret = 0;
-@@ -4950,6 +4954,74 @@ int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
- 	return ret;
- }
- 
-+static int phy_rtl8211e_led_fixup(struct phy_device *phydev)
-+{
-+        int val;
-+
-+        printk("%s in\n", __func__);
-+
-+        /*switch to extension page44*/
-+        phy_write(phydev, 31, 0x07);
-+        phy_write(phydev, 30, 0x2c);
-+
-+        /*set led1(yellow) act*/
-+        val = phy_read(phydev, 26);
-+        val &= (~(1<<4));// bit4=0
-+        val |= (1<<5);// bit5=1
-+        val &= (~(1<<6));// bit6=0
-+        phy_write(phydev, 26, val);
-+
-+        /*set led0(green) link*/
-+        val = phy_read(phydev, 28);
-+        val |= (7<<0);// bit0,1,2=1
-+        val &= (~(7<<4));// bit4,5,6=0
-+        val &= (~(7<<8));// bit8,9,10=0
-+        phy_write(phydev, 28, val);
-+
-+        /*switch back to page0*/
-+        phy_write(phydev,31,0x00);
-+
-+        return 0;
-+}
-+
-+static int phy_rtl8211f_led_fixup(struct phy_device *phydev)
-+{
-+        int val;
-+
-+        printk("%s in\n", __func__);
-+
-+        /*switch to extension page 0xd04*/
-+        phy_write(phydev, 31, 0xd04);
-+
-+
-+        /*set led1(yellow) act*/
-+        /*set led2(green) link*/
-+        val = 0xae00;
-+        phy_write(phydev, 16, val);
-+
-+        val = 0x0;
-+        phy_write(phydev, 17, val);
-+        /*switch back to page0*/
-+        phy_write(phydev,31,0x00);
-+
-+        return 0;
-+}
-+
-+static int phy_yt8531_led_fixup(struct phy_device *phydev)
-+{
-+        printk("%s in\n", __func__);
-+        phy_write(phydev, 0x1e, 0xa00d);
-+        phy_write(phydev, 0x1f, 0x670);
-+
-+        phy_write(phydev, 0x1e, 0xa00e);
-+        phy_write(phydev, 0x1f, 0x2070);
-+
-+        phy_write(phydev, 0x1e, 0xa00f);
-+        phy_write(phydev, 0x1f, 0x7e);
-+
-+        return 0;
-+}
-+
- /**
-  * stmmac_dvr_probe
-  * @device: device pointer
-@@ -5173,6 +5245,16 @@ int stmmac_dvr_probe(struct device *device,
- 		netdev_err(ndev, "failed to setup phy (%d)\n", ret);
- 		goto error_phy_setup;
- 	}
-+	/* register the PHY board fixup */
-+        ret = phy_register_fixup_for_uid(RTL_8211E_PHY_ID, 0xffffffff, phy_rtl8211e_led_fixup);
-+        if (ret)
-+                pr_warn("Cannot register PHY board fixup.\n");
-+        ret = phy_register_fixup_for_uid(RTL_8211F_PHY_ID, 0xffffffff, phy_rtl8211f_led_fixup);
-+        if (ret)
-+                pr_warn("Cannot register PHY board fixup.\n");
-+        ret = phy_register_fixup_for_uid(YT_8531C_PHY_ID, 0xffffffff, phy_yt8531_led_fixup);
-+        if (ret)
-+                pr_warn("Cannot register PHY board fixup.\n");
- 
- 	ret = register_netdev(ndev);
- 	if (ret) {
-diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
-index 17a4f6c..e37dfb9 100644
---- a/drivers/net/phy/motorcomm.c
-+++ b/drivers/net/phy/motorcomm.c
-@@ -26,6 +26,13 @@
- #include <linux/of.h>
- #include <linux/clk.h>
- 
-+static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.
-+
-+int genphy_config_init(struct phy_device *phydev)
-+{
-+	return  genphy_read_abilities(phydev);
-+}
-+
- static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
- {
- 	int ret;
-@@ -263,6 +270,38 @@ static int yt8521_config_intr(struct phy_device *phydev)
- 	return phy_write(phydev, REG_INT_MASK, val);
- }
- 
-+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
-+{
-+	int speed_mode, duplex;
-+
-+	int speed = SPEED_UNKNOWN;
-+
-+	duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
-+	speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
-+	switch (speed_mode) {
-+	case 0:
-+		if (is_utp)
-+			speed = SPEED_10;
-+		break;
-+	case 1:
-+		speed = SPEED_100;
-+		break;
-+	case 2:
-+		speed = SPEED_1000;
-+		break;
-+	case 3:
-+		break;
-+	default:
-+		speed = SPEED_UNKNOWN;
-+		break;
-+	}
-+
-+	phydev->speed = speed;
-+	phydev->duplex = duplex;
-+
-+	return 0;
-+}
-+
- static int yt8521_ack_interrupt(struct phy_device *phydev)
- {
- 	int val;
-@@ -273,6 +312,121 @@ static int yt8521_ack_interrupt(struct phy_device *phydev)
- 	return (val < 0) ? val : 0;
- }
- 
-+static int yt8521_read_status(struct phy_device *phydev)
-+{
-+	int ret;
-+	volatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val;
-+	volatile int link;
-+	int link_utp = 0, link_fiber = 0;
-+
-+ 	/* reading UTP */
-+	ret = ytphy_write_ext(phydev, 0xa000, 0);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
-+	if (val < 0)
-+		return val;
-+
-+	link = val & (BIT(YT8521_LINK_STATUS_BIT));
-+	if (link) {
-+		link_utp = 1;
-+		link_mode_8521 = 1;
-+		yt8521_adjust_status(phydev, val, 1);
-+	}
-+	else {
-+		link_utp = 0;
-+	}
-+ 
-+ 	/* reading Fiber */
-+	ret = ytphy_write_ext(phydev, 0xa000, 2);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
-+	if (val < 0)
-+		return val;
-+
-+	//note: below debug information is used to check multiple PHy ports.
-+	//printk (KERN_INFO "yt8521_read_status, fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev);
-+
-+	/* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case
-+	 * this is important for Linux kernel for that, missing linkdown event will cause problem.
-+	 */
-+	yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
-+	yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
-+	link = val & (BIT(YT8521_LINK_STATUS_BIT));
-+	if ((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val))
-+	{
-+		link = 0;
-+		printk(KERN_INFO "yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8521_fiber_latch_val, yt8521_fiber_curr_val);
-+	}
-+
-+	if (link) {
-+		link_fiber = 1;
-+		yt8521_adjust_status(phydev, val, 0);
-+		link_mode_8521 = 32; //fiber mode
-+
-+
-+	}
-+	else {
-+		link_fiber = 0;
-+	}
-+
-+	if (link_utp || link_fiber) {
-+		phydev->link = 1;
-+	}
-+	else {
-+		phydev->link = 0;
-+		link_mode_8521 = 0;
-+	}
-+
-+ 	if (link_utp) {
-+		ytphy_write_ext(phydev, 0xa000, 0);
-+	}
-+ 
-+	return 0;
-+}
-+
-+/*
-+ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and
-+ * this function handles this case and return 1 per linux kernel's polling.
-+ */
-+int yt8521_aneg_done(struct phy_device *phydev)
-+{
-+
-+	if ((32 == link_mode_8521) && (SPEED_100 == phydev->speed))
-+	{
-+		return 1/*link_mode_8521*/;
-+	}
-+
-+	return genphy_aneg_done(phydev);
-+}
-+
-+int yt8521_soft_reset(struct phy_device *phydev)
-+{
-+	int ret, val;
-+
-+	val = ytphy_read_ext(phydev, 0xa001);
-+	ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
-+
-+	ret = genphy_soft_reset(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+int yt8521_suspend(struct phy_device *phydev)
-+{
-+	return 0;
-+}
-+
-+int yt8521_resume(struct phy_device *phydev)
-+{
-+	return 0;
-+}
-+
- static struct phy_driver ytphy_drvs[] = {
- 	{
- 		.phy_id		= PHY_ID_YT8010,
-@@ -323,7 +477,30 @@ static struct phy_driver ytphy_drvs[] = {
- 		.config_intr	= yt8521_config_intr,
- 		.suspend	= genphy_suspend,
- 		.resume		= genphy_resume,
--	},
-+	}, {
-+		/* same as 8521 */
-+		.phy_id		= PHY_ID_YT8531S,
-+		.name 		= "YT8531S Ethernet",
-+		.phy_id_mask 	= MOTORCOMM_PHY_ID_MASK,
-+		.flags 		= PHY_POLL,
-+		.soft_reset 	= yt8521_soft_reset,
-+		.config_aneg 	= genphy_config_aneg,
-+		.aneg_done 	= yt8521_aneg_done,
-+		.config_init 	= yt8521_config_init,
-+		.read_status 	= yt8521_read_status,
-+		.suspend 	= yt8521_suspend,
-+		.resume 	= yt8521_resume,             
-+		}, {
-+		/* same as 8511 */
-+		.phy_id 	= PHY_ID_YT8531,
-+		.name 		= "YT8531 Gigabit Ethernet",
-+		.phy_id_mask 	= MOTORCOMM_PHY_ID_MASK,
-+		.config_aneg 	= genphy_config_aneg,
-+		.config_init 	= genphy_config_init,
-+		.read_status 	= genphy_read_status,
-+		.suspend 	= genphy_suspend,
-+		.resume 	= genphy_resume,              
-+	}
- };
- 
- module_phy_driver(ytphy_drvs);
-@@ -339,6 +516,8 @@ static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
- 	{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
- 	{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
- 	{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
-+	{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
-+	{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
- 	{ }
- };
- 
-diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
-index 950277e..3a35040 100644
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -32,6 +32,7 @@
- #include <linux/string.h>
- #include <linux/uaccess.h>
- #include <linux/unistd.h>
-+#include <linux/motorcomm_phy.h>
- 
- MODULE_DESCRIPTION("PHY library");
- MODULE_AUTHOR("Andy Fleming");
-@@ -409,6 +410,33 @@ int phy_unregister_fixup_for_id(const char *bus_id)
- }
- EXPORT_SYMBOL(phy_unregister_fixup_for_id);
- 
-+static int phy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum)
-+{
-+	int ret;
-+	int val;
-+
-+	ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = bus->read(bus, phy_id, REG_DEBUG_DATA);
-+
-+	return val;
-+}
-+
-+static int phy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val)
-+{
-+	int ret;
-+
-+	ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val);
-+
-+	return ret;
-+}
-+
- /* Returns 1 if fixup matches phydev in bus_id and phy_uid.
-  * Fixups can be set to match any in one or more fields.
-  */
-@@ -816,6 +844,50 @@ static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
- 	return 0;
- }
- 
-+int phy_set_out_125m(struct mii_bus* bus, int phy_id)
-+{
-+	int ret;
-+	int val;
-+
-+	ret = phy_mii_wr_ext(bus, phy_id, 0xa012, 0xd0);
-+	mdelay(100);
-+	val = phy_mii_rd_ext(bus, phy_id, 0xa012);
-+
-+	if (val != 0xd0)
-+	{
-+		printk(KERN_INFO "phy_set_out_125m error\n");
-+		return -1;
-+	}
-+
-+	/* disable auto sleep */
-+	val = phy_mii_rd_ext(bus, phy_id, 0x27);
-+	if (val < 0)
-+		return val;
-+
-+	val &= (~BIT(15));
-+
-+	ret = phy_mii_wr_ext(bus, phy_id, 0x27, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* enable RXC clock when no wire plug */
-+	val = phy_mii_rd_ext(bus, phy_id, 0xc);
-+	if (val < 0)
-+		return val;
-+
-+	/* ext reg 0xc.b[2:1]
-+	00-----25M from pll;
-+	01---- 25M from xtl;(default)
-+	10-----62.5M from pll;
-+	11----125M from pll(here set to this value)
-+	*/
-+	val |= (3 << 1);
-+	ret = phy_mii_wr_ext(bus, phy_id, 0xc, val);
-+	printk(KERN_INFO "phy_set_out_125m, phy clk out, val=%#08x\n", val);
-+
-+	return ret;
-+}
-+
- /**
-  * get_phy_device - reads the specified PHY device and returns its @phy_device
-  *		    struct
-@@ -853,6 +925,15 @@ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
- 	if (r)
- 		return ERR_PTR(r);
- 
-+	if(phy_id == PHY_ID_YT8531)
-+	{
-+		r = phy_set_out_125m(bus, addr);
-+		if (r<0)
-+		{
-+			printk (KERN_INFO "failed to set 125m clk out, ret=%d\n",r);
-+		}
-+	}
-+
- 	return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids);
- }
- EXPORT_SYMBOL(get_phy_device);
-diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h
-index facce6d..23cccca 100644
---- a/include/linux/motorcomm_phy.h
-+++ b/include/linux/motorcomm_phy.h
-@@ -14,6 +14,8 @@
- #define _MOTORCOMM_PHY_H
- 
- #define MOTORCOMM_PHY_ID_MASK	0x00000fff
-+#define MOTORCOMM_PHY_ID_8531_MASK	0xffffffff
-+#define MOTORCOMM_MPHY_ID_MASK	0x0000ffff
- 
- #define PHY_ID_YT8010		0x00000309
- #define PHY_ID_YT8510		0x00000109
-@@ -21,6 +23,9 @@
- #define PHY_ID_YT8512		0x00000118
- #define PHY_ID_YT8512B		0x00000128
- #define PHY_ID_YT8521		0x0000011a
-+#define PHY_ID_YT8531S		0x4f51e91a
-+#define PHY_ID_YT8531		0x4f51e91b
-+#define PHY_ID_YT8618		0x0000e889
- 
- #define REG_PHY_SPEC_STATUS		0x11
- #define REG_INT_MASK			0x12

target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch

@@ -20,7 +20,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  
  #include <dt-bindings/input/input.h>
  #include <dt-bindings/gpio/gpio.h>
-+#include "rk3328-dram-nanopi2-timing.dtsi"
++#include "rk3328-dram-default-timing.dtsi"
  #include "rk3328.dtsi"
  
  / {

target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch

@@ -1,52 +0,0 @@
-From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 17:24:30 +0800
-Subject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- drivers/phy/rockchip/Kconfig                  |    8 +
- drivers/phy/rockchip/Makefile                 |    1 +
- drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++
- 3 files changed, 1184 insertions(+)
- create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c
-
---- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
- 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
- 	  Innosilicon IP block.
- 
-+config PHY_ROCKCHIP_INNO_USB3
-+	tristate "Rockchip INNO USB 3.0 PHY Driver"
-+	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
-+	depends on USB_SUPPORT
-+	select GENERIC_PHY
-+	select USB_PHY
-+	help
-+	  Support for Rockchip USB 3.0 PHY with Innosilicon IP block.
-+
- config PHY_ROCKCHIP_PCIE
- 	tristate "Rockchip PCIe PHY Driver"
- 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
---- a/drivers/phy/rockchip/Makefile
-+++ b/drivers/phy/rockchip/Makefile
-@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC)		+= phy-
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
-+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3)	+= phy-rockchip-inno-usb3.o
- obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
- obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
- obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
---- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
-+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
-@@ -45,6 +45,8 @@ Required Properties:
-    - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
- - compatible: USBGRF should be one of the following:
-    - "rockchip,rv1108-usbgrf", "syscon": for rv1108
-+- compatible: USB3PHYGRF should be one of the following:
-+   - "rockchip,u3phy-grf", "syscon"
- - reg: physical base address of the controller and length of memory mapped
-   region.
- 

target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch

@@ -1,124 +0,0 @@
-From 2184ab853067b484ba5677e35f1a6955a5c023a1 Mon Sep 17 00:00:00 2001
-From: wowowow <you@example.com>
-Date: Wed, 20 Oct 2021 13:46:46 +0800
-Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node
-
----
- .../boot/dts/rockchip/rk3328-doornet1.dts     | 73 +++++++++++++++++++
- 1 file changed, 73 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
-index 8333351..d984163 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
-@@ -7,6 +7,7 @@
- 
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/gpio/gpio.h>
-+#include "rk3328-dram-nanopi2-timing.dtsi"
- #include "rk3328.dtsi"
- 
- / {
-@@ -56,6 +57,72 @@
- 		enable-active-high;
- 	};
- 
-+	dmc: dmc {
-+		  	compatible = "rockchip,rk3328-dmc";
-+		   	devfreq-events = <&dfi>;
-+			center-supply = <&vdd_log>;
-+			clocks = <&cru SCLK_DDRCLK>;
-+			clock-names = "dmc_clk";
-+			operating-points-v2 = <&dmc_opp_table>;
-+	    	ddr_timing = <&ddr_timing>;
-+			upthreshold = <40>;
-+			downdifferential = <20>;
-+			auto-min-freq = <786000>;
-+			auto-freq-en = <1>;
-+			#cooling-cells = <2>;
-+			status = "okay";
-+
-+		ddr_power_model: ddr_power_model {
-+			compatible = "ddr_power_model";
-+			dynamic-power-coefficient = <120>;
-+			static-power-coefficient = <200>;
-+			ts = <32000 4700 (-80) 2>;
-+			thermal-zone = "soc-thermal";
-+		};
-+	};
-+
-+	dmc_opp_table: dmc-opp-table {
-+		compatible = "operating-points-v2";
-+
-+		rockchip,leakage-voltage-sel = <
-+			1   10    0
-+			11  254   1
-+		>;
-+		nvmem-cells = <&logic_leakage>;
-+		nvmem-cell-names = "ddr_leakage";
-+
-+		opp-786000000 {
-+			opp-hz = /bits/ 64 <786000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-798000000 {
-+			opp-hz = /bits/ 64 <798000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-840000000 {
-+			opp-hz = /bits/ 64 <840000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-924000000 {
-+			opp-hz = /bits/ 64 <924000000>;
-+			opp-microvolt = <1100000>;
-+			opp-microvolt-L0 = <1100000>;
-+			opp-microvolt-L1 = <1075000>;
-+		};
-+		opp-1056000000 {
-+			opp-hz = /bits/ 64 <1056000000>;
-+			opp-microvolt = <1175000>;
-+			opp-microvolt-L0 = <1175000>;
-+			opp-microvolt-L1 = <1150000>;
-+		};
-+	};
-+
- 	leds {
- 		compatible = "gpio-leds";
- 		pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
-@@ -138,6 +205,10 @@
- 	cpu-supply = <&vdd_arm>;
- };
- 
-+&dfi {
-+	status = "okay";
-+};
-+
- &gmac2io {
- 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- 	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-@@ -201,6 +272,7 @@
- 				regulator-name = "vdd_log";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-init-microvolt = <1075000>;
- 				regulator-min-microvolt = <712500>;
- 				regulator-max-microvolt = <1450000>;
- 				regulator-ramp-delay = <12500>;
-@@ -215,6 +287,7 @@
- 				regulator-name = "vdd_arm";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-init-microvolt = <1225000>;				
- 				regulator-min-microvolt = <712500>;
- 				regulator-max-microvolt = <1450000>;
- 				regulator-ramp-delay = <12500>;
--- 
-2.25.1
-

target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch

@@ -1,193 +0,0 @@
-From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 19 Dec 2020 12:42:27 +0000
-Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices
-
-It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
-and for better performance.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Co-authored-by: gzelvis <gzelvis@gmail.com>
----
- .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++
- .../boot/dts/rockchip/rk3399-nanopi4.dtsi     |   2 +-
- 2 files changed, 157 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
-@@ -0,0 +1,152 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
-+ *
-+ * Copyright (c) 2020 Tianling Shen <cnsztl@gmail.com>
-+ * Copyright (c) 2020 gzelvis <gzelvis@gmail.com>
-+ */
-+
-+/ {
-+	cluster0_opp: opp-table0 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp00 {
-+			opp-hz = /bits/ 64 <408000000>;
-+			opp-microvolt = <800000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp01 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt = <800000>;
-+		};
-+		opp02 {
-+			opp-hz = /bits/ 64 <816000000>;
-+			opp-microvolt = <850000>;
-+		};
-+		opp03 {
-+			opp-hz = /bits/ 64 <1008000000>;
-+			opp-microvolt = <925000>;
-+		};
-+		opp04 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <1000000>;
-+		};
-+		opp05 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <1125000>;
-+		};
-+		opp06 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <1225000>;
-+		};
-+		opp07 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <1275000>;
-+		};
-+	};
-+
-+	cluster1_opp: opp-table1 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp00 {
-+			opp-hz = /bits/ 64 <408000000>;
-+			opp-microvolt = <800000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp01 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt = <800000>;
-+		};
-+		opp02 {
-+			opp-hz = /bits/ 64 <816000000>;
-+			opp-microvolt = <825000>;
-+		};
-+		opp03 {
-+			opp-hz = /bits/ 64 <1008000000>;
-+			opp-microvolt = <875000>;
-+		};
-+		opp04 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <950000>;
-+		};
-+		opp05 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <1025000>;
-+		};
-+		opp06 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <1100000>;
-+		};
-+		opp07 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <1200000>;
-+		};
-+		opp08 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <1250000>;
-+		};
-+		opp09 {
-+			opp-hz = /bits/ 64 <2208000000>;
-+			opp-microvolt = <1325000>;
-+		};
-+	};
-+
-+	gpu_opp_table: opp-table2 {
-+		compatible = "operating-points-v2";
-+
-+		opp00 {
-+			opp-hz = /bits/ 64 <200000000>;
-+			opp-microvolt = <800000>;
-+		};
-+		opp01 {
-+			opp-hz = /bits/ 64 <297000000>;
-+			opp-microvolt = <800000>;
-+		};
-+		opp02 {
-+			opp-hz = /bits/ 64 <400000000>;
-+			opp-microvolt = <825000>;
-+		};
-+		opp03 {
-+			opp-hz = /bits/ 64 <500000000>;
-+			opp-microvolt = <875000>;
-+		};
-+		opp04 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt = <925000>;
-+		};
-+		opp05 {
-+			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt = <1100000>;
-+		};
-+	};
-+};
-+
-+&cpu_l0 {
-+	operating-points-v2 = <&cluster0_opp>;
-+};
-+
-+&cpu_l1 {
-+	operating-points-v2 = <&cluster0_opp>;
-+};
-+
-+&cpu_l2 {
-+	operating-points-v2 = <&cluster0_opp>;
-+};
-+
-+&cpu_l3 {
-+	operating-points-v2 = <&cluster0_opp>;
-+};
-+
-+&cpu_b0 {
-+	operating-points-v2 = <&cluster1_opp>;
-+};
-+
-+&cpu_b1 {
-+	operating-points-v2 = <&cluster1_opp>;
-+};
-+
-+&gpu {
-+	operating-points-v2 = <&gpu_opp_table>;
-+};
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
-@@ -14,7 +14,7 @@
- /dts-v1/;
- #include <dt-bindings/input/linux-event-codes.h>
- #include "rk3399.dtsi"
--#include "rk3399-opp.dtsi"
-+#include "rk3399-nanopi4-opp.dtsi"
- 
- / {
- 	chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
-@@ -3,7 +3,7 @@
- /dts-v1/;
- #include <dt-bindings/input/linux-event-codes.h>
- #include "rk3399.dtsi"
--#include "rk3399-opp.dtsi"
-+#include "rk3399-nanopi4-opp.dtsi"
- 
- / {
- 	chosen {

target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch

@@ -0,0 +1,46 @@
+From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@immortalwrt.org>
+Date: Mon, 18 Oct 2021 12:47:30 +0800
+Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
+
+It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
+and for better performance.
+
+Co-development-by: gzelvis <gzelvis@gmail.com>
+Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+@@ -33,6 +33,14 @@
+ 			opp-hz = /bits/ 64 <1416000000>;
+ 			opp-microvolt = <1125000>;
+ 		};
++		opp06 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1225000>;
++		};
++		opp07 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1275000>;
++		};
+ 	};
+ 
+ 	cluster1_opp: opp-table1 {
+@@ -72,6 +80,14 @@
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1200000>;
+ 		};
++		opp08 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <1250000>;
++		};
++		opp09 {
++			opp-hz = /bits/ 64 <2208000000>;
++			opp-microvolt = <1325000>;
++		};
+ 	};
+ 
+ 	gpu_opp_table: opp-table2 {

target/linux/rockchip/patches-5.15/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch

@@ -8,15 +8,20 @@ stores the MAC address.
 
 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
 ---
- .../boot/dts/rockchip/rk3399-nanopi-r4s.dts    | 13 +++++++++++++
+ .../boot/dts/rockchip/rk3399-nanopi-r4s.dts    | 18 ++++++++++++++++++
-1 file changed, 13 insertions(+)
+ 1 file changed, 18 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -68,6 +68,19 @@
+@@ -68,6 +68,24 @@
  	status = "disabled";
  };
  
++&gmac {
++	nvmem-cells = <&mac_address>;
++	nvmem-cell-names = "mac-address";
++};
++
 +&i2c2 {
 +	eeprom@51 {
 +		compatible = "microchip,24c02", "atmel,24c02";

target/linux/rockchip/patches-5.15/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch

@@ -1,155 +0,0 @@
-From d269aa2ab975807764dc2509e4156bb9b6bd0d34 Mon Sep 17 00:00:00 2001
-From: Sugar Zhang <sugar.zhang@rock-chips.com>
-Date: Fri, 3 Sep 2021 21:23:24 +0800
-Subject: [PATCH] ASoC: rockchip: Add support for rv1126 pdm
-
-This patch adds support for rv1126 pdm controller which
-redesign cic filiter for better performance.
-
-Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
-Link: https://lore.kernel.org/r/1630675410-3354-1-git-send-email-sugar.zhang@rock-chips.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/rockchip/rockchip_pdm.c | 76 ++++++++++++++++++++++++++++---
- sound/soc/rockchip/rockchip_pdm.h |  3 ++
- 2 files changed, 73 insertions(+), 6 deletions(-)
-
---- a/sound/soc/rockchip/rockchip_pdm.c
-+++ b/sound/soc/rockchip/rockchip_pdm.c
-@@ -24,6 +24,7 @@
- enum rk_pdm_version {
- 	RK_PDM_RK3229,
- 	RK_PDM_RK3308,
-+	RK_PDM_RV1126,
- };
- 
- struct rk_pdm_dev {
-@@ -121,6 +122,55 @@ static unsigned int get_pdm_ds_ratio(uns
- 	return ratio;
- }
- 
-+static unsigned int get_pdm_cic_ratio(unsigned int clk)
-+{
-+	switch (clk) {
-+	case 4096000:
-+	case 5644800:
-+	case 6144000:
-+		return 0;
-+	case 2048000:
-+	case 2822400:
-+	case 3072000:
-+		return 1;
-+	case 1024000:
-+	case 1411200:
-+	case 1536000:
-+		return 2;
-+	default:
-+		return 1;
-+	}
-+}
-+
-+static unsigned int samplerate_to_bit(unsigned int samplerate)
-+{
-+	switch (samplerate) {
-+	case 8000:
-+	case 11025:
-+	case 12000:
-+		return 0;
-+	case 16000:
-+	case 22050:
-+	case 24000:
-+		return 1;
-+	case 32000:
-+		return 2;
-+	case 44100:
-+	case 48000:
-+		return 3;
-+	case 64000:
-+	case 88200:
-+	case 96000:
-+		return 4;
-+	case 128000:
-+	case 176400:
-+	case 192000:
-+		return 5;
-+	default:
-+		return 1;
-+	}
-+}
-+
- static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
- {
- 	return snd_soc_dai_get_drvdata(dai);
-@@ -166,7 +216,8 @@ static int rockchip_pdm_hw_params(struct
- 	if (ret)
- 		return -EINVAL;
- 
--	if (pdm->version == RK_PDM_RK3308) {
-+	if (pdm->version == RK_PDM_RK3308 ||
-+	    pdm->version == RK_PDM_RV1126) {
- 		rational_best_approximation(clk_out, clk_src,
- 					    GENMASK(16 - 1, 0),
- 					    GENMASK(16 - 1, 0),
-@@ -194,8 +245,18 @@ static int rockchip_pdm_hw_params(struct
- 				   PDM_CLK_FD_RATIO_MSK,
- 				   val);
- 	}
--	val = get_pdm_ds_ratio(samplerate);
--	regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
-+
-+	if (pdm->version == RK_PDM_RV1126) {
-+		val = get_pdm_cic_ratio(clk_out);
-+		regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val);
-+		val = samplerate_to_bit(samplerate);
-+		regmap_update_bits(pdm->regmap, PDM_CTRL0,
-+				   PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val));
-+	} else {
-+		val = get_pdm_ds_ratio(samplerate);
-+		regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
-+	}
-+
- 	regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
- 			   PDM_HPF_CF_MSK, PDM_HPF_60HZ);
- 	regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
-@@ -441,9 +502,10 @@ static bool rockchip_pdm_precious_reg(st
- }
- 
- static const struct reg_default rockchip_pdm_reg_defaults[] = {
--	{0x04, 0x78000017},
--	{0x08, 0x0bb8ea60},
--	{0x18, 0x0000001f},
-+	{ PDM_CTRL0, 0x78000017 },
-+	{ PDM_CTRL1, 0x0bb8ea60 },
-+	{ PDM_CLK_CTRL, 0x0000e401 },
-+	{ PDM_DMA_CTRL, 0x0000001f },
- };
- 
- static const struct regmap_config rockchip_pdm_regmap_config = {
-@@ -469,6 +531,8 @@ static const struct of_device_id rockchi
- 	  .data = (void *)RK_PDM_RK3308 },
- 	{ .compatible = "rockchip,rk3308-pdm",
- 	  .data = (void *)RK_PDM_RK3308 },
-+	{ .compatible = "rockchip,rv1126-pdm",
-+	  .data = (void *)RK_PDM_RV1126 },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
---- a/sound/soc/rockchip/rockchip_pdm.h
-+++ b/sound/soc/rockchip/rockchip_pdm.h
-@@ -41,6 +41,8 @@
- #define PDM_PATH1_EN		BIT(28)
- #define PDM_PATH0_EN		BIT(27)
- #define PDM_HWT_EN		BIT(26)
-+#define PDM_SAMPLERATE_MSK	GENMASK(7, 5)
-+#define PDM_SAMPLERATE(x)	((x) << 5)
- #define PDM_VDW_MSK		(0x1f << 0)
- #define PDM_VDW(X)		((X - 1) << 0)
- 
-@@ -66,6 +68,7 @@
- #define PDM_CLK_1280FS		(0x2 << 0)
- #define PDM_CLK_2560FS		(0x3 << 0)
- #define PDM_CLK_5120FS		(0x4 << 0)
-+#define PDM_CIC_RATIO_MSK	(0x3 << 0)
- 
- /* PDM HPF CTRL */
- #define PDM_HPF_LE		BIT(3)

target/linux/rockchip/patches-5.15/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch

@@ -1,26 +0,0 @@
-From d00d1cd4ab42f92d4d871deb9cdea1d7c262a213 Mon Sep 17 00:00:00 2001
-From: Sugar Zhang <sugar.zhang@rock-chips.com>
-Date: Fri, 3 Sep 2021 21:23:26 +0800
-Subject: [PATCH] ASoC: rockchip: pdm: Add support for rk3568 pdm
-
-This patch adds compatible for rk3568 which is the same
-with rv1126.
-
-Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
-Link: https://lore.kernel.org/r/1630675410-3354-3-git-send-email-sugar.zhang@rock-chips.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/rockchip/rockchip_pdm.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/sound/soc/rockchip/rockchip_pdm.c
-+++ b/sound/soc/rockchip/rockchip_pdm.c
-@@ -531,6 +531,8 @@ static const struct of_device_id rockchi
- 	  .data = (void *)RK_PDM_RK3308 },
- 	{ .compatible = "rockchip,rk3308-pdm",
- 	  .data = (void *)RK_PDM_RK3308 },
-+	{ .compatible = "rockchip,rk3568-pdm",
-+	  .data = (void *)RK_PDM_RV1126 },
- 	{ .compatible = "rockchip,rv1126-pdm",
- 	  .data = (void *)RK_PDM_RV1126 },
- 	{},

target/linux/rockchip/patches-5.15/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch

@@ -1,95 +0,0 @@
-From 13e6e042a6f9c2be676f421935e026308de3303c Mon Sep 17 00:00:00 2001
-From: Sugar Zhang <sugar.zhang@rock-chips.com>
-Date: Fri, 3 Sep 2021 21:23:28 +0800
-Subject: [PATCH] ASoC: rockchip: pdm: Add support for path map
-
-This patch adds property 'rockchip,path-map' for path mapping.
-
-e.g.
-
-"rockchip,path-map = <3 2 1 0>" means the mapping as follows:
-
-  path0 <-- sdi3
-  path1 <-- sdi2
-  path2 <-- sdi1
-  path3 <-- sdi0
-
-Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
-Link: https://lore.kernel.org/r/1630675410-3354-5-git-send-email-sugar.zhang@rock-chips.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/rockchip/rockchip_pdm.c | 34 +++++++++++++++++++++++++++++++
- sound/soc/rockchip/rockchip_pdm.h |  3 +++
- 2 files changed, 37 insertions(+)
-
---- a/sound/soc/rockchip/rockchip_pdm.c
-+++ b/sound/soc/rockchip/rockchip_pdm.c
-@@ -20,6 +20,7 @@
- 
- #define PDM_DMA_BURST_SIZE	(8) /* size * width: 8*4 = 32 bytes */
- #define PDM_SIGNOFF_CLK_RATE	(100000000)
-+#define PDM_PATH_MAX		(4)
- 
- enum rk_pdm_version {
- 	RK_PDM_RK3229,
-@@ -539,8 +540,36 @@ static const struct of_device_id rockchi
- };
- MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
- 
-+static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node)
-+{
-+	unsigned int path[PDM_PATH_MAX];
-+	int cnt = 0, ret = 0, i = 0, val = 0, msk = 0;
-+
-+	cnt = of_count_phandle_with_args(node, "rockchip,path-map",
-+					 NULL);
-+	if (cnt != PDM_PATH_MAX)
-+		return cnt;
-+
-+	ret = of_property_read_u32_array(node, "rockchip,path-map",
-+					 path, cnt);
-+	if (ret)
-+		return ret;
-+
-+	for (i = 0; i < cnt; i++) {
-+		if (path[i] >= PDM_PATH_MAX)
-+			return -EINVAL;
-+		msk |= PDM_PATH_MASK(i);
-+		val |= PDM_PATH(i, path[i]);
-+	}
-+
-+	regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val);
-+
-+	return 0;
-+}
-+
- static int rockchip_pdm_probe(struct platform_device *pdev)
- {
-+	struct device_node *node = pdev->dev.of_node;
- 	const struct of_device_id *match;
- 	struct rk_pdm_dev *pdm;
- 	struct resource *res;
-@@ -606,6 +635,11 @@ static int rockchip_pdm_probe(struct pla
- 	}
- 
- 	rockchip_pdm_rxctrl(pdm, 0);
-+
-+	ret = rockchip_pdm_path_parse(pdm, node);
-+	if (ret != 0 && ret != -ENOENT)
-+		goto err_suspend;
-+
- 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
- 	if (ret) {
- 		dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
---- a/sound/soc/rockchip/rockchip_pdm.h
-+++ b/sound/soc/rockchip/rockchip_pdm.h
-@@ -53,6 +53,9 @@
- #define PDM_FD_DENOMINATOR_MSK	GENMASK(15, 0)
- 
- /* PDM CLK CTRL */
-+#define PDM_PATH_SHIFT(x)	(8 + (x) * 2)
-+#define PDM_PATH_MASK(x)	(0x3 << PDM_PATH_SHIFT(x))
-+#define PDM_PATH(x, v)		((v) << PDM_PATH_SHIFT(x))
- #define PDM_CLK_FD_RATIO_MSK	BIT(6)
- #define PDM_CLK_FD_RATIO_40	(0X0 << 6)
- #define PDM_CLK_FD_RATIO_35	BIT(6)

target/linux/rockchip/patches-5.15/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch

@@ -1,32 +0,0 @@
-From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Wed, 28 Jul 2021 14:00:31 -0400
-Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes
-
-Add the thermal and tsadc nodes to the rk3568 device tree.
-There are two sensors, one for the cpu, one for the gpu.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3568-pinctrl.dtsi     |  9 +++
- arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 70 +++++++++++++++++++
- 2 files changed, 79 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
-@@ -3108,4 +3108,13 @@
- 				<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
- 		};
- 	};
-+
-+	tsadc {
-+		/omit-if-no-ref/
-+		tsadc_pin: tsadc-pin {
-+			rockchip,pins =
-+				/* tsadc_pin */
-+				<0 RK_PA1 0 &pcfg_pull_none>;
-+		};
-+	};
- };

target/linux/rockchip/patches-5.15/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch

@@ -1,28 +0,0 @@
-From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001
-From: Johan Jonker <jbx6244@gmail.com>
-Date: Thu, 30 Sep 2021 13:05:16 +0200
-Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc
- node
-
-The tsadc node in rk356x.dtsi has more resets then currently supported
-by the rockchip_thermal.c driver, so use
-devm_reset_control_array_get() to reset them all.
-
-Signed-off-by: Johan Jonker <jbx6244@gmail.com>
-Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/rockchip_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/rockchip_thermal.c
-+++ b/drivers/thermal/rockchip_thermal.c
-@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct
- 	if (IS_ERR(thermal->regs))
- 		return PTR_ERR(thermal->regs);
- 
--	thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
-+	thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
- 	if (IS_ERR(thermal->reset)) {
- 		error = PTR_ERR(thermal->reset);
- 		dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);

target/linux/rockchip/patches-5.15/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch

@@ -1,27 +0,0 @@
-From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megous@megous.com>
-Date: Sun, 29 Aug 2021 04:51:53 +0200
-Subject: [PATCH] mfd: rk808: Add support for power off on RK817
-
-RK817 has a power-off bit in SYS_CFG3. Add support for powering
-off the PMIC.
-
-Signed-off-by: Ondrej Jirman <megous@megous.com>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/mfd/rk808.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mfd/rk808.c
-+++ b/drivers/mfd/rk808.c
-@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void)
- 		reg = RK808_DEVCTRL_REG,
- 		bit = DEV_OFF_RST;
- 		break;
-+	case RK817_ID:
-+		reg = RK817_SYS_CFG(3);
-+		bit = DEV_OFF;
-+		break;
- 	case RK818_ID:
- 		reg = RK818_DEVCTRL_REG;
- 		bit = DEV_OFF;

target/linux/rockchip/patches-5.15/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch

@@ -1,45 +0,0 @@
-From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Wed, 15 Dec 2021 16:02:47 -0500
-Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2
-
-New Rockchip devices have the usb phy nodes as standalone devices.
-These nodes have register nodes with #address_cells = 2, but only use 32
-bit addresses.
-
-Adjust the driver to check if the returned address is "0", and adjust
-the index in that case.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -1098,12 +1098,21 @@ static int rockchip_usb2phy_probe(struct
- 		rphy->usbgrf = NULL;
- 	}
- 
--	if (of_property_read_u32(np, "reg", &reg)) {
-+	if (of_property_read_u32_index(np, "reg", 0, &reg)) {
- 		dev_err(dev, "the reg property is not assigned in %pOFn node\n",
- 			np);
- 		return -EINVAL;
- 	}
- 
-+	/* support address_cells=2 */
-+	if (reg == 0) {
-+		if (of_property_read_u32_index(np, "reg", 1, &reg)) {
-+			dev_err(dev, "the reg property is not assigned in %pOFn node\n",
-+				np);
-+			return -EINVAL;
-+		}
-+	}
-+
- 	rphy->dev = dev;
- 	phy_cfgs = match->data;
- 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;

target/linux/rockchip/patches-5.15/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch

@@ -1,237 +0,0 @@
-From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Wed, 15 Dec 2021 16:02:49 -0500
-Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts
-
-The rk3568 usb2phy has a single muxed interrupt that handles all
-interrupts.
-Allow the driver to plug in only a single interrupt as necessary.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++-----
- 1 file changed, 119 insertions(+), 49 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
-  * @dcd_retries: The retry count used to track Data contact
-  *		 detection process.
-  * @edev: extcon device for notification registration
-+ * @irq: muxed interrupt for single irq configuration
-  * @phy_cfg: phy register configuration, assigned by driver data.
-  * @ports: phy port instance.
-  */
-@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
- 	enum power_supply_type	chg_type;
- 	u8			dcd_retries;
- 	struct extcon_dev	*edev;
-+	int			irq;
- 	const struct rockchip_usb2phy_cfg	*phy_cfg;
- 	struct rockchip_usb2phy_port	ports[USB2PHY_NUM_PORTS];
- };
-@@ -934,6 +936,102 @@ static irqreturn_t rockchip_usb2phy_otg_
- 		return IRQ_NONE;
- }
- 
-+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
-+{
-+	struct rockchip_usb2phy *rphy = data;
-+	struct rockchip_usb2phy_port *rport;
-+	irqreturn_t ret = IRQ_NONE;
-+	unsigned int index;
-+
-+	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
-+		rport = &rphy->ports[index];
-+		if (!rport->phy)
-+			continue;
-+
-+		/* Handle linestate irq for both otg port and host port */
-+		ret = rockchip_usb2phy_linestate_irq(irq, rport);
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
-+					  struct rockchip_usb2phy_port *rport,
-+					  struct device_node *child_np)
-+{
-+	int ret;
-+
-+	/*
-+	 * If the usb2 phy used combined irq for otg and host port,
-+	 * don't need to init otg and host port irq separately.
-+	 */
-+	if (rphy->irq > 0)
-+		return 0;
-+
-+	switch (rport->port_id) {
-+	case USB2PHY_PORT_HOST:
-+		rport->ls_irq = of_irq_get_byname(child_np, "linestate");
-+		if (rport->ls_irq < 0) {
-+			dev_err(rphy->dev, "no linestate irq provided\n");
-+			return rport->ls_irq;
-+		}
-+
-+		ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
-+						rockchip_usb2phy_linestate_irq,
-+						IRQF_ONESHOT,
-+						"rockchip_usb2phy", rport);
-+		if (ret) {
-+			dev_err(rphy->dev, "failed to request linestate irq handle\n");
-+			return ret;
-+		}
-+		break;
-+	case USB2PHY_PORT_OTG:
-+		/*
-+		 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
-+		 * interrupts muxed together, so probe the otg-mux interrupt first,
-+		 * if not found, then look for the regular interrupts one by one.
-+		 */
-+		rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
-+		if (rport->otg_mux_irq > 0) {
-+			ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
-+							NULL,
-+							rockchip_usb2phy_otg_mux_irq,
-+							IRQF_ONESHOT,
-+							"rockchip_usb2phy_otg",
-+							rport);
-+			if (ret) {
-+				dev_err(rphy->dev,
-+					"failed to request otg-mux irq handle\n");
-+				return ret;
-+			}
-+		} else {
-+			rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
-+			if (rport->bvalid_irq < 0) {
-+				dev_err(rphy->dev, "no vbus valid irq provided\n");
-+				ret = rport->bvalid_irq;
-+				return ret;
-+			}
-+
-+			ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
-+							NULL,
-+							rockchip_usb2phy_bvalid_irq,
-+							IRQF_ONESHOT,
-+							"rockchip_usb2phy_bvalid",
-+							rport);
-+			if (ret) {
-+				dev_err(rphy->dev,
-+					"failed to request otg-bvalid irq handle\n");
-+				return ret;
-+			}
-+		}
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
- static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
- 					   struct rockchip_usb2phy_port *rport,
- 					   struct device_node *child_np)
-@@ -947,18 +1045,9 @@ static int rockchip_usb2phy_host_port_in
- 	mutex_init(&rport->mutex);
- 	INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
- 
--	rport->ls_irq = of_irq_get_byname(child_np, "linestate");
--	if (rport->ls_irq < 0) {
--		dev_err(rphy->dev, "no linestate irq provided\n");
--		return rport->ls_irq;
--	}
--
--	ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
--					rockchip_usb2phy_linestate_irq,
--					IRQF_ONESHOT,
--					"rockchip_usb2phy", rport);
-+	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
- 	if (ret) {
--		dev_err(rphy->dev, "failed to request linestate irq handle\n");
-+		dev_err(rphy->dev, "failed to setup host irq\n");
- 		return ret;
- 	}
- 
-@@ -1007,44 +1096,10 @@ static int rockchip_usb2phy_otg_port_ini
- 	INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
- 	INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
- 
--	/*
--	 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
--	 * interrupts muxed together, so probe the otg-mux interrupt first,
--	 * if not found, then look for the regular interrupts one by one.
--	 */
--	rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
--	if (rport->otg_mux_irq > 0) {
--		ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
--						NULL,
--						rockchip_usb2phy_otg_mux_irq,
--						IRQF_ONESHOT,
--						"rockchip_usb2phy_otg",
--						rport);
--		if (ret) {
--			dev_err(rphy->dev,
--				"failed to request otg-mux irq handle\n");
--			goto out;
--		}
--	} else {
--		rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
--		if (rport->bvalid_irq < 0) {
--			dev_err(rphy->dev, "no vbus valid irq provided\n");
--			ret = rport->bvalid_irq;
--			goto out;
--		}
--
--		ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
--						NULL,
--						rockchip_usb2phy_bvalid_irq,
--						IRQF_ONESHOT,
--						"rockchip_usb2phy_bvalid",
--						rport);
--		if (ret) {
--			dev_err(rphy->dev,
--				"failed to request otg-bvalid irq handle\n");
--			goto out;
--		}
--	}
-+	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
-+	if (ret) {
-+		dev_err(rphy->dev, "failed to init irq for host port\n");
-+		goto out;
- 
- 	if (!IS_ERR(rphy->edev)) {
- 		rport->event_nb.notifier_call = rockchip_otg_event;
-@@ -1117,6 +1172,7 @@ static int rockchip_usb2phy_probe(struct
- 	phy_cfgs = match->data;
- 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;
- 	rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
-+	rphy->irq = platform_get_irq_optional(pdev, 0);
- 	platform_set_drvdata(pdev, rphy);
- 
- 	ret = rockchip_usb2phy_extcon_register(rphy);
-@@ -1196,6 +1252,20 @@ next_child:
- 	}
- 
- 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+
-+	if (rphy->irq > 0) {
-+		ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
-+						rockchip_usb2phy_irq,
-+						IRQF_ONESHOT,
-+						"rockchip_usb2phy",
-+						rphy);
-+		if (ret) {
-+			dev_err(rphy->dev,
-+				"failed to request usb2phy irq handle\n");
-+			goto put_child;
-+		}
-+	}
-+
- 	return PTR_ERR_OR_ZERO(provider);
- 
- put_child:

target/linux/rockchip/patches-5.15/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch

@@ -1,44 +0,0 @@
-From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Wed, 15 Dec 2021 16:02:48 -0500
-Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes
-
-New Rockchip devices have the usb2 phy devices as standalone nodes
-instead of children of the grf node.
-Allow the driver to find the grf node from a phandle.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++-----
- 1 file changed, 12 insertions(+), 5 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -1136,12 +1136,19 @@ static int rockchip_usb2phy_probe(struct
- 		return -EINVAL;
- 	}
- 
--	if (!dev->parent || !dev->parent->of_node)
--		return -EINVAL;
-+	if (!dev->parent || !dev->parent->of_node) {
-+		rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
-+		if (IS_ERR(rphy->grf)) {
-+			dev_err(dev, "failed to locate usbgrf\n");
-+			return PTR_ERR(rphy->grf);
-+		}
-+	}
- 
--	rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
--	if (IS_ERR(rphy->grf))
--		return PTR_ERR(rphy->grf);
-+	else {
-+		rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
-+			if (IS_ERR(rphy->grf))
-+				return PTR_ERR(rphy->grf);
-+	}
- 
- 	if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
- 		rphy->usbgrf =

target/linux/rockchip/patches-5.15/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch

@@ -1,104 +0,0 @@
-From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Wed, 15 Dec 2021 16:02:50 -0500
-Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support
-
-The rk3568 usb2phy is a standalone device with a single muxed interrupt.
-Add support for the registers to the usb2phy driver.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++
- 1 file changed, 65 insertions(+)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -1100,6 +1100,7 @@ static int rockchip_usb2phy_otg_port_ini
- 	if (ret) {
- 		dev_err(rphy->dev, "failed to init irq for host port\n");
- 		goto out;
-+	}
- 
- 	if (!IS_ERR(rphy->edev)) {
- 		rport->event_nb.notifier_call = rockchip_otg_event;
-@@ -1511,6 +1512,69 @@ static const struct rockchip_usb2phy_cfg
- 	{ /* sentinel */ }
- };
- 
-+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
-+	{
-+		.reg = 0xfe8a0000,
-+		.num_ports	= 2,
-+		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
-+				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },
-+				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },
-+				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
-+				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
-+				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
-+			},
-+			[USB2PHY_PORT_HOST] = {
-+				/* Select suspend control from controller */
-+				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },
-+				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
-+				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
-+			}
-+		},
-+		.chg_det = {
-+			.opmode		= { 0x0000, 3, 0, 5, 1 },
-+			.cp_det		= { 0x00c0, 24, 24, 0, 1 },
-+			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },
-+			.dp_det		= { 0x00c0, 25, 25, 0, 1 },
-+			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },
-+			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },
-+			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },
-+			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },
-+			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },
-+			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },
-+		},
-+	},
-+	{
-+		.reg = 0xfe8b0000,
-+		.num_ports	= 2,
-+		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
-+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
-+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
-+			},
-+			[USB2PHY_PORT_HOST] = {
-+				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
-+				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
-+				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
-+			}
-+		},
-+	},
-+	{ /* sentinel */ }
-+};
-+
- static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
- 	{
- 		.reg = 0x100,
-@@ -1560,6 +1624,7 @@ static const struct of_device_id rockchi
- 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
- 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
- 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
-+	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
- 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
- 	{}
- };

target/linux/rockchip/patches-5.15/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch

@@ -1,44 +0,0 @@
-From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001
-From: Sascha Hauer <s.hauer@pengutronix.de>
-Date: Wed, 26 Jan 2022 15:55:33 +0100
-Subject: [PATCH] clk: rockchip: Add more PLL rates for rk3568
-
-This adds a few more PLL settings needed for some standard resolutions:
-
-297MHz    3840x2160-30.00
-241.5MHz  2560x1440-59.95
-135MHz    1280x1024-75.02
-119MHz    1680x1050-59.88
-108MHz    1280x1024-60.02
- 78.75MHz 1024x768-75.03
-
-Changes since v3:
-- new patch
-
-Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/clk/rockchip/clk-rk3568.c
-+++ b/drivers/clk/rockchip/clk-rk3568.c
-@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk
- 	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
- 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
- 	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
-+	RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
-+	RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
- 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
- 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
- 	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
-+	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
-+	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
-+	RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
- 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
- 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
-+	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
- 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
- 	{ /* sentinel */ },
- };

target/linux/rockchip/patches-5.15/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch

@@ -1,52 +0,0 @@
-From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001
-From: Sascha Hauer <s.hauer@pengutronix.de>
-Date: Wed, 26 Jan 2022 15:55:47 +0100
-Subject: [PATCH] clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference
- clock on rk3568
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-On the rk3568 we have this (simplified) situation:
-
- .--------.     .-----.    .---------.
--| hpll   |--.--| /n  |----|dclk_vop0|-
- `--------´  |  `-----´    `---------´
-             |  .-----.    .---------.
-             `--| /m  |----|dclk_vop1|-
-             |  `-----´    `---------´
-             |             .---------.
-             `-------------|hdmi_ref |-
-                           `---------´
-
-For the HDMI to work the HDMI reference clock needs to be the same as the
-pixel clock which means the dividers have be set to one. The last patch removed
-the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not
-changed on pixel clock changes. In order to allow the HDMI controller to
-set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the
-HDMI reference clock. With this the flow becomes:
-
-1) HDMI controller driver sets the rate to its pixel clock which means
-   hpll is set to the pixel clock
-2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change
-   the hpll clock anymore this means only the divider is adjusted to the
-   desired value of dividing by one.
-
-Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3568.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/rockchip/clk-rk3568.c
-+++ b/drivers/clk/rockchip/clk-rk3568.c
-@@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568
- 			RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
- 	GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
- 			RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
--	MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
-+	MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
- 			RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
- };
- 

target/linux/rockchip/patches-5.15/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch

@@ -1,49 +0,0 @@
-From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001
-From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-Date: Tue, 8 Feb 2022 17:13:25 +0800
-Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
-
-This patch implements a combo phy driver for Rockchip SoCs
-with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
-sata-phy or sgmii-phy.
-
-Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-Signed-off-by: Johan Jonker <jbx6244@gmail.com>
-Tested-by: Peter Geis <pgwipeout@gmail.com>
-Tested-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/Kconfig                  |   8 +
- drivers/phy/rockchip/Makefile                 |   1 +
- .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
- 3 files changed, 590 insertions(+)
- create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-
---- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
- 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
- 	  Innosilicon IP block.
- 
-+config PHY_ROCKCHIP_NANENG_COMBO_PHY
-+	tristate "Rockchip NANENG COMBO PHY Driver"
-+	depends on ARCH_ROCKCHIP && OF
-+	select GENERIC_PHY
-+	help
-+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
-+	  combo PHY with NaNeng IP block.
-+
- config PHY_ROCKCHIP_PCIE
- 	tristate "Rockchip PCIe PHY Driver"
- 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
---- a/drivers/phy/rockchip/Makefile
-+++ b/drivers/phy/rockchip/Makefile
-@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
-+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
- obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
- obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o

target/linux/rockchip/patches-5.15/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch

@@ -1,54 +0,0 @@
-From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Sat, 5 Mar 2022 16:58:34 -0500
-Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers
-
-Host drivers may not be able to support frequencies as low as dw-mmc
-supports. Unfortunately f_min isn't available when the drv_data->init
-function is called, as the mmc_host struct hasn't been set up yet.
-
-Support the host drivers saving the requested minimum frequency, so we
-can later set f_min when it is available.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/dw_mmc.c | 7 ++++++-
- drivers/mmc/host/dw_mmc.h | 2 ++
- 2 files changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/dw_mmc.c
-+++ b/drivers/mmc/host/dw_mmc.c
-@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct
- 	if (host->pdata->caps2)
- 		mmc->caps2 = host->pdata->caps2;
- 
--	mmc->f_min = DW_MCI_FREQ_MIN;
-+	/* if host has set a minimum_freq, we should respect it */
-+	if (host->minimum_speed)
-+		mmc->f_min = host->minimum_speed;
-+	else
-+		mmc->f_min = DW_MCI_FREQ_MIN;
-+
- 	if (!mmc->f_max)
- 		mmc->f_max = DW_MCI_FREQ_MAX;
- 
---- a/drivers/mmc/host/dw_mmc.h
-+++ b/drivers/mmc/host/dw_mmc.h
-@@ -99,6 +99,7 @@ struct dw_mci_dma_slave {
-  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
-  *	rate and timeout calculations.
-  * @current_speed: Configured rate of the controller.
-+ * @minimum_speed: Stored minimum rate of the controller.
-  * @fifoth_val: The value of FIFOTH register.
-  * @verid: Denote Version ID.
-  * @dev: Device associated with the MMC controller.
-@@ -200,6 +201,7 @@ struct dw_mci {
- 
- 	u32			bus_hz;
- 	u32			current_speed;
-+	u32			minimum_speed;
- 	u32			fifoth_val;
- 	u16			verid;
- 	struct device		*dev;

target/linux/rockchip/patches-5.15/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch

@@ -1,79 +0,0 @@
-From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Sat, 5 Mar 2022 16:58:35 -0500
-Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
-
-The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
-hardware supports. This leads to a situation during card initialization
-where the clock is set lower than the clock driver can support. The
-dw-mmc-rockchip driver spews errors when this happens.
-For normal operation this only happens a few times during boot, but when
-cd-broken is enabled (in cases such as the SoQuartz module) this fires
-multiple times each poll cycle.
-
-Fix this by testing the lowest possible frequency that the clock driver
-can support which is within the mmc specification. Divide that rate by
-the internal divider and set f_min to this.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
- 1 file changed, 23 insertions(+), 4 deletions(-)
-
---- a/drivers/mmc/host/dw_mmc-rockchip.c
-+++ b/drivers/mmc/host/dw_mmc-rockchip.c
-@@ -15,7 +15,9 @@
- #include "dw_mmc.h"
- #include "dw_mmc-pltfm.h"
- 
--#define RK3288_CLKGEN_DIV       2
-+#define RK3288_CLKGEN_DIV	2
-+
-+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
- 
- struct dw_mci_rockchip_priv_data {
- 	struct clk		*drv_clk;
-@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct
- 
- 	ret = clk_set_rate(host->ciu_clk, cclkin);
- 	if (ret)
--		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
-+		dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
- 
- 	bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
- 	if (bus_hz != host->bus_hz) {
-@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct
- 
- static int dw_mci_rockchip_init(struct dw_mci *host)
- {
-+	int ret, i;
-+
- 	/* It is slot 8 on Rockchip SoCs */
- 	host->sdio_id0 = 8;
- 
--	if (of_device_is_compatible(host->dev->of_node,
--				    "rockchip,rk3288-dw-mshc"))
-+	if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
- 		host->bus_hz /= RK3288_CLKGEN_DIV;
- 
-+		/* clock driver will fail if the clock is less than the lowest source clock
-+		 * divided by the internal clock divider. Test for the lowest available
-+		 * clock and set the minimum freq to clock / clock divider.
-+		 */
-+
-+		for (i = 0; i < ARRAY_SIZE(freqs); i++) {
-+			ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
-+			if (ret > 0) {
-+				host->minimum_speed = ret / RK3288_CLKGEN_DIV;
-+				break;
-+			}
-+		}
-+		if (ret < 0)
-+			dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
-+	}
-+
- 	return 0;
- }
- 

target/linux/rockchip/patches-5.15/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch

@@ -1,110 +0,0 @@
-From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Tue, 8 Feb 2022 14:40:23 -0500
-Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c
-
-This adds reboot support to the rk808 pmic driver and enables it for
-the rk809 and rk817 devices.
-This only enables if the rockchip,system-power-controller flag is set.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com
----
- drivers/mfd/rk808.c       | 44 +++++++++++++++++++++++++++++++++++++++
- include/linux/mfd/rk808.h |  1 +
- 2 files changed, 45 insertions(+)
-
---- a/drivers/mfd/rk808.c
-+++ b/drivers/mfd/rk808.c
-@@ -19,6 +19,7 @@
- #include <linux/module.h>
- #include <linux/of_device.h>
- #include <linux/regmap.h>
-+#include <linux/reboot.h>
- 
- struct rk808_reg_data {
- 	int addr;
-@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void)
- 		reg = RK808_DEVCTRL_REG,
- 		bit = DEV_OFF_RST;
- 		break;
-+	case RK809_ID:
- 	case RK817_ID:
- 		reg = RK817_SYS_CFG(3);
- 		bit = DEV_OFF;
-@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void)
- 		dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
- }
- 
-+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
-+{
-+	struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
-+	unsigned int reg, bit;
-+	int ret;
-+
-+	switch (rk808->variant) {
-+	case RK809_ID:
-+	case RK817_ID:
-+		reg = RK817_SYS_CFG(3);
-+		bit = DEV_RST;
-+		break;
-+
-+	default:
-+		return NOTIFY_DONE;
-+	}
-+	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
-+	if (ret)
-+		dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
-+
-+	return NOTIFY_DONE;
-+}
-+
-+static struct notifier_block rk808_restart_handler = {
-+	.notifier_call = rk808_restart_notify,
-+	.priority = 192,
-+};
-+
- static void rk8xx_shutdown(struct i2c_client *client)
- {
- 	struct rk808 *rk808 = i2c_get_clientdata(client);
-@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client
- 	if (of_property_read_bool(np, "rockchip,system-power-controller")) {
- 		rk808_i2c_client = client;
- 		pm_power_off = rk808_pm_power_off;
-+
-+		switch (rk808->variant) {
-+		case RK809_ID:
-+		case RK817_ID:
-+			ret = register_restart_handler(&rk808_restart_handler);
-+			if (ret)
-+				dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
-+			break;
-+		default:
-+			dev_dbg(&client->dev, "pmic controlled board reset not supported\n");
-+			break;
-+		}
- 	}
- 
- 	return 0;
-@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_clien
- 	if (pm_power_off == rk808_pm_power_off)
- 		pm_power_off = NULL;
- 
-+	unregister_restart_handler(&rk808_restart_handler);
-+
- 	return 0;
- }
- 
---- a/include/linux/mfd/rk808.h
-+++ b/include/linux/mfd/rk808.h
-@@ -373,6 +373,7 @@ enum rk805_reg {
- #define SWITCH2_EN	BIT(6)
- #define SWITCH1_EN	BIT(5)
- #define DEV_OFF_RST	BIT(3)
-+#define DEV_RST		BIT(2)
- #define DEV_OFF		BIT(0)
- #define RTC_STOP	BIT(0)
- 

target/linux/rockchip/patches-5.15/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch

@@ -1,51 +0,0 @@
-From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Fri, 8 Apr 2022 11:12:34 -0400
-Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566
-
-The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
-the combophy as the clock source. As combophy0 doesn't exist on rk3566,
-we need to set the clock source to the usb2 phy instead.
-
-Add handling to the grf driver to handle this on boot.
-
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
-Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/soc/rockchip/grf.c
-+++ b/drivers/soc/rockchip/grf.c
-@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk
- 	.num_values = ARRAY_SIZE(rk3399_defaults),
- };
- 
-+#define RK3566_GRF_USB3OTG0_CON1	0x0104
-+
-+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
-+	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
-+	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
-+	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
-+};
-+
-+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
-+	.values = rk3566_defaults,
-+	.num_values = ARRAY_SIZE(rk3566_defaults),
-+};
-+
-+
- static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
- 	{
- 		.compatible = "rockchip,rk3036-grf",
-@@ -130,6 +144,9 @@ static const struct of_device_id rockchi
- 	}, {
- 		.compatible = "rockchip,rk3399-grf",
- 		.data = (void *)&rk3399_grf,
-+	}, {
-+		.compatible = "rockchip,rk3566-pipe-grf",
-+		.data = (void *)&rk3566_pipegrf,
- 	},
- 	{ /* sentinel */ },
- };

target/linux/rockchip/patches-5.15/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch

@@ -1,71 +0,0 @@
-From 5f6bfab6da6531238e899fdf29efd6d0185adc3e Mon Sep 17 00:00:00 2001
-From: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
-Date: Mon, 14 Feb 2022 21:29:53 +0000
-Subject: [PATCH] media: hantro: Add support for Hantro G1 on RK356x
-
-RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8
-video formats.
-
-This patch adds support for RK356x family in existing Hantro
-video decoder kernel driver.
-
-Tested on [1] with FFmpeg v4l2_request code taken from [2]
-with MPEG2, H.642 and VP8 samples with results [3].
-
-[1] https://github.com/warpme/minimyth2
-[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
-[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt
-
-Signed-off-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
-Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
----
- drivers/staging/media/hantro/hantro_drv.c      |  1 +
- drivers/staging/media/hantro/hantro_hw.h       |  1 +
- drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 ++++++++++++++
- 3 files changed, 16 insertions(+)
-
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -588,6 +588,7 @@ static const struct of_device_id of_hant
- 	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
- 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
- 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
-+	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
- #endif
- #ifdef CONFIG_VIDEO_HANTRO_IMX8M
- 	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -215,6 +215,7 @@ extern const struct hantro_variant rk306
- extern const struct hantro_variant rk3288_vpu_variant;
- extern const struct hantro_variant rk3328_vpu_variant;
- extern const struct hantro_variant rk3399_vpu_variant;
-+extern const struct hantro_variant rk3568_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
- 
- extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -551,6 +551,20 @@ const struct hantro_variant rk3399_vpu_v
- 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
- };
- 
-+const struct hantro_variant rk3568_vpu_variant = {
-+	.dec_offset = 0x400,
-+	.dec_fmts = rk3399_vpu_dec_fmts,
-+	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
-+	.codec = HANTRO_MPEG2_DECODER |
-+		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
-+	.codec_ops = rk3399_vpu_codec_ops,
-+	.irqs = rockchip_vdpu2_irqs,
-+	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
-+	.init = rockchip_vpu_hw_init,
-+	.clk_names = rockchip_vpu_clk_names,
-+	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
-+};
-+
- const struct hantro_variant px30_vpu_variant = {
- 	.enc_offset = 0x0,
- 	.enc_fmts = rockchip_vpu_enc_fmts,

target/linux/rockchip/patches-5.15/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch

@@ -1,42 +0,0 @@
-From 6a98df08ccd55e87947d253b19925691763e755c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 13 Apr 2022 22:22:52 -0500
-Subject: [PATCH] phy: rockchip-inno-usb2: Fix muxed interrupt support
-
-This commit fixes two issues with the muxed interrupt handler. First,
-the OTG port has the "bvalid" interrupt enabled, not "linestate". Since
-only the linestate interrupt was handled, and not the bvalid interrupt,
-plugging in a cable to the OTG port caused an interrupt storm.
-
-Second, the return values from the individual port IRQ handlers need to
-be OR-ed together. Otherwise, the lack of an interrupt from the last
-port would cause the handler to erroneously return IRQ_NONE.
-
-Fixes: ed2b5a8e6b98 ("phy: phy-rockchip-inno-usb2: support muxed interrupts")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20220414032258.40984-2-samuel@sholland.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -948,8 +948,14 @@ static irqreturn_t rockchip_usb2phy_irq(
- 		if (!rport->phy)
- 			continue;
- 
--		/* Handle linestate irq for both otg port and host port */
--		ret = rockchip_usb2phy_linestate_irq(irq, rport);
-+		switch (rport->port_id) {
-+		case USB2PHY_PORT_OTG:
-+			ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
-+			break;
-+		case USB2PHY_PORT_HOST:
-+			ret |= rockchip_usb2phy_linestate_irq(irq, rport);
-+			break;
-+		}
- 	}
- 
- 	return ret;

target/linux/rockchip/patches-5.15/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch

@@ -1,37 +0,0 @@
-From 656f7fcb1272df590e10cb82e07cd2b79bbf60d1 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 13 Apr 2022 22:22:53 -0500
-Subject: [PATCH] phy: rockchip-inno-usb2: Do not check bvalid twice
-
-The bvalid interrupt handler already checks bvalid status. The muxed IRQ
-handler just needs to call the other handler (plus any other handlers
-that will be added).
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20220414032258.40984-3-samuel@sholland.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++------
- 1 file changed, 4 insertions(+), 6 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -927,13 +927,11 @@ static irqreturn_t rockchip_usb2phy_bval
- 
- static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
- {
--	struct rockchip_usb2phy_port *rport = data;
--	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
-+	irqreturn_t ret = IRQ_NONE;
- 
--	if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
--		return rockchip_usb2phy_bvalid_irq(irq, data);
--	else
--		return IRQ_NONE;
-+	ret |= rockchip_usb2phy_bvalid_irq(irq, data);
-+
-+	return ret;
- }
- 
- static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)

target/linux/rockchip/patches-5.15/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch

@@ -1,31 +0,0 @@
-From 5a709a46e4270a6130877c052260d9a6d14ac685 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 13 Apr 2022 22:22:54 -0500
-Subject: [PATCH] phy: rockchip-inno-usb2: Do not lock in bvalid IRQ handler
-
-Clearing the IRQ is atomic, so there is no need to hold the mutex.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Link: https://lore.kernel.org/r/20220414032258.40984-4-samuel@sholland.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ----
- 1 file changed, 4 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -913,13 +913,9 @@ static irqreturn_t rockchip_usb2phy_bval
- 	if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
- 		return IRQ_NONE;
- 
--	mutex_lock(&rport->mutex);
--
- 	/* clear bvalid detect irq pending status */
- 	property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
- 
--	mutex_unlock(&rport->mutex);
--
- 	rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
- 
- 	return IRQ_HANDLED;