From 22d08ddd3d23e4ad3b98b943089d03af832c3022 Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Mon, 1 Aug 2022 16:02:39 +0800 Subject: [PATCH] rockchip: revert to origin defaults The current target code is too chaotic, the patches are messy and disorderly, and there are still many duplicate code. Pack it back to half a year ago. --- package/boot/uboot-rockchip/Makefile | 70 +- ...016-uboot-add-FastRhino-R66S-support.patch | 92 - ...ip-rk3568-Add-support-for-Station-P2.patch | 78 - ...8-Add-support-for-EmbedFire-DoorNet1.patch | 549 -- ...28-Add-support-for-Orangepi-R1-Plus.patch} | 0 ...dd-support-for-Orangepi-R1-Plus-LTS.patch} | 0 ...9-Add-support-for-EmbedFire-DoorNet2.patch | 984 -- ...dd-support-for-FriendlyARM-NanoPi-R.patch} | 0 ...Add-support-for-FriendlyARM-NanoPi-R.patch | 110 + .../patches/900-arm-boot-add-dts-files.patch | 11 - .../src/arch/arm/dts/rk3399-nanopi-r4se.dts | 135 - .../configs/fastrhino-r66s-rk3568_defconfig | 97 - .../src/configs/nanopi-r4se-rk3399_defconfig | 65 - target/linux/rockchip/Makefile | 5 +- .../armv8/base-files/etc/board.d/01_leds | 10 +- .../armv8/base-files/etc/board.d/02_network | 28 +- .../etc/hotplug.d/net/40-net-smp-affinity | 21 +- target/linux/rockchip/armv8/config-5.10 | 1 - target/linux/rockchip/armv8/config-5.19 | 841 -- target/linux/rockchip/armv8/config-5.4 | 1 - .../arch/arm64/boot/dts/rockchip/rk3566.dtsi | 35 - .../boot/dts/rockchip/rk3568-nanopi-r5s.dts} | 370 +- .../arch/arm64/boot/dts/rockchip/rk3568.dtsi | 143 - .../arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1706 ---- .../gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ------ .../gpu/drm/rockchip/rockchip_drm_vop2.h | 477 - .../gpu/drm/rockchip/rockchip_vop2_reg.c | 281 - .../rockchip/phy-rockchip-naneng-combphy.c | 581 -- .../include/dt-bindings/soc/rockchip,vop2.h | 14 - .../boot/dts/rockchip/rk3328-doornet1.dts | 495 - .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 47 - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 70 - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 39 - .../boot/dts/rockchip/rk3399-doornet2.dts | 113 - .../boot/dts/rockchip/rk3399-doornet2.dtsi | 636 -- .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 152 - .../boot/dts/rockchip/rk3399-rock-pi-4.dts | 19 - .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 825 -- .../arm64/boot/dts/rockchip/rk3568-r66s.dts | 541 -- .../boot/dts/rockchip/rk3568-rock-3a.dts | 617 -- .../boot/dts/rockchip/rk3568-station-p2.dts | 787 -- .../bindings/phy/phy-rockchip-inno-usb3.yaml | 157 - .../devicetree/bindings/rng/rockchip,rng.txt | 45 - ...g.dtsi => rk3328-dram-default-timing.dtsi} | 0 .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 49 - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 66 - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 39 - .../boot/dts/rockchip/rk3399-doornet2-4gb.dts | 113 - .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 825 -- .../arm64/boot/dts/rockchip/rk3568-r66s.dts | 542 -- .../boot/dts/rockchip/rk3568-station-p2.dts | 787 -- .../drivers/char/hw_random/rockchip-rng.c | 249 +- .../files/drivers/net/phy/motorcomm.c | 414 + .../files/drivers/phy/rockchip/p3phy.fw | 8192 ----------------- .../phy/rockchip/phy-rockchip-inno-usb3.c | 1175 --- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 343 - .../files/include/linux/motorcomm_phy.h | 73 + .../rockchip/files/include/linux/phy/pcie.h | 12 - target/linux/rockchip/image/armv8.mk | 54 +- target/linux/rockchip/modules.mk | 30 +- ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 11 +- ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 2 +- ...d-OF-node-for-pcie-eth-on-NanoPi-R4S.patch | 2 +- ...-initial-signal-voltage-on-power-off.patch | 2 +- .../108-nanopi-r4s-sd-signalling.patch} | 0 ...8-Add-support-for-EmbedFire-DoorNet1.patch | 434 - ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 79 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 10 +- ...support-for-FriendlyARM-NanoPi-Neo3.patch} | 6 +- ...9-Add-support-for-EmbedFire-DoorNet2.patch | 768 -- ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 101 - ...Add-driver-for-Motorcomm-YT85xx-PHYs.patch | 418 - ...Add-driver-for-Motorcomm-YT8531-PHYs.patch | 475 - ...anopi-r2s-add-rk3328-dmc-relate-node.patch | 2 +- ...-add-driver-for-Rockchip-USB-3.0-PHY.patch | 52 - ...-doornet1-add-rk3328-dmc-relate-node.patch | 124 - ...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 193 - ...chip-rk3399-overclock-to-2.2-1.8-GHz.patch | 46 + ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 11 +- ...-rockchip-Add-support-for-rv1126-pdm.patch | 155 - ...kchip-pdm-Add-support-for-rk3568-pdm.patch | 26 - ...ockchip-pdm-Add-support-for-path-map.patch | 95 - ...-dts-rockchip-add-rk3568-tsadc-nodes.patch | 32 - ...hip_thermal-Allow-more-resets-for-ts.patch | 28 - ...8-Add-support-for-power-off-on-RK817.patch | 27 - ...ip-inno-usb2-support-address_cells-2.patch | 45 - ...p-inno-usb2-support-muxed-interrupts.patch | 237 - ...no-usb2-support-standalone-phy-nodes.patch | 44 - ...ockchip-inno-usb2-add-rk3568-support.patch | 104 - ...ckchip-Add-more-PLL-rates-for-rk3568.patch | 44 - ...SET_RATE_PARENT-to-the-HDMI-referenc.patch | 52 - ...chip-add-naneng-combo-phy-for-RK3568.patch | 49 - ...port-setting-f_min-from-host-drivers.patch | 54 - ...hip-Fix-handling-invalid-clock-rates.patch | 79 - ...-rk808-Add-reboot-support-to-rk808.c.patch | 110 - ...c-rockchip-set-dwc3-clock-for-rk3566.patch | 51 - ...-Add-support-for-Hantro-G1-on-RK356x.patch | 71 - ...nno-usb2-Fix-muxed-interrupt-support.patch | 42 - ...-inno-usb2-Do-not-check-bvalid-twice.patch | 37 - ...b2-Do-not-lock-in-bvalid-IRQ-handler.patch | 31 - ...b2-Support-multi-bit-mask-properties.patch | 29 - ...chip-inno-usb2-Handle-bvalid-falling.patch | 58 - ...phy-rockchip-inno-usb2-Handle-ID-IRQ.patch | 230 - ...p-Mark-hclk_vo-as-critical-on-rk3568.patch | 66 - ...ed-drm_encoder-into-rockchip_decoder.patch | 601 -- ...crtc_endpoint_id-to-rockchip_encoder.patch | 88 - ...rename-vpll-clock-to-reference-clock.patch | 93 - ...-rockchip-dw_hdmi-add-rk3568-support.patch | 84 - ...ckchip-dw_hdmi-add-regulator-support.patch | 109 - ...rm-rockchip-Make-VOP-driver-optional.patch | 65 - ...2-v5.19-drm-rockchip-Add-VOP2-driver.patch | 149 - ...kchip-dwc-Reset-core-at-driver-probe.patch | 72 - ...hip-dwc-Add-legacy-interrupt-support.patch | 163 - ...ockchip-vop2-unlock-on-error-path-in.patch | 27 - ...antro-Add-support-for-RK356x-encoder.patch | 96 - ...no-usb2-Ignore-OTG-IRQs-in-host-mode.patch | 36 - ...-Fix-RK3399-H.264-format-advertising.patch | 126 - ...sb2-Prevent-incorrect-error-on-probe.patch | 27 - ...hip-inno-usb2-Sync-initial-otg-state.patch | 33 - ...v6.0-arm64-enable-THP_SWAP-for-arm64.patch | 123 - .../patches-5.15/105-rockchip-rock-pi-4.patch | 18 + ...d-OF-node-for-pcie-eth-on-NanoPi-R4S.patch | 4 +- .../108-phy-rockchip-Support-PCIe-v3.patch | 106 - .../patches-5.15/108-rockchip-rock-pi-4.patch | 10 - ...ts-rockchip-rk3568-Add-PCIe-v3-nodes.patch | 174 - ...328-Add-support-for-OrangePi-R1-Plus.patch | 52 + ...8-Add-support-for-EmbedFire-DoorNet1.patch | 509 - ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 79 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 64 + ...support-for-FriendlyARM-NanoPi-Neo3.patch} | 18 + ...9-Add-support-for-EmbedFire-DoorNet2.patch | 768 -- ...rk3399-add-support-for-GuangMiao-G4C.patch | 10 - ...ip-add-hardware-random-number-genera.patch | 19 - ...ip-add-devfreq-driver-for-rk3328-dmc.patch | 4 +- ...anopi-r2s-add-rk3328-dmc-relate-node.patch | 10 +- .../900-arm64-boot-add-dts-files.patch | 24 - ...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 193 - ...chip-rk3399-overclock-to-2.2-1.8-GHz.patch | 46 + ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 31 - ...-rockchip-add-Quartz64-A-fan-pinctrl.patch | 39 - ...ip-enable-sdr-104-for-sdmmc-on-Quart.patch | 32 - ...ip-enable-sfc-controller-on-Quartz64.patch | 41 - ...ckchip-Add-rk3568-PCIe2x1-controller.patch | 74 - ...ip-Enable-PCIe-controller-on-quartz6.patch | 80 - ...ip-add-pine64-touch-panel-display-to.patch | 131 - ...4-dts-rockchip-rk356x-Add-VOP2-nodes.patch | 106 - ...4-dts-rockchip-rk356x-Add-HDMI-nodes.patch | 56 - ...chip-rk3568-evb-Enable-VOP2-and-hdmi.patch | 90 - ...ip-enable-vop2-and-hdmi-tx-on-quartz.patch | 91 - ...ts-rockchip-adjust-whitespace-around.patch | 105 - ...kchip-Add-HDMI-audio-nodes-to-rk356x.patch | 67 - ...chip-Enable-HDMI-audio-on-Quartz64-A.patch | 40 - ...4-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch | 53 - ...ip-set-display-regulators-to-always-.patch | 44 - ...ip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch | 90 - ...chip-Enable-HDMI-audio-on-BPI-R2-Pro.patch | 40 - ...ip-configure-thermal-shutdown-for-BP.patch | 26 - ...ockchip-enable-the-gpu-on-BPI-R2-Pro.patch | 28 - ...ip-Add-missing-space-around-regulato.patch | 31 - ...s-rockchip-add-ROCK-Pi-S-DTS-support.patch | 245 - ...kchip-rock-pi-s-add-more-peripherals.patch | 100 - ...ip-align-gpio-key-node-names-with-dt.patch | 369 - ...ip-enable-hdmi-tx-audio-on-rk3568-ev.patch | 40 - ...chip-enable-hdmi-tx-audio-on-rock-3a.patch | 39 - ...ip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch | 72 - ...t7530-rework-mt7530_hw_vlan_-add-del.patch | 87 - ...et-dsa-mt7530-rework-mt753-01-_setup.patch | 75 - ...et-cpu-port-via-dp-cpu_dp-instead-of.patch | 117 - ...-Kconfig-dependencies-for-display-po.patch | 46 - ...ove-unneeded-semicolon-from-vop2-dri.patch | 29 - ...ix-spelling-mistake-aligened-aligned.patch | 26 - ...-drm-Drop-drm_edid.h-from-drm_crtc.h.patch | 569 -- ...-Don-t-crash-for-invalid-duplicate_s.patch | 33 - ...o-usb2-Prevent-incorrect-error-on-pr.patch | 28 - ...indings-phy-rockchip-add-PCIe-v3-phy.patch | 97 - ...ings-soc-grf-add-pcie30-phy-pipe-grf.patch | 28 - .../0046-phy-rockchip-Support-PCIe-v3.patch | 55 - ...ts-rockchip-rk3568-Add-PCIe-v3-nodes.patch | 144 - ...chip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch | 127 - ...56x-fix-upper-usb-port-on-BPI-R2-Pro.patch | 28 - .../0051-rockchip-add-pci3-for-rock3-a.patch | 211 - ...FriendlyElec-NanoPi-R5S-rk3568-board.patch | 18 - ...-rockchip-use-system-LED-for-OpenWrt.patch | 31 - ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 24 - ...add-support-for-FriendlyARM-NanoPi-N.patch | 397 - ...add-driver-for-Motorcomm-YT85xx+PHYs.patch | 2243 ----- ...ip-add-hardware-random-number-genera.patch | 69 - ...ip-add-devfreq-driver-for-rk3328-dmc.patch | 44 - ...setting-ddr-clock-via-SIP-Version-2-.patch | 210 - ...eq-rockchip-dfi-add-more-soc-support.patch | 662 -- ...m64-dts-rockchip-rk3328-add-dfi-node.patch | 27 - ...anopi-r2s-add-rk3328-dmc-relate-node.patch | 126 - ...-initial-signal-voltage-on-power-off.patch | 35 - .../0900-arm-boot-add-dts-files.patch | 42 - ...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 21 - ...ip-add-more-cpu-operating-points-for.patch | 44 - ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 11 +- ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 2 +- ...d-OF-node-for-pcie-eth-on-NanoPi-R4S.patch | 4 +- .../107-nanopi-r4s-sd-signalling.patch | 26 + ...8-Add-support-for-EmbedFire-DoorNet1.patch | 433 - ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 79 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 10 +- ...support-for-FriendlyARM-NanoPi-Neo3.patch} | 6 +- ...9-Add-support-for-EmbedFire-DoorNet2.patch | 768 -- ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 94 - ...Add-driver-for-Motorcomm-YT85xx-PHYs.patch | 418 - ...Add-driver-for-Motorcomm-YT8531-PHYs.patch | 467 - ...ip-add-devfreq-driver-for-rk3328-dmc.patch | 6 +- ...eq-rockchip-dfi-add-more-soc-support.patch | 18 +- ...anopi-r2s-add-rk3328-dmc-relate-node.patch | 2 +- ...-add-driver-for-Rockchip-USB-3.0-PHY.patch | 52 - ...-doornet1-add-rk3328-dmc-relate-node.patch | 124 - ...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 194 - ...chip-rk3399-overclock-to-2.2-1.8-GHz.patch | 46 + 215 files changed, 1483 insertions(+), 44579 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch delete mode 100644 package/boot/uboot-rockchip/patches/017-rockchip-rk3568-Add-support-for-Station-P2.patch delete mode 100644 package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch rename package/boot/uboot-rockchip/patches/{304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch => 302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch} (100%) rename package/boot/uboot-rockchip/patches/{306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch => 303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch} (100%) delete mode 100644 package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch rename package/boot/uboot-rockchip/patches/{305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch => 304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch} (100%) create mode 100644 package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch delete mode 100644 package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch delete mode 100644 package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts delete mode 100644 package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig delete mode 100644 package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig delete mode 100644 target/linux/rockchip/armv8/config-5.19 delete mode 100644 target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3566.dtsi rename target/linux/rockchip/{files/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts => files-5.15/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts} (67%) delete mode 100644 target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi delete mode 100644 target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk356x.dtsi delete mode 100644 target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c delete mode 100644 target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h delete mode 100644 target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c delete mode 100644 target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c delete mode 100644 target/linux/rockchip/files-5.15/include/dt-bindings/soc/rockchip,vop2.h delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts delete mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts delete mode 100644 target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml delete mode 100644 target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt rename target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/{rk3328-dram-nanopi2-timing.dtsi => rk3328-dram-default-timing.dtsi} (100%) delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-doornet2-4gb.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts create mode 100644 target/linux/rockchip/files/drivers/net/phy/motorcomm.c delete mode 100644 target/linux/rockchip/files/drivers/phy/rockchip/p3phy.fw delete mode 100644 target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-inno-usb3.c delete mode 100644 target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 target/linux/rockchip/files/include/linux/motorcomm_phy.h delete mode 100644 target/linux/rockchip/files/include/linux/phy/pcie.h rename target/linux/rockchip/{patches-5.19/0105-nanopi-r4s-sd-signalling.patch => patches-5.10/108-nanopi-r4s-sd-signalling.patch} (100%) delete mode 100644 target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch create mode 100644 target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch rename target/linux/rockchip/patches-5.10/{207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch => 205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch} (97%) delete mode 100644 target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch delete mode 100644 target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch delete mode 100644 target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch delete mode 100644 target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch delete mode 100644 target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch delete mode 100644 target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch create mode 100644 target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch delete mode 100644 target/linux/rockchip/patches-5.15/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch delete mode 100644 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target/linux/rockchip/patches-5.4/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch delete mode 100644 target/linux/rockchip/patches-5.4/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch create mode 100644 target/linux/rockchip/patches-5.4/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index ab922002b..28d295c99 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -1,6 +1,6 @@ # # This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. +# See /LICENSE for more information. # include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk @@ -69,36 +69,14 @@ define U-Boot/orangepi-r1-plus-lts-rk3328 USE_RKBIN:=1 endef -define U-Boot/doornet1-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=DoorNet1 - BUILD_DEVICES:= \ - embedfire_doornet1 - DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.49.elf - USE_RKBIN:=1 -endef # RK3399 boards -define U-Boot/doornet2-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=DoorNet2 - BUILD_DEVICES:= \ - embedfire_doornet2 - DEPENDS:=+PACKAGE_u-boot-doornet2-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf - USE_RKBIN:=1 -endef - define U-Boot/guangmiao-g4c-rk3399 BUILD_SUBTARGET:=armv8 NAME:=GuangMiao G4C BUILD_DEVICES:= \ - sharevdi_guangmiao-g4c \ - embedfire_doornet2-4gb + sharevdi_guangmiao-g4c DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip ATF:=rk3399_bl31.elf @@ -126,39 +104,17 @@ define U-Boot/nanopi-r4se-rk3399 USE_RKBIN:=1 endef -define U-Boot/fastrhino-r66s-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=FastRhin-R66S - BUILD_DEVICES:= \ - fastrhino_r66s - DEPENDS:=+PACKAGE_u-boot-fastrhino-r66s-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - define U-Boot/nanopi-r5s-rk3568 BUILD_SUBTARGET:=armv8 - NAME:=NANOPI-R5S + NAME:=NanoPi R5S BUILD_DEVICES:= \ - friendlyelec_nanopi-r5s + friendlyarm_nanopi-r5s DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568 PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor ATF:=rk3568_bl31_v1.28.elf DDR:=rk3568_ddr_1560MHz_v1.13.bin endef -define U-Boot/rock-3a-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=ROCK-3A - BUILD_DEVICES:= \ - radxa_rock-3a - DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - define U-Boot/rock-pi-4-rk3399 BUILD_SUBTARGET:=armv8 NAME:=Rock Pi 4 @@ -179,33 +135,17 @@ define U-Boot/rockpro64-rk3399 ATF:=rk3399_bl31.elf endef -define U-Boot/station-p2-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=StationP2 - BUILD_DEVICES:= \ - firefly_station-p2 - DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - UBOOT_TARGETS := \ - doornet2-rk3399 \ - fastrhino-r66s-rk3568 \ guangmiao-g4c-rk3399 \ nanopi-r4s-rk3399 \ nanopi-r4se-rk3399 \ nanopi-r5s-rk3568 \ - rock-3a-rk3568 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ - doornet1-rk3328 \ nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ - orangepi-r1-plus-lts-rk3328 \ - station-p2-rk3568 + orangepi-r1-plus-lts-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch b/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch deleted file mode 100644 index 4e489f0a8..000000000 --- a/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch +++ /dev/null @@ -1,92 +0,0 @@ ---- /dev/null -+++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,dm-spl; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-fastrhino-r66s.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "FastRhino R66S"; -+ compatible = "fastrhino,r66s", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/board/fastrhino/fastrhino-r66s-rk3568/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_FASTRHINO_R66S_RK3568 -+ -+config SYS_BOARD -+ default "fastrhino-r66s-rk3568" -+ -+config SYS_VENDOR -+ default "fastrhino" -+ -+config SYS_CONFIG_NAME -+ default "fastrhino-r66s-rk3568" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/fastrhino/fastrhino-r66s-rk3568/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += fastrhino-r66s-rk3568.o ---- /dev/null -+++ b/board/fastrhino/fastrhino-r66s-rk3568/fastrhino-r66s-rk3568.c -@@ -0,0 +1,4 @@ -+ // SPDX-License-Identifier: GPL-2.0+ -+/* -+ * -+ */ ---- /dev/null -+++ b/include/configs/fastrhino-r66s-rk3568.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __FASTRHINO_R66S_RK3568_H -+#define __FASTRHINO_R66S_RK3568_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ -+#endif diff --git a/package/boot/uboot-rockchip/patches/017-rockchip-rk3568-Add-support-for-Station-P2.patch b/package/boot/uboot-rockchip/patches/017-rockchip-rk3568-Add-support-for-Station-P2.patch deleted file mode 100644 index da1070da4..000000000 --- a/package/boot/uboot-rockchip/patches/017-rockchip-rk3568-Add-support-for-Station-P2.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001 -From: huangjf -Date: Thu, 7 Apr 2022 16:22:56 +0800 -Subject: [PATCH] rockchip: rk3568: Add support for Station P2 - ---- - configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) - create mode 100644 configs/station-p2-rk3568_defconfig - -diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig -new file mode 100644 -index 0000000000..435be99edf ---- /dev/null -+++ b/configs/station-p2-rk3568_defconfig -@@ -0,0 +1,59 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_ERRNO_STR=y --- -2.20.1 - diff --git a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch b/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch deleted file mode 100644 index a4214f1ca..000000000 --- a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch +++ /dev/null @@ -1,549 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - rk3308-roc-cc.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ -+ rk3328-doornet1.dtb \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-roc-cc.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3328-doornet1-u-boot.dtsi -@@ -0,0 +1,46 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * Copyright (c) 2021 EmbedFire -+ */ -+ -+#include "rk3328-u-boot.dtsi" -+#include "rk3328-sdram-ddr4-666.dtsi" -+/ { -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &emmc; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; -+ }; -+}; -+ -+&gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&pinctrl { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc0m1_pin { -+ u-boot,dm-spl; -+}; -+ -+&pcfg_pull_up_4ma { -+ u-boot,dm-spl; -+}; -+ -+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -+&vcc_sd { -+ u-boot,dm-spl; -+}; -+ -+&gmac2io { -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3328-doornet1.dts -@@ -0,0 +1,385 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 David Bauer -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet1"; -+ compatible = "embedfire,doornet1", "rockchip,rk3328"; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&reset_button_pin>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ lan_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:wan"; -+ }; -+ }; -+ -+ vcc_io_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_io_sdio"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ startup-delay-us = <2000>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211f>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io_33>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ rx_delay = <0x54>; -+ snps,aal; -+ tx_delay = <0x20>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211f: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vdd_5v>; -+ vcc2-supply = <&vdd_5v>; -+ vcc3-supply = <&vdd_5v>; -+ vcc4-supply = <&vdd_5v>; -+ vcc5-supply = <&vcc_io_33>; -+ vcc6-supply = <&vdd_5v>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io_33: DCDC_REG4 { -+ regulator-name = "vcc_io_33"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io_33>; -+ vccio1-supply = <&vcc_io_33>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io_sdio>; -+ vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io_33>; -+ vccio6-supply = <&vcc_io_33>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ button { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sd { -+ sdio_vcc_pin: sdio-vcc-pin { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io_33>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ ---- /dev/null -+++ b/configs/doornet1-rk3328_defconfig -@@ -0,0 +1,99 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-doornet1.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-doornet1" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch rename to package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch diff --git a/package/boot/uboot-rockchip/patches/306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch b/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/306-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch rename to package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch diff --git a/package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch deleted file mode 100644 index 05b510e24..000000000 --- a/package/boot/uboot-rockchip/patches/303-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch +++ /dev/null @@ -1,984 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -121,6 +121,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \ - rk3368-px5-evb.dtb \ - - dtb-$(CONFIG_ROCKCHIP_RK3399) += \ -+ rk3399-doornet2.dtb \ - rk3399-evb.dtb \ - rk3399-ficus.dtb \ - rk3399-firefly.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Jagan Teki -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" -+#include "rk3399-sdram-ddr3-1866.dtsi" -+ -+/{ -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; -+ }; -+}; -+ -+&sdmmc { -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2.dts -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3399-doornet2.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet2"; -+ compatible = "embedfire,doornet2", "rockchip,rk3399"; -+ -+ /delete-node/ display-subsystem; -+ -+ gpio-leds { -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ -+ /delete-node/ status; -+ -+ lan_led: led-lan { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ sys_led: led-sys { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "red:sys"; -+ default-state = "on"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+ -+ gpio-keys { -+ pinctrl-0 = <&reset_button_pin>; -+ -+ /delete-node/ power; -+ -+ reset { -+ debounce-interval = <50>; -+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ }; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ status = "disabled"; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ /delete-node/ leds-gpio; -+ -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rockchip-key { -+ /delete-node/ power-key; -+ -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&sdhci { -+ status = "okay"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&uart0 { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ ---- /dev/null -+++ b/arch/arm/dts/rk3399-doornet2.dtsi -@@ -0,0 +1,750 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc5v0_sys"; -+ vin-supply = <&vdd_5v>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_s3"; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* -+ * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only -+ * drives the enable pin, but we can't quite model that. -+ */ -+ vcca0v9_s3: vcca0v9-s3 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcca0v9_s3"; -+ vin-supply = <&vcc1v8_s3>; -+ }; -+ -+ /* As above, actually supplied by vcc3v3_sys */ -+ vcca1v8_s3: vcca1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_s3"; -+ vin-supply = <&vcc1v8_s3>; -+ }; -+ -+ vbus_typec: vbus-typec { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vbus_typec"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_key>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&leds_gpio>; -+ -+ status { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; -+ phy-handle = <&rtl8211f>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc3v3_s3>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211f: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <30000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c7>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "xin32k", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_cam: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_cam"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_touch"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmupll: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_pmupll"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <3000000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcca3v0_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <200000>; -+ i2c-scl-rising-time-ns = <150>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ vbus-supply = <&vbus_typec>; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <2>; -+ num-lanes = <2>; -+ vpcie0v9-supply = <&vcca0v9_s3>; -+ vpcie1v8-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-leds { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ phy { -+ phy_intb: phy-intb { -+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_rstb: phy-rstb { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ power_key: power-key { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_reg_on_h: wifi-reg_on-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "active"; -+ pinctrl-0 = <&pwm2_pin_pull_down>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <4000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -+ ---- /dev/null -+++ b/configs/doornet2-rk3399_defconfig -@@ -0,0 +1,65 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-doornet2" -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-doornet2.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -+ diff --git a/package/boot/uboot-rockchip/patches/305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/305-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch rename to package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 000000000..696ca4218 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,110 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -157,6 +157,7 @@ + rk3399-nanopi-m4b.dtb \ + rk3399-nanopi-neo4.dtb \ + rk3399-nanopi-r4s.dtb \ ++ rk3399-nanopi-r4se.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4se.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * FriendlyElec NanoPC-T4 board device tree source ++ * ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2018 Collabora Ltd. ++ * ++ * Copyright (c) 2020 Jensen Huang ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi-r4s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R4SE"; ++ compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/nanopi-r4se-rk3399_defconfig +@@ -0,0 +1,65 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch deleted file mode 100644 index c24ffd30a..000000000 --- a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -157,6 +157,8 @@ - rk3399-nanopi-m4b.dtb \ - rk3399-nanopi-neo4.dtb \ - rk3399-nanopi-r4s.dtb \ -+ rk3399-nanopi-r4se.dtb \ -+ rk3568-fastrhino-r66s.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-puma-haikou.dtb \ diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts deleted file mode 100644 index d4a0c58f7..000000000 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-nanopi-r4se.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPC-T4 board device tree source - * - * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * - * Copyright (c) 2020 Jensen Huang - * Copyright (c) 2020 Marty Jones - * Copyright (c) 2021 Tianling Shen - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi R4SE"; - compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; - - /delete-node/ display-subsystem; - - gpio-leds { - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - - /delete-node/ led-0; - - lan_led: led-lan { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; - }; - - sys_led: led-sys { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:power"; - default-state = "on"; - }; - - wan_led: led-wan { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - }; - }; - - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - - /delete-node/ power; - - reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c4 { - status = "disabled"; -}; - -&pcie0 { - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; -}; - -&pinctrl { - gpio-leds { - /delete-node/ status-led-pin; - - lan_led_pin: lan-led-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - /delete-node/ power-key; - - reset_button_pin: reset-button-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdio0 { - status = "disabled"; -}; - -&u2phy0_host { - phy-supply = <&vdd_5v>; -}; - -&u2phy1_host { - status = "disabled"; -}; - -&uart0 { - status = "disabled"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_sys>; -}; diff --git a/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig deleted file mode 100644 index 87e73cdc8..000000000 --- a/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig +++ /dev/null @@ -1,97 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_DEFAULT_DEVICE_TREE="rk3568-fastrhino-r66s" -CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_TARGET_FASTRHINO_R66S_RK3568=y -CONFIG_DEBUG_UART_BASE=0xFE660000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_SYS_LOAD_ADDR=0xc00800 -CONFIG_API=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb" -# CONFIG_SYS_DEVICE_NULLDEV is not set -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -# CONFIG_SPL_DOS_PARTITION is not set -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_WARN=y -CONFIG_SPL_REGMAP=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_CLK=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_ROCKCHIP_GPIO_V2=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_POWER_DOMAIN=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_SPL_RAM=y -CONFIG_DM_RESET=y -CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_SYSRESET_PSCI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_LAN75XX=y -CONFIG_USB_ETHER_LAN78XX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig b/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig deleted file mode 100644 index e92fb5e88..000000000 --- a/package/boot/uboot-rockchip/src/configs/nanopi-r4se-rk3399_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=24000000 -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" -CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y -CONFIG_DEBUG_UART_BASE=0xFF1A0000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_DEBUG_UART=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_TPL=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM_RK3399_LPDDR4=y -CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_ASIX88179=y -CONFIG_USB_ETHER_MCS7830=y -CONFIG_USB_ETHER_RTL8152=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_DM_VIDEO=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_ROCKCHIP=y -CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_ERRNO_STR=y diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index 6e31d4eeb..b8842e252 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa SUBTARGETS:=armv8 KERNEL_PATCHVER=5.15 -KERNEL_TESTING_PATCHVER=5.19 +KERNEL_TESTING_PATCHVER=5.10 define Target/Description Build firmware image for Rockchip SoC devices. @@ -17,8 +17,7 @@ endef include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \ - automount autocore-arm autosamba fdisk cfdisk e2fsprogs ethtool haveged htop \ - luci-app-zerotier luci-app-ipsec-vpnd luci-app-diskman usbutils usb-modeswitch + automount autocore-arm e2fsprogs ethtool haveged htop usb-modeswitch KERNELNAME:=Image dtbs diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index 79816ae43..bae451e8e 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -9,7 +9,6 @@ boardname="${board##*,}" board_config_update case $board in -embedfire,doornet1|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ xunlong,orangepi-r1-plus|\ @@ -17,24 +16,17 @@ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1" ;; -embedfire,doornet2|\ friendlyarm,nanopi-r4s|\ friendlyarm,nanopi-r4se|\ sharevdi,guangmiao-g4c) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; -firefly,rk3568-roc-pc) - ucidef_set_led_timer "health" "health" "firefly:yellow:user" "200" "800" - ;; -friendlyelec,nanopi-r5s) +friendlyarm,nanopi-r5s) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2" ;; -radxa,rock3a) - ucidef_set_led_netdev "lan" "LAN" "user-led" "br-lan" - ;; esac board_config_flush diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index edd4eb516..50880e19e 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -8,8 +8,6 @@ rockchip_setup_interfaces() local board="$1" case "$board" in - embedfire,doornet1|\ - embedfire,doornet2|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ friendlyarm,nanopi-r4s|\ @@ -19,11 +17,7 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; - fastrhino,r66s|\ - firefly,rk3568-roc-pc) - ucidef_set_interfaces_lan_wan "eth0" "eth1" - ;; - friendlyelec,nanopi-r5s) + friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0" ;; *) @@ -34,7 +28,7 @@ rockchip_setup_interfaces() nanopi_r2s_generate_mac() { - local sd_hash=$(sha256sum /sys/class/block/mmcblk*/device/cid | head -n 1) + local sd_hash=$(sha256sum /sys/class/block/mmcblk0/device/cid) local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)") echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")" } @@ -47,24 +41,16 @@ rockchip_setup_macs() local label_mac="" case "$board" in - embedfire,doornet1|\ - embedfire,doornet2|\ - fastrhino,r66s|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ - sharevdi,guangmiao-g4c|\ - friendlyelec,nanopi-r5s|\ - firefly,rk3568-roc-pc) + friendlyarm,nanopi-r5s|\ + sharevdi,guangmiao-g4c) wan_mac=$(nanopi_r2s_generate_mac) lan_mac=$(macaddr_add "$wan_mac" +1) ;; - friendlyarm,nanopi-r4se|\ - friendlyarm,nanopi-r4s) - if [ -f /sys/bus/i2c/devices/2-0051/eeprom ]; then - wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa) - else - wan_mac=$(nanopi_r2s_generate_mac) - fi + friendlyarm,nanopi-r4s|\ + friendlyarm,nanopi-r4se) + wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa) lan_mac=$(macaddr_setbit_la "$wan_mac") ;; xunlong,orangepi-r1-plus|\ diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 43d9c4ee3..e53cb7bbe 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -5,13 +5,12 @@ get_device_irq() { local device="$1" local line - local seconds="0" + local seconds # wait up to 10 seconds for the irq/device to appear - while [ "${seconds}" -le 10 ]; do + for seconds in $(seq 0 9); do line=$(grep -m 1 "${device}\$" /proc/interrupts) && break - seconds="$(( seconds + 2 ))" - sleep 2 + sleep 1 done echo ${line} | sed 's/:.*//' } @@ -29,7 +28,10 @@ set_interface_core() { } case "$(board_name)" in -embedfire,doornet1|\ +fastrhino,r66s) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + ;; friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ xunlong,orangepi-r1-plus|\ @@ -37,18 +39,13 @@ xunlong,orangepi-r1-plus-lts) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb3" ;; -embedfire,doornet2|\ friendlyarm,nanopi-r4s|\ +friendlyarm,nanopi-r4se|\ sharevdi,guangmiao-g4c) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; -fastrhino,r66s|\ -firefly,rk3568-roc-pc) - set_interface_core 2 "eth0" - set_interface_core 4 "eth1" - ;; -friendlyelec,nanopi-r5s) +friendlyarm,nanopi-r5s) set_interface_core 0 "eth0" set_interface_core 2 "eth1" set_interface_core 4 "eth2" diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10 index 41e65622d..83775722d 100644 --- a/target/linux/rockchip/armv8/config-5.10 +++ b/target/linux/rockchip/armv8/config-5.10 @@ -448,7 +448,6 @@ CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y -# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y diff --git a/target/linux/rockchip/armv8/config-5.19 b/target/linux/rockchip/armv8/config-5.19 deleted file mode 100644 index 319f59cb0..000000000 --- a/target/linux/rockchip/armv8/config-5.19 +++ /dev/null @@ -1,841 +0,0 @@ -CONFIG_64BIT=y -CONFIG_AF_UNIX_OOB=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SME=y -CONFIG_ARM64_SVE=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_FFA_SMCCC=y -CONFIG_ARM_FFA_TRANSPORT=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_RK3399_DMC_DEVFREQ=y -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_HAVE_SHMEM=y -CONFIG_ARM_SCMI_HAVE_TRANSPORT=y -CONFIG_ARM_SCMI_POWER_DOMAIN=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y -CONFIG_ARM_SCMI_TRANSPORT_SMC=y -# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMCCC_SOC_ID=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINARY_PRINTF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BLOCK_LEGACY_AUTOLOAD=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CHARGER_GPIO=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -# CONFIG_COMMON_CLK_RS9_PCIE is not set -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC64=y -CONFIG_CRC64_ROCKSOFT=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC64_ROCKSOFT=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -# CONFIG_DM9051 is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DRM=y -# CONFIG_DRM_ANALOGIX_ANX7625 is not set -CONFIG_DRM_BRIDGE=y -# CONFIG_DRM_CHIPONE_ICN6211 is not set -CONFIG_DRM_DEBUG_MODESET_LOCK=y -CONFIG_DRM_DISPLAY_HDMI_HELPER=y -CONFIG_DRM_DISPLAY_HELPER=y -CONFIG_DRM_DW_HDMI=y -CONFIG_DRM_DW_MIPI_DSI=y -# CONFIG_DRM_FSL_LDB is not set -CONFIG_DRM_GEM_CMA_HELPER=y -# CONFIG_DRM_ITE_IT6505 is not set -# CONFIG_DRM_ITE_IT66121 is not set -CONFIG_DRM_KMS_HELPER=y -# CONFIG_DRM_LONTIUM_LT8912B is not set -# CONFIG_DRM_LONTIUM_LT9211 is not set -# CONFIG_DRM_LONTIUM_LT9611UXC is not set -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_NOMODESET=y -CONFIG_DRM_PANEL=y -# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set -# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set -CONFIG_DRM_PANEL_BRIDGE=y -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_EDP is not set -# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set -# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set -# CONFIG_DRM_PANEL_JDI_R63452 is not set -# CONFIG_DRM_PANEL_KHADAS_TS050 is not set -# CONFIG_DRM_PANEL_MIPI_DBI is not set -# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set -# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set -# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set -# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set -# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set -# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set -# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set -# CONFIG_DRM_RCAR_MIPI_DSI is not set -# CONFIG_DRM_RCAR_USE_LVDS is not set -CONFIG_DRM_ROCKCHIP=y -# CONFIG_DRM_SIMPLEDRM is not set -# CONFIG_DRM_SSD130X is not set -# CONFIG_DRM_TI_SN65DSI83 is not set -CONFIG_DTC=y -CONFIG_DT_IDLE_GENPD=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FB_CMDLINE=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FORTIFY_SOURCE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -# CONFIG_FUN_ETH is not set -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC12_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PHY_MIPI_DPHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -# CONFIG_GPIO_CASCADE is not set -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ROCKCHIP=y -# CONFIG_GPIO_SIM is not set -CONFIG_GRO_CELLS=y -# CONFIG_HARDENED_USERCOPY is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y -# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_RK805_PWRKEY=y -CONFIG_INPUT_SPARSEKMAP=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -# CONFIG_KEXEC_SIG is not set -CONFIG_KSM=y -# CONFIG_LAN966X_SWITCH is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -# CONFIG_LEDS_PWM_MULTICOLOR is not set -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_LTO_NONE=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -# CONFIG_MFD_MAX77714 is not set -CONFIG_MFD_RK808=y -# CONFIG_MFD_SIMPLE_MFD_I2C is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_CYPRESS=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -# CONFIG_NET_DSA_REALTEK is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_DAVICOM=y -CONFIG_NET_VENDOR_FUNGIBLE=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_VERBOSE_ERRORS is not set -# CONFIG_OCTEON_EP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_SPLIT_BTF=y -CONFIG_PAHOLE_VERSION=121 -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PATA_SIS=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_STUB=y -CONFIG_PCS_XPCS=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -CONFIG_PHY_ROCKCHIP_DPHY_RX0=y -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=y -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_RK805=y -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_PWM_XILINX is not set -# CONFIG_QFMT_V1 is not set -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_KSTACK_OFFSET=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_ARM_SCMI is not set -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -# CONFIG_REGULATOR_RT5190A is not set -# CONFIG_REGULATOR_RT5759 is not set -# CONFIG_REGULATOR_SY7636A is not set -# CONFIG_REGULATOR_TPS6286X is not set -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SCMI=y -CONFIG_RFS_ACCEL=y -# CONFIG_ROCKCHIP_ANALOGIX_DP is not set -# CONFIG_ROCKCHIP_CDN_DP is not set -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -# CONFIG_ROCKCHIP_LVDS is not set -CONFIG_ROCKCHIP_MBOX=y -# CONFIG_ROCKCHIP_OTP is not set -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_RGB is not set -CONFIG_ROCKCHIP_RK3066_HDMI=y -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_ROCKCHIP_VOP=y -CONFIG_ROCKCHIP_VOP2=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_HOST=y -CONFIG_SATA_PMP=y -CONFIG_SATA_SIS=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -# CONFIG_SCSI_SAS_ATA is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -# CONFIG_SENSORS_ARM_SCMI is not set -CONFIG_SENSORS_ARM_SCPI=y -# CONFIG_SENSORS_NCT6775_I2C is not set -# CONFIG_SENSORS_SY7636A is not set -# CONFIG_SENSORS_TMP464 is not set -CONFIG_SERIAL_8250_ASPEED_VUART=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FINTEK=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_PCIPS2=y -CONFIG_SERIO_RAW=y -# CONFIG_SFC_SIENA is not set -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_SPIDEV=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STACKDEPOT=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STACKTRACE=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSVIPC_COMPAT=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -# CONFIG_TINYDRM_ILI9163 is not set -CONFIG_TRACE_CLOCK=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TRANS_TABLE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_DP_ALTMODE is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_FSA4480 is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_RT1719 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_TYPEC_WUSB3801 is not set -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USERIO=y -CONFIG_VIDEOMODE_HELPERS=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -# CONFIG_VMWARE_VMCI is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_WATCHDOG is not set -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4 index 78d56adbc..0e3d00953 100644 --- a/target/linux/rockchip/armv8/config-5.4 +++ b/target/linux/rockchip/armv8/config-5.4 @@ -427,7 +427,6 @@ CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y -# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3566.dtsi deleted file mode 100644 index 6c4b17d27..000000000 --- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3566"; -}; - -&pipegrf { - compatible = "rockchip,rk3566-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>; - phy-names = "usb2-phy"; - extcon = <&usb2phy0>; - maximum-speed = "high-speed"; -}; - -&vop { - compatible = "rockchip,rk3566-vop"; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts similarity index 67% rename from target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts rename to target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index 6b5093a1a..d26f5a826 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -1,70 +1,72 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2022 Marty Jones + * Copyright (c) 2022 Tianling Shen + */ /dts-v1/; + #include #include #include -#include #include "rk3568.dtsi" / { - model = "Radxa ROCK3 Model A"; - compatible = "radxa,rock3a", "rockchip,rk3568"; + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568"; aliases { - ethernet0 = &gmac1; + ethernet0 = &gmac0; mmc0 = &sdmmc0; mmc1 = &sdhci; + + led-boot = &sys_led; + led-failsafe = &sys_led; + led-running = &sys_led; + led-upgrade = &sys_led; }; chosen: chosen { stdout-path = "serial2:1500000n8"; }; - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - leds { compatible = "gpio-leds"; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, + <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; - led_user: led-0 { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; + lan1_led: led-0 { + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + }; + + lan2_led: led-1 { + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + }; + + sys_led: led-2 { + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + }; + + wan_led: led-3 { + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "wan_led"; }; }; - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - vcc12v_dcin: vcc12v-dcin { + vdd_5v: vdd-5v { compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; + regulator-name = "vdd_5v"; regulator-always-on; regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; vcc3v3_sys: vcc3v3-sys { @@ -74,27 +76,27 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; + vin-supply = <&vdd_5v>; }; - vcc5v0_sys: vcc5v0-sys { + vcc3v3_sysp: vcc3v3-sysp { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc3v3_sysp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_sysp: vcc5v0-sysp { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sysp"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; + vin-supply = <&vcc3v3_sysp>; }; vcc5v0_usb_host: vcc5v0-usb-host { @@ -106,30 +108,18 @@ regulator-name = "vcc5v0_usb_host"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; + vin-supply = <&vcc5v0_sysp>; }; - vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { + vcc3v3_pcie: vcc3v3-pcie { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sysp>; }; }; @@ -141,6 +131,10 @@ status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -157,50 +151,32 @@ cpu-supply = <&vdd_cpu>; }; -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; +&gmac0 { clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + phy-handle = <&rgmii_phy0>; status = "okay"; }; &i2c0 { + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; status = "okay"; vdd_cpu: regulator@1c { @@ -210,10 +186,11 @@ regulator-name = "vdd_cpu"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc3v3_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -225,15 +202,12 @@ reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + pinctrl-0 = <&pmic_int>; rockchip,system-power-controller; - #sound-dai-cells = <0>; + wakeup-source; + vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; @@ -243,7 +217,6 @@ vcc7-supply = <&vcc3v3_sys>; vcc8-supply = <&vcc3v3_sys>; vcc9-supply = <&vcc3v3_sys>; - wakeup-source; regulators { vdd_logic: DCDC_REG1 { @@ -427,57 +400,132 @@ vcc3v3_sd: SWITCH_REG2 { regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; }; + }; +}; - codec { - mic-in-differential; +&i2c5 { + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_int>; + }; +}; + +&pcie2x1 { + num-lanes = <1>; + num-viewport = <4>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@00 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_1: pcie@01,0 { + reg = <0x000000 0 0 0 0>; }; }; }; -&i2s0_8ch { +&pcie30phy { + data-lanes = <1 2>; status = "okay"; }; -&i2s1_8ch { - rockchip,trcm-sync-tx-only; +&pcie3x1 { + num-lanes = <1>; + num-viewport = <4>; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; status = "okay"; -}; -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + pcie@10 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + }; }; }; +&pcie3x2 { + num-lanes = <1>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + leds { + lan1_led_pin: lan1-led-pin { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + eth_phy { + gmac_int: gmac-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; pmic { pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -485,20 +533,12 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; }; }; &pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; pmuio2-supply = <&vcc3v3_pmu>; vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; vccio3-supply = <&vccio_sd>; vccio4-supply = <&vcc_1v8>; vccio5-supply = <&vcc_3v3>; @@ -507,6 +547,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8>; status = "okay"; @@ -517,9 +561,7 @@ max-frequency = <200000000>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; status = "okay"; }; @@ -581,7 +623,6 @@ }; &usb2phy0_otg { - vbus-supply = <&vcc5v0_usb_otg>; status = "okay"; }; @@ -590,28 +631,9 @@ }; &usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; &usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi deleted file mode 100644 index 2bdf8c7e9..000000000 --- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3568"; - - sata0: sata@fc000000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc000000 0 0x1000>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, - <&cru CLK_SATA0_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - qos_pcie3x1: qos@fe190080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190080 0x0 0x20>; - }; - - qos_pcie3x2: qos@fe190100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190100 0x0 0x20>; - }; - - qos_sata0: qos@fe190200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190200 0x0 0x20>; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - combphy0: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, - <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY0>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - #phy-cells = <1>; - status = "disabled"; - }; -}; - -&cpu0_opp_table { - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; -}; - -&pipegrf { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_pcie3x1>, - <&qos_pcie3x2>, - <&qos_sata0>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; -}; - -&vop { - compatible = "rockchip,rk3568-vop"; -}; diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk356x.dtsi deleted file mode 100644 index 319981c3e..000000000 --- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ /dev/null @@ -1,1706 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1150000>; - clock-latency-ns = <40000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1150000>; - opp-suspend; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <975000 975000 1150000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1050000 1050000 1150000>; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - }; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <825000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; - }; - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - }; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "HDMI"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - status = "disabled"; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - pinctrl-0 = <&clk32k_out0>; - pinctrl-names = "default"; - #clock-cells = <0>; - }; - - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - sata1: sata@fc400000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc400000 0 0x1000>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, - <&cru CLK_SATA1_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - sata2: sata@fc800000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc800000 0 0x1000>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, - <&cru CLK_SATA2_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy2 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - usb_host0_xhci: usb@fcc00000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG0>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - usb_host1_xhci: usb@fd000000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "host"; - phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG1>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3568-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - pipegrf: syscon@fdc50000 { - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; - rockchip,grf = <&grf>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - interrupts = ; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fdd90000 { - compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfdd90000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3568-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_GPU */ - power-domain@RK3568_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU_PRE>, - <&cru PCLK_GPU_PRE>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3568_PD_VI { - reg = ; - clocks = <&cru HCLK_VI>, - <&cru PCLK_VI>; - pm_qos = <&qos_isp>, - <&qos_vicap0>, - <&qos_vicap1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VO { - reg = ; - clocks = <&cru HCLK_VO>, - <&cru PCLK_VO>, - <&cru ACLK_VOP_PRE>; - pm_qos = <&qos_hdcp>, - <&qos_vop_m0>, - <&qos_vop_m1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RGA { - reg = ; - clocks = <&cru HCLK_RGA_PRE>, - <&cru PCLK_RGA_PRE>; - pm_qos = <&qos_ebc>, - <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc>, - <&qos_rga_rd>, - <&qos_rga_wr>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VPU { - reg = ; - clocks = <&cru HCLK_VPU_PRE>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVDEC { - clocks = <&cru HCLK_RKVDEC_PRE>; - reg = ; - pm_qos = <&qos_rkvdec>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVENC { - reg = ; - clocks = <&cru HCLK_RKVENC_PRE>; - pm_qos = <&qos_rkvenc_rd_m0>, - <&qos_rkvenc_rd_m1>, - <&qos_rkvenc_wr_m0>; - #power-domain-cells = <0>; - }; - }; - }; - - gpu: gpu@fde60000 { - compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; - reg = <0x0 0xfde60000 0x0 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; - clock-names = "gpu", "bus"; - #cooling-cells = <2>; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3568_PD_GPU>; - status = "disabled"; - }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - vop: vop@fe040000 { - reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; - iommus = <&vop_mmu>; - power-domains = <&power RK3568_PD_VO>; - rockchip,grf = <&grf>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp1: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp2: port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - vop_mmu: iommu@fe043e00 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@fe0a0000 { - compatible = "rockchip,rk3568-dw-hdmi"; - reg = <0x0 0xfe0a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_HOST>, - <&cru CLK_HDMI_SFR>, - <&cru CLK_HDMI_CEC>, - <&pmucru CLK_HDMI_REF>, - <&cru HCLK_VO>; - clock-names = "iahb", "isfr", "cec", "ref"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - power-domains = <&power RK3568_PD_VO>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; - }; - - qos_rkvenc_rd_m0: qos@fe138080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138080 0x0 0x20>; - }; - - qos_rkvenc_rd_m1: qos@fe138100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138100 0x0 0x20>; - }; - - qos_rkvenc_wr_m0: qos@fe138180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138180 0x0 0x20>; - }; - - qos_isp: qos@fe148000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148000 0x0 0x20>; - }; - - qos_vicap0: qos@fe148080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148080 0x0 0x20>; - }; - - qos_vicap1: qos@fe148100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148100 0x0 0x20>; - }; - - qos_vpu: qos@fe150000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe150000 0x0 0x20>; - }; - - qos_ebc: qos@fe158000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158000 0x0 0x20>; - }; - - qos_iep: qos@fe158100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158100 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fe158180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158180 0x0 0x20>; - }; - - qos_jpeg_enc: qos@fe158200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158200 0x0 0x20>; - }; - - qos_rga_rd: qos@fe158280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158280 0x0 0x20>; - }; - - qos_rga_wr: qos@fe158300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158300 0x0 0x20>; - }; - - qos_npu: qos@fe180000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe180000 0x0 0x20>; - }; - - qos_pcie2x1: qos@fe190000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190000 0x0 0x20>; - }; - - qos_sata1: qos@fe190280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190280 0x0 0x20>; - }; - - qos_sata2: qos@fe190300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190300 0x0 0x20>; - }; - - qos_usb3_0: qos@fe190380 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190380 0x0 0x20>; - }; - - qos_usb3_1: qos@fe190400 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190400 0x0 0x20>; - }; - - qos_rkvdec: qos@fe198000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe198000 0x0 0x20>; - }; - - qos_hdcp: qos@fe1a8000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8000 0x0 0x20>; - }; - - qos_vop_m0: qos@fe1a8080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8080 0x0 0x20>; - }; - - qos_vop_m1: qos@fe1a8100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; - - pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie"; - reg = <0x3 0xc0000000 0x0 0x00400000>, - <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; - reg-names = "dbi", "apb", "config"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msi", "legacy", "err"; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - linux,pci-domain = <0>; - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: mmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sfc: spi@fe300000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe300000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - spdif: spdif@fe460000 { - compatible = "rockchip,rk3568-spdif"; - reg = <0x0 0xfe460000 0x0 0x1000>; - interrupts = ; - clock-names = "mclk", "hclk"; - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; - dmas = <&dmac1 1>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe400000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe400000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 0>; - dma-names = "tx"; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe410000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe410000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, - <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 3>, <&dmac1 2>; - dma-names = "rx", "tx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx - &i2s1m0_lrcktx &i2s1m0_lrckrx - &i2s1m0_sdi0 &i2s1m0_sdi1 - &i2s1m0_sdi2 &i2s1m0_sdi3 - &i2s1m0_sdo0 &i2s1m0_sdo1 - &i2s1m0_sdo2 &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe430000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe430000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, - <&cru HCLK_I2S3_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 6>, <&dmac1 7>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@fe440000 { - compatible = "rockchip,rk3568-pdm"; - reg = <0x0 0xfe440000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac1 9>; - dma-names = "rx"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_clk1 - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-names = "default"; - resets = <&cru SRST_M_PDM>; - reset-names = "pdm-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@fe600000 { - compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - interrupts = ; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - }; - - spi0: spi@fe610000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe610000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 20>, <&dmac0 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@fe620000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe620000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 22>, <&dmac0 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@fe630000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe630000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 24>, <&dmac0 25>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@fe640000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe640000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 26>, <&dmac0 27>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_threshold: gpu-threshold { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_target: gpu-target { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_target>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@fe710000 { - compatible = "rockchip,rk3568-tsadc"; - reg = <0x0 0xfe710000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; - assigned-clock-rates = <17000000>, <700000>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, - <&cru SRST_TSADCPHY>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_pin>; - pinctrl-1 = <&tsadc_shutorg>; - pinctrl-2 = <&tsadc_pin>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = ; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - combphy1: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, - <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY1>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - #phy-cells = <1>; - status = "disabled"; - }; - - combphy2: phy@fe840000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe840000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY2_REF>, - <&cru PCLK_PIPEPHY2>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY2>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf2>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2phy0: usb2phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy0_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy0_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy1_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy1_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" diff --git a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c deleted file mode 100644 index 0b49fed16..000000000 --- a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ /dev/null @@ -1,2706 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * Author: Andy Yan - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "rockchip_drm_drv.h" -#include "rockchip_drm_gem.h" -#include "rockchip_drm_fb.h" -#include "rockchip_drm_vop2.h" - -/* - * VOP2 architecture - * - +----------+ +-------------+ +-----------+ - | Cluster | | Sel 1 from 6| | 1 from 3 | - | window0 | | Layer0 | | RGB | - +----------+ +-------------+ +---------------+ +-------------+ +-----------+ - +----------+ +-------------+ |N from 6 layers| | | - | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ - | window1 | | Layer1 | | | | | | 1 from 3 | - +----------+ +-------------+ +---------------+ +-------------+ | LVDS | - +----------+ +-------------+ +-----------+ - | Esmart | | Sel 1 from 6| - | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ - +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | - +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | - | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ - | Window1 | | Layer3 | +---------------+ +-------------+ - +----------+ +-------------+ +-----------+ - +----------+ +-------------+ | 1 from 3 | - | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | - | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ - +----------+ +-------------+ | Overlay2 +--->| Video Port2 | - +----------+ +-------------+ | | | | +-----------+ - | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | - | Window1 | | Layer5 | | eDP | - +----------+ +-------------+ +-----------+ - * - */ - -enum vop2_data_format { - VOP2_FMT_ARGB8888 = 0, - VOP2_FMT_RGB888, - VOP2_FMT_RGB565, - VOP2_FMT_XRGB101010, - VOP2_FMT_YUV420SP, - VOP2_FMT_YUV422SP, - VOP2_FMT_YUV444SP, - VOP2_FMT_YUYV422 = 8, - VOP2_FMT_YUYV420, - VOP2_FMT_VYUY422, - VOP2_FMT_VYUY420, - VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, - VOP2_FMT_YUV420SP_TILE_16x2, - VOP2_FMT_YUV422SP_TILE_8x4, - VOP2_FMT_YUV422SP_TILE_16x2, - VOP2_FMT_YUV420SP_10, - VOP2_FMT_YUV422SP_10, - VOP2_FMT_YUV444SP_10, -}; - -enum vop2_afbc_format { - VOP2_AFBC_FMT_RGB565, - VOP2_AFBC_FMT_ARGB2101010 = 2, - VOP2_AFBC_FMT_YUV420_10BIT, - VOP2_AFBC_FMT_RGB888, - VOP2_AFBC_FMT_ARGB8888, - VOP2_AFBC_FMT_YUV420 = 9, - VOP2_AFBC_FMT_YUV422 = 0xb, - VOP2_AFBC_FMT_YUV422_10BIT = 0xe, - VOP2_AFBC_FMT_INVALID = -1, -}; - -union vop2_alpha_ctrl { - u32 val; - struct { - /* [0:1] */ - u32 color_mode:1; - u32 alpha_mode:1; - /* [2:3] */ - u32 blend_mode:2; - u32 alpha_cal_mode:1; - /* [5:7] */ - u32 factor_mode:3; - /* [8:9] */ - u32 alpha_en:1; - u32 src_dst_swap:1; - u32 reserved:6; - /* [16:23] */ - u32 glb_alpha:8; - } bits; -}; - -struct vop2_alpha { - union vop2_alpha_ctrl src_color_ctrl; - union vop2_alpha_ctrl dst_color_ctrl; - union vop2_alpha_ctrl src_alpha_ctrl; - union vop2_alpha_ctrl dst_alpha_ctrl; -}; - -struct vop2_alpha_config { - bool src_premulti_en; - bool dst_premulti_en; - bool src_pixel_alpha_en; - bool dst_pixel_alpha_en; - u16 src_glb_alpha_value; - u16 dst_glb_alpha_value; -}; - -struct vop2_win { - struct vop2 *vop2; - struct drm_plane base; - const struct vop2_win_data *data; - struct regmap_field *reg[VOP2_WIN_MAX_REG]; - - /** - * @win_id: graphic window id, a cluster may be split into two - * graphics windows. - */ - u8 win_id; - u8 delay; - u32 offset; - - enum drm_plane_type type; -}; - -struct vop2_video_port { - struct drm_crtc crtc; - struct vop2 *vop2; - struct clk *dclk; - unsigned int id; - const struct vop2_video_port_regs *regs; - const struct vop2_video_port_data *data; - - struct completion dsp_hold_completion; - - /** - * @win_mask: Bitmask of windows attached to the video port; - */ - u32 win_mask; - - struct vop2_win *primary_plane; - struct drm_pending_vblank_event *event; - - unsigned int nlayers; -}; - -struct vop2 { - struct device *dev; - struct drm_device *drm; - struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; - - const struct vop2_data *data; - /* - * Number of windows that are registered as plane, may be less than the - * total number of hardware windows. - */ - u32 registered_num_wins; - - void __iomem *regs; - struct regmap *map; - - struct regmap *grf; - - /* physical map length of vop2 register */ - u32 len; - - void __iomem *lut_regs; - - /* protects crtc enable/disable */ - struct mutex vop2_lock; - - int irq; - - /* - * Some global resources are shared between all video ports(crtcs), so - * we need a ref counter here. - */ - unsigned int enable_count; - struct clk *hclk; - struct clk *aclk; - - /* must be put at the end of the struct */ - struct vop2_win win[]; -}; - -static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) -{ - return container_of(crtc, struct vop2_video_port, crtc); -} - -static struct vop2_win *to_vop2_win(struct drm_plane *p) -{ - return container_of(p, struct vop2_win, base); -} - -static void vop2_lock(struct vop2 *vop2) -{ - mutex_lock(&vop2->vop2_lock); -} - -static void vop2_unlock(struct vop2 *vop2) -{ - mutex_unlock(&vop2->vop2_lock); -} - -static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) -{ - regmap_write(vop2->map, offset, v); -} - -static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) -{ - regmap_write(vp->vop2->map, vp->data->offset + offset, v); -} - -static u32 vop2_readl(struct vop2 *vop2, u32 offset) -{ - u32 val; - - regmap_read(vop2->map, offset, &val); - - return val; -} - -static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) -{ - regmap_field_write(win->reg[reg], v); -} - -static bool vop2_cluster_window(const struct vop2_win *win) -{ - return win->data->feature & WIN_FEATURE_CLUSTER; -} - -static void vop2_cfg_done(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - - regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, - BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); -} - -static void vop2_win_disable(struct vop2_win *win) -{ - vop2_win_write(win, VOP2_WIN_ENABLE, 0); - - if (vop2_cluster_window(win)) - vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); -} - -static enum vop2_data_format vop2_convert_format(u32 format) -{ - switch (format) { - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - return VOP2_FMT_ARGB8888; - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - return VOP2_FMT_RGB888; - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - return VOP2_FMT_RGB565; - case DRM_FORMAT_NV12: - return VOP2_FMT_YUV420SP; - case DRM_FORMAT_NV16: - return VOP2_FMT_YUV422SP; - case DRM_FORMAT_NV24: - return VOP2_FMT_YUV444SP; - case DRM_FORMAT_YUYV: - case DRM_FORMAT_YVYU: - return VOP2_FMT_VYUY422; - case DRM_FORMAT_VYUY: - case DRM_FORMAT_UYVY: - return VOP2_FMT_YUYV422; - default: - DRM_ERROR("unsupported format[%08x]\n", format); - return -EINVAL; - } -} - -static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) -{ - switch (format) { - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - return VOP2_AFBC_FMT_ARGB8888; - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - return VOP2_AFBC_FMT_RGB888; - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - return VOP2_AFBC_FMT_RGB565; - case DRM_FORMAT_NV12: - return VOP2_AFBC_FMT_YUV420; - case DRM_FORMAT_NV16: - return VOP2_AFBC_FMT_YUV422; - default: - return VOP2_AFBC_FMT_INVALID; - } - - return VOP2_AFBC_FMT_INVALID; -} - -static bool vop2_win_rb_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - case DRM_FORMAT_BGR888: - case DRM_FORMAT_BGR565: - return true; - default: - return false; - } -} - -static bool vop2_afbc_rb_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV24: - return true; - default: - return false; - } -} - -static bool vop2_afbc_uv_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV12: - case DRM_FORMAT_NV16: - return true; - default: - return false; - } -} - -static bool vop2_win_uv_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV12: - case DRM_FORMAT_NV16: - case DRM_FORMAT_NV24: - return true; - default: - return false; - } -} - -static bool vop2_win_dither_up(u32 format) -{ - switch (format) { - case DRM_FORMAT_BGR565: - case DRM_FORMAT_RGB565: - return true; - default: - return false; - } -} - -static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) -{ - /* - * FIXME: - * - * There is no media type for YUV444 output, - * so when out_mode is AAAA or P888, assume output is YUV444 on - * yuv format. - * - * From H/W testing, YUV444 mode need a rb swap. - */ - if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || - bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || - bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || - bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || - ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || - bus_format == MEDIA_BUS_FMT_YUV10_1X30) && - (output_mode == ROCKCHIP_OUT_MODE_AAAA || - output_mode == ROCKCHIP_OUT_MODE_P888))) - return true; - else - return false; -} - -static bool is_yuv_output(u32 bus_format) -{ - switch (bus_format) { - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_YUV10_1X30: - case MEDIA_BUS_FMT_UYYVYY8_0_5X24: - case MEDIA_BUS_FMT_UYYVYY10_0_5X30: - case MEDIA_BUS_FMT_YUYV8_2X8: - case MEDIA_BUS_FMT_YVYU8_2X8: - case MEDIA_BUS_FMT_UYVY8_2X8: - case MEDIA_BUS_FMT_VYUY8_2X8: - case MEDIA_BUS_FMT_YUYV8_1X16: - case MEDIA_BUS_FMT_YVYU8_1X16: - case MEDIA_BUS_FMT_UYVY8_1X16: - case MEDIA_BUS_FMT_VYUY8_1X16: - return true; - default: - return false; - } -} - -static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) -{ - int i; - - if (modifier == DRM_FORMAT_MOD_LINEAR) - return false; - - for (i = 0 ; i < plane->modifier_count; i++) - if (plane->modifiers[i] == modifier) - return true; - - return false; -} - -static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, - u64 modifier) -{ - struct vop2_win *win = to_vop2_win(plane); - struct vop2 *vop2 = win->vop2; - - if (modifier == DRM_FORMAT_MOD_INVALID) - return false; - - if (modifier == DRM_FORMAT_MOD_LINEAR) - return true; - - if (!rockchip_afbc(plane, modifier)) { - drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", - modifier); - - return false; - } - - return vop2_convert_afbc_format(format) >= 0; -} - -static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, - bool afbc_half_block_en) -{ - struct drm_rect *src = &pstate->src; - struct drm_framebuffer *fb = pstate->fb; - u32 bpp = fb->format->cpp[0] * 8; - u32 vir_width = (fb->pitches[0] << 3) / bpp; - u32 width = drm_rect_width(src) >> 16; - u32 height = drm_rect_height(src) >> 16; - u32 act_xoffset = src->x1 >> 16; - u32 act_yoffset = src->y1 >> 16; - u32 align16_crop = 0; - u32 align64_crop = 0; - u32 height_tmp; - u8 tx, ty; - u8 bottom_crop_line_num = 0; - - /* 16 pixel align */ - if (height & 0xf) - align16_crop = 16 - (height & 0xf); - - height_tmp = height + align16_crop; - - /* 64 pixel align */ - if (height_tmp & 0x3f) - align64_crop = 64 - (height_tmp & 0x3f); - - bottom_crop_line_num = align16_crop + align64_crop; - - switch (pstate->rotation & - (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | - DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { - case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: - tx = 16 - ((act_xoffset + width) & 0xf); - ty = bottom_crop_line_num - act_yoffset; - break; - case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: - tx = bottom_crop_line_num - act_yoffset; - ty = vir_width - width - act_xoffset; - break; - case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: - tx = act_yoffset; - ty = act_xoffset; - break; - case DRM_MODE_REFLECT_X: - tx = 16 - ((act_xoffset + width) & 0xf); - ty = act_yoffset; - break; - case DRM_MODE_REFLECT_Y: - tx = act_xoffset; - ty = bottom_crop_line_num - act_yoffset; - break; - case DRM_MODE_ROTATE_90: - tx = bottom_crop_line_num - act_yoffset; - ty = act_xoffset; - break; - case DRM_MODE_ROTATE_270: - tx = act_yoffset; - ty = vir_width - width - act_xoffset; - break; - case 0: - tx = act_xoffset; - ty = act_yoffset; - break; - } - - if (afbc_half_block_en) - ty &= 0x7f; - -#define TRANSFORM_XOFFSET GENMASK(7, 0) -#define TRANSFORM_YOFFSET GENMASK(23, 16) - return FIELD_PREP(TRANSFORM_XOFFSET, tx) | - FIELD_PREP(TRANSFORM_YOFFSET, ty); -} - -/* - * A Cluster window has 2048 x 16 line buffer, which can - * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. - * for Cluster_lb_mode register: - * 0: half mode, for plane input width range 2048 ~ 4096 - * 1: half mode, for cluster work at 2 * 2048 plane mode - * 2: half mode, for rotate_90/270 mode - * - */ -static int vop2_get_cluster_lb_mode(struct vop2_win *win, - struct drm_plane_state *pstate) -{ - if ((pstate->rotation & DRM_MODE_ROTATE_270) || - (pstate->rotation & DRM_MODE_ROTATE_90)) - return 2; - else - return 0; -} - -static u16 vop2_scale_factor(u32 src, u32 dst) -{ - u32 fac; - int shift; - - if (src == dst) - return 0; - - if (dst < 2) - return U16_MAX; - - if (src < 2) - return 0; - - if (src > dst) - shift = 12; - else - shift = 16; - - src--; - dst--; - - fac = DIV_ROUND_UP(src << shift, dst) - 1; - - if (fac > U16_MAX) - return U16_MAX; - - return fac; -} - -static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, - u32 src_w, u32 src_h, u32 dst_w, - u32 dst_h, u32 pixel_format) -{ - const struct drm_format_info *info; - u16 hor_scl_mode, ver_scl_mode; - u16 hscl_filter_mode, vscl_filter_mode; - u8 gt2 = 0; - u8 gt4 = 0; - u32 val; - - info = drm_format_info(pixel_format); - - if (src_h >= (4 * dst_h)) { - gt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { - gt2 = 1; - src_h >>= 1; - } - - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); - - if (hor_scl_mode == SCALE_UP) - hscl_filter_mode = VOP2_SCALE_UP_BIC; - else - hscl_filter_mode = VOP2_SCALE_DOWN_BIL; - - if (ver_scl_mode == SCALE_UP) - vscl_filter_mode = VOP2_SCALE_UP_BIL; - else - vscl_filter_mode = VOP2_SCALE_DOWN_BIL; - - /* - * RK3568 VOP Esmart/Smart dsp_w should be even pixel - * at scale down mode - */ - if (!(win->data->feature & WIN_FEATURE_AFBDC)) { - if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { - drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", - win->data->name, dst_w); - dst_w++; - } - } - - val = vop2_scale_factor(src_w, dst_w); - vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); - val = vop2_scale_factor(src_h, dst_h); - vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); - - vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); - vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); - - vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); - vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); - - if (vop2_cluster_window(win)) - return; - - vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); - vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); - - if (info->is_yuv) { - src_w /= info->hsub; - src_h /= info->vsub; - - gt4 = 0; - gt2 = 0; - - if (src_h >= (4 * dst_h)) { - gt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { - gt2 = 1; - src_h >>= 1; - } - - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); - - val = vop2_scale_factor(src_w, dst_w); - vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); - - val = vop2_scale_factor(src_h, dst_h); - vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); - - vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); - vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); - vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); - vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); - vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); - vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); - } -} - -static int vop2_convert_csc_mode(int csc_mode) -{ - switch (csc_mode) { - case V4L2_COLORSPACE_SMPTE170M: - case V4L2_COLORSPACE_470_SYSTEM_M: - case V4L2_COLORSPACE_470_SYSTEM_BG: - return CSC_BT601L; - case V4L2_COLORSPACE_REC709: - case V4L2_COLORSPACE_SMPTE240M: - case V4L2_COLORSPACE_DEFAULT: - return CSC_BT709L; - case V4L2_COLORSPACE_JPEG: - return CSC_BT601F; - case V4L2_COLORSPACE_BT2020: - return CSC_BT2020; - default: - return CSC_BT709L; - } -} - -/* - * colorspace path: - * Input Win csc Output - * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) - * RGB --> R2Y __/ - * - * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) - * RGB --> 709To2020->R2Y __/ - * - * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) - * RGB --> R2Y __/ - * - * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) - * RGB --> 709To2020->R2Y __/ - * - * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) - * RGB --> R2Y __/ - * - * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) - * RGB --> R2Y(601) __/ - * - * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) - * RGB --> bypass __/ - * - * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) - * - * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) - * - * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) - * - * 11. RGB --> bypass --> RGB_OUTPUT(709) - */ - -static void vop2_setup_csc_mode(struct vop2_video_port *vp, - struct vop2_win *win, - struct drm_plane_state *pstate) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); - int is_input_yuv = pstate->fb->format->is_yuv; - int is_output_yuv = is_yuv_output(vcstate->bus_format); - int input_csc = V4L2_COLORSPACE_DEFAULT; - int output_csc = vcstate->color_space; - bool r2y_en, y2r_en; - int csc_mode; - - if (is_input_yuv && !is_output_yuv) { - y2r_en = true; - r2y_en = false; - csc_mode = vop2_convert_csc_mode(input_csc); - } else if (!is_input_yuv && is_output_yuv) { - y2r_en = false; - r2y_en = true; - csc_mode = vop2_convert_csc_mode(output_csc); - } else { - y2r_en = false; - r2y_en = false; - csc_mode = false; - } - - vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); - vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); - vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); -} - -static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) -{ - struct vop2 *vop2 = vp->vop2; - - vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); - vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); -} - -static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) -{ - struct vop2 *vop2 = vp->vop2; - - vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); -} - -static int vop2_core_clks_prepare_enable(struct vop2 *vop2) -{ - int ret; - - ret = clk_prepare_enable(vop2->hclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(vop2->aclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); - goto err; - } - - return 0; -err: - clk_disable_unprepare(vop2->hclk); - - return ret; -} - -static void vop2_enable(struct vop2 *vop2) -{ - int ret; - - ret = pm_runtime_get_sync(vop2->dev); - if (ret < 0) { - drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); - return; - } - - ret = vop2_core_clks_prepare_enable(vop2); - if (ret) { - pm_runtime_put_sync(vop2->dev); - return; - } - - ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); - if (ret) { - drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); - return; - } - - if (vop2->data->soc_id == 3566) - vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); - - vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); - - /* - * Disable auto gating, this is a workaround to - * avoid display image shift when a window enabled. - */ - regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, - RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); - - vop2_writel(vop2, RK3568_SYS0_INT_CLR, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS0_INT_EN, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS1_INT_CLR, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS1_INT_EN, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -} - -static void vop2_disable(struct vop2 *vop2) -{ - rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); - - pm_runtime_put_sync(vop2->dev); - - clk_disable_unprepare(vop2->aclk); - clk_disable_unprepare(vop2->hclk); -} - -static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - int ret; - - vop2_lock(vop2); - - drm_crtc_vblank_off(crtc); - - /* - * Vop standby will take effect at end of current frame, - * if dsp hold valid irq happen, it means standby complete. - * - * we must wait standby complete when we want to disable aclk, - * if not, memory bus maybe dead. - */ - reinit_completion(&vp->dsp_hold_completion); - - vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); - - vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); - - ret = wait_for_completion_timeout(&vp->dsp_hold_completion, - msecs_to_jiffies(50)); - if (!ret) - drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); - - vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); - - clk_disable_unprepare(vp->dclk); - - vop2->enable_count--; - - if (!vop2->enable_count) - vop2_disable(vop2); - - vop2_unlock(vop2); - - if (crtc->state->event && !crtc->state->active) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - - crtc->state->event = NULL; - } -} - -static int vop2_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *astate) -{ - struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); - struct drm_framebuffer *fb = pstate->fb; - struct drm_crtc *crtc = pstate->crtc; - struct drm_crtc_state *cstate; - struct vop2_video_port *vp; - struct vop2 *vop2; - const struct vop2_data *vop2_data; - struct drm_rect *dest = &pstate->dst; - struct drm_rect *src = &pstate->src; - int min_scale = FRAC_16_16(1, 8); - int max_scale = FRAC_16_16(8, 1); - int format; - int ret; - - if (!crtc) - return 0; - - vp = to_vop2_video_port(crtc); - vop2 = vp->vop2; - vop2_data = vop2->data; - - cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); - if (WARN_ON(!cstate)) - return -EINVAL; - - ret = drm_atomic_helper_check_plane_state(pstate, cstate, - min_scale, max_scale, - true, true); - if (ret) - return ret; - - if (!pstate->visible) - return 0; - - format = vop2_convert_format(fb->format->format); - if (format < 0) - return format; - - if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || - drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { - drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", - drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, - drm_rect_width(dest), drm_rect_height(dest)); - pstate->visible = false; - return 0; - } - - if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || - drm_rect_height(src) >> 16 > vop2_data->max_input.height) { - drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", - drm_rect_width(src) >> 16, - drm_rect_height(src) >> 16, - vop2_data->max_input.width, - vop2_data->max_input.height); - return -EINVAL; - } - - /* - * Src.x1 can be odd when do clip, but yuv plane start point - * need align with 2 pixel. - */ - if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { - drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); - return -EINVAL; - } - - return 0; -} - -static void vop2_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) -{ - struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); - struct vop2_win *win = to_vop2_win(plane); - struct vop2 *vop2 = win->vop2; - - drm_dbg(vop2->drm, "%s disable\n", win->data->name); - - if (!old_pstate->crtc) - return; - - vop2_win_disable(win); - vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); -} - -/* - * The color key is 10 bit, so all format should - * convert to 10 bit here. - */ -static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) -{ - struct drm_plane_state *pstate = plane->state; - struct drm_framebuffer *fb = pstate->fb; - struct vop2_win *win = to_vop2_win(plane); - u32 color_key_en = 0; - u32 r = 0; - u32 g = 0; - u32 b = 0; - - if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { - vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); - return; - } - - switch (fb->format->format) { - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - r = (color_key & 0xf800) >> 11; - g = (color_key & 0x7e0) >> 5; - b = (color_key & 0x1f); - r <<= 5; - g <<= 4; - b <<= 5; - color_key_en = 1; - break; - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - r = (color_key & 0xff0000) >> 16; - g = (color_key & 0xff00) >> 8; - b = (color_key & 0xff); - r <<= 2; - g <<= 2; - b <<= 2; - color_key_en = 1; - break; - } - - vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); - vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); -} - -static void vop2_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) -{ - struct drm_plane_state *pstate = plane->state; - struct drm_crtc *crtc = pstate->crtc; - struct vop2_win *win = to_vop2_win(plane); - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; - struct vop2 *vop2 = win->vop2; - struct drm_framebuffer *fb = pstate->fb; - u32 bpp = fb->format->cpp[0] * 8; - u32 actual_w, actual_h, dsp_w, dsp_h; - u32 act_info, dsp_info; - u32 format; - u32 afbc_format; - u32 rb_swap; - u32 uv_swap; - struct drm_rect *src = &pstate->src; - struct drm_rect *dest = &pstate->dst; - u32 afbc_tile_num; - u32 transform_offset; - bool dither_up; - bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; - bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; - bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; - bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; - struct rockchip_gem_object *rk_obj; - unsigned long offset; - bool afbc_en; - dma_addr_t yrgb_mst; - dma_addr_t uv_mst; - - /* - * can't update plane when vop2 is disabled. - */ - if (WARN_ON(!crtc)) - return; - - if (!pstate->visible) { - vop2_plane_atomic_disable(plane, state); - return; - } - - afbc_en = rockchip_afbc(plane, fb->modifier); - - offset = (src->x1 >> 16) * fb->format->cpp[0]; - - /* - * AFBC HDR_PTR must set to the zero offset of the framebuffer. - */ - if (afbc_en) - offset = 0; - else if (pstate->rotation & DRM_MODE_REFLECT_Y) - offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; - else - offset += (src->y1 >> 16) * fb->pitches[0]; - - rk_obj = to_rockchip_obj(fb->obj[0]); - - yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; - if (fb->format->is_yuv) { - int hsub = fb->format->hsub; - int vsub = fb->format->vsub; - - offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; - offset += (src->y1 >> 16) * fb->pitches[1] / vsub; - - if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) - offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; - - rk_obj = to_rockchip_obj(fb->obj[0]); - uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; - } - - actual_w = drm_rect_width(src) >> 16; - actual_h = drm_rect_height(src) >> 16; - dsp_w = drm_rect_width(dest); - - if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { - drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", - vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); - dsp_w = adjusted_mode->hdisplay - dest->x1; - if (dsp_w < 4) - dsp_w = 4; - actual_w = dsp_w * actual_w / drm_rect_width(dest); - } - - dsp_h = drm_rect_height(dest); - - if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { - drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", - vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); - dsp_h = adjusted_mode->vdisplay - dest->y1; - if (dsp_h < 4) - dsp_h = 4; - actual_h = dsp_h * actual_h / drm_rect_height(dest); - } - - /* - * This is workaround solution for IC design: - * esmart can't support scale down when actual_w % 16 == 1. - */ - if (!(win->data->feature & WIN_FEATURE_AFBDC)) { - if (actual_w > dsp_w && (actual_w & 0xf) == 1) { - drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", - vp->id, win->data->name, actual_w); - actual_w -= 1; - } - } - - if (afbc_en && actual_w % 4) { - drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", - vp->id, win->data->name, actual_w); - actual_w = ALIGN_DOWN(actual_w, 4); - } - - act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); - dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); - - format = vop2_convert_format(fb->format->format); - - drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", - vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, - dest->x1, dest->y1, - &fb->format->format, - afbc_en ? "AFBC" : "", &yrgb_mst); - - if (afbc_en) { - u32 stride; - - /* the afbc superblock is 16 x 16 */ - afbc_format = vop2_convert_afbc_format(fb->format->format); - - /* Enable color transform for YTR */ - if (fb->modifier & AFBC_FORMAT_MOD_YTR) - afbc_format |= (1 << 4); - - afbc_tile_num = ALIGN(actual_w, 16) >> 4; - - /* - * AFBC pic_vir_width is count by pixel, this is different - * with WIN_VIR_STRIDE. - */ - stride = (fb->pitches[0] << 3) / bpp; - if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) - drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n", - vp->id, win->data->name, stride); - - rb_swap = vop2_afbc_rb_swap(fb->format->format); - uv_swap = vop2_afbc_uv_swap(fb->format->format); - /* - * This is a workaround for crazy IC design, Cluster - * and Esmart/Smart use different format configuration map: - * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. - * - * This is one thing we can make the convert simple: - * AFBCD decode all the YUV data to YUV444. So we just - * set all the yuv 10 bit to YUV444_10. - */ - if (fb->format->is_yuv && bpp == 10) - format = VOP2_CLUSTER_YUV444_10; - - if (vop2_cluster_window(win)) - vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); - vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); - vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); - vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); - vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); - vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); - if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); - transform_offset = vop2_afbc_transform_offset(pstate, false); - } else { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); - transform_offset = vop2_afbc_transform_offset(pstate, true); - } - vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); - vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); - vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); - vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); - vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); - vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); - } else { - vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); - } - - vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); - - if (rotate_90 || rotate_270) { - act_info = swahw32(act_info); - actual_w = drm_rect_height(src) >> 16; - actual_h = drm_rect_width(src) >> 16; - } - - vop2_win_write(win, VOP2_WIN_FORMAT, format); - vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); - - rb_swap = vop2_win_rb_swap(fb->format->format); - vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); - if (!vop2_cluster_window(win)) { - uv_swap = vop2_win_uv_swap(fb->format->format); - vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); - } - - if (fb->format->is_yuv) { - vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); - vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); - } - - vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); - if (!vop2_cluster_window(win)) - vop2_plane_setup_color_key(plane, 0); - vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); - vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); - vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); - - vop2_setup_csc_mode(vp, win, pstate); - - dither_up = vop2_win_dither_up(fb->format->format); - vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); - - vop2_win_write(win, VOP2_WIN_ENABLE, 1); - - if (vop2_cluster_window(win)) { - int lb_mode = vop2_get_cluster_lb_mode(win, pstate); - - vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); - vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); - } -} - -static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { - .atomic_check = vop2_plane_atomic_check, - .atomic_update = vop2_plane_atomic_update, - .atomic_disable = vop2_plane_atomic_disable, -}; - -static const struct drm_plane_funcs vop2_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, - .reset = drm_atomic_helper_plane_reset, - .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, - .format_mod_supported = rockchip_vop2_mod_supported, -}; - -static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); - - return 0; -} - -static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); -} - -static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | - CRTC_STEREO_DOUBLE); - - return true; -} - -static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - - switch (vcstate->bus_format) { - case MEDIA_BUS_FMT_RGB565_1X16: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; - break; - case MEDIA_BUS_FMT_RGB666_1X18: - case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; - *dsp_ctrl |= RGB888_TO_RGB666; - break; - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_UYYVYY8_0_5X24: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; - break; - default: - break; - } - - if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) - *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; - - *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, - DITHER_DOWN_ALLEGRO); -} - -static void vop2_post_config(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_display_mode *mode = &crtc->state->adjusted_mode; - u16 vtotal = mode->crtc_vtotal; - u16 hdisplay = mode->crtc_hdisplay; - u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; - u16 vdisplay = mode->crtc_vdisplay; - u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; - u32 left_margin = 100, right_margin = 100; - u32 top_margin = 100, bottom_margin = 100; - u16 hsize = hdisplay * (left_margin + right_margin) / 200; - u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; - u16 hact_end, vact_end; - u32 val; - - vsize = rounddown(vsize, 2); - hsize = rounddown(hsize, 2); - hact_st += hdisplay * (100 - left_margin) / 200; - hact_end = hact_st + hsize; - val = hact_st << 16; - val |= hact_end; - vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); - vact_st += vdisplay * (100 - top_margin) / 200; - vact_end = vact_st + vsize; - val = vact_st << 16; - val |= vact_end; - vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); - val = scl_cal_scale2(vdisplay, vsize) << 16; - val |= scl_cal_scale2(hdisplay, hsize); - vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); - - val = 0; - if (hdisplay != hsize) - val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; - if (vdisplay != vsize) - val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; - vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); - - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - u16 vact_st_f1 = vtotal + vact_st + 1; - u16 vact_end_f1 = vact_st_f1 + vsize; - - val = vact_st_f1 << 16 | vact_end_f1; - vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); - } - - vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); -} - -static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, - u32 polflags) -{ - struct vop2 *vop2 = vp->vop2; - u32 die, dip; - - die = vop2_readl(vop2, RK3568_DSP_IF_EN); - dip = vop2_readl(vop2, RK3568_DSP_IF_POL); - - switch (id) { - case ROCKCHIP_VOP2_EP_RGB0: - die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_RGB | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); - if (polflags & POLFLAG_DCLK_INV) - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); - else - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); - break; - case ROCKCHIP_VOP2_EP_HDMI0: - die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_HDMI | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); - break; - case ROCKCHIP_VOP2_EP_EDP0: - die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_EDP | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); - break; - case ROCKCHIP_VOP2_EP_MIPI0: - die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_MIPI1: - die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_LVDS0: - die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_LVDS1: - die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); - break; - default: - drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); - return; - }; - - dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; - - vop2_writel(vop2, RK3568_DSP_IF_EN, die); - vop2_writel(vop2, RK3568_DSP_IF_POL, dip); -} - -static int us_to_vertical_line(struct drm_display_mode *mode, int us) -{ - return us * mode->clock / mode->htotal / 1000; -} - -static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - const struct vop2_data *vop2_data = vop2->data; - const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; - struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - struct drm_display_mode *mode = &crtc->state->adjusted_mode; - unsigned long clock = mode->crtc_clock * 1000; - u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; - u16 hdisplay = mode->crtc_hdisplay; - u16 htotal = mode->crtc_htotal; - u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; - u16 hact_end = hact_st + hdisplay; - u16 vdisplay = mode->crtc_vdisplay; - u16 vtotal = mode->crtc_vtotal; - u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; - u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; - u16 vact_end = vact_st + vdisplay; - u8 out_mode; - u32 dsp_ctrl = 0; - int act_end; - u32 val, polflags; - int ret; - struct drm_encoder *encoder; - - drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", - hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", - drm_mode_vrefresh(mode), vcstate->output_type, vp->id); - - vop2_lock(vop2); - - ret = clk_prepare_enable(vp->dclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", - vp->id, ret); - return; - } - - if (!vop2->enable_count) - vop2_enable(vop2); - - vop2->enable_count++; - - vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); - - polflags = 0; - if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - polflags |= POLFLAG_DCLK_INV; - if (mode->flags & DRM_MODE_FLAG_PHSYNC) - polflags |= BIT(HSYNC_POSITIVE); - if (mode->flags & DRM_MODE_FLAG_PVSYNC) - polflags |= BIT(VSYNC_POSITIVE); - - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - - rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); - } - - if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && - !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) - out_mode = ROCKCHIP_OUT_MODE_P888; - else - out_mode = vcstate->output_mode; - - dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); - - if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; - - if (is_yuv_output(vcstate->bus_format)) - dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; - - vop2_dither_setup(crtc, &dsp_ctrl); - - vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); - val = hact_st << 16; - val |= hact_end; - vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); - - val = vact_st << 16; - val |= vact_end; - vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); - - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - u16 vact_st_f1 = vtotal + vact_st + 1; - u16 vact_end_f1 = vact_st_f1 + vdisplay; - - val = vact_st_f1 << 16 | vact_end_f1; - vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); - - val = vtotal << 16 | (vtotal + vsync_len); - vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; - dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; - vtotal += vtotal + 1; - act_end = vact_end_f1; - } else { - act_end = vact_end; - } - - vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), - (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); - - vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); - - if (mode->flags & DRM_MODE_FLAG_DBLCLK) { - dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; - clock *= 2; - } - - vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); - - clk_set_rate(vp->dclk, clock); - - vop2_post_config(crtc); - - vop2_cfg_done(vp); - - vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); - - drm_crtc_vblank_on(crtc); - - vop2_unlock(vop2); -} - -static int vop2_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_plane *plane; - int nplanes = 0; - struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - - drm_atomic_crtc_state_for_each_plane(plane, crtc_state) - nplanes++; - - if (nplanes > vp->nlayers) - return -EINVAL; - - return 0; -} - -static bool is_opaque(u16 alpha) -{ - return (alpha >> 8) == 0xff; -} - -static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config, - struct vop2_alpha *alpha) -{ - int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; - int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; - int src_color_mode = alpha_config->src_premulti_en ? - ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; - int dst_color_mode = alpha_config->dst_premulti_en ? - ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; - - alpha->src_color_ctrl.val = 0; - alpha->dst_color_ctrl.val = 0; - alpha->src_alpha_ctrl.val = 0; - alpha->dst_alpha_ctrl.val = 0; - - if (!alpha_config->src_pixel_alpha_en) - alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; - else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en) - alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX; - else - alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; - - alpha->src_color_ctrl.bits.alpha_en = 1; - - if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) { - alpha->src_color_ctrl.bits.color_mode = src_color_mode; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; - } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) { - alpha->src_color_ctrl.bits.color_mode = src_color_mode; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE; - } else { - alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; - } - alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8; - alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - - alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; - alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8; - alpha->dst_color_ctrl.bits.color_mode = dst_color_mode; - alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; - - alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode; - alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE; - - alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en) - alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX; - else - alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; - alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION; - alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; -} - -static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) -{ - struct vop2_video_port *vp; - int used_layer = 0; - int i; - - for (i = 0; i < port_id; i++) { - vp = &vop2->vps[i]; - used_layer += hweight32(vp->win_mask); - } - - return used_layer; -} - -static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) -{ - u32 offset = (main_win->data->phys_id * 0x10); - struct vop2_alpha_config alpha_config; - struct vop2_alpha alpha; - struct drm_plane_state *bottom_win_pstate; - bool src_pixel_alpha_en = false; - u16 src_glb_alpha_val, dst_glb_alpha_val; - bool premulti_en = false; - bool swap = false; - - /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */ - bottom_win_pstate = main_win->base.state; - src_glb_alpha_val = 0; - dst_glb_alpha_val = main_win->base.state->alpha; - - if (!bottom_win_pstate->fb) - return; - - alpha_config.src_premulti_en = premulti_en; - alpha_config.dst_premulti_en = false; - alpha_config.src_pixel_alpha_en = src_pixel_alpha_en; - alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ - alpha_config.src_glb_alpha_value = src_glb_alpha_val; - alpha_config.dst_glb_alpha_value = dst_glb_alpha_val; - vop2_parse_alpha(&alpha_config, &alpha); - - alpha.src_color_ctrl.bits.src_dst_swap = swap; - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); -} - -static void vop2_setup_alpha(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - struct drm_framebuffer *fb; - struct vop2_alpha_config alpha_config; - struct vop2_alpha alpha; - struct drm_plane *plane; - int pixel_alpha_en; - int premulti_en, gpremulti_en = 0; - int mixer_id; - u32 offset; - bool bottom_layer_alpha_en = false; - u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; - - mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); - alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ - - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - - if (plane->state->normalized_zpos == 0 && - !is_opaque(plane->state->alpha) && - !vop2_cluster_window(win)) { - /* - * If bottom layer have global alpha effect [except cluster layer, - * because cluster have deal with bottom layer global alpha value - * at cluster mix], bottom layer mix need deal with global alpha. - */ - bottom_layer_alpha_en = true; - dst_global_alpha = plane->state->alpha; - } - } - - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - int zpos = plane->state->normalized_zpos; - - if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) - premulti_en = 1; - else - premulti_en = 0; - - plane = &win->base; - fb = plane->state->fb; - - pixel_alpha_en = fb->format->has_alpha; - - alpha_config.src_premulti_en = premulti_en; - - if (bottom_layer_alpha_en && zpos == 1) { - gpremulti_en = premulti_en; - /* Cd = Cs + (1 - As) * Cd * Agd */ - alpha_config.dst_premulti_en = false; - alpha_config.src_pixel_alpha_en = pixel_alpha_en; - alpha_config.src_glb_alpha_value = plane->state->alpha; - alpha_config.dst_glb_alpha_value = dst_global_alpha; - } else if (vop2_cluster_window(win)) { - /* Mix output data only have pixel alpha */ - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = true; - alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - } else { - /* Cd = Cs + (1 - As) * Cd */ - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = pixel_alpha_en; - alpha_config.src_glb_alpha_value = plane->state->alpha; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - } - - vop2_parse_alpha(&alpha_config, &alpha); - - offset = (mixer_id + zpos - 1) * 0x10; - vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); - } - - if (vp->id == 0) { - if (bottom_layer_alpha_en) { - /* Transfer pixel alpha to hdr mix */ - alpha_config.src_premulti_en = gpremulti_en; - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = true; - alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - vop2_parse_alpha(&alpha_config, &alpha); - - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, - alpha.dst_alpha_ctrl.val); - } else { - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); - } - } -} - -static void vop2_setup_layer_mixer(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - struct drm_plane *plane; - u32 layer_sel = 0; - u32 port_sel; - unsigned int nlayer, ofs; - struct drm_display_mode *adjusted_mode; - u16 hsync_len; - u16 hdisplay; - u32 bg_dly; - u32 pre_scan_dly; - int i; - struct vop2_video_port *vp0 = &vop2->vps[0]; - struct vop2_video_port *vp1 = &vop2->vps[1]; - struct vop2_video_port *vp2 = &vop2->vps[2]; - - adjusted_mode = &vp->crtc.state->adjusted_mode; - hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; - hdisplay = adjusted_mode->crtc_hdisplay; - - bg_dly = vp->data->pre_scan_max_dly[3]; - vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), - FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); - - pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; - vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); - - vop2_writel(vop2, RK3568_OVL_CTRL, 0); - port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); - port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; - - if (vp0->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, - vp0->nlayers - 1); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); - - if (vp1->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, - (vp0->nlayers + vp1->nlayers - 1)); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); - - if (vp2->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, - (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); - - layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); - - ofs = 0; - for (i = 0; i < vp->id; i++) - ofs += vop2->vps[i].nlayers; - - nlayer = 0; - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_CLUSTER0: - port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); - break; - case ROCKCHIP_VOP2_CLUSTER1: - port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); - break; - case ROCKCHIP_VOP2_ESMART0: - port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); - break; - case ROCKCHIP_VOP2_ESMART1: - port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); - break; - case ROCKCHIP_VOP2_SMART0: - port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); - break; - case ROCKCHIP_VOP2_SMART1: - port_sel &= ~RK3568_OVL_PORT_SEL__SMART1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); - break; - } - - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, - 0x7); - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, - win->data->layer_sel_id); - nlayer++; - } - - /* configure unused layers to 0x5 (reserved) */ - for (; nlayer < vp->nlayers; nlayer++) { - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); - } - - vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); - vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); - vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); -} - -static void vop2_setup_dly_for_windows(struct vop2 *vop2) -{ - struct vop2_win *win; - int i = 0; - u32 cdly = 0, sdly = 0; - - for (i = 0; i < vop2->data->win_size; i++) { - u32 dly; - - win = &vop2->win[i]; - dly = win->delay; - - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_CLUSTER0: - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); - break; - case ROCKCHIP_VOP2_CLUSTER1: - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); - break; - case ROCKCHIP_VOP2_ESMART0: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); - break; - case ROCKCHIP_VOP2_ESMART1: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); - break; - case ROCKCHIP_VOP2_SMART0: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); - break; - case ROCKCHIP_VOP2_SMART1: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); - break; - } - } - - vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); - vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); -} - -static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - struct drm_plane *plane; - - vp->win_mask = 0; - - drm_atomic_crtc_for_each_plane(plane, crtc) { - struct vop2_win *win = to_vop2_win(plane); - - win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT]; - - vp->win_mask |= BIT(win->data->phys_id); - - if (vop2_cluster_window(win)) - vop2_setup_cluster_alpha(vop2, win); - } - - if (!vp->win_mask) - return; - - vop2_setup_layer_mixer(vp); - vop2_setup_alpha(vp); - vop2_setup_dly_for_windows(vop2); -} - -static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_post_config(crtc); - - vop2_cfg_done(vp); - - spin_lock_irq(&crtc->dev->event_lock); - - if (crtc->state->event) { - WARN_ON(drm_crtc_vblank_get(crtc)); - vp->event = crtc->state->event; - crtc->state->event = NULL; - } - - spin_unlock_irq(&crtc->dev->event_lock); -} - -static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { - .mode_fixup = vop2_crtc_mode_fixup, - .atomic_check = vop2_crtc_atomic_check, - .atomic_begin = vop2_crtc_atomic_begin, - .atomic_flush = vop2_crtc_atomic_flush, - .atomic_enable = vop2_crtc_atomic_enable, - .atomic_disable = vop2_crtc_atomic_disable, -}; - -static void vop2_crtc_reset(struct drm_crtc *crtc) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - - if (crtc->state) { - __drm_atomic_helper_crtc_destroy_state(crtc->state); - kfree(vcstate); - } - - vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL); - if (!vcstate) - return; - - crtc->state = &vcstate->base; - crtc->state->crtc = crtc; -} - -static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) -{ - struct rockchip_crtc_state *vcstate, *old_vcstate; - - old_vcstate = to_rockchip_crtc_state(crtc->state); - - vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL); - if (!vcstate) - return NULL; - - __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); - - return &vcstate->base; -} - -static void vop2_crtc_destroy_state(struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); - - __drm_atomic_helper_crtc_destroy_state(&vcstate->base); - kfree(vcstate); -} - -static const struct drm_crtc_funcs vop2_crtc_funcs = { - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .destroy = drm_crtc_cleanup, - .reset = vop2_crtc_reset, - .atomic_duplicate_state = vop2_crtc_duplicate_state, - .atomic_destroy_state = vop2_crtc_destroy_state, - .enable_vblank = vop2_crtc_enable_vblank, - .disable_vblank = vop2_crtc_disable_vblank, -}; - -static irqreturn_t vop2_isr(int irq, void *data) -{ - struct vop2 *vop2 = data; - const struct vop2_data *vop2_data = vop2->data; - u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; - int ret = IRQ_NONE; - int i; - - /* - * The irq is shared with the iommu. If the runtime-pm state of the - * vop2-device is disabled the irq has to be targeted at the iommu. - */ - if (!pm_runtime_get_if_in_use(vop2->dev)) - return IRQ_NONE; - - for (i = 0; i < vop2_data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - struct drm_crtc *crtc = &vp->crtc; - u32 irqs; - - irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); - vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); - - if (irqs & VP_INT_DSP_HOLD_VALID) { - complete(&vp->dsp_hold_completion); - ret = IRQ_HANDLED; - } - - if (irqs & VP_INT_FS_FIELD) { - drm_crtc_handle_vblank(crtc); - spin_lock(&crtc->dev->event_lock); - if (vp->event) { - u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); - - if (!(val & BIT(vp->id))) { - drm_crtc_send_vblank_event(crtc, vp->event); - vp->event = NULL; - drm_crtc_vblank_put(crtc); - } - } - spin_unlock(&crtc->dev->event_lock); - - ret = IRQ_HANDLED; - } - - if (irqs & VP_INT_POST_BUF_EMPTY) { - drm_err_ratelimited(vop2->drm, - "POST_BUF_EMPTY irq err at vp%d\n", - vp->id); - ret = IRQ_HANDLED; - } - } - - axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); - vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); - axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); - vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); - - for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { - if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { - drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); - ret = IRQ_HANDLED; - } - } - - pm_runtime_put(vop2->dev); - - return ret; -} - -static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, - unsigned long possible_crtcs) -{ - const struct vop2_win_data *win_data = win->data; - unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE); - int ret; - - ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, - &vop2_plane_funcs, win_data->formats, - win_data->nformats, - win_data->format_modifiers, - win->type, win_data->name); - if (ret) { - drm_err(vop2->drm, "failed to initialize plane %d\n", ret); - return ret; - } - - drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); - - if (win->data->supported_rotations) - drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, - DRM_MODE_ROTATE_0 | - win->data->supported_rotations); - drm_plane_create_alpha_property(&win->base); - drm_plane_create_blend_mode_property(&win->base, blend_caps); - drm_plane_create_zpos_property(&win->base, win->win_id, 0, - vop2->registered_num_wins - 1); - - return 0; -} - -static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) -{ - int i; - - for (i = 0; i < vop2->data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - - if (!vp->crtc.port) - continue; - if (vp->primary_plane) - continue; - - return vp; - } - - return NULL; -} - -#define NR_LAYERS 6 - -static int vop2_create_crtc(struct vop2 *vop2) -{ - const struct vop2_data *vop2_data = vop2->data; - struct drm_device *drm = vop2->drm; - struct device *dev = vop2->dev; - struct drm_plane *plane; - struct device_node *port; - struct vop2_video_port *vp; - int i, nvp, nvps = 0; - int ret; - - for (i = 0; i < vop2_data->nr_vps; i++) { - const struct vop2_video_port_data *vp_data; - struct device_node *np; - char dclk_name[9]; - - vp_data = &vop2_data->vp[i]; - vp = &vop2->vps[i]; - vp->vop2 = vop2; - vp->id = vp_data->id; - vp->regs = vp_data->regs; - vp->data = vp_data; - - snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); - vp->dclk = devm_clk_get(vop2->dev, dclk_name); - if (IS_ERR(vp->dclk)) { - drm_err(vop2->drm, "failed to get %s\n", dclk_name); - return PTR_ERR(vp->dclk); - } - - np = of_graph_get_remote_node(dev->of_node, i, -1); - if (!np) { - drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); - continue; - } - of_node_put(np); - - port = of_graph_get_port_by_id(dev->of_node, i); - if (!port) { - drm_err(vop2->drm, "no port node found for video_port%d\n", i); - return -ENOENT; - } - - vp->crtc.port = port; - nvps++; - } - - nvp = 0; - for (i = 0; i < vop2->registered_num_wins; i++) { - struct vop2_win *win = &vop2->win[i]; - u32 possible_crtcs; - - if (vop2->data->soc_id == 3566) { - /* - * On RK3566 these windows don't have an independent - * framebuffer. They share the framebuffer with smart0, - * esmart0 and cluster0 respectively. - */ - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_SMART1: - case ROCKCHIP_VOP2_ESMART1: - case ROCKCHIP_VOP2_CLUSTER1: - continue; - } - } - - if (win->type == DRM_PLANE_TYPE_PRIMARY) { - vp = find_vp_without_primary(vop2); - if (vp) { - possible_crtcs = BIT(nvp); - vp->primary_plane = win; - nvp++; - } else { - /* change the unused primary window to overlay window */ - win->type = DRM_PLANE_TYPE_OVERLAY; - } - } - - if (win->type == DRM_PLANE_TYPE_OVERLAY) - possible_crtcs = (1 << nvps) - 1; - - ret = vop2_plane_init(vop2, win, possible_crtcs); - if (ret) { - drm_err(vop2->drm, "failed to init plane %s: %d\n", - win->data->name, ret); - return ret; - } - } - - for (i = 0; i < vop2_data->nr_vps; i++) { - vp = &vop2->vps[i]; - - if (!vp->crtc.port) - continue; - - plane = &vp->primary_plane->base; - - ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, - &vop2_crtc_funcs, - "video_port%d", vp->id); - if (ret) { - drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); - return ret; - } - - drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); - - init_completion(&vp->dsp_hold_completion); - } - - /* - * On the VOP2 it's very hard to change the number of layers on a VP - * during runtime, so we distribute the layers equally over the used - * VPs - */ - for (i = 0; i < vop2->data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - - if (vp->crtc.port) - vp->nlayers = NR_LAYERS / nvps; - } - - return 0; -} - -static void vop2_destroy_crtc(struct drm_crtc *crtc) -{ - of_node_put(crtc->port); - - /* - * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() - * references the CRTC. - */ - drm_crtc_cleanup(crtc); -} - -static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { - [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), - [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), - [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), - [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), - [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), - [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), - [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), - [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), - [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), - [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), - [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), - [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), - [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), - [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), - [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), - - /* Scale */ - [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), - [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), - [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), - [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), - [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), - [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), - [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), - - /* cluster regs */ - [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), - [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), - [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), - - /* afbc regs */ - [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), - [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), - [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), - [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), - [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), - [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), - [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), - [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), - [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), - [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), - [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), - [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), - [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), - [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), - [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), - [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), - [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, - [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, - [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, - [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, - [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, -}; - -static int vop2_cluster_init(struct vop2_win *win) -{ - struct vop2 *vop2 = win->vop2; - struct reg_field *cluster_regs; - int ret, i; - - cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), - GFP_KERNEL); - if (!cluster_regs) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) - if (cluster_regs[i].reg != 0xffffffff) - cluster_regs[i].reg += win->offset; - - ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, - cluster_regs, - ARRAY_SIZE(vop2_cluster_regs)); - - kfree(cluster_regs); - - return ret; -}; - -static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { - [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), - [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), - [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), - [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), - [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), - [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), - [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), - [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), - [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), - [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), - [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), - [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), - [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), - [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), - [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), - [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), - [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), - [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), - [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), - - /* Scale */ - [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), - [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), - [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), - [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), - [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), - [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), - [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), - [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), - [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), - [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), - [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), - [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), - [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), - [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), - [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), - [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), - [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), - [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, - [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, - [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, -}; - -static int vop2_esmart_init(struct vop2_win *win) -{ - struct vop2 *vop2 = win->vop2; - struct reg_field *esmart_regs; - int ret, i; - - esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), - GFP_KERNEL); - if (!esmart_regs) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) - if (esmart_regs[i].reg != 0xffffffff) - esmart_regs[i].reg += win->offset; - - ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, - esmart_regs, - ARRAY_SIZE(vop2_esmart_regs)); - - kfree(esmart_regs); - - return ret; -}; - -static int vop2_win_init(struct vop2 *vop2) -{ - const struct vop2_data *vop2_data = vop2->data; - struct vop2_win *win; - int i, ret; - - for (i = 0; i < vop2_data->win_size; i++) { - const struct vop2_win_data *win_data = &vop2_data->win[i]; - - win = &vop2->win[i]; - win->data = win_data; - win->type = win_data->type; - win->offset = win_data->base; - win->win_id = i; - win->vop2 = vop2; - if (vop2_cluster_window(win)) - ret = vop2_cluster_init(win); - else - ret = vop2_esmart_init(win); - if (ret) - return ret; - } - - vop2->registered_num_wins = vop2_data->win_size; - - return 0; -} - -/* - * The window registers are only updated when config done is written. - * Until that they read back the old value. As we read-modify-write - * these registers mark them as non-volatile. This makes sure we read - * the new values from the regmap register cache. - */ -static const struct regmap_range vop2_nonvolatile_range[] = { - regmap_reg_range(0x1000, 0x23ff), -}; - -static const struct regmap_access_table vop2_volatile_table = { - .no_ranges = vop2_nonvolatile_range, - .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), -}; - -static const struct regmap_config vop2_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x3000, - .name = "vop2", - .volatile_table = &vop2_volatile_table, - .cache_type = REGCACHE_RBTREE, -}; - -static int vop2_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - const struct vop2_data *vop2_data; - struct drm_device *drm = data; - struct vop2 *vop2; - struct resource *res; - size_t alloc_size; - int ret; - - vop2_data = of_device_get_match_data(dev); - if (!vop2_data) - return -ENODEV; - - /* Allocate vop2 struct and its vop2_win array */ - alloc_size = sizeof(*vop2) + sizeof(*vop2->win) * vop2_data->win_size; - vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); - if (!vop2) - return -ENOMEM; - - vop2->dev = dev; - vop2->data = vop2_data; - vop2->drm = drm; - - dev_set_drvdata(dev, vop2); - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); - if (!res) { - drm_err(vop2->drm, "failed to get vop2 register byname\n"); - return -EINVAL; - } - - vop2->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(vop2->regs)) - return PTR_ERR(vop2->regs); - vop2->len = resource_size(res); - - vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); - - ret = vop2_win_init(vop2); - if (ret) - return ret; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut"); - if (res) { - vop2->lut_regs = devm_ioremap_resource(dev, res); - if (IS_ERR(vop2->lut_regs)) - return PTR_ERR(vop2->lut_regs); - } - - vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); - - vop2->hclk = devm_clk_get(vop2->dev, "hclk"); - if (IS_ERR(vop2->hclk)) { - drm_err(vop2->drm, "failed to get hclk source\n"); - return PTR_ERR(vop2->hclk); - } - - vop2->aclk = devm_clk_get(vop2->dev, "aclk"); - if (IS_ERR(vop2->aclk)) { - drm_err(vop2->drm, "failed to get aclk source\n"); - return PTR_ERR(vop2->aclk); - } - - vop2->irq = platform_get_irq(pdev, 0); - if (vop2->irq < 0) { - drm_err(vop2->drm, "cannot find irq for vop2\n"); - return vop2->irq; - } - - mutex_init(&vop2->vop2_lock); - - ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); - if (ret) - return ret; - - ret = vop2_create_crtc(vop2); - if (ret) - return ret; - - rockchip_drm_dma_init_device(vop2->drm, vop2->dev); - - pm_runtime_enable(&pdev->dev); - - return 0; -} - -static void vop2_unbind(struct device *dev, struct device *master, void *data) -{ - struct vop2 *vop2 = dev_get_drvdata(dev); - struct drm_device *drm = vop2->drm; - struct list_head *plane_list = &drm->mode_config.plane_list; - struct list_head *crtc_list = &drm->mode_config.crtc_list; - struct drm_crtc *crtc, *tmpc; - struct drm_plane *plane, *tmpp; - - pm_runtime_disable(dev); - - list_for_each_entry_safe(plane, tmpp, plane_list, head) - drm_plane_cleanup(plane); - - list_for_each_entry_safe(crtc, tmpc, crtc_list, head) - vop2_destroy_crtc(crtc); -} - -const struct component_ops vop2_component_ops = { - .bind = vop2_bind, - .unbind = vop2_unbind, -}; -EXPORT_SYMBOL_GPL(vop2_component_ops); diff --git a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h deleted file mode 100644 index c727093a0..000000000 --- a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ /dev/null @@ -1,477 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Author:Mark Yao - */ - -#ifndef _ROCKCHIP_DRM_VOP2_H -#define _ROCKCHIP_DRM_VOP2_H - -#include "rockchip_drm_vop.h" - -#include -#include - -#define VOP_FEATURE_OUTPUT_10BIT BIT(0) - -#define WIN_FEATURE_AFBDC BIT(0) -#define WIN_FEATURE_CLUSTER BIT(1) - -/* - * the delay number of a window in different mode. - */ -enum win_dly_mode { - VOP2_DLY_MODE_DEFAULT, /**< default mode */ - VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ - VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ - VOP2_DLY_MODE_MAX, -}; - -struct vop_rect { - int width; - int height; -}; - -enum vop2_scale_up_mode { - VOP2_SCALE_UP_NRST_NBOR, - VOP2_SCALE_UP_BIL, - VOP2_SCALE_UP_BIC, -}; - -enum vop2_scale_down_mode { - VOP2_SCALE_DOWN_NRST_NBOR, - VOP2_SCALE_DOWN_BIL, - VOP2_SCALE_DOWN_AVG, -}; - -enum vop2_win_regs { - VOP2_WIN_ENABLE, - VOP2_WIN_FORMAT, - VOP2_WIN_CSC_MODE, - VOP2_WIN_XMIRROR, - VOP2_WIN_YMIRROR, - VOP2_WIN_RB_SWAP, - VOP2_WIN_UV_SWAP, - VOP2_WIN_ACT_INFO, - VOP2_WIN_DSP_INFO, - VOP2_WIN_DSP_ST, - VOP2_WIN_YRGB_MST, - VOP2_WIN_UV_MST, - VOP2_WIN_YRGB_VIR, - VOP2_WIN_UV_VIR, - VOP2_WIN_YUV_CLIP, - VOP2_WIN_Y2R_EN, - VOP2_WIN_R2Y_EN, - VOP2_WIN_COLOR_KEY, - VOP2_WIN_COLOR_KEY_EN, - VOP2_WIN_DITHER_UP, - - /* scale regs */ - VOP2_WIN_SCALE_YRGB_X, - VOP2_WIN_SCALE_YRGB_Y, - VOP2_WIN_SCALE_CBCR_X, - VOP2_WIN_SCALE_CBCR_Y, - VOP2_WIN_YRGB_HOR_SCL_MODE, - VOP2_WIN_YRGB_HSCL_FILTER_MODE, - VOP2_WIN_YRGB_VER_SCL_MODE, - VOP2_WIN_YRGB_VSCL_FILTER_MODE, - VOP2_WIN_CBCR_VER_SCL_MODE, - VOP2_WIN_CBCR_HSCL_FILTER_MODE, - VOP2_WIN_CBCR_HOR_SCL_MODE, - VOP2_WIN_CBCR_VSCL_FILTER_MODE, - VOP2_WIN_VSD_CBCR_GT2, - VOP2_WIN_VSD_CBCR_GT4, - VOP2_WIN_VSD_YRGB_GT2, - VOP2_WIN_VSD_YRGB_GT4, - VOP2_WIN_BIC_COE_SEL, - - /* cluster regs */ - VOP2_WIN_CLUSTER_ENABLE, - VOP2_WIN_AFBC_ENABLE, - VOP2_WIN_CLUSTER_LB_MODE, - - /* afbc regs */ - VOP2_WIN_AFBC_FORMAT, - VOP2_WIN_AFBC_RB_SWAP, - VOP2_WIN_AFBC_UV_SWAP, - VOP2_WIN_AFBC_AUTO_GATING_EN, - VOP2_WIN_AFBC_BLOCK_SPLIT_EN, - VOP2_WIN_AFBC_PIC_VIR_WIDTH, - VOP2_WIN_AFBC_TILE_NUM, - VOP2_WIN_AFBC_PIC_OFFSET, - VOP2_WIN_AFBC_PIC_SIZE, - VOP2_WIN_AFBC_DSP_OFFSET, - VOP2_WIN_AFBC_TRANSFORM_OFFSET, - VOP2_WIN_AFBC_HDR_PTR, - VOP2_WIN_AFBC_HALF_BLOCK_EN, - VOP2_WIN_AFBC_ROTATE_270, - VOP2_WIN_AFBC_ROTATE_90, - VOP2_WIN_MAX_REG, -}; - -struct vop2_win_data { - const char *name; - unsigned int phys_id; - - u32 base; - enum drm_plane_type type; - - u32 nformats; - const u32 *formats; - const uint64_t *format_modifiers; - const unsigned int supported_rotations; - - /** - * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 - */ - unsigned int layer_sel_id; - uint64_t feature; - - unsigned int max_upscale_factor; - unsigned int max_downscale_factor; - const u8 dly[VOP2_DLY_MODE_MAX]; -}; - -struct vop2_video_port_data { - unsigned int id; - u32 feature; - u16 gamma_lut_len; - u16 cubic_lut_len; - struct vop_rect max_output; - const u8 pre_scan_max_dly[4]; - const struct vop2_video_port_regs *regs; - unsigned int offset; -}; - -struct vop2_data { - u8 nr_vps; - const struct vop2_ctrl *ctrl; - const struct vop2_win_data *win; - const struct vop2_video_port_data *vp; - const struct vop_csc_table *csc_table; - struct vop_rect max_input; - struct vop_rect max_output; - - unsigned int win_size; - unsigned int soc_id; -}; - -/* interrupt define */ -#define FS_NEW_INTR BIT(4) -#define ADDR_SAME_INTR BIT(5) -#define LINE_FLAG1_INTR BIT(6) -#define WIN0_EMPTY_INTR BIT(7) -#define WIN1_EMPTY_INTR BIT(8) -#define WIN2_EMPTY_INTR BIT(9) -#define WIN3_EMPTY_INTR BIT(10) -#define HWC_EMPTY_INTR BIT(11) -#define POST_BUF_EMPTY_INTR BIT(12) -#define PWM_GEN_INTR BIT(13) -#define DMA_FINISH_INTR BIT(14) -#define FS_FIELD_INTR BIT(15) -#define FE_INTR BIT(16) -#define WB_UV_FIFO_FULL_INTR BIT(17) -#define WB_YRGB_FIFO_FULL_INTR BIT(18) -#define WB_COMPLETE_INTR BIT(19) - -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_BT1120 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -#define ROCKCHIP_OUT_MODE_BT656 5 -#define ROCKCHIP_OUT_MODE_S888 8 -#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 -#define ROCKCHIP_OUT_MODE_YUV420 14 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 - -enum vop_csc_format { - CSC_BT601L, - CSC_BT709L, - CSC_BT601F, - CSC_BT2020, -}; - -enum src_factor_mode { - SRC_FAC_ALPHA_ZERO, - SRC_FAC_ALPHA_ONE, - SRC_FAC_ALPHA_DST, - SRC_FAC_ALPHA_DST_INVERSE, - SRC_FAC_ALPHA_SRC, - SRC_FAC_ALPHA_SRC_GLOBAL, -}; - -enum dst_factor_mode { - DST_FAC_ALPHA_ZERO, - DST_FAC_ALPHA_ONE, - DST_FAC_ALPHA_SRC, - DST_FAC_ALPHA_SRC_INVERSE, - DST_FAC_ALPHA_DST, - DST_FAC_ALPHA_DST_GLOBAL, -}; - -#define RK3568_GRF_VO_CON1 0x0364 -/* System registers definition */ -#define RK3568_REG_CFG_DONE 0x000 -#define RK3568_VERSION_INFO 0x004 -#define RK3568_SYS_AUTO_GATING_CTRL 0x008 -#define RK3568_SYS_AXI_LUT_CTRL 0x024 -#define RK3568_DSP_IF_EN 0x028 -#define RK3568_DSP_IF_CTRL 0x02c -#define RK3568_DSP_IF_POL 0x030 -#define RK3568_WB_CTRL 0x40 -#define RK3568_WB_XSCAL_FACTOR 0x44 -#define RK3568_WB_YRGB_MST 0x48 -#define RK3568_WB_CBR_MST 0x4C -#define RK3568_OTP_WIN_EN 0x050 -#define RK3568_LUT_PORT_SEL 0x058 -#define RK3568_SYS_STATUS0 0x060 -#define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) -#define RK3568_SYS0_INT_EN 0x80 -#define RK3568_SYS0_INT_CLR 0x84 -#define RK3568_SYS0_INT_STATUS 0x88 -#define RK3568_SYS1_INT_EN 0x90 -#define RK3568_SYS1_INT_CLR 0x94 -#define RK3568_SYS1_INT_STATUS 0x98 -#define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) -#define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) -#define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) -#define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) - -/* Video Port registers definition */ -#define RK3568_VP_DSP_CTRL 0x00 -#define RK3568_VP_MIPI_CTRL 0x04 -#define RK3568_VP_COLOR_BAR_CTRL 0x08 -#define RK3568_VP_3D_LUT_CTRL 0x10 -#define RK3568_VP_3D_LUT_MST 0x20 -#define RK3568_VP_DSP_BG 0x2C -#define RK3568_VP_PRE_SCAN_HTIMING 0x30 -#define RK3568_VP_POST_DSP_HACT_INFO 0x34 -#define RK3568_VP_POST_DSP_VACT_INFO 0x38 -#define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C -#define RK3568_VP_POST_SCL_CTRL 0x40 -#define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 -#define RK3568_VP_DSP_HTOTAL_HS_END 0x48 -#define RK3568_VP_DSP_HACT_ST_END 0x4C -#define RK3568_VP_DSP_VTOTAL_VS_END 0x50 -#define RK3568_VP_DSP_VACT_ST_END 0x54 -#define RK3568_VP_DSP_VS_ST_END_F1 0x58 -#define RK3568_VP_DSP_VACT_ST_END_F1 0x5C -#define RK3568_VP_BCSH_CTRL 0x60 -#define RK3568_VP_BCSH_BCS 0x64 -#define RK3568_VP_BCSH_H 0x68 -#define RK3568_VP_BCSH_COLOR_BAR 0x6C - -/* Overlay registers definition */ -#define RK3568_OVL_CTRL 0x600 -#define RK3568_OVL_LAYER_SEL 0x604 -#define RK3568_OVL_PORT_SEL 0x608 -#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 -#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 -#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 -#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C -#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 -#define RK3568_MIX0_DST_COLOR_CTRL 0x654 -#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 -#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C -#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 -#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 -#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 -#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC -#define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) -#define RK3568_CLUSTER_DLY_NUM 0x6F0 -#define RK3568_SMART_DLY_NUM 0x6F8 - -/* Cluster register definition, offset relative to window base */ -#define RK3568_CLUSTER_WIN_CTRL0 0x00 -#define RK3568_CLUSTER_WIN_CTRL1 0x04 -#define RK3568_CLUSTER_WIN_YRGB_MST 0x10 -#define RK3568_CLUSTER_WIN_CBR_MST 0x14 -#define RK3568_CLUSTER_WIN_VIR 0x18 -#define RK3568_CLUSTER_WIN_ACT_INFO 0x20 -#define RK3568_CLUSTER_WIN_DSP_INFO 0x24 -#define RK3568_CLUSTER_WIN_DSP_ST 0x28 -#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 -#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C -#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 -#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 -#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 -#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C -#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 -#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 -#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 -#define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C - -#define RK3568_CLUSTER_CTRL 0x100 - -/* (E)smart register definition, offset relative to window base */ -#define RK3568_SMART_CTRL0 0x00 -#define RK3568_SMART_CTRL1 0x04 -#define RK3568_SMART_REGION0_CTRL 0x10 -#define RK3568_SMART_REGION0_YRGB_MST 0x14 -#define RK3568_SMART_REGION0_CBR_MST 0x18 -#define RK3568_SMART_REGION0_VIR 0x1C -#define RK3568_SMART_REGION0_ACT_INFO 0x20 -#define RK3568_SMART_REGION0_DSP_INFO 0x24 -#define RK3568_SMART_REGION0_DSP_ST 0x28 -#define RK3568_SMART_REGION0_SCL_CTRL 0x30 -#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 -#define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 -#define RK3568_SMART_REGION0_SCL_OFFSET 0x3C -#define RK3568_SMART_REGION1_CTRL 0x40 -#define RK3568_SMART_REGION1_YRGB_MST 0x44 -#define RK3568_SMART_REGION1_CBR_MST 0x48 -#define RK3568_SMART_REGION1_VIR 0x4C -#define RK3568_SMART_REGION1_ACT_INFO 0x50 -#define RK3568_SMART_REGION1_DSP_INFO 0x54 -#define RK3568_SMART_REGION1_DSP_ST 0x58 -#define RK3568_SMART_REGION1_SCL_CTRL 0x60 -#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 -#define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 -#define RK3568_SMART_REGION1_SCL_OFFSET 0x6C -#define RK3568_SMART_REGION2_CTRL 0x70 -#define RK3568_SMART_REGION2_YRGB_MST 0x74 -#define RK3568_SMART_REGION2_CBR_MST 0x78 -#define RK3568_SMART_REGION2_VIR 0x7C -#define RK3568_SMART_REGION2_ACT_INFO 0x80 -#define RK3568_SMART_REGION2_DSP_INFO 0x84 -#define RK3568_SMART_REGION2_DSP_ST 0x88 -#define RK3568_SMART_REGION2_SCL_CTRL 0x90 -#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 -#define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 -#define RK3568_SMART_REGION2_SCL_OFFSET 0x9C -#define RK3568_SMART_REGION3_CTRL 0xA0 -#define RK3568_SMART_REGION3_YRGB_MST 0xA4 -#define RK3568_SMART_REGION3_CBR_MST 0xA8 -#define RK3568_SMART_REGION3_VIR 0xAC -#define RK3568_SMART_REGION3_ACT_INFO 0xB0 -#define RK3568_SMART_REGION3_DSP_INFO 0xB4 -#define RK3568_SMART_REGION3_DSP_ST 0xB8 -#define RK3568_SMART_REGION3_SCL_CTRL 0xC0 -#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 -#define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 -#define RK3568_SMART_REGION3_SCL_OFFSET 0xCC -#define RK3568_SMART_COLOR_KEY_CTRL 0xD0 - -/* HDR register definition */ -#define RK3568_HDR_LUT_CTRL 0x2000 -#define RK3568_HDR_LUT_MST 0x2004 -#define RK3568_SDR2HDR_CTRL 0x2010 -#define RK3568_HDR2SDR_CTRL 0x2020 -#define RK3568_HDR2SDR_SRC_RANGE 0x2024 -#define RK3568_HDR2SDR_NORMFACEETF 0x2028 -#define RK3568_HDR2SDR_DST_RANGE 0x202C -#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 -#define RK3568_HDR_EETF_OETF_Y0 0x203C -#define RK3568_HDR_SAT_Y0 0x20C0 -#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 -#define RK3568_HDR_OETF_DX_POW1 0x2200 -#define RK3568_HDR_OETF_XN1 0x2300 - -#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) - -#define RK3568_VP_DSP_CTRL__STANDBY BIT(31) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) -#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) -#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) -#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) -#define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) -#define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) -#define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) -#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) -#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) - -#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) -#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) - -#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) -#define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) -#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) -#define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) -#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) -#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) -#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) -#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) -#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) -#define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) -#define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) -#define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) -#define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) -#define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) - -#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) -#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) -#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) -#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) - -#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) -#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) - -#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) - -#define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) - -#define VOP2_SYS_AXI_BUS_NUM 2 - -#define VOP2_CLUSTER_YUV444_10 0x12 - -#define VOP2_COLOR_KEY_MASK BIT(31) - -#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) - -#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) - -#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) -#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) -#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) -#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) -#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) -#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) -#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) -#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) -#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) -#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) -#define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) - -#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) - -#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) -#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) -#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) -#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) - -#define VP_INT_DSP_HOLD_VALID BIT(6) -#define VP_INT_FS_FIELD BIT(5) -#define VP_INT_POST_BUF_EMPTY BIT(4) -#define VP_INT_LINE_FLAG1 BIT(3) -#define VP_INT_LINE_FLAG0 BIT(2) -#define VOP2_INT_BUS_ERRPR BIT(1) -#define VP_INT_FS BIT(0) - -#define POLFLAG_DCLK_INV BIT(3) - -enum vop2_layer_phy_id { - ROCKCHIP_VOP2_CLUSTER0 = 0, - ROCKCHIP_VOP2_CLUSTER1, - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_SMART0, - ROCKCHIP_VOP2_SMART1, - ROCKCHIP_VOP2_CLUSTER2, - ROCKCHIP_VOP2_CLUSTER3, - ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_ESMART3, - ROCKCHIP_VOP2_PHY_ID_INVALID = -1, -}; - -extern const struct component_ops vop2_component_ops; - -#endif /* _ROCKCHIP_DRM_VOP2_H */ diff --git a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c deleted file mode 100644 index 9bf0637bf..000000000 --- a/target/linux/rockchip/files-5.15/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ /dev/null @@ -1,281 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) Rockchip Electronics Co.Ltd - * Author: Andy Yan - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rockchip_drm_vop2.h" - -static const uint32_t formats_win_full_10bit[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, - DRM_FORMAT_NV12, - DRM_FORMAT_NV16, - DRM_FORMAT_NV24, -}; - -static const uint32_t formats_win_full_10bit_yuyv[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, - DRM_FORMAT_NV12, - DRM_FORMAT_NV16, - DRM_FORMAT_NV24, - DRM_FORMAT_YVYU, - DRM_FORMAT_VYUY, -}; - -static const uint32_t formats_win_lite[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, -}; - -static const uint64_t format_modifiers[] = { - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID, -}; - -static const uint64_t format_modifiers_afbc[] = { - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_CBR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_CBR | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_CBR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_CBR | - AFBC_FORMAT_MOD_SPARSE), - - /* SPLIT mandates SPARSE, RGB modes mandates YTR */ - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_SPARSE | - AFBC_FORMAT_MOD_SPLIT), - DRM_FORMAT_MOD_INVALID, -}; - -static const struct vop2_video_port_data rk3568_vop_video_ports[] = { - { - .id = 0, - .feature = VOP_FEATURE_OUTPUT_10BIT, - .gamma_lut_len = 1024, - .cubic_lut_len = 9 * 9 * 9, - .max_output = { 4096, 2304 }, - .pre_scan_max_dly = { 69, 53, 53, 42 }, - .offset = 0xc00, - }, { - .id = 1, - .gamma_lut_len = 1024, - .max_output = { 2048, 1536 }, - .pre_scan_max_dly = { 40, 40, 40, 40 }, - .offset = 0xd00, - }, { - .id = 2, - .gamma_lut_len = 1024, - .max_output = { 1920, 1080 }, - .pre_scan_max_dly = { 40, 40, 40, 40 }, - .offset = 0xe00, - }, -}; - -/* - * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win. - * Every cluster can work as 4K win or split into two win. - * All win in cluster support AFBCD. - * - * Every esmart win and smart win support 4 Multi-region. - * - * Scale filter mode: - * - * * Cluster: bicubic for horizontal scale up, others use bilinear - * * ESmart: - * * nearest-neighbor/bilinear/bicubic for scale up - * * nearest-neighbor/bilinear/average for scale down - * - * - * @TODO describe the wind like cpu-map dt nodes; - */ -static const struct vop2_win_data rk3568_vop_win_data[] = { - { - .name = "Smart0-win0", - .phys_id = ROCKCHIP_VOP2_SMART0, - .base = 0x1c00, - .formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .format_modifiers = format_modifiers, - .layer_sel_id = 3, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Smart1-win0", - .phys_id = ROCKCHIP_VOP2_SMART1, - .formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .format_modifiers = format_modifiers, - .base = 0x1e00, - .layer_sel_id = 7, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Esmart1-win0", - .phys_id = ROCKCHIP_VOP2_ESMART1, - .formats = formats_win_full_10bit_yuyv, - .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), - .format_modifiers = format_modifiers, - .base = 0x1a00, - .layer_sel_id = 6, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Esmart0-win0", - .phys_id = ROCKCHIP_VOP2_ESMART0, - .formats = formats_win_full_10bit_yuyv, - .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), - .format_modifiers = format_modifiers, - .base = 0x1800, - .layer_sel_id = 2, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_OVERLAY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Cluster0-win0", - .phys_id = ROCKCHIP_VOP2_CLUSTER0, - .base = 0x1000, - .formats = formats_win_full_10bit, - .nformats = ARRAY_SIZE(formats_win_full_10bit), - .format_modifiers = format_modifiers_afbc, - .layer_sel_id = 0, - .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, - .max_upscale_factor = 4, - .max_downscale_factor = 4, - .dly = { 0, 27, 21 }, - .type = DRM_PLANE_TYPE_OVERLAY, - .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, - }, { - .name = "Cluster1-win0", - .phys_id = ROCKCHIP_VOP2_CLUSTER1, - .base = 0x1200, - .formats = formats_win_full_10bit, - .nformats = ARRAY_SIZE(formats_win_full_10bit), - .format_modifiers = format_modifiers_afbc, - .layer_sel_id = 1, - .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_OVERLAY, - .max_upscale_factor = 4, - .max_downscale_factor = 4, - .dly = { 0, 27, 21 }, - .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, - }, -}; - -static const struct vop2_data rk3566_vop = { - .nr_vps = 3, - .max_input = { 4096, 2304 }, - .max_output = { 4096, 2304 }, - .vp = rk3568_vop_video_ports, - .win = rk3568_vop_win_data, - .win_size = ARRAY_SIZE(rk3568_vop_win_data), - .soc_id = 3566, -}; - -static const struct vop2_data rk3568_vop = { - .nr_vps = 3, - .max_input = { 4096, 2304 }, - .max_output = { 4096, 2304 }, - .vp = rk3568_vop_video_ports, - .win = rk3568_vop_win_data, - .win_size = ARRAY_SIZE(rk3568_vop_win_data), - .soc_id = 3568, -}; - -static const struct of_device_id vop2_dt_match[] = { - { - .compatible = "rockchip,rk3566-vop", - .data = &rk3566_vop, - }, { - .compatible = "rockchip,rk3568-vop", - .data = &rk3568_vop, - }, { - }, -}; -MODULE_DEVICE_TABLE(of, vop2_dt_match); - -static int vop2_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - - return component_add(dev, &vop2_component_ops); -} - -static int vop2_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &vop2_component_ops); - - return 0; -} - -struct platform_driver vop2_platform_driver = { - .probe = vop2_probe, - .remove = vop2_remove, - .driver = { - .name = "rockchip-vop2", - .of_match_table = of_match_ptr(vop2_dt_match), - }, -}; diff --git a/target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c deleted file mode 100644 index 7b213825f..000000000 --- a/target/linux/rockchip/files-5.15/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver - * - * Copyright (C) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define BIT_WRITEABLE_SHIFT 16 -#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) -#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) -#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) - -/* COMBO PHY REG */ -#define PHYREG6 0x14 -#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) -#define PHYREG6_PLL_DIV_SHIFT 6 -#define PHYREG6_PLL_DIV_2 1 - -#define PHYREG7 0x18 -#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) -#define PHYREG7_TX_RTERM_SHIFT 4 -#define PHYREG7_TX_RTERM_50OHM 8 -#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) -#define PHYREG7_RX_RTERM_SHIFT 0 -#define PHYREG7_RX_RTERM_44OHM 15 - -#define PHYREG8 0x1C -#define PHYREG8_SSC_EN BIT(4) - -#define PHYREG11 0x28 -#define PHYREG11_SU_TRIM_0_7 0xF0 - -#define PHYREG12 0x2C -#define PHYREG12_PLL_LPF_ADJ_VALUE 4 - -#define PHYREG13 0x30 -#define PHYREG13_RESISTER_MASK GENMASK(5, 4) -#define PHYREG13_RESISTER_SHIFT 0x4 -#define PHYREG13_RESISTER_HIGH_Z 3 -#define PHYREG13_CKRCV_AMP0 BIT(7) - -#define PHYREG14 0x34 -#define PHYREG14_CKRCV_AMP1 BIT(0) - -#define PHYREG15 0x38 -#define PHYREG15_CTLE_EN BIT(0) -#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) -#define PHYREG15_SSC_CNT_SHIFT 6 -#define PHYREG15_SSC_CNT_VALUE 1 - -#define PHYREG16 0x3C -#define PHYREG16_SSC_CNT_VALUE 0x5f - -#define PHYREG18 0x44 -#define PHYREG18_PLL_LOOP 0x32 - -#define PHYREG32 0x7C -#define PHYREG32_SSC_MASK GENMASK(7, 4) -#define PHYREG32_SSC_DIR_SHIFT 4 -#define PHYREG32_SSC_UPWARD 0 -#define PHYREG32_SSC_DOWNWARD 1 -#define PHYREG32_SSC_OFFSET_SHIFT 6 -#define PHYREG32_SSC_OFFSET_500PPM 1 - -#define PHYREG33 0x80 -#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) -#define PHYREG33_PLL_KVCO_SHIFT 2 -#define PHYREG33_PLL_KVCO_VALUE 2 - -struct rockchip_combphy_priv; - -struct combphy_reg { - u16 offset; - u16 bitend; - u16 bitstart; - u16 disable; - u16 enable; -}; - -struct rockchip_combphy_grfcfg { - struct combphy_reg pcie_mode_set; - struct combphy_reg usb_mode_set; - struct combphy_reg sgmii_mode_set; - struct combphy_reg qsgmii_mode_set; - struct combphy_reg pipe_rxterm_set; - struct combphy_reg pipe_txelec_set; - struct combphy_reg pipe_txcomp_set; - struct combphy_reg pipe_clk_25m; - struct combphy_reg pipe_clk_100m; - struct combphy_reg pipe_phymode_sel; - struct combphy_reg pipe_rate_sel; - struct combphy_reg pipe_rxterm_sel; - struct combphy_reg pipe_txelec_sel; - struct combphy_reg pipe_txcomp_sel; - struct combphy_reg pipe_clk_ext; - struct combphy_reg pipe_sel_usb; - struct combphy_reg pipe_sel_qsgmii; - struct combphy_reg pipe_phy_status; - struct combphy_reg con0_for_pcie; - struct combphy_reg con1_for_pcie; - struct combphy_reg con2_for_pcie; - struct combphy_reg con3_for_pcie; - struct combphy_reg con0_for_sata; - struct combphy_reg con1_for_sata; - struct combphy_reg con2_for_sata; - struct combphy_reg con3_for_sata; - struct combphy_reg pipe_con0_for_sata; - struct combphy_reg pipe_xpcs_phy_ready; -}; - -struct rockchip_combphy_cfg { - const struct rockchip_combphy_grfcfg *grfcfg; - int (*combphy_cfg)(struct rockchip_combphy_priv *priv); -}; - -struct rockchip_combphy_priv { - u8 type; - void __iomem *mmio; - int num_clks; - struct clk_bulk_data *clks; - struct device *dev; - struct regmap *pipe_grf; - struct regmap *phy_grf; - struct phy *phy; - struct reset_control *phy_rst; - const struct rockchip_combphy_cfg *cfg; - bool enable_ssc; - bool ext_refclk; - struct clk *refclk; -}; - -static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, - int mask, int val, int reg) -{ - unsigned int temp; - - temp = readl(priv->mmio + reg); - temp = (temp & ~(mask)) | val; - writel(temp, priv->mmio + reg); -} - -static int rockchip_combphy_param_write(struct regmap *base, - const struct combphy_reg *reg, bool en) -{ - u32 val, mask, tmp; - - tmp = en ? reg->enable : reg->disable; - mask = GENMASK(reg->bitend, reg->bitstart); - val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); - - return regmap_write(base, reg->offset, val); -} - -static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) -{ - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - u32 mask, val; - - mask = GENMASK(cfg->pipe_phy_status.bitend, - cfg->pipe_phy_status.bitstart); - - regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); - val = (val & mask) >> cfg->pipe_phy_status.bitstart; - - return val; -} - -static int rockchip_combphy_init(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - u32 val; - int ret; - - ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); - if (ret) { - dev_err(priv->dev, "failed to enable clks\n"); - return ret; - } - - switch (priv->type) { - case PHY_TYPE_PCIE: - case PHY_TYPE_USB3: - case PHY_TYPE_SATA: - case PHY_TYPE_SGMII: - case PHY_TYPE_QSGMII: - if (priv->cfg->combphy_cfg) - ret = priv->cfg->combphy_cfg(priv); - break; - default: - dev_err(priv->dev, "incompatible PHY type\n"); - ret = -EINVAL; - break; - } - - if (ret) { - dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); - goto err_clk; - } - - ret = reset_control_deassert(priv->phy_rst); - if (ret) - goto err_clk; - - if (priv->type == PHY_TYPE_USB3) { - ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, - priv, val, - val == cfg->pipe_phy_status.enable, - 10, 1000); - if (ret) - dev_warn(priv->dev, "wait phy status ready timeout\n"); - } - - return 0; - -err_clk: - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - - return ret; -} - -static int rockchip_combphy_exit(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); - - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - reset_control_assert(priv->phy_rst); - - return 0; -} - -static const struct phy_ops rochchip_combphy_ops = { - .init = rockchip_combphy_init, - .exit = rockchip_combphy_exit, - .owner = THIS_MODULE, -}; - -static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); - - if (args->args_count != 1) { - dev_err(dev, "invalid number of arguments\n"); - return ERR_PTR(-EINVAL); - } - - if (priv->type != PHY_NONE && priv->type != args->args[0]) - dev_warn(dev, "phy type select %d overwriting type %d\n", - args->args[0], priv->type); - - priv->type = args->args[0]; - - return priv->phy; -} - -static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) -{ - int i; - - priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); - if (priv->num_clks < 1) - return -EINVAL; - - priv->refclk = NULL; - for (i = 0; i < priv->num_clks; i++) { - if (!strncmp(priv->clks[i].id, "ref", 3)) { - priv->refclk = priv->clks[i].clk; - break; - } - } - - if (!priv->refclk) { - dev_err(dev, "no refclk found\n"); - return -EINVAL; - } - - priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); - if (IS_ERR(priv->pipe_grf)) { - dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); - return PTR_ERR(priv->pipe_grf); - } - - priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); - if (IS_ERR(priv->phy_grf)) { - dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); - return PTR_ERR(priv->phy_grf); - } - - priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); - - priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); - - priv->phy_rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(priv->phy_rst)) - return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); - - return 0; -} - -static int rockchip_combphy_probe(struct platform_device *pdev) -{ - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct rockchip_combphy_priv *priv; - const struct rockchip_combphy_cfg *phy_cfg; - struct resource *res; - int ret; - - phy_cfg = of_device_get_match_data(dev); - if (!phy_cfg) { - dev_err(dev, "no OF match data provided\n"); - return -EINVAL; - } - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(priv->mmio)) { - ret = PTR_ERR(priv->mmio); - return ret; - } - - priv->dev = dev; - priv->type = PHY_NONE; - priv->cfg = phy_cfg; - - ret = rockchip_combphy_parse_dt(dev, priv); - if (ret) - return ret; - - ret = reset_control_assert(priv->phy_rst); - if (ret) { - dev_err(dev, "failed to reset phy\n"); - return ret; - } - - priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); - return PTR_ERR(priv->phy); - } - - dev_set_drvdata(dev, priv); - phy_set_drvdata(priv->phy, priv); - - phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); - - return PTR_ERR_OR_ZERO(phy_provider); -} - -static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) -{ - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - unsigned long rate; - u32 val; - - switch (priv->type) { - case PHY_TYPE_PCIE: - /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); - break; - - case PHY_TYPE_USB3: - /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); - - /* Enable adaptive CTLE for USB3.0 Rx. */ - val = readl(priv->mmio + PHYREG15); - val |= PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); - - /* Set PLL KVCO fine tuning signals. */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, - PHYREG33); - - /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); - - /* Set PLL input clock divider 1/2. */ - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, - PHYREG6); - - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); - rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); - break; - - case PHY_TYPE_SATA: - /* Enable adaptive CTLE for SATA Rx. */ - val = readl(priv->mmio + PHYREG15); - val |= PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); - /* - * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. - * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) - */ - val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; - val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; - writel(val, priv->mmio + PHYREG7); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); - break; - - case PHY_TYPE_SGMII: - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); - break; - - case PHY_TYPE_QSGMII: - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); - break; - - default: - dev_err(priv->dev, "incompatible PHY type\n"); - return -EINVAL; - } - - rate = clk_get_rate(priv->refclk); - - switch (rate) { - case REF_CLOCK_24MHz: - if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { - /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ - val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); - - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); - } - break; - - case REF_CLOCK_25MHz: - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); - break; - - case REF_CLOCK_100MHz: - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); - if (priv->type == PHY_TYPE_PCIE) { - /* PLL KVCO fine tuning. */ - val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); - - /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); - - val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - val, PHYREG6); - - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); - } else if (priv->type == PHY_TYPE_SATA) { - /* downward spread spectrum +500ppm */ - val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; - val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); - } - break; - - default: - dev_err(priv->dev, "unsupported rate: %lu\n", rate); - return -EINVAL; - } - - if (priv->ext_refclk) { - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); - if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { - val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; - val |= PHYREG13_CKRCV_AMP0; - rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); - - val = readl(priv->mmio + PHYREG14); - val |= PHYREG14_CKRCV_AMP1; - writel(val, priv->mmio + PHYREG14); - } - } - - if (priv->enable_ssc) { - val = readl(priv->mmio + PHYREG8); - val |= PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); - } - - return 0; -} - -static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { - /* pipe-phy-grf */ - .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, - .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, - .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, - .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, - .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, - .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, - .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, - .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, - .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, - .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, - .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, - .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, - .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, - .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, - .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, - .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, - .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, - .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, - .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, - .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, - .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, - .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, - .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, - .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, - .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, - .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, - /* pipe-grf */ - .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, - .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, -}; - -static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { - .grfcfg = &rk3568_combphy_grfcfgs, - .combphy_cfg = rk3568_combphy_cfg, -}; - -static const struct of_device_id rockchip_combphy_of_match[] = { - { - .compatible = "rockchip,rk3568-naneng-combphy", - .data = &rk3568_combphy_cfgs, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); - -static struct platform_driver rockchip_combphy_driver = { - .probe = rockchip_combphy_probe, - .driver = { - .name = "rockchip-naneng-combphy", - .of_match_table = rockchip_combphy_of_match, - }, -}; -module_platform_driver(rockchip_combphy_driver); - -MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/files-5.15/include/dt-bindings/soc/rockchip,vop2.h b/target/linux/rockchip/files-5.15/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 6e66a802b..000000000 --- a/target/linux/rockchip/files-5.15/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts deleted file mode 100644 index 6f9cf81f8..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts +++ /dev/null @@ -1,495 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 EmbedFire - */ - -/dts-v1/; - -#include -#include -#include "rk3328-dram-nanopi2-timing.dtsi" -#include "rk3328.dtsi" - -/ { - model = "EmbedFire DoorNet1"; - compatible = "embedfire,doornet1", "rockchip,rk3328"; - - aliases { - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - // mmc1 = &sdmmc; - // mmc0 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clk: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&reset_button_pin>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <50>; - }; - }; - - vcc_rtl8153: vcc-rtl8153-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8153_en_drv>; - regulator-always-on; - regulator-name = "vcc_rtl8153"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - dmc: dmc { - compatible = "rockchip,rk3328-dmc"; - devfreq-events = <&dfi>; - center-supply = <&vdd_log>; - clocks = <&cru SCLK_DDRCLK>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - ddr_timing = <&ddr_timing>; - upthreshold = <40>; - downdifferential = <20>; - auto-min-freq = <786000>; - auto-freq-en = <1>; - #cooling-cells = <2>; - status = "okay"; - - ddr_power_model: ddr_power_model { - compatible = "ddr_power_model"; - dynamic-power-coefficient = <120>; - static-power-coefficient = <200>; - ts = <32000 4700 (-80) 2>; - thermal-zone = "soc-thermal"; - }; - }; - - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - - rockchip,leakage-voltage-sel = < - 1 10 0 - 11 254 1 - >; - nvmem-cells = <&logic_leakage>; - nvmem-cell-names = "ddr_leakage"; - - opp-786000000 { - opp-hz = /bits/ 64 <786000000>; - opp-microvolt = <1075000>; - opp-microvolt-L0 = <1075000>; - opp-microvolt-L1 = <1050000>; - }; - opp-798000000 { - opp-hz = /bits/ 64 <798000000>; - opp-microvolt = <1075000>; - opp-microvolt-L0 = <1075000>; - opp-microvolt-L1 = <1050000>; - }; - opp-840000000 { - opp-hz = /bits/ 64 <840000000>; - opp-microvolt = <1075000>; - opp-microvolt-L0 = <1075000>; - opp-microvolt-L1 = <1050000>; - }; - opp-924000000 { - opp-hz = /bits/ 64 <924000000>; - opp-microvolt = <1100000>; - opp-microvolt-L0 = <1100000>; - opp-microvolt-L1 = <1075000>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <1175000>; - opp-microvolt-L0 = <1175000>; - opp-microvolt-L1 = <1150000>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; - - lan_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "doornet1:green:lan"; - }; - - sys_led: led-1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "doornet1:red:sys"; - }; - - wan_led: led-2 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - label = "doornet1:green:wan"; - }; - - wifi_enable: wifi_enable { - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - label = "wifi-enable"; - }; - }; - - vcc_io_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - enable-active-high; - gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sdio_vcc_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_io_sdio"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-settling-time-us = <5000>; - regulator-type = "voltage"; - startup-delay-us = <2000>; - states = <1800000 0x1 - 3300000 0x0>; - vin-supply = <&vcc_io_33>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io_33>; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&dfi { - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vcc_io_33>; - pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-delays-us = <0 1000000 50000>; - snps,reset-active-low; - tx_delay = <0x18>; - rx_delay = <0x24>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vdd_5v>; - vcc2-supply = <&vdd_5v>; - vcc3-supply = <&vdd_5v>; - vcc4-supply = <&vdd_5v>; - vcc5-supply = <&vcc_io_33>; - vcc6-supply = <&vdd_5v>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io_33: DCDC_REG4 { - regulator-name = "vcc_io_33"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; - usb { - rtl8153_en_drv: rtl8153-en-drv { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&io_domains { - pmuio-supply = <&vcc_io_33>; - vccio1-supply = <&vcc_io_33>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io_33>; - vccio6-supply = <&vcc_io_33>; - status = "okay"; -}; - -&pinctrl { - button { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ethernet-phy { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_pin: wifi_pin{ - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sd { - sdio_vcc_pin: sdio-vcc-pin { - rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_io_sdio>; - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io_33>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; - dr_mode = "host"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdrd3 { - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Second port is for USB 3.0 */ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; - - realtek,led-data = <0x87>; - }; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts deleted file mode 100644 index adf91a030..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021 Tianling Shen - */ - -/dts-v1/; - -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-id0000.011a", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lan_led { - label = "nanopi-r2c:green:lan"; -}; - -&sys_led { - label = "nanopi-r2c:red:sys"; -}; - -&wan_led { - label = "nanopi-r2c:green:wan"; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts deleted file mode 100644 index ee37573d6..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#include "rk3328-orangepi-r1-plus.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus LTS"; - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -}; - -/delete-node/ &rtl8211e; -&gmac2io { - phy-handle = <ðphy3>; - snps,reset-delays-us = <0 15000 50000>; - tx_delay = <0x19>; - rx_delay = <0x05>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy3: ethernet-phy@0 { - reg = <0x0>; - keep-clkout-on; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_io_sdio>; - status = "okay"; -}; - -&dmc_opp_table { - opp-1056000000 { - status = "disabled"; - }; - opp-924000000 { - status = "disabled"; - }; - opp-840000000 { - status = "disabled"; - }; - opp-798000000 { - status = "disabled"; - }; -}; - -&sys_led { - label = "orangepi-r1-plus-lts:red:sys"; -}; - -&wan_led { - label = "orangepi-r1-plus-lts:green:wan"; -}; - -&lan_led { - label = "orangepi-r1-plus-lts:green:lan"; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts deleted file mode 100644 index ed585daf4..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus"; - compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -}; - -&lan_led { - label = "orangepi-r1-plus:green:lan"; -}; - -&spi0 { - max-freq = <48000000>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&sys_led { - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - label = "orangepi-r1-plus:red:sys"; -}; - -&sys_led_pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&uart1 { - status = "okay"; -}; - -&wan_led { - label = "orangepi-r1-plus:green:wan"; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts deleted file mode 100644 index 7b9d5efaf..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3399-doornet2.dtsi" - -/ { - model = "EmbedFire DoorNet2 1GB"; - compatible = "embedfire,doornet2", "rockchip,rk3399"; - - aliases { - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - }; - - /delete-node/ display-subsystem; - - gpio-leds { - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - - /delete-node/ status; - - lan_led: led-lan { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; - }; - - sys_led: led-sys { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:sys"; - default-state = "on"; - }; - - wan_led: led-wan { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - }; - }; - - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - - /delete-node/ power; - - reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&pcie0 { - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; - - pcie@0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - pcie-eth@0,0 { - compatible = "realtek,r8168"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x870>; - }; - }; -}; - -&pinctrl { - gpio-leds { - /delete-node/ leds-gpio; - - lan_led_pin: lan-led-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - /delete-node/ power-key; - - reset_button_pin: reset-button-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&u2phy0_host { - phy-supply = <&vdd_5v>; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_sys>; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi deleted file mode 100644 index 4f6bddafe..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi +++ /dev/null @@ -1,636 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include "rk3399.dtsi" - -/ { - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_sys"; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc5v0_sys"; - vin-supply = <&vdd_5v>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_s3"; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vbus_typec"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_gpio>; - - status { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_s3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 100000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c7>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu_b"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "rtc_clko_wifi"; - #clock-cells = <1>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_center"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_cpu_l"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_cam: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_cam"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_touch"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_pmupll"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <3000000>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sdio"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcca3v0_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc_1v5"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc_3v0"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s3"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <200000>; - i2c-scl-rising-time-ns = <150>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pcie_phy { - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; - num-lanes = <4>; - status = "okay"; -}; - -&pinctrl { - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - leds_gpio: leds-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ethernet-phy { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - pmic { - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - power_key: power-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - /* external pullup to VCC1V8_PMUPLL */ - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_reg_on_h: wifi-reg_on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc0_det_l: sdmmc0-det-l { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi deleted file mode 100644 index 0c700e32d..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - * - * Copyright (c) 2020 Tianling Shen - * Copyright (c) 2020 gzelvis - */ - -/ { - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1225000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1275000>; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; - }; - opp08 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <1250000>; - }; - opp09 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1325000>; - }; - }; - - gpu_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <800000>; - }; - opp01 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <875000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000>; - }; - opp05 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1100000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts deleted file mode 100644 index f6e7710a0..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/* TODO - * Delete this file and migrate RockPi 4 to RockPi 4A after - * removing Kernel 5.4. - */ - - -/dts-v1/; -#include "rk3399-rock-pi-4.dtsi" - -/ { - model = "Radxa ROCK Pi 4"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts deleted file mode 100644 index 3cda9452d..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ /dev/null @@ -1,825 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "FriendlyElec NanoPi R5S"; - compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 18 102 170 255>; - #cooling-cells = <2>; - fan-supply = <&vcc5v0_sysp>; - pwms = <&pwm0 0 50000 0>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - cspmu: cspmu@fd90c000 { - compatible = "rockchip,cspmu"; - reg = <0x0 0xfd90c000 0x0 0x1000>, - <0x0 0xfd90d000 0x0 0x1000>, - <0x0 0xfd90e000 0x0 0x1000>, - <0x0 0xfd90f000 0x0 0x1000>; - }; - - gpio-key { - compatible = "gpio-key"; - pinctrl-names = "default"; - pinctrl-0 = <&key1_pin>; - - button@1 { - debounce-interval = <50>; - gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - sys_led: led-sys { - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - label = "red:power"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - wan_led: led-wan { - gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - pinctrl-names = "default"; - pinctrl-0 = <&wan_led_pin>; - }; - - lan1_led: led-lan1 { - gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - label = "green:lan1"; - pinctrl-names = "default"; - pinctrl-0 = <&lan1_led_pin>; - }; - - lan2_led: led-lan2 { - gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; - label = "green:lan2"; - pinctrl-names = "default"; - pinctrl-0 = <&lan2_led_pin>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vdd_usbc: vdd-usbc { - compatible = "regulator-fixed"; - regulator-name = "vdd_usbc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pcie>; - }; - - vcc3v3_ngff: vcc3v3-ngff-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ngff"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pcie>; - }; - - vcc5v0_usb: vcc5v0_usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sysp: vcc5v0-sysp { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sysp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - - -&i2c5 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - - -&mdio0 { - rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_int>; - }; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_ngff>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie2x1 { - num-viewport = <4>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - - sys_led_pin: sys-led-pin { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan1_led_pin: lan1-led-pin { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan2_led_pin: lan2-led-pin { - rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - gmac_int: gmac-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-key { - key1_pin: key1-pin { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtc { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0-usb-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm4 { - status = "disabled"; -}; - -&pwm5 { - status = "disabled"; -}; - -&pwm7 { - status = "disabled"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "disabled"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&spi3 { - pinctrl-0 = <&spi3m1_pins>; - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - status = "disabled"; -}; - -&uart2 { - status = "okay"; -}; - -&uart7 { - pinctrl-0 = <&uart7m1_xfer>; - status = "disabled"; -}; - -&uart9 { - pinctrl-0 = <&uart9m1_xfer>; - status = "disabled"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; \ No newline at end of file diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts deleted file mode 100644 index 934b17d55..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "FastRhino R66S"; - compatible = "fastrhino,r66s", "rockchip,rk3568"; - - aliases { - ethernet0 = &rtl8125_1; - ethernet1 = &rtl8125_2; - led-boot = &power_led; - led-failsafe = &power_led; - led-running = &power_led; - led-upgrade = &power_led; - mmc0 = &sdmmc0; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led_pin>; - - power_led: led-power { - label = "green:power"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&reset_button_pin>; - - reset { - debounce-interval = <50>; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc5v0_sys"; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-init-microvolt = <950000>; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - }; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; - - pcie@10 { - reg = <0x00100000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_1: pcie-eth@10,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x4078>; - }; - }; -}; - -&pcie3x2 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; - - pcie@20 { - reg = <0x00200000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_2: pcie-eth@20,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x4078>; - }; - }; -}; - -&pinctrl { - gpio-leds { - power_led_pin: power-led-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts deleted file mode 100644 index 6b5093a1a..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ /dev/null @@ -1,617 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Radxa ROCK3 Model A"; - compatible = "radxa,rock3a", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_user: led-0 { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - codec { - mic-in-differential; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - vbus-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts deleted file mode 100644 index 3883c1827..000000000 --- a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts +++ /dev/null @@ -1,787 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Firefly Station P2"; - compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac0_clkin: external-gmac0-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac0_clkin"; - #clock-cells = <0>; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - power_led: power { - label = "firefly:blue:power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_power>; - }; - - user_led: user { - label = "firefly:yellow:user"; - linux,default-trigger = "ir-user-click"; - default-state = "off"; - gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_user>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-always-on; - enable-active-high; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc_hub_reset: vcc-hub-reset { - compatible = "regulator-fixed"; - regulator-name = "vcc_hub_reset"; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_hub_reset_en>; - regulator-always-on; - }; - - pcie_pi6c_oe: pcie-pi6c-oe { - compatible = "regulator-fixed"; - regulator-name = "pcie_pi6c_oe_en"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pi6c_oe_en>; - regulator-always-on; - }; - - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_lcd1_n: vcc3v3-lcd1-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - &gmac0_clkinout>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus - &gmac1m1_clkinout>; - - tx_delay = <0x4f>; - rx_delay = <0x26>; - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&hdmi { - status = "okay"; - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pinctrl { - leds { - led_power: led-power { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_user: led-user { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc_hub_reset_en: vcc-hub-reset-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb0_int { - fusb0_int: fusb0-int { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pi6c_oe_en: pcie-pi6c-oe-en { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc2 { - max-frequency = <150000000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - sd-uhs-sdr104; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vop { - status = "okay"; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -}; - -&vop_mmu { - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x2{ - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; diff --git a/target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml b/target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml deleted file mode 100644 index f4f286251..000000000 --- a/target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml +++ /dev/null @@ -1,157 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK - -maintainers: - -properties: - compatible: - enum: - - rockchip,rk3328-u3phy - - reg: - - description: the base address of the USB 3.0 PHY - - interrupts: - maxItems: 1 - - interrupt-names: - items: - - const: linestate - description: host/otg linestate interrupt - - clocks: - maxItems: 2 - - clock-names: - items: - - const: u3phy-otg - description: USB 3.0 PHY UTMI - - const: u3phy-pipe - description: USB 3.0 PHY Pipe - - resets: - maxItems: 6 - - reset-names: - items: - - const: u3phy-u2-por - description: USB 2.0 logic of USB 3.0 PHY - - const: u3phy-u3-por - description: USB 3.0 logic of USB 3.0 PHY - - const: u3phy-pipe-mac - description: USB 3.0 PHY pipe MAC - - const: u3phy-utmi-mac - description: USB 3.0 PHY utmi MAC - - const: u3phy-utmi-apb - description: USB 3.0 PHY utmi apb - - const: u3phy-pipe-apb - description: USB 3.0 PHY pipe apb - - "#phy-cells": - const: 1 - - rockchip,u3phygrf: - $ref: /schemas/types.yaml#/definitions/phandle-array - type: array - - description: phandle to the syscon managing the - "USB 3.0 PHY general register files". - - vbus-drv-gpios: - $ref: /schemas/types.yaml#/definitions/phandle-array - type: array - - description: phandle for gpio vbus supply - -required: - - compatible - - reg - - interrupts - - interrupt-names - - clocks - - clock-names - - resets - - reset-names - - "#phy-cells" - - rockchip,u3phygrf - -patternProperties: - "^u3phy_utmi@[0-9a-f]+$": - type: object - - properties: - - description: USB 2.0 utmi phy. - - rockchip,odt-val-tuning: - type: boolean - - description: specify 45ohm ODT tuning value. - - "phy-cells": - const: 0 - - required: - - reg - - "#phy-cells" - -patternProperties: - "^u3phy_pipe@[0-9a-f]+$": - type: object - - properties: - - description: USB 3.0 pipe phy. - - rockchip,refclk-25m-quirk : - - - description: phy reference clock changed to 25m quirk. - - "phy-cells": - const: 0 - - required: - - reg - - "#phy-cells" - -examples: - -usb3phy_grf: syscon@ff460000 { - compatible = "rockchip,usb3phy-grf", "syscon"; - reg = <0x0 0xff460000 0x0 0x1000>; -}; - -... - -u3phy: usb3-phy@ff470000 { - compatible = "rockchip,rk3328-u3phy"; - reg = <0x0 0xff470000 0x0 0x0>; - rockchip,u3phygrf = <&usb3phy_grf>; - interrupts = ; - interrupt-names = "linestate"; - clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; - clock-names = "u3phy-otg", "u3phy-pipe"; - resets = <&cru SRST_USB3PHY_U2>, - <&cru SRST_USB3PHY_U3>, - <&cru SRST_USB3PHY_PIPE>, - <&cru SRST_USB3OTG_UTMI>, - <&cru SRST_USB3PHY_OTG_P>, - <&cru SRST_USB3PHY_PIPE_P>; - reset-names = "u3phy-u2-por", "u3phy-u3-por", - "u3phy-pipe-mac", "u3phy-utmi-mac", - "u3phy-utmi-apb", "u3phy-pipe-apb"; - vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - u3phy_utmi: utmi@ff470000 { - reg = <0x0 0xff470000 0x0 0x8000>; - #phy-cells = <0>; - }; - - u3phy_pipe: pipe@ff478000 { - reg = <0x0 0xff478000 0x0 0x8000>; - #phy-cells = <0>; - }; -}; diff --git a/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt b/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt deleted file mode 100644 index d5f41c464..000000000 --- a/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt +++ /dev/null @@ -1,45 +0,0 @@ -Rockchip Hardware Random Number Generator - -Required properties: - -- compatible : should be one of the following. - "rockchip,cryptov1-rng" for crypto v1 - "rockchip,cryptov2-rng" for crypto v2 - "rockchip,trngv1" for independent trng, such as rk3588. -- reg : Specifies base physical address and size of the registers map. -- clocks : Phandle to clock-controller plus clock-specifier pair. -- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name. -- assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, - <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO> -- assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>, - <200000000>, <100000000> -- resets : Used for module reset -- reset-names : Reset names, should be "reset" -Example: - - rng: rng@100fc000 { - compatible = "rockchip,cryptov1-rng"; - reg = <0x100fc000 0x4000>; - clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; - clock-names = "clk_crypto", "hclk_crypto"; - assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; - assigned-clock-rates = <150000000>, <100000000>; - resets = <&cru SRST_CRYPTO>; - reset-names = "reset"; - status = "disabled"; - }; - - rng: rng@ff2f0000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xff2f0000 0x0 0x4000>; - clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, - <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; - clock-names = "clk_crypto", "clk_crypto_apk", - "aclk_crypto", "hclk_crypto"; - assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, - <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; - assigned-clock-rates = <150000000>, <150000000>, - <200000000>, <100000000>; - resets = <&cru SRST_CRYPTO>; - reset-names = "reset"; - }; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi similarity index 100% rename from target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi rename to target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts deleted file mode 100644 index 530739a69..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021 Tianling Shen - */ - -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-id0000.011a", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lan_led { - label = "nanopi-r2c:green:lan"; -}; - -&rtl8153 { - realtek,led-data = <0x78>; -}; - -&sys_led { - label = "nanopi-r2c:red:sys"; -}; - -&wan_led { - label = "nanopi-r2c:green:wan"; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts deleted file mode 100644 index a690c062f..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Xunlong Software. Co., Ltd. - * (http://www.orangepi.org) - * - * Copyright (c) 2021 Tianling Shen - */ - -#include "rk3328-orangepi-r1-plus.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus LTS"; - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -}; - -&dmc_opp_table { - opp-798000000 { - status = "disabled"; - }; - opp-840000000 { - status = "disabled"; - }; - opp-924000000 { - status = "disabled"; - }; - opp-1056000000 { - status = "disabled"; - }; -}; - -&gmac2io { - phy-handle = <&yt8531c>; - tx_delay = <0x19>; - rx_delay = <0x05>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8531c: ethernet-phy@0 { - compatible = "ethernet-phy-id4f51.e91b", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <15000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lan_led { - label = "orangepi-r1-plus-lts:green:lan"; -}; - -&rtl8153 { - realtek,led-data = <0x78>; -}; - -&sys_led { - label = "orangepi-r1-plus-lts:red:sys"; -}; - -&wan_led { - label = "orangepi-r1-plus-lts:green:wan"; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts deleted file mode 100644 index ed585daf4..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus"; - compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -}; - -&lan_led { - label = "orangepi-r1-plus:green:lan"; -}; - -&spi0 { - max-freq = <48000000>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&sys_led { - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - label = "orangepi-r1-plus:red:sys"; -}; - -&sys_led_pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&uart1 { - status = "okay"; -}; - -&wan_led { - label = "orangepi-r1-plus:green:wan"; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-doornet2-4gb.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-doornet2-4gb.dts deleted file mode 100644 index dbbe3758c..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-doornet2-4gb.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3399-doornet2.dtsi" - -/ { - model = "EmbedFire DoorNet2-4GB"; - compatible = "embedfire,doornet2", "rockchip,rk3399"; - - aliases { - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - }; - - /delete-node/ display-subsystem; - - gpio-leds { - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - - /delete-node/ status; - - lan_led: led-lan { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; - }; - - sys_led: led-sys { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:sys"; - default-state = "on"; - }; - - wan_led: led-wan { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - }; - }; - - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - - /delete-node/ power; - - reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&pcie0 { - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; - - pcie@0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - pcie-eth@0,0 { - compatible = "realtek,r8168"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x870>; - }; - }; -}; - -&pinctrl { - gpio-leds { - /delete-node/ leds-gpio; - - lan_led_pin: lan-led-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - /delete-node/ power-key; - - reset_button_pin: reset-button-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&u2phy0_host { - phy-supply = <&vdd_5v>; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_sys>; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts deleted file mode 100644 index 3cda9452d..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ /dev/null @@ -1,825 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "FriendlyElec NanoPi R5S"; - compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 18 102 170 255>; - #cooling-cells = <2>; - fan-supply = <&vcc5v0_sysp>; - pwms = <&pwm0 0 50000 0>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - cspmu: cspmu@fd90c000 { - compatible = "rockchip,cspmu"; - reg = <0x0 0xfd90c000 0x0 0x1000>, - <0x0 0xfd90d000 0x0 0x1000>, - <0x0 0xfd90e000 0x0 0x1000>, - <0x0 0xfd90f000 0x0 0x1000>; - }; - - gpio-key { - compatible = "gpio-key"; - pinctrl-names = "default"; - pinctrl-0 = <&key1_pin>; - - button@1 { - debounce-interval = <50>; - gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - sys_led: led-sys { - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - label = "red:power"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - wan_led: led-wan { - gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - pinctrl-names = "default"; - pinctrl-0 = <&wan_led_pin>; - }; - - lan1_led: led-lan1 { - gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - label = "green:lan1"; - pinctrl-names = "default"; - pinctrl-0 = <&lan1_led_pin>; - }; - - lan2_led: led-lan2 { - gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; - label = "green:lan2"; - pinctrl-names = "default"; - pinctrl-0 = <&lan2_led_pin>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vdd_usbc: vdd-usbc { - compatible = "regulator-fixed"; - regulator-name = "vdd_usbc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pcie>; - }; - - vcc3v3_ngff: vcc3v3-ngff-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ngff"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pcie>; - }; - - vcc5v0_usb: vcc5v0_usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sysp: vcc5v0-sysp { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sysp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - - -&i2c5 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - - -&mdio0 { - rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_int>; - }; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_ngff>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie2x1 { - num-viewport = <4>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - - sys_led_pin: sys-led-pin { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan1_led_pin: lan1-led-pin { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan2_led_pin: lan2-led-pin { - rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - gmac_int: gmac-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-key { - key1_pin: key1-pin { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtc { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0-usb-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm4 { - status = "disabled"; -}; - -&pwm5 { - status = "disabled"; -}; - -&pwm7 { - status = "disabled"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "disabled"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&spi3 { - pinctrl-0 = <&spi3m1_pins>; - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - status = "disabled"; -}; - -&uart2 { - status = "okay"; -}; - -&uart7 { - pinctrl-0 = <&uart7m1_xfer>; - status = "disabled"; -}; - -&uart9 { - pinctrl-0 = <&uart9m1_xfer>; - status = "disabled"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; \ No newline at end of file diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts deleted file mode 100644 index 36fa0a0b3..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts +++ /dev/null @@ -1,542 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "FastRhino R66S"; - compatible = "fastrhino,r66s", "rockchip,rk3568"; - - aliases { - ethernet0 = &rtl8125_1; - ethernet1 = &rtl8125_2; - led-boot = &power_led; - led-failsafe = &power_led; - led-running = &power_led; - led-upgrade = &power_led; - mmc0 = &sdmmc0; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&reset_button_pin>; - - reset { - debounce-interval = <50>; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led_pin>; - - power_led: led-power { - label = "green:power"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-init-microvolt = <950000>; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - }; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; - - pcie@10 { - reg = <0x00100000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_1: pcie-eth@10,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x4078>; - }; - }; -}; - -&pcie3x2 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; - - pcie@20 { - reg = <0x00200000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_2: pcie-eth@20,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x4078>; - }; - }; -}; - -&pinctrl { - gpio-leds { - power_led_pin: power-led-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts deleted file mode 100644 index 3883c1827..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-station-p2.dts +++ /dev/null @@ -1,787 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Firefly Station P2"; - compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac0_clkin: external-gmac0-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac0_clkin"; - #clock-cells = <0>; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - power_led: power { - label = "firefly:blue:power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_power>; - }; - - user_led: user { - label = "firefly:yellow:user"; - linux,default-trigger = "ir-user-click"; - default-state = "off"; - gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_user>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-always-on; - enable-active-high; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc_hub_reset: vcc-hub-reset { - compatible = "regulator-fixed"; - regulator-name = "vcc_hub_reset"; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_hub_reset_en>; - regulator-always-on; - }; - - pcie_pi6c_oe: pcie-pi6c-oe { - compatible = "regulator-fixed"; - regulator-name = "pcie_pi6c_oe_en"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pi6c_oe_en>; - regulator-always-on; - }; - - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_lcd1_n: vcc3v3-lcd1-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - &gmac0_clkinout>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus - &gmac1m1_clkinout>; - - tx_delay = <0x4f>; - rx_delay = <0x26>; - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&hdmi { - status = "okay"; - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pinctrl { - leds { - led_power: led-power { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_user: led-user { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc_hub_reset_en: vcc-hub-reset-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb0_int { - fusb0_int: fusb0-int { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pi6c_oe_en: pcie-pi6c-oe-en { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc2 { - max-frequency = <150000000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - sd-uhs-sdr104; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vop { - status = "okay"; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -}; - -&vop_mmu { - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x2{ - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; diff --git a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c index 08ad08148..9a61f8087 100644 --- a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c +++ b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c @@ -21,7 +21,7 @@ #define ROCKCHIP_AUTOSUSPEND_DELAY 100 #define ROCKCHIP_POLL_PERIOD_US 100 -#define ROCKCHIP_POLL_TIMEOUT_US 50000 +#define ROCKCHIP_POLL_TIMEOUT_US 10000 #define RK_MAX_RNG_BYTE (32) /* start of CRYPTO V1 register define */ @@ -37,8 +37,7 @@ /* end of CRYPTO V1 register define */ /* start of CRYPTO V2 register define */ -#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400 -#define CRYPTO_V2_RNG_CTL 0x0 +#define CRYPTO_V2_RNG_CTL 0x0400 #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) @@ -49,48 +48,11 @@ #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) #define CRYPTO_V2_RNG_ENABLE BIT(1) #define CRYPTO_V2_RNG_START BIT(0) -#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004 -#define CRYPTO_V2_RNG_DOUT_0 0x0010 +#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 +#define CRYPTO_V2_RNG_DOUT_0 0x0410 /* end of CRYPTO V2 register define */ -/* start of TRNG_V1 register define */ -/* TRNG is no longer subordinate to the Crypto module */ -#define TRNG_V1_CTRL 0x0000 -#define TRNG_V1_CTRL_NOP _SBF(0, 0x00) -#define TRNG_V1_CTRL_RAND _SBF(0, 0x01) -#define TRNG_V1_CTRL_SEED _SBF(0, 0x02) - -#define TRNG_V1_STAT 0x0004 -#define TRNG_V1_STAT_SEEDED BIT(9) -#define TRNG_V1_STAT_GENERATING BIT(30) -#define TRNG_V1_STAT_RESEEDING BIT(31) - -#define TRNG_V1_MODE 0x0008 -#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00) -#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01) - -#define TRNG_V1_IE 0x0010 -#define TRNG_V1_IE_GLBL_EN BIT(31) -#define TRNG_V1_IE_SEED_DONE_EN BIT(1) -#define TRNG_V1_IE_RAND_RDY_EN BIT(0) - -#define TRNG_V1_ISTAT 0x0014 -#define TRNG_V1_ISTAT_RAND_RDY BIT(0) - -/* RAND0 ~ RAND7 */ -#define TRNG_V1_RAND0 0x0020 -#define TRNG_V1_RAND7 0x003C - -#define TRNG_V1_AUTO_RQSTS 0x0060 - -#define TRNG_V1_VERSION 0x00F0 -#define TRNG_v1_VERSION_CODE 0x46bc -/* end of TRNG_V1 register define */ - struct rk_rng_soc_data { - u32 default_offset; - - int (*rk_rng_init)(struct hwrng *rng); int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); }; @@ -137,38 +99,6 @@ static void rk_rng_cleanup(struct hwrng *rng) clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); } -static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -{ - int ret; - int read_len = 0; - struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); - - if (!rk_rng->soc_data->rk_rng_read) - return -EFAULT; - - ret = pm_runtime_get_sync(rk_rng->dev); - if (ret < 0) { - pm_runtime_put_noidle(rk_rng->dev); - return ret; - } - - ret = 0; - while (max > ret) { - read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret, - max - ret, wait); - if (read_len < 0) { - ret = read_len; - break; - } - ret += read_len; - } - - pm_runtime_mark_last_busy(rk_rng->dev); - pm_runtime_put_sync_autosuspend(rk_rng->dev); - - return ret; -} - static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, size_t size) { @@ -178,12 +108,18 @@ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); } -static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) +static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) { int ret = 0; u32 reg_ctrl = 0; struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + ret = pm_runtime_get_sync(rk_rng->dev); + if (ret < 0) { + pm_runtime_put_noidle(rk_rng->dev); + return ret; + } + /* enable osc_ring to get entropy, sample period is set as 100 */ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); @@ -208,15 +144,24 @@ out: rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), CRYPTO_V1_CTRL); + pm_runtime_mark_last_busy(rk_rng->dev); + pm_runtime_put_sync_autosuspend(rk_rng->dev); + return ret; } -static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) +static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) { int ret = 0; u32 reg_ctrl = 0; struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + ret = pm_runtime_get_sync(rk_rng->dev); + if (ret < 0) { + pm_runtime_put_noidle(rk_rng->dev); + return ret; + } + /* enable osc_ring to get entropy, sample period is set as 100 */ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); @@ -226,7 +171,7 @@ static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait reg_ctrl |= CRYPTO_V2_RNG_START; rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), - CRYPTO_V2_RNG_CTL); + CRYPTO_V2_RNG_CTL); ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl, !(reg_ctrl & CRYPTO_V2_RNG_START), @@ -243,139 +188,28 @@ out: /* close TRNG */ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); - return ret; -} - -static int rk_trng_v1_init(struct hwrng *rng) -{ - int ret; - uint32_t auto_reseed_cnt = 1000; - uint32_t reg_ctrl, status, version; - struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); - - ret = pm_runtime_get_sync(rk_rng->dev); - if (ret < 0) { - pm_runtime_put_noidle(rk_rng->dev); - return ret; - } - - version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); - if (version != TRNG_v1_VERSION_CODE) { - dev_err(rk_rng->dev, - "wrong trng version, expected = %08x, actual = %08x\n", - TRNG_V1_VERSION, version); - ret = -EFAULT; - goto exit; - } - - status = rk_rng_readl(rk_rng, TRNG_V1_STAT); - - /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */ - if (!(status & TRNG_V1_STAT_SEEDED) || - (status & TRNG_V1_STAT_GENERATING) || - (status & TRNG_V1_STAT_RESEEDING)) { - uint32_t mask = TRNG_V1_STAT_SEEDED | - TRNG_V1_STAT_GENERATING | - TRNG_V1_STAT_RESEEDING; - - udelay(10); - - /* wait for GENERATING and RESEEDING flag to clear */ - readl_poll_timeout(rk_rng->mem + TRNG_V1_STAT, reg_ctrl, - (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED, - ROCKCHIP_POLL_PERIOD_US, - ROCKCHIP_POLL_TIMEOUT_US); - } - - /* clear ISTAT flag because trng may auto reseeding when power on */ - reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); - rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); - - /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */ - rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS); - - ret = 0; -exit: pm_runtime_mark_last_busy(rk_rng->dev); pm_runtime_put_sync_autosuspend(rk_rng->dev); return ret; } -static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -{ - int ret = 0; - u32 reg_ctrl = 0; - struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); - - /* clear ISTAT anyway */ - reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); - rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); - - /* generate 256bit random */ - rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); - rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); - - /* - * Generate2 56 bit random data will cost 1024 clock cycles. - * Estimated at 150M RNG module frequency, it takes 6.7 microseconds. - */ - udelay(10); - reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); - if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) { - /* wait RAND_RDY triggered */ - ret = readl_poll_timeout(rk_rng->mem + TRNG_V1_ISTAT, reg_ctrl, - (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY), - ROCKCHIP_POLL_PERIOD_US, - ROCKCHIP_POLL_TIMEOUT_US); - if (ret < 0) - goto out; - } - - ret = min_t(size_t, max, RK_MAX_RNG_BYTE); - - rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret); - - /* clear all status flag */ - rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -out: - /* close TRNG */ - rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); - - return ret; -} - -static const struct rk_rng_soc_data rk_crypto_v1_soc_data = { - .default_offset = 0, - - .rk_rng_read = rk_crypto_v1_read, +static const struct rk_rng_soc_data rk_rng_v1_soc_data = { + .rk_rng_read = rk_rng_v1_read, }; -static const struct rk_rng_soc_data rk_crypto_v2_soc_data = { - .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET, - - .rk_rng_read = rk_crypto_v2_read, -}; - -static const struct rk_rng_soc_data rk_trng_v1_soc_data = { - .default_offset = 0, - - .rk_rng_init = rk_trng_v1_init, - .rk_rng_read = rk_trng_v1_read, +static const struct rk_rng_soc_data rk_rng_v2_soc_data = { + .rk_rng_read = rk_rng_v2_read, }; static const struct of_device_id rk_rng_dt_match[] = { { .compatible = "rockchip,cryptov1-rng", - .data = (void *)&rk_crypto_v1_soc_data, + .data = (void *)&rk_rng_v1_soc_data, }, { .compatible = "rockchip,cryptov2-rng", - .data = (void *)&rk_crypto_v2_soc_data, - }, - { - .compatible = "rockchip,trngv1", - .data = (void *)&rk_trng_v1_soc_data, + .data = (void *)&rk_rng_v2_soc_data, }, { }, }; @@ -388,7 +222,6 @@ static int rk_rng_probe(struct platform_device *pdev) struct rk_rng *rk_rng; struct device_node *np = pdev->dev.of_node; const struct of_device_id *match; - resource_size_t map_size; dev_dbg(&pdev->dev, "probing...\n"); rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); @@ -404,27 +237,13 @@ static int rk_rng_probe(struct platform_device *pdev) rk_rng->rng.init = rk_rng_init; rk_rng->rng.cleanup = rk_rng_cleanup, #endif - rk_rng->rng.read = rk_rng_read; + rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; rk_rng->rng.quality = 999; - rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size); + rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rk_rng->mem)) return PTR_ERR(rk_rng->mem); - /* compatible with crypto v2 module */ - /* - * With old dtsi configurations, the RNG base was equal to the crypto - * base, so both drivers could not be enabled at the same time. - * RNG base = CRYPTO base + RNG offset - * (Since RK356X, RNG module is no longer belongs to CRYPTO module) - * - * With new dtsi configurations, CRYPTO regs is divided into two parts - * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base. - * RNG driver and CRYPTO driver could be enabled at the same time. - */ - if (map_size > rk_rng->soc_data->default_offset) - rk_rng->mem += rk_rng->soc_data->default_offset; - rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks); if (rk_rng->clk_num < 0) { dev_err(&pdev->dev, "failed to get clks property\n"); @@ -434,7 +253,7 @@ static int rk_rng_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rk_rng); pm_runtime_set_autosuspend_delay(&pdev->dev, - ROCKCHIP_AUTOSUSPEND_DELAY); + ROCKCHIP_AUTOSUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); @@ -444,10 +263,6 @@ static int rk_rng_probe(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); } - /* for some platform need hardware operation when probe */ - if (rk_rng->soc_data->rk_rng_init) - ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng); - return ret; } @@ -470,7 +285,7 @@ static int rk_rng_runtime_resume(struct device *dev) static const struct dev_pm_ops rk_rng_pm_ops = { SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, - rk_rng_runtime_resume, NULL) + rk_rng_runtime_resume, NULL) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) }; diff --git a/target/linux/rockchip/files/drivers/net/phy/motorcomm.c b/target/linux/rockchip/files/drivers/net/phy/motorcomm.c new file mode 100644 index 000000000..04955bb6f --- /dev/null +++ b/target/linux/rockchip/files/drivers/net/phy/motorcomm.c @@ -0,0 +1,414 @@ +/* + * drivers/net/phy/motorcomm.c + * + * Driver for Motorcomm PHYs + * + * Author: Leilei Zhao + * + * Copyright (c) 2019 Motorcomm, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Support : Motorcomm Phys: + * Giga phys: yt8511, yt8521 + * 100/10 Phys : yt8512, yt8512b, yt8510 + * Automotive 100Mb Phys : yt8010 + * Automotive 100/10 hyper range Phys: yt8510 + */ + +#include +#include +#include +#include +#include +#include + +static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) +{ + int ret; + int val; + + ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); + if (ret < 0) + return ret; + + val = phy_read(phydev, REG_DEBUG_DATA); + + return val; +} + +static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) +{ + int ret; + + ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); + if (ret < 0) + return ret; + + ret = phy_write(phydev, REG_DEBUG_DATA, val); + + return ret; +} + +static int yt8010_config_aneg(struct phy_device *phydev) +{ + phydev->speed = SPEED_100; + return 0; +} + +static int yt8511_config_init(struct phy_device *phydev) +{ + int ret; + int val; + + /* disable auto sleep */ + val = ytphy_read_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1); + if (val < 0) + return val; + + val &= (~BIT(YT8511_EN_SLEEP_SW_BIT)); + ret = ytphy_write_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1, val); + if (ret < 0) + return ret; + + /* output SyncE clock (125mhz) even link is down */ + ret = ytphy_write_ext(phydev, 0xa012, 0xd0); + if (ret < 0) + return ret; + + /* enable RXC clock when no wire plug */ + val = ytphy_read_ext(phydev, 0xc); + if (val < 0) + return val; + + /* ext reg 0xc.b[2:1] + 00-----25M from pll; + 01---- 25M from xtl;(default) + 10-----62.5M from pll; + 11----125M from pll(here set to this value) + */ + val |= (3 << 1); + ret = ytphy_write_ext(phydev, 0xc, val); + if (ret < 0) + return ret; + + /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */ + ytphy_write_ext(phydev, 0xa00b, 0xe004); + ytphy_write_ext(phydev, 0xa00c, 0); + ytphy_write_ext(phydev, 0xa00d, 0x2600); + ytphy_write_ext(phydev, 0xa00e, 0x0070); + ytphy_write_ext(phydev, 0xa00f, 0x000a); + + return 0; +} + +static int yt8512_clk_init(struct phy_device *phydev) +{ + int ret; + int val; + + val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); + if (val < 0) + return val; + + val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; + + ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); + if (ret < 0) + return ret; + + val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); + if (val < 0) + return val; + + val |= YT8512_CONTROL1_RMII_EN; + + ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); + if (ret < 0) + return ret; + + val = phy_read(phydev, MII_BMCR); + if (val < 0) + return val; + + val |= YT_SOFTWARE_RESET; + ret = phy_write(phydev, MII_BMCR, val); + + return ret; +} + +static int yt8512_led_init(struct phy_device *phydev) +{ + int ret; + int val; + int mask; + + val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); + if (val < 0) + return val; + + val |= YT8512_LED0_ACT_BLK_IND; + + mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | + YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | + YT8512_LED0_BT_ON_EN; + val &= ~mask; + + ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); + if (ret < 0) + return ret; + + val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); + if (val < 0) + return val; + + val |= YT8512_LED1_BT_ON_EN; + + mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; + val &= ~mask; + + ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); + + return ret; +} + +static int yt8512_config_init(struct phy_device *phydev) +{ + int ret; + int val; + + ret = yt8512_clk_init(phydev); + if (ret < 0) + return ret; + + ret = yt8512_led_init(phydev); + + /* disable auto sleep */ + val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); + if (val < 0) + return val; + + val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); + + ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); + if (ret < 0) + return ret; + + return ret; +} + +static int yt8512_read_status(struct phy_device *phydev) +{ + int ret; + int val; + int speed, speed_mode, duplex; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + val = phy_read(phydev, REG_PHY_SPEC_STATUS); + if (val < 0) + return val; + + duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; + speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; + switch (speed_mode) { + case 0: + speed = SPEED_10; + break; + case 1: + speed = SPEED_100; + break; + case 2: + case 3: + default: + speed = SPEED_UNKNOWN; + break; + } + + phydev->speed = speed; + phydev->duplex = duplex; + + return 0; +} + +static int yt8521_config_init(struct phy_device *phydev) +{ + int ret; + int val; + + /* disable auto sleep */ + val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); + if (val < 0) + return val; + + val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); + ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); + if (ret < 0) + return ret; + + /* switch to access UTP */ + ret = ytphy_write_ext(phydev, 0xa000, 0); + if (ret < 0) + return ret; + + /* enable RXC clock when no wire plug */ + val = ytphy_read_ext(phydev, 0xc); + if (val < 0) + return val; + + val &= ~(1 << 12); + ret = ytphy_write_ext(phydev, 0xc, val); + if (ret < 0) + return ret; + + /* output SyncE clock (125mhz) even link is down */ + ret = ytphy_write_ext(phydev, 0xa012, 0x38); + if (ret < 0) + return ret; + + /* disable rgmii clk 2ns delay */ + val = ytphy_read_ext(phydev, 0xa001); + if (val < 0) + return val; + + val &= ~(1 << 8); + ret = ytphy_write_ext(phydev, 0xa001, val); + if (ret < 0) + return ret; + + /* setup delay */ + val = (1 << 10) | (0xf << 4) | 5; + ret = ytphy_write_ext(phydev, 0xa003, val); + if (ret < 0) + return ret; + + /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */ + ytphy_write_ext(phydev, 0xa00b, 0xe004); + ytphy_write_ext(phydev, 0xa00c, 0); + ytphy_write_ext(phydev, 0xa00d, 0x2600); + ytphy_write_ext(phydev, 0xa00e, 0x0070); + ytphy_write_ext(phydev, 0xa00f, 0x000a); + + return 0; +} + +static int yt8521_config_intr(struct phy_device *phydev) +{ + int val; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + val = BIT(14) | BIT(13) | BIT(11) | BIT(10); + else + val = 0; + + return phy_write(phydev, REG_INT_MASK, val); +} + +static int yt8521_ack_interrupt(struct phy_device *phydev) +{ + int val; + + val = phy_read(phydev, REG_INT_STATUS); + phydev_dbg(phydev, "intr status 0x04%x\n", val); + + return (val < 0) ? val : 0; +} + +static struct phy_driver ytphy_drvs[] = { + { + .phy_id = PHY_ID_YT8010, + .name = "YT8010 Automotive Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_BASIC_FEATURES, + .config_aneg = yt8010_config_aneg, + .read_status = genphy_read_status, + }, { + .phy_id = PHY_ID_YT8510, + .name = "YT8510 100/10Mb Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_BASIC_FEATURES, + .read_status = genphy_read_status, + }, { + .phy_id = PHY_ID_YT8511, + .name = "YT8511 Gigabit Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_YT8512, + .name = "YT8512 Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_BASIC_FEATURES, + .config_init = yt8512_config_init, + .read_status = yt8512_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_YT8512B, + .name = "YT8512B Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_BASIC_FEATURES, + .config_init = yt8512_config_init, + .read_status = yt8512_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_YT8521, + .name = "YT8521 Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + /* PHY_GBIT_FEATURES */ + .config_init = yt8521_config_init, + .ack_interrupt = yt8521_ack_interrupt, + .config_intr = yt8521_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + /* same as 8521 */ + .phy_id = PHY_ID_YT8531S, + .name = "YT8531S Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + /* PHY_GBIT_FEATURES */ + .config_init = yt8521_config_init, + .ack_interrupt = yt8521_ack_interrupt, + .config_intr = yt8521_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + /* same as 8511 */ + .phy_id = PHY_ID_YT8531, + .name = "YT8531 Gigabit Ethernet", + .phy_id_mask = MOTORCOMM_PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .config_init = yt8511_config_init, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, +}; + +module_phy_driver(ytphy_drvs); + +MODULE_DESCRIPTION("Motorcomm PHY driver"); +MODULE_AUTHOR("Leilei Zhao"); +MODULE_LICENSE("GPL"); + +static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { + { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, + { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK }, + { PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); diff --git a/target/linux/rockchip/files/drivers/phy/rockchip/p3phy.fw b/target/linux/rockchip/files/drivers/phy/rockchip/p3phy.fw deleted file mode 100644 index 301c42837..000000000 --- a/target/linux/rockchip/files/drivers/phy/rockchip/p3phy.fw +++ /dev/null @@ -1,8192 +0,0 @@ -0x081D, -0xFFFF, -0x33AF, -0x33AE, -0x0C4F, -0xD10D, -0x0D0F, -0xD306, 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a/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-inno-usb3.c +++ /dev/null @@ -1,1175 +0,0 @@ -/* - * Rockchip USB 3.0 PHY with Innosilicon IP block driver - * - * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define U3PHY_PORT_NUM 2 -#define U3PHY_MAX_CLKS 4 -#define BIT_WRITEABLE_SHIFT 16 -#define SCHEDULE_DELAY (60 * HZ) - -#define U3PHY_APB_RST BIT(0) -#define U3PHY_POR_RST BIT(1) -#define U3PHY_MAC_RST BIT(2) - -struct rockchip_u3phy; -struct rockchip_u3phy_port; - -enum rockchip_u3phy_type { - U3PHY_TYPE_PIPE, - U3PHY_TYPE_UTMI, -}; - -enum rockchip_u3phy_pipe_pwr { - PIPE_PWR_P0 = 0, - PIPE_PWR_P1 = 1, - PIPE_PWR_P2 = 2, - PIPE_PWR_P3 = 3, - PIPE_PWR_MAX = 4, -}; - -enum rockchip_u3phy_rest_req { - U3_POR_RSTN = 0, - U2_POR_RSTN = 1, - PIPE_MAC_RSTN = 2, - UTMI_MAC_RSTN = 3, - PIPE_APB_RSTN = 4, - UTMI_APB_RSTN = 5, - U3PHY_RESET_MAX = 6, -}; - -enum rockchip_u3phy_utmi_state { - PHY_UTMI_HS_ONLINE = 0, - PHY_UTMI_DISCONNECT = 1, - PHY_UTMI_CONNECT = 2, - PHY_UTMI_FS_LS_ONLINE = 4, -}; - -/* - * @rvalue: reset value - * @dvalue: desired value - */ -struct u3phy_reg { - unsigned int offset; - unsigned int bitend; - unsigned int bitstart; - unsigned int rvalue; - unsigned int dvalue; -}; - -struct rockchip_u3phy_grfcfg { - struct u3phy_reg um_suspend; - struct u3phy_reg ls_det_en; - struct u3phy_reg ls_det_st; - struct u3phy_reg um_ls; - struct u3phy_reg um_hstdct; - struct u3phy_reg u2_only_ctrl; - struct u3phy_reg u3_disable; - struct u3phy_reg pp_pwr_st; - struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX]; -}; - -/** - * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration. - * @u2_pre_emp: usb2-phy pre-emphasis tuning. - * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning. - * @u2_odt_tuning: usb2-phy odt 45ohm tuning. - */ -struct rockchip_u3phy_apbcfg { - unsigned int u2_pre_emp; - unsigned int u2_pre_emp_sth; - unsigned int u2_odt_tuning; -}; - -struct rockchip_u3phy_cfg { - unsigned int reg; - const struct rockchip_u3phy_grfcfg grfcfg; - - int (*phy_pipe_power)(struct rockchip_u3phy *, - struct rockchip_u3phy_port *, - bool on); - int (*phy_tuning)(struct rockchip_u3phy *, - struct rockchip_u3phy_port *, - struct device_node *); - int (*phy_cp_test)(struct rockchip_u3phy *, - struct rockchip_u3phy_port *); -}; - -struct rockchip_u3phy_port { - struct phy *phy; - void __iomem *base; - unsigned int index; - unsigned char type; - bool suspended; - bool refclk_25m_quirk; - struct mutex mutex; /* mutex for updating register */ - struct delayed_work um_sm_work; -}; - -struct rockchip_u3phy { - struct device *dev; - struct regmap *u3phy_grf; - struct regmap *grf; - int um_ls_irq; - struct clk *clks[U3PHY_MAX_CLKS]; - struct dentry *root; - struct regulator *vbus; - struct reset_control *rsts[U3PHY_RESET_MAX]; - struct rockchip_u3phy_apbcfg apbcfg; - const struct rockchip_u3phy_cfg *cfgs; - struct rockchip_u3phy_port ports[U3PHY_PORT_NUM]; - struct usb_phy usb_phy; - bool vbus_enabled; -}; - -static inline int param_write(void __iomem *base, - const struct u3phy_reg *reg, bool desired) -{ - unsigned int val, mask; - unsigned int tmp = desired ? reg->dvalue : reg->rvalue; - int ret = 0; - - mask = GENMASK(reg->bitend, reg->bitstart); - val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); - ret = regmap_write(base, reg->offset, val); - - return ret; -} - -static inline bool param_exped(void __iomem *base, - const struct u3phy_reg *reg, - unsigned int value) -{ - int ret; - unsigned int tmp, orig; - unsigned int mask = GENMASK(reg->bitend, reg->bitstart); - - ret = regmap_read(base, reg->offset, &orig); - if (ret) - return false; - - tmp = (orig & mask) >> reg->bitstart; - return tmp == value; -} - -static int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en) -{ - int ret = 0; - - if (!u3phy->vbus) - return 0; - - if (en && !u3phy->vbus_enabled) { - ret = regulator_enable(u3phy->vbus); - if (ret) - dev_err(u3phy->dev, - "Failed to enable VBUS supply\n"); - } else if (!en && u3phy->vbus_enabled) { - ret = regulator_disable(u3phy->vbus); - } - - if (ret == 0) - u3phy->vbus_enabled = en; - - return ret; -} - -static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused) -{ - struct rockchip_u3phy *u3phy = s->private; - - if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) - dev_info(u3phy->dev, "u2\n"); - else - dev_info(u3phy->dev, "u3\n"); - - return 0; -} - -static int rockchip_u3phy_usb2_only_open(struct inode *inode, - struct file *file) -{ - return single_open(file, rockchip_u3phy_usb2_only_show, - inode->i_private); -} - -static ssize_t rockchip_u3phy_usb2_only_write(struct file *file, - const char __user *ubuf, - size_t count, loff_t *ppos) -{ - struct seq_file *s = file->private_data; - struct rockchip_u3phy *u3phy = s->private; - struct rockchip_u3phy_port *u3phy_port; - char buf[32]; - u8 index; - - if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) - return -EFAULT; - - if (!strncmp(buf, "u3", 2) && - param_exped(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) { - dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n"); - - rockchip_set_vbus_power(u3phy, false); - - param_write(u3phy->grf, - &u3phy->cfgs->grfcfg.u3_disable, false); - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.u2_only_ctrl, false); - - for (index = 0; index < U3PHY_PORT_NUM; index++) { - u3phy_port = &u3phy->ports[index]; - /* enable u3 rx termimation */ - if (u3phy_port->type == U3PHY_TYPE_PIPE) - writel(0x30, u3phy_port->base + 0xd8); - } - - atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); - - rockchip_set_vbus_power(u3phy, true); - } else if (!strncmp(buf, "u2", 2) && - param_exped(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) { - dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n"); - - rockchip_set_vbus_power(u3phy, false); - - param_write(u3phy->grf, - &u3phy->cfgs->grfcfg.u3_disable, true); - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.u2_only_ctrl, true); - - for (index = 0; index < U3PHY_PORT_NUM; index++) { - u3phy_port = &u3phy->ports[index]; - /* disable u3 rx termimation */ - if (u3phy_port->type == U3PHY_TYPE_PIPE) - writel(0x20, u3phy_port->base + 0xd8); - } - - atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); - - rockchip_set_vbus_power(u3phy, true); - } else { - dev_info(u3phy->dev, "Same or illegal mode\n"); - } - - return count; -} - -static const struct file_operations rockchip_u3phy_usb2_only_fops = { - .open = rockchip_u3phy_usb2_only_open, - .write = rockchip_u3phy_usb2_only_write, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy) -{ - struct dentry *root; - struct dentry *file; - int ret; - - root = debugfs_create_dir(dev_name(u3phy->dev), NULL); - if (!root) { - ret = -ENOMEM; - goto err0; - } - - u3phy->root = root; - - file = debugfs_create_file("u3phy_mode", 0644, root, - u3phy, &rockchip_u3phy_usb2_only_fops); - if (!file) { - ret = -ENOMEM; - goto err1; - } - return 0; - -err1: - debugfs_remove_recursive(root); -err0: - return ret; -} - -static const char *get_rest_name(enum rockchip_u3phy_rest_req rst) -{ - switch (rst) { - case U2_POR_RSTN: - return "u3phy-u2-por"; - case U3_POR_RSTN: - return "u3phy-u3-por"; - case PIPE_MAC_RSTN: - return "u3phy-pipe-mac"; - case UTMI_MAC_RSTN: - return "u3phy-utmi-mac"; - case UTMI_APB_RSTN: - return "u3phy-utmi-apb"; - case PIPE_APB_RSTN: - return "u3phy-pipe-apb"; - default: - return "invalid"; - } -} - -static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, - unsigned int flag) -{ - int rst; - - if (flag & U3PHY_APB_RST) { - dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); - for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) { - if (u3phy->rsts[rst]) - reset_control_deassert(u3phy->rsts[rst]); - } - } - - if (flag & U3PHY_POR_RST) { - usleep_range(12, 15); - dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); - for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) { - if (u3phy->rsts[rst]) - reset_control_deassert(u3phy->rsts[rst]); - } - } - - if (flag & U3PHY_MAC_RST) { - usleep_range(1200, 1500); - dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); - for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++) - if (u3phy->rsts[rst]) - reset_control_deassert(u3phy->rsts[rst]); - } -} - -static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy) -{ - int rst; - - dev_dbg(u3phy->dev, "assert u3phy reset\n"); - for (rst = 0; rst < U3PHY_RESET_MAX; rst++) - if (u3phy->rsts[rst]) - reset_control_assert(u3phy->rsts[rst]); -} - -static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy) -{ - int ret, clk; - - for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) { - ret = clk_prepare_enable(u3phy->clks[clk]); - if (ret) - goto err_disable_clks; - } - return 0; - -err_disable_clks: - while (--clk >= 0) - clk_disable_unprepare(u3phy->clks[clk]); - return ret; -} - -static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy) -{ - int clk; - - for (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--) - if (u3phy->clks[clk]) - clk_disable_unprepare(u3phy->clks[clk]); -} - -static int rockchip_u3phy_init(struct phy *phy) -{ - return 0; -} - -static int rockchip_u3phy_exit(struct phy *phy) -{ - return 0; -} - -static int rockchip_u3phy_power_on(struct phy *phy) -{ - struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); - struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - int ret; - - dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", - (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); - - if (!u3phy_port->suspended) - return 0; - - ret = rockchip_u3phy_clk_enable(u3phy); - if (ret) - return ret; - - if (u3phy_port->type == U3PHY_TYPE_UTMI) { - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.um_suspend, false); - } else { - /* current in p2 ? */ - if (param_exped(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) - goto done; - - if (u3phy->cfgs->phy_pipe_power) { - dev_dbg(u3phy->dev, "do pipe power up\n"); - u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); - } - - /* exit to p0 */ - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); - usleep_range(90, 100); - - /* enter to p2 from p0 */ - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], - false); - udelay(3); - } - -done: - rockchip_set_vbus_power(u3phy, true); - u3phy_port->suspended = false; - return 0; -} - -static int rockchip_u3phy_power_off(struct phy *phy) -{ - struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); - struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - - dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", - (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); - - if (u3phy_port->suspended) - return 0; - - if (u3phy_port->type == U3PHY_TYPE_UTMI) { - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.um_suspend, true); - } else { - /* current in p3 ? */ - if (param_exped(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) - goto done; - - /* exit to p0 */ - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); - udelay(2); - - /* enter to p3 from p0 */ - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true); - udelay(6); - - if (u3phy->cfgs->phy_pipe_power) { - dev_dbg(u3phy->dev, "do pipe power down\n"); - u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); - } - } - -done: - rockchip_u3phy_clk_disable(u3phy); - u3phy_port->suspended = true; - return 0; -} - -static __maybe_unused int rockchip_u3phy_cp_test(struct phy *phy) -{ - struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); - struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - int ret; - - if (u3phy->cfgs->phy_cp_test) { - /* - * When do USB3 compliance test, we may connect the oscilloscope - * front panel Aux Out to the DUT SSRX+, the Aux Out of the - * oscilloscope outputs a negative pulse whose width is between - * 300- 400 ns which may trigger some DUTs to change the CP test - * pattern. - * - * The Inno USB3 PHY disable the function to detect the negative - * pulse in SSRX+ by default, so we need to enable the function - * to toggle the CP test pattern before do USB3 compliance test. - */ - dev_dbg(u3phy->dev, "prepare for u3phy compliance test\n"); - ret = u3phy->cfgs->phy_cp_test(u3phy, u3phy_port); - if (ret) - return ret; - } - - return 0; -} - -static __maybe_unused -struct phy *rockchip_u3phy_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct rockchip_u3phy *u3phy = dev_get_drvdata(dev); - struct rockchip_u3phy_port *u3phy_port = NULL; - struct device_node *phy_np = args->np; - int index; - - if (args->args_count != 1) { - dev_err(dev, "invalid number of cells in 'phy' property\n"); - return ERR_PTR(-EINVAL); - } - - for (index = 0; index < U3PHY_PORT_NUM; index++) { - if (phy_np == u3phy->ports[index].phy->dev.of_node) { - u3phy_port = &u3phy->ports[index]; - break; - } - } - - if (!u3phy_port) { - dev_err(dev, "failed to find appropriate phy\n"); - return ERR_PTR(-EINVAL); - } - - return u3phy_port->phy; -} - -static struct phy_ops rockchip_u3phy_ops = { - .init = rockchip_u3phy_init, - .exit = rockchip_u3phy_exit, - .power_on = rockchip_u3phy_power_on, - .power_off = rockchip_u3phy_power_off, - .owner = THIS_MODULE, -}; - -/* - * The function manage host-phy port state and suspend/resume phy port - * to save power automatically. - * - * we rely on utmi_linestate and utmi_hostdisconnect to identify whether - * devices is disconnect or not. Besides, we do not need care it is FS/LS - * disconnected or HS disconnected, actually, we just only need get the - * device is disconnected at last through rearm the delayed work, - * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. - */ -static void rockchip_u3phy_um_sm_work(struct work_struct *work) -{ - struct rockchip_u3phy_port *u3phy_port = - container_of(work, struct rockchip_u3phy_port, um_sm_work.work); - struct rockchip_u3phy *u3phy = - dev_get_drvdata(u3phy_port->phy->dev.parent); - unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - - u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1; - unsigned int ul, uhd, state; - unsigned int ul_mask, uhd_mask; - int ret; - - mutex_lock(&u3phy_port->mutex); - - ret = regmap_read(u3phy->u3phy_grf, - u3phy->cfgs->grfcfg.um_ls.offset, &ul); - if (ret < 0) - goto next_schedule; - - ret = regmap_read(u3phy->u3phy_grf, - u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd); - if (ret < 0) - goto next_schedule; - - uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, - u3phy->cfgs->grfcfg.um_hstdct.bitstart); - ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, - u3phy->cfgs->grfcfg.um_ls.bitstart); - - /* stitch on um_ls and um_hstdct as phy state */ - state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) | - (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh); - - switch (state) { - case PHY_UTMI_HS_ONLINE: - dev_dbg(&u3phy_port->phy->dev, "HS online\n"); - break; - case PHY_UTMI_FS_LS_ONLINE: - /* - * For FS/LS device, the online state share with connect state - * from um_ls and um_hstdct register, so we distinguish - * them via suspended flag. - * - * Plus, there are two cases, one is D- Line pull-up, and D+ - * line pull-down, the state is 4; another is D+ line pull-up, - * and D- line pull-down, the state is 2. - */ - if (!u3phy_port->suspended) { - /* D- line pull-up, D+ line pull-down */ - dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); - break; - } - /* fall through */ - case PHY_UTMI_CONNECT: - if (u3phy_port->suspended) { - dev_dbg(&u3phy_port->phy->dev, "Connected\n"); - rockchip_u3phy_power_on(u3phy_port->phy); - u3phy_port->suspended = false; - } else { - /* D+ line pull-up, D- line pull-down */ - dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); - } - break; - case PHY_UTMI_DISCONNECT: - if (!u3phy_port->suspended) { - dev_dbg(&u3phy_port->phy->dev, "Disconnected\n"); - rockchip_u3phy_power_off(u3phy_port->phy); - u3phy_port->suspended = true; - } - - /* - * activate the linestate detection to get the next device - * plug-in irq. - */ - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.ls_det_st, true); - param_write(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.ls_det_en, true); - - /* - * we don't need to rearm the delayed work when the phy port - * is suspended. - */ - mutex_unlock(&u3phy_port->mutex); - return; - default: - dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n"); - break; - } - -next_schedule: - mutex_unlock(&u3phy_port->mutex); - schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY); -} - -static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data) -{ - struct rockchip_u3phy_port *u3phy_port = data; - struct rockchip_u3phy *u3phy = - dev_get_drvdata(u3phy_port->phy->dev.parent); - - if (!param_exped(u3phy->u3phy_grf, - &u3phy->cfgs->grfcfg.ls_det_st, - u3phy->cfgs->grfcfg.ls_det_st.dvalue)) - return IRQ_NONE; - - dev_dbg(u3phy->dev, "utmi linestate interrupt\n"); - mutex_lock(&u3phy_port->mutex); - - /* disable linestate detect irq and clear its status */ - param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false); - param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true); - - mutex_unlock(&u3phy_port->mutex); - - /* - * In this case for host phy, a new device is plugged in, meanwhile, - * if the phy port is suspended, we need rearm the work to resume it - * and mange its states; otherwise, we just return irq handled. - */ - if (u3phy_port->suspended) { - dev_dbg(u3phy->dev, "schedule utmi sm work\n"); - rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work); - } - - return IRQ_HANDLED; -} - -static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, - struct platform_device *pdev) - -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - int ret, i, clk; - - u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate"); - if (u3phy->um_ls_irq < 0) { - dev_err(dev, "get utmi linestate irq failed\n"); - return -ENXIO; - } - - /* Get Vbus regulators */ - u3phy->vbus = devm_regulator_get_optional(dev, "vbus"); - if (IS_ERR(u3phy->vbus)) { - ret = PTR_ERR(u3phy->vbus); - if (ret == -EPROBE_DEFER) - return ret; - - dev_warn(dev, "Failed to get VBUS supply regulator\n"); - u3phy->vbus = NULL; - } - - for (clk = 0; clk < U3PHY_MAX_CLKS; clk++) { - u3phy->clks[clk] = of_clk_get(np, clk); - if (IS_ERR(u3phy->clks[clk])) { - ret = PTR_ERR(u3phy->clks[clk]); - if (ret == -EPROBE_DEFER) - goto err_put_clks; - u3phy->clks[clk] = NULL; - break; - } - } - - for (i = 0; i < U3PHY_RESET_MAX; i++) { - u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i)); - if (IS_ERR(u3phy->rsts[i])) { - dev_info(dev, "no %s reset control specified\n", - get_rest_name(i)); - u3phy->rsts[i] = NULL; - } - } - - return 0; - -err_put_clks: - while (--clk >= 0) - clk_put(u3phy->clks[clk]); - return ret; -} - -static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, - struct rockchip_u3phy_port *u3phy_port, - struct device_node *child_np) -{ - struct resource res; - struct phy *phy; - int ret; - - dev_dbg(u3phy->dev, "u3phy port initialize\n"); - - mutex_init(&u3phy_port->mutex); - u3phy_port->suspended = true; /* initial status */ - - phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops); - if (IS_ERR(phy)) { - dev_err(u3phy->dev, "failed to create phy\n"); - return PTR_ERR(phy); - } - - u3phy_port->phy = phy; - - ret = of_address_to_resource(child_np, 0, &res); - if (ret) { - dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", - child_np->name); - return ret; - } - - u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); - if (IS_ERR(u3phy_port->base)) { - dev_err(u3phy->dev, "failed to remap phy regs\n"); - return PTR_ERR(u3phy_port->base); - } - - if (!of_node_cmp(child_np->name, "pipe")) { - u3phy_port->type = U3PHY_TYPE_PIPE; - u3phy_port->refclk_25m_quirk = - of_property_read_bool(child_np, - "rockchip,refclk-25m-quirk"); - } else { - u3phy_port->type = U3PHY_TYPE_UTMI; - INIT_DELAYED_WORK(&u3phy_port->um_sm_work, - rockchip_u3phy_um_sm_work); - - ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, - NULL, rockchip_u3phy_um_ls_irq, - IRQF_ONESHOT, "rockchip_u3phy", - u3phy_port); - if (ret) { - dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n"); - return ret; - } - } - - if (u3phy->cfgs->phy_tuning) { - dev_dbg(u3phy->dev, "do u3phy tuning\n"); - ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); - if (ret) - return ret; - } - - phy_set_drvdata(u3phy_port->phy, u3phy_port); - return 0; -} - -static int rockchip_u3phy_on_init(struct usb_phy *usb_phy) -{ - struct rockchip_u3phy *u3phy = - container_of(usb_phy, struct rockchip_u3phy, usb_phy); - - rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST); - return 0; -} - -static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy) -{ - struct rockchip_u3phy *u3phy = - container_of(usb_phy, struct rockchip_u3phy, usb_phy); - int rst; - - for (rst = 0; rst < U3PHY_RESET_MAX; rst++) - if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && - rst != PIPE_APB_RSTN) - reset_control_assert(u3phy->rsts[rst]); - udelay(1); -} - -static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy, - enum usb_device_speed speed) -{ - struct rockchip_u3phy *u3phy = - container_of(usb_phy, struct rockchip_u3phy, usb_phy); - - dev_info(u3phy->dev, "%s device has disconnected\n", - (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1"); - - if (speed == USB_SPEED_SUPER) - atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL); - - return 0; -} - -static int rockchip_u3phy_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct device_node *child_np; - struct phy_provider *provider; - struct rockchip_u3phy *u3phy; - const struct rockchip_u3phy_cfg *phy_cfgs; - const struct of_device_id *match; - unsigned int reg[2]; - int index, ret; - - match = of_match_device(dev->driver->of_match_table, dev); - if (!match || !match->data) { - dev_err(dev, "phy-cfgs are not assigned!\n"); - return -EINVAL; - } - - u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL); - if (!u3phy) - return -ENOMEM; - - u3phy->u3phy_grf = - syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf"); - if (IS_ERR(u3phy->u3phy_grf)) - return PTR_ERR(u3phy->u3phy_grf); - - u3phy->grf = - syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(u3phy->grf)) { - dev_err(dev, "Missing rockchip,grf property\n"); - return PTR_ERR(u3phy->grf); - } - - if (of_property_read_u32_array(np, "reg", reg, 2)) { - dev_err(dev, "the reg property is not assigned in %s node\n", - np->name); - return -EINVAL; - } - - u3phy->dev = dev; - u3phy->vbus_enabled = false; - phy_cfgs = match->data; - platform_set_drvdata(pdev, u3phy); - - /* find out a proper config which can be matched with dt. */ - index = 0; - while (phy_cfgs[index].reg) { - if (phy_cfgs[index].reg == reg[1]) { - u3phy->cfgs = &phy_cfgs[index]; - break; - } - - ++index; - } - - if (!u3phy->cfgs) { - dev_err(dev, "no phy-cfgs can be matched with %s node\n", - np->name); - return -EINVAL; - } - - ret = rockchip_u3phy_parse_dt(u3phy, pdev); - if (ret) { - dev_err(dev, "parse dt failed, ret(%d)\n", ret); - return ret; - } - - ret = rockchip_u3phy_clk_enable(u3phy); - if (ret) { - dev_err(dev, "clk enable failed, ret(%d)\n", ret); - return ret; - } - - rockchip_u3phy_rest_assert(u3phy); - rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST); - - index = 0; - for_each_available_child_of_node(np, child_np) { - struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; - - u3phy_port->index = index; - ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np); - if (ret) { - dev_err(dev, "u3phy port init failed,ret(%d)\n", ret); - goto put_child; - } - - /* to prevent out of boundary */ - if (++index >= U3PHY_PORT_NUM) - break; - } - - provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR_OR_NULL(provider)) - goto put_child; - - rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST); - rockchip_u3phy_clk_disable(u3phy); - - u3phy->usb_phy.dev = dev; - u3phy->usb_phy.init = rockchip_u3phy_on_init; - u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown; - u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect; - usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3); - ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier); - - rockchip_u3phy_debugfs_init(u3phy); - - dev_info(dev, "Rockchip u3phy initialized successfully\n"); - return 0; - -put_child: - of_node_put(child_np); - return ret; -} - -static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy, - struct rockchip_u3phy_port *u3phy_port, - bool on) -{ - unsigned int reg; - - if (on) { - reg = readl(u3phy_port->base + 0x1a8); - reg &= ~BIT(4); /* ldo power up */ - writel(reg, u3phy_port->base + 0x1a8); - - reg = readl(u3phy_port->base + 0x044); - reg &= ~BIT(4); /* bg power on */ - writel(reg, u3phy_port->base + 0x044); - - reg = readl(u3phy_port->base + 0x150); - reg |= BIT(6); /* tx bias enable */ - writel(reg, u3phy_port->base + 0x150); - - reg = readl(u3phy_port->base + 0x080); - reg &= ~BIT(2); /* tx cm power up */ - writel(reg, u3phy_port->base + 0x080); - - reg = readl(u3phy_port->base + 0x0c0); - /* tx obs enable and rx cm enable */ - reg |= (BIT(3) | BIT(4)); - writel(reg, u3phy_port->base + 0x0c0); - - udelay(1); - } else { - reg = readl(u3phy_port->base + 0x1a8); - reg |= BIT(4); /* ldo power down */ - writel(reg, u3phy_port->base + 0x1a8); - - reg = readl(u3phy_port->base + 0x044); - reg |= BIT(4); /* bg power down */ - writel(reg, u3phy_port->base + 0x044); - - reg = readl(u3phy_port->base + 0x150); - reg &= ~BIT(6); /* tx bias disable */ - writel(reg, u3phy_port->base + 0x150); - - reg = readl(u3phy_port->base + 0x080); - reg |= BIT(2); /* tx cm power down */ - writel(reg, u3phy_port->base + 0x080); - - reg = readl(u3phy_port->base + 0x0c0); - /* tx obs disable and rx cm disable */ - reg &= ~(BIT(3) | BIT(4)); - writel(reg, u3phy_port->base + 0x0c0); - } - - return 0; -} - -static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, - struct rockchip_u3phy_port *u3phy_port, - struct device_node *child_np) -{ - if (u3phy_port->type == U3PHY_TYPE_UTMI) { - /* - * For rk3328 SoC, pre-emphasis and pre-emphasis strength must - * be written as one fixed value as below. - * - * Dissimilarly, the odt 45ohm value should be flexibly tuninged - * for the different boards to adjust HS eye height, so its - * value can be assigned in DT in code design. - */ - - /* {bits[2:0]=111}: always enable pre-emphasis */ - u3phy->apbcfg.u2_pre_emp = 0x0f; - - /* {bits[5:3]=000}: pre-emphasis strength as the weakest */ - u3phy->apbcfg.u2_pre_emp_sth = 0x41; - - /* {bits[4:0]=10101}: odt 45ohm tuning */ - u3phy->apbcfg.u2_odt_tuning = 0xb5; - /* optional override of the odt 45ohm tuning */ - of_property_read_u32(child_np, "rockchip,odt-val-tuning", - &u3phy->apbcfg.u2_odt_tuning); - - writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); - writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); - writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); - } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { - if (u3phy_port->refclk_25m_quirk) { - dev_dbg(u3phy->dev, "switch to 25m refclk\n"); - /* ref clk switch to 25M */ - writel(0x64, u3phy_port->base + 0x11c); - writel(0x64, u3phy_port->base + 0x028); - writel(0x01, u3phy_port->base + 0x020); - writel(0x21, u3phy_port->base + 0x030); - writel(0x06, u3phy_port->base + 0x108); - writel(0x00, u3phy_port->base + 0x118); - } else { - /* configure for 24M ref clk */ - writel(0x80, u3phy_port->base + 0x10c); - writel(0x01, u3phy_port->base + 0x118); - writel(0x38, u3phy_port->base + 0x11c); - writel(0x83, u3phy_port->base + 0x020); - writel(0x02, u3phy_port->base + 0x108); - } - - /* Enable SSC */ - udelay(3); - writel(0x08, u3phy_port->base + 0x000); - writel(0x0c, u3phy_port->base + 0x120); - - /* Tuning Rx for compliance RJTL test */ - writel(0x70, u3phy_port->base + 0x150); - writel(0x12, u3phy_port->base + 0x0c8); - writel(0x05, u3phy_port->base + 0x148); - writel(0x08, u3phy_port->base + 0x068); - writel(0xf0, u3phy_port->base + 0x1c4); - writel(0xff, u3phy_port->base + 0x070); - writel(0x0f, u3phy_port->base + 0x06c); - writel(0xe0, u3phy_port->base + 0x060); - - /* - * Tuning Tx to increase the bias current - * used in TX driver and RX EQ, it can - * also increase the voltage of LFPS. - */ - writel(0x08, u3phy_port->base + 0x180); - } else { - dev_err(u3phy->dev, "invalid u3phy port type\n"); - return -EINVAL; - } - - return 0; -} - -static int rk322xh_u3phy_cp_test_enable(struct rockchip_u3phy *u3phy, - struct rockchip_u3phy_port *u3phy_port) -{ - if (u3phy_port->type == U3PHY_TYPE_PIPE) { - writel(0x0c, u3phy_port->base + 0x408); - } else { - dev_err(u3phy->dev, "The u3phy type is not pipe\n"); - return -EINVAL; - } - - return 0; -} - -static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = { - { - .reg = 0xff470000, - .grfcfg = { - .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 }, - .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 }, - .um_ls = { 0x0030, 5, 4, 0, 1 }, - .um_hstdct = { 0x0030, 7, 7, 0, 1 }, - .ls_det_en = { 0x0040, 0, 0, 0, 1 }, - .ls_det_st = { 0x0044, 0, 0, 0, 1 }, - .pp_pwr_st = { 0x0034, 14, 13, 0, 0}, - .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005}, - {0x0020, 14, 0, 0x0014, 0x000d}, - {0x0020, 14, 0, 0x0014, 0x0015}, - {0x0020, 14, 0, 0x0014, 0x001d} }, - .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101}, - }, - .phy_pipe_power = rk3328_u3phy_pipe_power, - .phy_tuning = rk3328_u3phy_tuning, - .phy_cp_test = rk322xh_u3phy_cp_test_enable, - }, - { /* sentinel */ } -}; - -static const struct of_device_id rockchip_u3phy_dt_match[] = { - { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs }, - {} -}; -MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match); - -static struct platform_driver rockchip_u3phy_driver = { - .probe = rockchip_u3phy_probe, - .driver = { - .name = "rockchip-u3phy", - .of_match_table = rockchip_u3phy_dt_match, - }, -}; -module_platform_driver(rockchip_u3phy_driver); - -MODULE_AUTHOR("Frank Wang "); -MODULE_AUTHOR("William Wu "); -MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c deleted file mode 100644 index 457648c21..000000000 --- a/target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Rockchip PCIE3.0 phy driver - * - * Copyright (C) 2020 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Register for RK3568 */ -#define GRF_PCIE30PHY_CON1 0x4 -#define GRF_PCIE30PHY_CON4 0x10 -#define GRF_PCIE30PHY_CON6 0x18 -#define GRF_PCIE30PHY_CON9 0x24 -#define GRF_PCIE30PHY_STATUS0 0x80 -#define SRAM_INIT_DONE(reg) (reg & BIT(14)) - -#define RK3568_BIFURCATION_LANE_0_1 BIT(0) - -/* Register for RK3588 */ -#define PHP_GRF_PCIESEL_CON 0x100 -#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 -#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 -#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 -#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) - -#define RK3588_BIFURCATION_LANE_0_1 BIT(0) -#define RK3588_BIFURCATION_LANE_2_3 BIT(1) -#define RK3588_LANE_AGGREGATION BIT(2) - -struct rockchip_p3phy_ops; - -struct rockchip_p3phy_priv { - const struct rockchip_p3phy_ops *ops; - void __iomem *mmio; - /* mode: RC, EP */ - int mode; - /* pcie30_phymode: Aggregation, Bifurcation */ - int pcie30_phymode; - struct regmap *phy_grf; - struct regmap *pipe_grf; - struct reset_control *p30phy; - struct phy *phy; - struct clk_bulk_data *clks; - int num_clks; - int num_lanes; - u32 lanes[4]; -}; - -struct rockchip_p3phy_ops { - int (*phy_init)(struct rockchip_p3phy_priv *priv); -}; - -static u16 phy_fw[] = { - #include "p3phy.fw" -}; - -static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) -{ - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); - - /* Actually We don't care EP/RC mode, but just record it */ - switch (submode) { - case PHY_MODE_PCIE_RC: - priv->mode = PHY_MODE_PCIE_RC; - break; - case PHY_MODE_PCIE_EP: - priv->mode = PHY_MODE_PCIE_EP; - break; - default: - dev_err(&phy->dev, "%s, invalid mode\n", __func__); - return -EINVAL; - } - - return 0; -} - -static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) -{ - struct phy *phy = priv->phy; - bool bifurcation = false; - int ret; - int i; - u32 reg; - - /* Deassert PCIe PMA output clamp mode */ - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); - - for (i = 0; i < priv->num_lanes; i++) { - dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); - if (priv->lanes[i] > 1) - bifurcation = true; - } - - /* Set bifurcation if needed, and it doesn't care RC/EP */ - if (bifurcation) { - dev_info(&phy->dev, "bifurcation enabled\n"); - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, - (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, - BIT(15) | BIT(31)); - } else { - dev_info(&phy->dev, "bifurcation disabled\n"); - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, - (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); - } - - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass - - reset_control_deassert(priv->p30phy); - - ret = regmap_read_poll_timeout(priv->phy_grf, - GRF_PCIE30PHY_STATUS0, - reg, SRAM_INIT_DONE(reg), - 0, 500); - if (ret) { - dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", - __func__, reg); - return ret; - } - - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, - (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram - for (i = 0; i < 8192; i++) - writel(phy_fw[i], priv->mmio + (i<<2)); - - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, - (0x0 << 8) | (0x3 << (8 + 16))); - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, - (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done - - dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n"); - return 0; -} - -static const struct rockchip_p3phy_ops rk3568_ops = { - .phy_init = rockchip_p3phy_rk3568_init, -}; - -static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) -{ - u32 reg = 0; - u8 mode = 0; - int ret; - int i; - - /* Deassert PCIe PMA output clamp mode */ - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); - - /* Set bifurcation if needed */ - for (i = 0; i < priv->num_lanes; i++) { - if (!priv->lanes[i]) - mode |= (BIT(i) << 3); - - if (priv->lanes[i] > 1) - mode |= (BIT(i) >> 1); - } - - if (!mode) - reg = RK3588_LANE_AGGREGATION; - else { - if (mode & (BIT(0) | BIT(1))) - reg |= RK3588_BIFURCATION_LANE_0_1; - - if (mode & (BIT(2) | BIT(3))) - reg |= RK3588_BIFURCATION_LANE_2_3; - } - - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); - - /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ - if (!IS_ERR(priv->pipe_grf)) { - reg = (mode & (BIT(6) | BIT(7))) >> 6; - if (reg) - regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, - (reg << 16) | reg); - } - - reset_control_deassert(priv->p30phy); - - ret = regmap_read_poll_timeout(priv->phy_grf, - RK3588_PCIE3PHY_GRF_PHY0_STATUS1, - reg, RK3588_SRAM_INIT_DONE(reg), - 0, 500); - ret |= regmap_read_poll_timeout(priv->phy_grf, - RK3588_PCIE3PHY_GRF_PHY1_STATUS1, - reg, RK3588_SRAM_INIT_DONE(reg), - 0, 500); - if (ret) - pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", - __func__, reg); - return ret; -} - -static const struct rockchip_p3phy_ops rk3588_ops = { - .phy_init = rockchip_p3phy_rk3588_init, -}; - -static int rochchip_p3phy_init(struct phy *phy) -{ - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); - int ret; - - ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); - if (ret) { - pr_err("failed to enable PCIe bulk clks %d\n", ret); - return ret; - } - - reset_control_assert(priv->p30phy); - udelay(1); - - if (priv->ops->phy_init) { - ret = priv->ops->phy_init(priv); - if (ret) - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - } - - return ret; -} - -static int rochchip_p3phy_exit(struct phy *phy) -{ - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); - - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - reset_control_assert(priv->p30phy); - return 0; -} - -static const struct phy_ops rochchip_p3phy_ops = { - .init = rochchip_p3phy_init, - .exit = rochchip_p3phy_exit, - .set_mode = rockchip_p3phy_set_mode, - .owner = THIS_MODULE, -}; - -static int rockchip_p3phy_probe(struct platform_device *pdev) -{ - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct rockchip_p3phy_priv *priv; - struct device_node *np = dev->of_node; - struct resource *res; - int ret; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(priv->mmio)) { - ret = PTR_ERR(priv->mmio); - return ret; - } - - priv->ops = of_device_get_match_data(&pdev->dev); - if (!priv->ops) { - dev_err(&pdev->dev, "no of match data provided\n"); - return -EINVAL; - } - - priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); - if (IS_ERR(priv->phy_grf)) { - dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); - return PTR_ERR(priv->phy_grf); - } - - priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, - "rockchip,pipe-grf"); - if (IS_ERR(priv->pipe_grf)) - dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); - - priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", - priv->lanes, 2, - ARRAY_SIZE(priv->lanes)); - - /* if no data-lanes assume aggregation */ - if (priv->num_lanes == -EINVAL) { - dev_dbg(dev, "no data-lanes property found\n"); - priv->num_lanes = 1; - priv->lanes[0] = 1; - } else if (priv->num_lanes < 0) { - dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); - return priv->num_lanes; - } - - priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); - return PTR_ERR(priv->phy); - } - - priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); - if (IS_ERR(priv->p30phy)) { - return dev_err_probe(dev, PTR_ERR(priv->p30phy), - "failed to get phy reset control\n"); - } - if (!priv->p30phy) - dev_info(dev, "no phy reset control specified\n"); - - priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); - if (priv->num_clks < 1) - return -ENODEV; - - dev_set_drvdata(dev, priv); - phy_set_drvdata(priv->phy, priv); - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - return PTR_ERR_OR_ZERO(phy_provider); -} - -static const struct of_device_id rockchip_p3phy_of_match[] = { - { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, - { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, - { }, -}; -MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); - -static struct platform_driver rockchip_p3phy_driver = { - .probe = rockchip_p3phy_probe, - .driver = { - .name = "rockchip-snps-pcie3-phy", - .of_match_table = rockchip_p3phy_of_match, - }, -}; -module_platform_driver(rockchip_p3phy_driver); -MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/files/include/linux/motorcomm_phy.h b/target/linux/rockchip/files/include/linux/motorcomm_phy.h new file mode 100644 index 000000000..4ef801c81 --- /dev/null +++ b/target/linux/rockchip/files/include/linux/motorcomm_phy.h @@ -0,0 +1,73 @@ +/* + * include/linux/motorcomm_phy.h + * + * Motorcomm PHY IDs + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _MOTORCOMM_PHY_H +#define _MOTORCOMM_PHY_H + +#define MOTORCOMM_PHY_ID_MASK 0x00000fff +#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff + +#define PHY_ID_YT8010 0x00000309 +#define PHY_ID_YT8510 0x00000109 +#define PHY_ID_YT8511 0x0000010a +#define PHY_ID_YT8512 0x00000118 +#define PHY_ID_YT8512B 0x00000128 +#define PHY_ID_YT8521 0x0000011a +#define PHY_ID_YT8531S 0x4f51e91a +#define PHY_ID_YT8531 0x4f51e91b + +#define REG_PHY_SPEC_STATUS 0x11 +#define REG_INT_MASK 0x12 +#define REG_INT_STATUS 0x13 +#define REG_DEBUG_ADDR_OFFSET 0x1e +#define REG_DEBUG_DATA 0x1f + +#define YT8511_EXTREG_SLEEP_CONTROL1 0x27 +#define YT8511_EN_SLEEP_SW_BIT 15 + +#define YT8512_EXTREG_AFE_PLL 0x50 +#define YT8512_EXTREG_EXTEND_COMBO 0x4000 +#define YT8512_EXTREG_LED0 0x40c0 +#define YT8512_EXTREG_LED1 0x40c3 + +#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 + +#define YT_SOFTWARE_RESET 0x8000 + +#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 +#define YT8512_CONTROL1_RMII_EN 0x0001 +#define YT8512_LED0_ACT_BLK_IND 0x1000 +#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 +#define YT8512_LED0_BT_BLK_EN 0x0002 +#define YT8512_LED0_HT_BLK_EN 0x0004 +#define YT8512_LED0_COL_BLK_EN 0x0008 +#define YT8512_LED0_BT_ON_EN 0x0010 +#define YT8512_LED1_BT_ON_EN 0x0010 +#define YT8512_LED1_TXACT_BLK_EN 0x0100 +#define YT8512_LED1_RXACT_BLK_EN 0x0200 +#define YT8512_SPEED_MODE 0xc000 +#define YT8512_DUPLEX 0x2000 + +#define YT8512_SPEED_MODE_BIT 14 +#define YT8512_DUPLEX_BIT 13 +#define YT8512_EN_SLEEP_SW_BIT 15 + +#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 +#define YT8521_EN_SLEEP_SW_BIT 15 + +#define YT8521_SPEED_MODE 0xc000 +#define YT8521_DUPLEX 0x2000 +#define YT8521_SPEED_MODE_BIT 14 +#define YT8521_DUPLEX_BIT 13 +#define YT8521_LINK_STATUS_BIT 10 + +#endif /* _MOTORCOMM_PHY_H */ diff --git a/target/linux/rockchip/files/include/linux/phy/pcie.h b/target/linux/rockchip/files/include/linux/phy/pcie.h deleted file mode 100644 index 93c997f52..000000000 --- a/target/linux/rockchip/files/include/linux/phy/pcie.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ -#ifndef __PHY_PCIE_H -#define __PHY_PCIE_H - -#define PHY_MODE_PCIE_RC 20 -#define PHY_MODE_PCIE_EP 21 -#define PHY_MODE_PCIE_BIFURCATION 22 - -#endif diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 21e94212b..dd8b0bd44 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -2,46 +2,6 @@ # # Copyright (C) 2020 Tobias Maedel -define Device/embedfire_doornet1 - DEVICE_VENDOR := EmbedFire - DEVICE_MODEL := DoorNet1 - SOC := rk3328 - UBOOT_DEVICE_NAME := doornet1-rk3328 - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata - DEVICE_PACKAGES := kmod-usb-net-rtl8152 kmod-rtl8821cu -endef -TARGET_DEVICES += embedfire_doornet1 - -define Device/embedfire_doornet2 - DEVICE_VENDOR := EmbedFire - DEVICE_MODEL := DoorNet2 1GB - SOC := rk3399 - UBOOT_DEVICE_NAME := doornet2-rk3399 - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata - DEVICE_PACKAGES := kmod-r8168 -urngd -endef -TARGET_DEVICES += embedfire_doornet2 - -define Device/fastrhino_r66s - DEVICE_VENDOR := FastRhino - DEVICE_MODEL := R66S - SOC := rk3568 - UBOOT_DEVICE_NAME := fastrhino-r66s-rk3568 - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-r8125 -endef -TARGET_DEVICES += fastrhino_r66s - -define Device/firefly_station-p2 - DEVICE_VENDOR := Firefly - DEVICE_MODEL := Station P2 - SOC := rk3568 - UBOOT_DEVICE_NAME := station-p2-rk3568 - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-brcmfmac kmod-ikconfig kmod-ata-ahci-platform station-p2-firmware wpad-openssl -endef -TARGET_DEVICES += firefly_station-p2 - define Device/friendlyarm_nanopi-neo3 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi NEO3 @@ -91,7 +51,7 @@ define Device/friendlyarm_nanopi-r4se endef TARGET_DEVICES += friendlyarm_nanopi-r4se -define Device/friendlyelec_nanopi-r5s +define Device/friendlyarm_nanopi-r5s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R5S SOC := rk3568 @@ -99,7 +59,7 @@ define Device/friendlyelec_nanopi-r5s IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-r8125 endef -TARGET_DEVICES += friendlyelec_nanopi-r5s +TARGET_DEVICES += friendlyarm_nanopi-r5s define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 @@ -111,16 +71,6 @@ define Device/pine64_rockpro64 endef TARGET_DEVICES += pine64_rockpro64 -define Device/radxa_rock-3a - DEVICE_VENDOR := Radxa - DEVICE_MODEL := ROCK3 Model A - SOC := rk3568 - SUPPORTED_DEVICES := radxa,rock3a - UBOOT_DEVICE_NAME := rock-3a-rk3568 - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata -endef -TARGET_DEVICES += radxa_rock-3a - define Device/radxa_rock-pi-4 DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK Pi 4 diff --git a/target/linux/rockchip/modules.mk b/target/linux/rockchip/modules.mk index 107017dbd..84aca3fbd 100644 --- a/target/linux/rockchip/modules.mk +++ b/target/linux/rockchip/modules.mk @@ -16,8 +16,6 @@ define KernelPackage/drm-rockchip CONFIG_PHY_ROCKCHIP_INNO_HDMI \ CONFIG_DRM_DW_HDMI \ CONFIG_DRM_DW_HDMI_CEC \ - CONFIG_ROCKCHIP_VOP=y \ - CONFIG_ROCKCHIP_VOP2=y CONFIG_ROCKCHIP_ANALOGIX_DP=n \ CONFIG_ROCKCHIP_CDN_DP=n \ CONFIG_ROCKCHIP_DW_HDMI=y \ @@ -34,7 +32,8 @@ define KernelPackage/drm-rockchip $(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \ $(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.ko \ $(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \ - $(LINUX_DIR)/drivers/media/cec/core/cec.ko \ + $(LINUX_DIR)/drivers/media/cec/cec.ko@lt5.10 \ + $(LINUX_DIR)/drivers/media/cec/core/cec.ko@ge5.10 \ $(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \ $(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@ge5.15 \ $(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \ @@ -48,23 +47,20 @@ endef $(eval $(call KernelPackage,drm-rockchip)) -define KernelPackage/gpu-lima - SUBMENU:=$(VIDEO_MENU) - TITLE:=Mali-4xx GPU support - DEPENDS:=@TARGET_rockchip +kmod-drm +define KernelPackage/saradc-rockchip + SUBMENU:=$(IIO_MENU) + TITLE:=Rockchip SARADC support + DEPENDS:=@TARGET_rockchip +kmod-industrialio-triggered-buffer KCONFIG:= \ - CONFIG_DRM_VGEM \ - CONFIG_DRM_GEM_CMA_HELPER=y \ - CONFIG_DRM_LIMA + CONFIG_RESET_CONTROLLER=y \ + CONFIG_ROCKCHIP_SARADC FILES:= \ - $(LINUX_DIR)/drivers/gpu/drm/vgem/vgem.ko \ - $(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko \ - $(LINUX_DIR)/drivers/gpu/drm/lima/lima.ko - AUTOLOAD:=$(call AutoProbe,lima vgem) + $(LINUX_DIR)/drivers/iio/adc/rockchip_saradc.ko + AUTOLOAD:=$(call AutoProbe,rockchip_saradc) endef -define KernelPackage/gpu-lima/description - Open-source reverse-engineered driver for Mali-4xx GPUs +define KernelPackage/saradc-rockchip/description + Support for the SARADC found in SoCs from Rockchip endef -$(eval $(call KernelPackage,gpu-lima)) +$(eval $(call KernelPackage,saradc-rockchip)) diff --git a/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch index a5631b632..cd6640f94 100644 --- a/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch @@ -8,15 +8,20 @@ stores the MAC address. Signed-off-by: Tianling Shen --- - .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 13 +++++++++++++ -1 file changed, 13 insertions(+) + .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -75,6 +75,19 @@ &emmc_phy { +@@ -68,6 +68,24 @@ status = "disabled"; }; ++&gmac { ++ nvmem-cells = <&mac_address>; ++ nvmem-cell-names = "mac-address"; ++}; ++ +&i2c2 { + eeprom@51 { + compatible = "microchip,24c02", "atmel,24c02"; diff --git a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch index 0acfae5de..d25460fe9 100644 --- a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -19,7 +19,7 @@ Signed-off-by: David Bauer dr_mode = "host"; status = "okay"; + -+ usb-eth@2 { ++ usb_eth: usb-eth@2 { + compatible = "realtek,rtl8153"; + reg = <2>; + diff --git a/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch index 563a7f6df..d76563efc 100644 --- a/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch @@ -11,7 +11,7 @@ + #size-cells = <2>; + + pcie-eth@0,0 { -+ compatible = "realtek,r8168"; ++ compatible = "pci10ec,8168"; + reg = <0x000000 0 0 0 0>; + + realtek,led-data = <0x870>; diff --git a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch index acc3e2c14..ef3011585 100644 --- a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -32,4 +32,4 @@ Signed-off-by: Jonas Karlman + host->ios.clock = 0; host->ios.vdd = 0; - \ No newline at end of file + diff --git a/target/linux/rockchip/patches-5.19/0105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.10/108-nanopi-r4s-sd-signalling.patch similarity index 100% rename from target/linux/rockchip/patches-5.19/0105-nanopi-r4s-sd-signalling.patch rename to target/linux/rockchip/patches-5.10/108-nanopi-r4s-sd-signalling.patch diff --git a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch deleted file mode 100644 index efd3cd233..000000000 --- a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch +++ /dev/null @@ -1,434 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -@@ -0,0 +1,419 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 EmbedFire -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet1"; -+ compatible = "embedfire,doornet1", "rockchip,rk3328"; -+ -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ // mmc1 = &sdmmc; -+ // mmc0 = &emmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&reset_button_pin>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ vcc_rtl8153: vcc-rtl8153-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtl8153_en_drv>; -+ regulator-always-on; -+ regulator-name = "vcc_rtl8153"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ lan_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:wan"; -+ }; -+ -+ wifi_enable: wifi_enable { -+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ label = "wifi-enable"; -+ }; -+ }; -+ -+ vcc_io_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_io_sdio"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ startup-delay-us = <2000>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io_33>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-delays-us = <0 1000000 50000>; -+ snps,reset-active-low; -+ tx_delay = <0x18>; -+ rx_delay = <0x24>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vdd_5v>; -+ vcc2-supply = <&vdd_5v>; -+ vcc3-supply = <&vdd_5v>; -+ vcc4-supply = <&vdd_5v>; -+ vcc5-supply = <&vcc_io_33>; -+ vcc6-supply = <&vdd_5v>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io_33: DCDC_REG4 { -+ regulator-name = "vcc_io_33"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+ usb { -+ rtl8153_en_drv: rtl8153-en-drv { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io_33>; -+ vccio1-supply = <&vcc_io_33>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io_sdio>; -+ vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io_33>; -+ vccio6-supply = <&vcc_io_33>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ button { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_pin: wifi_pin{ -+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sd { -+ sdio_vcc_pin: sdio-vcc-pin { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io_33>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+ -+ usb-eth@2 { -+ compatible = "realtek,rtl8153"; -+ reg = <2>; -+ -+ realtek,led-data = <0x87>; -+ }; -+}; --- -2.25.1 diff --git a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 000000000..28c337554 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,79 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021 Tianling Shen ++ */ ++ ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&dmc_opp_table { ++ opp-798000000 { ++ status = "disabled"; ++ }; ++ opp-840000000 { ++ status = "disabled"; ++ }; ++ opp-924000000 { ++ status = "disabled"; ++ }; ++ opp-1056000000 { ++ status = "disabled"; ++ }; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-id4f51.e91b", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus-lts:green:lan"; ++}; ++ ++&sys_led { ++ label = "orangepi-r1-plus-lts:red:sys"; ++}; ++ ++&usb_eth { ++ realtek,led-data = <0x78>; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus-lts:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index f7e84c4ee..078efd4da 100644 --- a/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,8 +1,8 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od +@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb @@ -10,7 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -@@ -0,0 +1,47 @@ +@@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. @@ -55,6 +55,10 @@ + label = "nanopi-r2c:red:sys"; +}; + ++&usb_eth { ++ realtek,led-data = <0x78>; ++}; ++ +&wan_led { + label = "nanopi-r2c:green:wan"; +}; diff --git a/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-5.10/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch similarity index 97% rename from target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch rename to target/linux/rockchip/patches-5.10/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch index 44ed7d9cd..dffaf4395 100644 --- a/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch +++ b/target/linux/rockchip/patches-5.10/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch @@ -37,15 +37,11 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi index 479906f3a..5f6ffb496 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -3,6 +3,11 @@ +@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-station-p2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb diff --git a/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch deleted file mode 100644 index 154f5e655..000000000 --- a/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch +++ /dev/null @@ -1,768 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3399-doornet2.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet2 1GB"; -+ compatible = "embedfire,doornet2", "rockchip,rk3399"; -+ -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ -+ /delete-node/ display-subsystem; -+ -+ gpio-leds { -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ -+ /delete-node/ status; -+ -+ lan_led: led-lan { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ sys_led: led-sys { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "red:sys"; -+ default-state = "on"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+ -+ gpio-keys { -+ pinctrl-0 = <&reset_button_pin>; -+ -+ /delete-node/ power; -+ -+ reset { -+ debounce-interval = <50>; -+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ }; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ -+ pcie@0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ pcie-eth@0,0 { -+ compatible = "realtek,r8168"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x870>; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ /delete-node/ leds-gpio; -+ -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rockchip-key { -+ /delete-node/ power-key; -+ -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -@@ -0,0 +1,637 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc5v0_sys"; -+ vin-supply = <&vdd_5v>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_s3"; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vbus_typec: vbus-typec { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vbus_typec"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_key>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&leds_gpio>; -+ -+ status { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc3v3_s3>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 100000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c7>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "xin32k", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_cam: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_cam"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_touch"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmupll: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_pmupll"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <3000000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcca3v0_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <200000>; -+ i2c-scl-rising-time-ns = <150>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ status = "okay"; -+}; -+ -+&i2c7 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <2>; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-leds { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ power_key: power-key { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_reg_on_h: wifi-reg_on-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -+ diff --git a/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch deleted file mode 100644 index eabd5bb3b..000000000 --- a/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001 -From: baiywt -Date: Mon, 15 Nov 2021 16:51:43 +0800 -Subject: [PATCH] Add support for OrangePi R1 Plus LTS - ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 44 +++++++++++++++++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 23373c752..552d97555 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -5,6 +5,7 @@ - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -new file mode 100644 -index 000000000..c65f7c417 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,70 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; -+ -+/delete-node/ &rtl8211e; -+&gmac2io { -+ phy-handle = <ðphy3>; -+ snps,reset-delays-us = <0 15000 50000>; -+ tx_delay = <0x19>; -+ rx_delay = <0x05>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy3: ethernet-phy@0 { -+ reg = <0x0>; -+ keep-clkout-on; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&dmc_opp_table { -+ opp-1056000000 { -+ status = "disabled"; -+ }; -+ opp-924000000 { -+ status = "disabled"; -+ }; -+ opp-840000000 { -+ status = "disabled"; -+ }; -+ opp-798000000 { -+ status = "disabled"; -+ }; -+}; -+ -+&sys_led { -+ label = "orangepi-r1-plus-lts:red:sys"; -+}; -+ -+&wan_led { -+ label = "orangepi-r1-plus-lts:green:wan"; -+}; -+ -+&lan_led { -+ label = "orangepi-r1-plus-lts:green:lan"; -+}; --- -2.25.1 diff --git a/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch b/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch index e478541c0..9ded06653 100644 --- a/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch +++ b/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch @@ -37,421 +37,3 @@ Signed-off-by: hmz007 obj-$(CONFIG_NATIONAL_PHY) += national.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o ---- /dev/null -+++ b/drivers/net/phy/motorcomm.c -@@ -0,0 +1,345 @@ -+/* -+ * drivers/net/phy/motorcomm.c -+ * -+ * Driver for Motorcomm PHYs -+ * -+ * Author: Leilei Zhao -+ * -+ * Copyright (c) 2019 Motorcomm, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * Support : Motorcomm Phys: -+ * Giga phys: yt8511, yt8521 -+ * 100/10 Phys : yt8512, yt8512b, yt8510 -+ * Automotive 100Mb Phys : yt8010 -+ * Automotive 100/10 hyper range Phys: yt8510 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ -+static int yt8010_config_aneg(struct phy_device *phydev) -+{ -+ phydev->speed = SPEED_100; -+ return 0; -+} -+ -+static int yt8512_clk_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONTROL1_RMII_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, MII_BMCR); -+ if (val < 0) -+ return val; -+ -+ val |= YT_SOFTWARE_RESET; -+ ret = phy_write(phydev, MII_BMCR, val); -+ -+ return ret; -+} -+ -+static int yt8512_led_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int mask; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED0_ACT_BLK_IND; -+ -+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | -+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | -+ YT8512_LED0_BT_ON_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED1_BT_ON_EN; -+ -+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); -+ -+ return ret; -+} -+ -+static int yt8512_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ ret = yt8512_clk_init(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = yt8512_led_init(phydev); -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ return ret; -+} -+ -+static int yt8512_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int speed, speed_mode, duplex; -+ -+ ret = genphy_update_link(phydev); -+ if (ret) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; -+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ case 3: -+ default: -+ speed = SPEED_UNKNOWN; -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ -+ return 0; -+} -+ -+static int yt8521_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); -+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ /* switch to access UTP */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = ytphy_read_ext(phydev, 0xc); -+ if (val < 0) -+ return val; -+ -+ val &= ~(1 << 12); -+ ret = ytphy_write_ext(phydev, 0xc, val); -+ if (ret < 0) -+ return ret; -+ -+ /* output SyncE clock (125mhz) even link is down */ -+ ret = ytphy_write_ext(phydev, 0xa012, 0x38); -+ if (ret < 0) -+ return ret; -+ -+ /* disable rgmii clk 2ns delay */ -+ val = ytphy_read_ext(phydev, 0xa001); -+ if (val < 0) -+ return val; -+ -+ val &= ~(1 << 8); -+ ret = ytphy_write_ext(phydev, 0xa001, val); -+ if (ret < 0) -+ return ret; -+ -+ /* setup delay */ -+ val = (1 << 10) | (0xf << 4) | 5; -+ ret = ytphy_write_ext(phydev, 0xa003, val); -+ if (ret < 0) -+ return ret; -+ -+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */ -+ ytphy_write_ext(phydev, 0xa00b, 0xe004); -+ ytphy_write_ext(phydev, 0xa00c, 0); -+ ytphy_write_ext(phydev, 0xa00d, 0x2600); -+ ytphy_write_ext(phydev, 0xa00e, 0x0070); -+ ytphy_write_ext(phydev, 0xa00f, 0x000a); -+ -+ return 0; -+} -+ -+static int yt8521_config_intr(struct phy_device *phydev) -+{ -+ int val; -+ -+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) -+ val = BIT(14) | BIT(13) | BIT(11) | BIT(10); -+ else -+ val = 0; -+ -+ return phy_write(phydev, REG_INT_MASK, val); -+} -+ -+static int yt8521_ack_interrupt(struct phy_device *phydev) -+{ -+ int val; -+ -+ val = phy_read(phydev, REG_INT_STATUS); -+ phydev_dbg(phydev, "intr status 0x04%x\n", val); -+ -+ return (val < 0) ? val : 0; -+} -+ -+static struct phy_driver ytphy_drvs[] = { -+ { -+ .phy_id = PHY_ID_YT8010, -+ .name = "YT8010 Automotive Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .features = PHY_BASIC_FEATURES, -+ .config_aneg = yt8010_config_aneg, -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8510, -+ .name = "YT8510 100/10Mb Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .features = PHY_BASIC_FEATURES, -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8511, -+ .name = "YT8511 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .features = PHY_GBIT_FEATURES, -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512, -+ .name = "YT8512 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .features = PHY_BASIC_FEATURES, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512B, -+ .name = "YT8512B Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .features = PHY_BASIC_FEATURES, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8521, -+ .name = "YT8521 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ /* PHY_GBIT_FEATURES */ -+ .config_init = yt8521_config_init, -+ .ack_interrupt = yt8521_ack_interrupt, -+ .config_intr = yt8521_config_intr, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, -+}; -+ -+module_phy_driver(ytphy_drvs); -+ -+MODULE_DESCRIPTION("Motorcomm PHY driver"); -+MODULE_AUTHOR("Leilei Zhao"); -+MODULE_LICENSE("GPL"); -+ -+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { -+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); ---- /dev/null -+++ b/include/linux/motorcomm_phy.h -@@ -0,0 +1,67 @@ -+/* -+ * include/linux/motorcomm_phy.h -+ * -+ * Motorcomm PHY IDs -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef _MOTORCOMM_PHY_H -+#define _MOTORCOMM_PHY_H -+ -+#define MOTORCOMM_PHY_ID_MASK 0x00000fff -+ -+#define PHY_ID_YT8010 0x00000309 -+#define PHY_ID_YT8510 0x00000109 -+#define PHY_ID_YT8511 0x0000010a -+#define PHY_ID_YT8512 0x00000118 -+#define PHY_ID_YT8512B 0x00000128 -+#define PHY_ID_YT8521 0x0000011a -+ -+#define REG_PHY_SPEC_STATUS 0x11 -+#define REG_INT_MASK 0x12 -+#define REG_INT_STATUS 0x13 -+#define REG_DEBUG_ADDR_OFFSET 0x1e -+#define REG_DEBUG_DATA 0x1f -+ -+#define YT8512_EXTREG_AFE_PLL 0x50 -+#define YT8512_EXTREG_EXTEND_COMBO 0x4000 -+#define YT8512_EXTREG_LED0 0x40c0 -+#define YT8512_EXTREG_LED1 0x40c3 -+ -+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 -+ -+#define YT_SOFTWARE_RESET 0x8000 -+ -+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 -+#define YT8512_CONTROL1_RMII_EN 0x0001 -+#define YT8512_LED0_ACT_BLK_IND 0x1000 -+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 -+#define YT8512_LED0_BT_BLK_EN 0x0002 -+#define YT8512_LED0_HT_BLK_EN 0x0004 -+#define YT8512_LED0_COL_BLK_EN 0x0008 -+#define YT8512_LED0_BT_ON_EN 0x0010 -+#define YT8512_LED1_BT_ON_EN 0x0010 -+#define YT8512_LED1_TXACT_BLK_EN 0x0100 -+#define YT8512_LED1_RXACT_BLK_EN 0x0200 -+#define YT8512_SPEED_MODE 0xc000 -+#define YT8512_DUPLEX 0x2000 -+ -+#define YT8512_SPEED_MODE_BIT 14 -+#define YT8512_DUPLEX_BIT 13 -+#define YT8512_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 -+#define YT8521_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_SPEED_MODE 0xc000 -+#define YT8521_DUPLEX 0x2000 -+#define YT8521_SPEED_MODE_BIT 14 -+#define YT8521_DUPLEX_BIT 13 -+#define YT8521_LINK_STATUS_BIT 10 -+ -+#endif /* _MOTORCOMM_PHY_H */ diff --git a/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch b/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch deleted file mode 100644 index 9b9c46dfb..000000000 --- a/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch +++ /dev/null @@ -1,475 +0,0 @@ -From abf36eb72942657cef05ebcb2897eaea9064ad06 Mon Sep 17 00:00:00 2001 -From: From: fengying0347 -Date: Thu, 13 Jan 2022 12:59:36 +0800 -Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs - ---- - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 82 ++++++++ - drivers/net/phy/motorcomm.c | 181 +++++++++++++++++- - drivers/net/phy/phy_device.c | 83 ++++++++ - include/linux/motorcomm_phy.h | 5 + - 4 files changed, 350 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 8dc4def..bcd46ca 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -121,6 +121,10 @@ static void stmmac_exit_fs(struct net_device *dev); - - #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) - -+#define RTL_8211E_PHY_ID 0x001cc915 -+#define RTL_8211F_PHY_ID 0x001cc916 -+#define YT_8531C_PHY_ID 0x4f51e91b -+ - int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) - { - int ret = 0; -@@ -4950,6 +4954,74 @@ int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) - return ret; - } - -+static int phy_rtl8211e_led_fixup(struct phy_device *phydev) -+{ -+ int val; -+ -+ printk("%s in\n", __func__); -+ -+ /*switch to extension page44*/ -+ phy_write(phydev, 31, 0x07); -+ phy_write(phydev, 30, 0x2c); -+ -+ /*set led1(yellow) act*/ -+ val = phy_read(phydev, 26); -+ val &= (~(1<<4));// bit4=0 -+ val |= (1<<5);// bit5=1 -+ val &= (~(1<<6));// bit6=0 -+ phy_write(phydev, 26, val); -+ -+ /*set led0(green) link*/ -+ val = phy_read(phydev, 28); -+ val |= (7<<0);// bit0,1,2=1 -+ val &= (~(7<<4));// bit4,5,6=0 -+ val &= (~(7<<8));// bit8,9,10=0 -+ phy_write(phydev, 28, val); -+ -+ /*switch back to page0*/ -+ phy_write(phydev,31,0x00); -+ -+ return 0; -+} -+ -+static int phy_rtl8211f_led_fixup(struct phy_device *phydev) -+{ -+ int val; -+ -+ printk("%s in\n", __func__); -+ -+ /*switch to extension page 0xd04*/ -+ phy_write(phydev, 31, 0xd04); -+ -+ -+ /*set led1(yellow) act*/ -+ /*set led2(green) link*/ -+ val = 0xae00; -+ phy_write(phydev, 16, val); -+ -+ val = 0x0; -+ phy_write(phydev, 17, val); -+ /*switch back to page0*/ -+ phy_write(phydev,31,0x00); -+ -+ return 0; -+} -+ -+static int phy_yt8531_led_fixup(struct phy_device *phydev) -+{ -+ printk("%s in\n", __func__); -+ phy_write(phydev, 0x1e, 0xa00d); -+ phy_write(phydev, 0x1f, 0x670); -+ -+ phy_write(phydev, 0x1e, 0xa00e); -+ phy_write(phydev, 0x1f, 0x2070); -+ -+ phy_write(phydev, 0x1e, 0xa00f); -+ phy_write(phydev, 0x1f, 0x7e); -+ -+ return 0; -+} -+ - /** - * stmmac_dvr_probe - * @device: device pointer -@@ -5173,6 +5245,16 @@ int stmmac_dvr_probe(struct device *device, - netdev_err(ndev, "failed to setup phy (%d)\n", ret); - goto error_phy_setup; - } -+ /* register the PHY board fixup */ -+ ret = phy_register_fixup_for_uid(RTL_8211E_PHY_ID, 0xffffffff, phy_rtl8211e_led_fixup); -+ if (ret) -+ pr_warn("Cannot register PHY board fixup.\n"); -+ ret = phy_register_fixup_for_uid(RTL_8211F_PHY_ID, 0xffffffff, phy_rtl8211f_led_fixup); -+ if (ret) -+ pr_warn("Cannot register PHY board fixup.\n"); -+ ret = phy_register_fixup_for_uid(YT_8531C_PHY_ID, 0xffffffff, phy_yt8531_led_fixup); -+ if (ret) -+ pr_warn("Cannot register PHY board fixup.\n"); - - ret = register_netdev(ndev); - if (ret) { -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -index 17a4f6c..e37dfb9 100644 ---- a/drivers/net/phy/motorcomm.c -+++ b/drivers/net/phy/motorcomm.c -@@ -26,6 +26,13 @@ - #include - #include - -+static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32. -+ -+int genphy_config_init(struct phy_device *phydev) -+{ -+ return genphy_read_abilities(phydev); -+} -+ - static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) - { - int ret; -@@ -263,6 +270,38 @@ static int yt8521_config_intr(struct phy_device *phydev) - return phy_write(phydev, REG_INT_MASK, val); - } - -+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp) -+{ -+ int speed_mode, duplex; -+ -+ int speed = SPEED_UNKNOWN; -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT; -+ speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ if (is_utp) -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ speed = SPEED_1000; -+ break; -+ case 3: -+ break; -+ default: -+ speed = SPEED_UNKNOWN; -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ -+ return 0; -+} -+ - static int yt8521_ack_interrupt(struct phy_device *phydev) - { - int val; -@@ -273,6 +312,121 @@ static int yt8521_ack_interrupt(struct phy_device *phydev) - return (val < 0) ? val : 0; - } - -+static int yt8521_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ volatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ -+ /* reading UTP */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ link_mode_8521 = 1; -+ yt8521_adjust_status(phydev, val, 1); -+ } -+ else { -+ link_utp = 0; -+ } -+ -+ /* reading Fiber */ -+ ret = ytphy_write_ext(phydev, 0xa000, 2); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ //note: below debug information is used to check multiple PHy ports. -+ //printk (KERN_INFO "yt8521_read_status, fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev); -+ -+ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case -+ * this is important for Linux kernel for that, missing linkdown event will cause problem. -+ */ -+ yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR); -+ yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR); -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if ((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val)) -+ { -+ link = 0; -+ printk(KERN_INFO "yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8521_fiber_latch_val, yt8521_fiber_curr_val); -+ } -+ -+ if (link) { -+ link_fiber = 1; -+ yt8521_adjust_status(phydev, val, 0); -+ link_mode_8521 = 32; //fiber mode -+ -+ -+ } -+ else { -+ link_fiber = 0; -+ } -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } -+ else { -+ phydev->link = 0; -+ link_mode_8521 = 0; -+ } -+ -+ if (link_utp) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ } -+ -+ return 0; -+} -+ -+/* -+ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and -+ * this function handles this case and return 1 per linux kernel's polling. -+ */ -+int yt8521_aneg_done(struct phy_device *phydev) -+{ -+ -+ if ((32 == link_mode_8521) && (SPEED_100 == phydev->speed)) -+ { -+ return 1/*link_mode_8521*/; -+ } -+ -+ return genphy_aneg_done(phydev); -+} -+ -+int yt8521_soft_reset(struct phy_device *phydev) -+{ -+ int ret, val; -+ -+ val = ytphy_read_ext(phydev, 0xa001); -+ ytphy_write_ext(phydev, 0xa001, (val & ~0x8000)); -+ -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+int yt8521_suspend(struct phy_device *phydev) -+{ -+ return 0; -+} -+ -+int yt8521_resume(struct phy_device *phydev) -+{ -+ return 0; -+} -+ - static struct phy_driver ytphy_drvs[] = { - { - .phy_id = PHY_ID_YT8010, -@@ -323,7 +477,30 @@ static struct phy_driver ytphy_drvs[] = { - .config_intr = yt8521_config_intr, - .suspend = genphy_suspend, - .resume = genphy_resume, -- }, -+ }, { -+ /* same as 8521 */ -+ .phy_id = PHY_ID_YT8531S, -+ .name = "YT8531S Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .flags = PHY_POLL, -+ .soft_reset = yt8521_soft_reset, -+ .config_aneg = genphy_config_aneg, -+ .aneg_done = yt8521_aneg_done, -+ .config_init = yt8521_config_init, -+ .read_status = yt8521_read_status, -+ .suspend = yt8521_suspend, -+ .resume = yt8521_resume, -+ }, { -+ /* same as 8511 */ -+ .phy_id = PHY_ID_YT8531, -+ .name = "YT8531 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+ .config_aneg = genphy_config_aneg, -+ .config_init = genphy_config_init, -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ } - }; - - module_phy_driver(ytphy_drvs); -@@ -339,6 +516,8 @@ static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { - { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, - { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, - { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK }, -+ { PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK }, - { } - }; - -diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c -index 950277e..3a35040 100644 ---- a/drivers/net/phy/phy_device.c -+++ b/drivers/net/phy/phy_device.c -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - - MODULE_DESCRIPTION("PHY library"); - MODULE_AUTHOR("Andy Fleming"); -@@ -409,6 +410,33 @@ int phy_unregister_fixup_for_id(const char *bus_id) - } - EXPORT_SYMBOL(phy_unregister_fixup_for_id); - -+static int phy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = bus->read(bus, phy_id, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int phy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ - /* Returns 1 if fixup matches phydev in bus_id and phy_uid. - * Fixups can be set to match any in one or more fields. - */ -@@ -816,6 +844,50 @@ static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id) - return 0; - } - -+int phy_set_out_125m(struct mii_bus* bus, int phy_id) -+{ -+ int ret; -+ int val; -+ -+ ret = phy_mii_wr_ext(bus, phy_id, 0xa012, 0xd0); -+ mdelay(100); -+ val = phy_mii_rd_ext(bus, phy_id, 0xa012); -+ -+ if (val != 0xd0) -+ { -+ printk(KERN_INFO "phy_set_out_125m error\n"); -+ return -1; -+ } -+ -+ /* disable auto sleep */ -+ val = phy_mii_rd_ext(bus, phy_id, 0x27); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(15)); -+ -+ ret = phy_mii_wr_ext(bus, phy_id, 0x27, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = phy_mii_rd_ext(bus, phy_id, 0xc); -+ if (val < 0) -+ return val; -+ -+ /* ext reg 0xc.b[2:1] -+ 00-----25M from pll; -+ 01---- 25M from xtl;(default) -+ 10-----62.5M from pll; -+ 11----125M from pll(here set to this value) -+ */ -+ val |= (3 << 1); -+ ret = phy_mii_wr_ext(bus, phy_id, 0xc, val); -+ printk(KERN_INFO "phy_set_out_125m, phy clk out, val=%#08x\n", val); -+ -+ return ret; -+} -+ - /** - * get_phy_device - reads the specified PHY device and returns its @phy_device - * struct -@@ -853,6 +925,15 @@ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45) - if (r) - return ERR_PTR(r); - -+ if(phy_id == PHY_ID_YT8531) -+ { -+ r = phy_set_out_125m(bus, addr); -+ if (r<0) -+ { -+ printk (KERN_INFO "failed to set 125m clk out, ret=%d\n",r); -+ } -+ } -+ - return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids); - } - EXPORT_SYMBOL(get_phy_device); -diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h -index facce6d..23cccca 100644 ---- a/include/linux/motorcomm_phy.h -+++ b/include/linux/motorcomm_phy.h -@@ -14,6 +14,8 @@ - #define _MOTORCOMM_PHY_H - - #define MOTORCOMM_PHY_ID_MASK 0x00000fff -+#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff -+#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff - - #define PHY_ID_YT8010 0x00000309 - #define PHY_ID_YT8510 0x00000109 -@@ -21,6 +23,9 @@ - #define PHY_ID_YT8512 0x00000118 - #define PHY_ID_YT8512B 0x00000128 - #define PHY_ID_YT8521 0x0000011a -+#define PHY_ID_YT8531S 0x4f51e91a -+#define PHY_ID_YT8531 0x4f51e91b -+#define PHY_ID_YT8618 0x0000e889 - - #define REG_PHY_SPEC_STATUS 0x11 - #define REG_INT_MASK 0x12 diff --git a/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch index d93b9a77b..4933f0b58 100644 --- a/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch +++ b/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch @@ -20,7 +20,7 @@ Signed-off-by: hmz007 #include #include -+#include "rk3328-dram-nanopi2-timing.dtsi" ++#include "rk3328-dram-default-timing.dtsi" #include "rk3328.dtsi" / { diff --git a/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch b/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch deleted file mode 100644 index f369f2bcd..000000000 --- a/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch +++ /dev/null @@ -1,52 +0,0 @@ -From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001 -From: hmz007 -Date: Tue, 19 Nov 2019 17:24:30 +0800 -Subject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY - -Signed-off-by: hmz007 ---- - drivers/phy/rockchip/Kconfig | 8 + - drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++ - 3 files changed, 1184 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY - Enable this to support the Rockchip MIPI/LVDS/TTL PHY with - Innosilicon IP block. - -+config PHY_ROCKCHIP_INNO_USB3 -+ tristate "Rockchip INNO USB 3.0 PHY Driver" -+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -+ depends on USB_SUPPORT -+ select GENERIC_PHY -+ select USB_PHY -+ help -+ Support for Rockchip USB 3.0 PHY with Innosilicon IP block. -+ - config PHY_ROCKCHIP_PCIE - tristate "Rockchip PCIe PHY Driver" - depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy- - obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o -+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o ---- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt -+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt -@@ -45,6 +45,8 @@ Required Properties: - - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 - - compatible: USBGRF should be one of the following: - - "rockchip,rv1108-usbgrf", "syscon": for rv1108 -+- compatible: USB3PHYGRF should be one of the following: -+ - "rockchip,u3phy-grf", "syscon" - - reg: physical base address of the controller and length of memory mapped - region. - diff --git a/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch deleted file mode 100644 index 54cd42051..000000000 --- a/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 2184ab853067b484ba5677e35f1a6955a5c023a1 Mon Sep 17 00:00:00 2001 -From: wowowow -Date: Wed, 20 Oct 2021 13:46:46 +0800 -Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node - ---- - .../boot/dts/rockchip/rk3328-doornet1.dts | 73 +++++++++++++++++++ - 1 file changed, 73 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -index 8333351..d984163 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -@@ -7,6 +7,7 @@ - - #include - #include -+#include "rk3328-dram-nanopi2-timing.dtsi" - #include "rk3328.dtsi" - - / { -@@ -56,6 +57,72 @@ - enable-active-high; - }; - -+ dmc: dmc { -+ compatible = "rockchip,rk3328-dmc"; -+ devfreq-events = <&dfi>; -+ center-supply = <&vdd_log>; -+ clocks = <&cru SCLK_DDRCLK>; -+ clock-names = "dmc_clk"; -+ operating-points-v2 = <&dmc_opp_table>; -+ ddr_timing = <&ddr_timing>; -+ upthreshold = <40>; -+ downdifferential = <20>; -+ auto-min-freq = <786000>; -+ auto-freq-en = <1>; -+ #cooling-cells = <2>; -+ status = "okay"; -+ -+ ddr_power_model: ddr_power_model { -+ compatible = "ddr_power_model"; -+ dynamic-power-coefficient = <120>; -+ static-power-coefficient = <200>; -+ ts = <32000 4700 (-80) 2>; -+ thermal-zone = "soc-thermal"; -+ }; -+ }; -+ -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ rockchip,leakage-voltage-sel = < -+ 1 10 0 -+ 11 254 1 -+ >; -+ nvmem-cells = <&logic_leakage>; -+ nvmem-cell-names = "ddr_leakage"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000>; -+ opp-microvolt-L0 = <1100000>; -+ opp-microvolt-L1 = <1075000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000>; -+ opp-microvolt-L0 = <1175000>; -+ opp-microvolt-L1 = <1150000>; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -@@ -138,6 +205,10 @@ - cpu-supply = <&vdd_arm>; - }; - -+&dfi { -+ status = "okay"; -+}; -+ - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -@@ -201,6 +272,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -215,6 +287,7 @@ - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; --- -2.25.1 - diff --git a/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch deleted file mode 100644 index ba31f0751..000000000 --- a/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch +++ /dev/null @@ -1,193 +0,0 @@ -From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 19 Dec 2020 12:42:27 +0000 -Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices - -It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, -and for better performance. - -Signed-off-by: Tianling Shen -Co-authored-by: gzelvis ---- - .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++ - .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- - 2 files changed, 157 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi -@@ -0,0 +1,152 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * Copyright (c) 2020 Tianling Shen -+ * Copyright (c) 2020 gzelvis -+ */ -+ -+/ { -+ cluster0_opp: opp-table0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <800000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <925000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1000000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1125000>; -+ }; -+ opp06 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1225000>; -+ }; -+ opp07 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1275000>; -+ }; -+ }; -+ -+ cluster1_opp: opp-table1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <800000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <825000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <875000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <950000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1025000>; -+ }; -+ opp06 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1100000>; -+ }; -+ opp07 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1200000>; -+ }; -+ opp08 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <1250000>; -+ }; -+ opp09 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <1325000>; -+ }; -+ }; -+ -+ gpu_opp_table: opp-table2 { -+ compatible = "operating-points-v2"; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <297000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <825000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <875000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <925000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1100000>; -+ }; -+ }; -+}; -+ -+&cpu_l0 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l1 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l2 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l3 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_b0 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&cpu_b1 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&gpu { -+ operating-points-v2 = <&gpu_opp_table>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -@@ -14,7 +14,7 @@ - /dts-v1/; - #include - #include "rk3399.dtsi" --#include "rk3399-opp.dtsi" -+#include "rk3399-nanopi4-opp.dtsi" - - / { - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -@@ -3,7 +3,7 @@ - /dts-v1/; - #include - #include "rk3399.dtsi" --#include "rk3399-opp.dtsi" -+#include "rk3399-nanopi4-opp.dtsi" - - / { - chosen { diff --git a/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch new file mode 100644 index 000000000..12cb932d1 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch @@ -0,0 +1,46 @@ +From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon, 18 Oct 2021 12:47:30 +0800 +Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz + +It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, +and for better performance. + +Co-development-by: gzelvis +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi +@@ -33,6 +33,14 @@ + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000>; + }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1225000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1275000>; ++ }; + }; + + cluster1_opp: opp-table1 { +@@ -72,6 +80,14 @@ + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp09 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1325000>; ++ }; + }; + + gpu_opp_table: opp-table2 { diff --git a/target/linux/rockchip/patches-5.15/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.15/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch index 74e3f17f3..cd6640f94 100644 --- a/target/linux/rockchip/patches-5.15/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.15/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch @@ -8,15 +8,20 @@ stores the MAC address. Signed-off-by: Tianling Shen --- - .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 13 +++++++++++++ -1 file changed, 13 insertions(+) + .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,19 @@ +@@ -68,6 +68,24 @@ status = "disabled"; }; ++&gmac { ++ nvmem-cells = <&mac_address>; ++ nvmem-cell-names = "mac-address"; ++}; ++ +&i2c2 { + eeprom@51 { + compatible = "microchip,24c02", "atmel,24c02"; diff --git a/target/linux/rockchip/patches-5.15/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch b/target/linux/rockchip/patches-5.15/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch deleted file mode 100644 index 58d4b15cf..000000000 --- a/target/linux/rockchip/patches-5.15/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch +++ /dev/null @@ -1,155 +0,0 @@ -From d269aa2ab975807764dc2509e4156bb9b6bd0d34 Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:24 +0800 -Subject: [PATCH] ASoC: rockchip: Add support for rv1126 pdm - -This patch adds support for rv1126 pdm controller which -redesign cic filiter for better performance. - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-1-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 76 ++++++++++++++++++++++++++++--- - sound/soc/rockchip/rockchip_pdm.h | 3 ++ - 2 files changed, 73 insertions(+), 6 deletions(-) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -24,6 +24,7 @@ - enum rk_pdm_version { - RK_PDM_RK3229, - RK_PDM_RK3308, -+ RK_PDM_RV1126, - }; - - struct rk_pdm_dev { -@@ -121,6 +122,55 @@ static unsigned int get_pdm_ds_ratio(uns - return ratio; - } - -+static unsigned int get_pdm_cic_ratio(unsigned int clk) -+{ -+ switch (clk) { -+ case 4096000: -+ case 5644800: -+ case 6144000: -+ return 0; -+ case 2048000: -+ case 2822400: -+ case 3072000: -+ return 1; -+ case 1024000: -+ case 1411200: -+ case 1536000: -+ return 2; -+ default: -+ return 1; -+ } -+} -+ -+static unsigned int samplerate_to_bit(unsigned int samplerate) -+{ -+ switch (samplerate) { -+ case 8000: -+ case 11025: -+ case 12000: -+ return 0; -+ case 16000: -+ case 22050: -+ case 24000: -+ return 1; -+ case 32000: -+ return 2; -+ case 44100: -+ case 48000: -+ return 3; -+ case 64000: -+ case 88200: -+ case 96000: -+ return 4; -+ case 128000: -+ case 176400: -+ case 192000: -+ return 5; -+ default: -+ return 1; -+ } -+} -+ - static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai) - { - return snd_soc_dai_get_drvdata(dai); -@@ -166,7 +216,8 @@ static int rockchip_pdm_hw_params(struct - if (ret) - return -EINVAL; - -- if (pdm->version == RK_PDM_RK3308) { -+ if (pdm->version == RK_PDM_RK3308 || -+ pdm->version == RK_PDM_RV1126) { - rational_best_approximation(clk_out, clk_src, - GENMASK(16 - 1, 0), - GENMASK(16 - 1, 0), -@@ -194,8 +245,18 @@ static int rockchip_pdm_hw_params(struct - PDM_CLK_FD_RATIO_MSK, - val); - } -- val = get_pdm_ds_ratio(samplerate); -- regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val); -+ -+ if (pdm->version == RK_PDM_RV1126) { -+ val = get_pdm_cic_ratio(clk_out); -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val); -+ val = samplerate_to_bit(samplerate); -+ regmap_update_bits(pdm->regmap, PDM_CTRL0, -+ PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val)); -+ } else { -+ val = get_pdm_ds_ratio(samplerate); -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val); -+ } -+ - regmap_update_bits(pdm->regmap, PDM_HPF_CTRL, - PDM_HPF_CF_MSK, PDM_HPF_60HZ); - regmap_update_bits(pdm->regmap, PDM_HPF_CTRL, -@@ -441,9 +502,10 @@ static bool rockchip_pdm_precious_reg(st - } - - static const struct reg_default rockchip_pdm_reg_defaults[] = { -- {0x04, 0x78000017}, -- {0x08, 0x0bb8ea60}, -- {0x18, 0x0000001f}, -+ { PDM_CTRL0, 0x78000017 }, -+ { PDM_CTRL1, 0x0bb8ea60 }, -+ { PDM_CLK_CTRL, 0x0000e401 }, -+ { PDM_DMA_CTRL, 0x0000001f }, - }; - - static const struct regmap_config rockchip_pdm_regmap_config = { -@@ -469,6 +531,8 @@ static const struct of_device_id rockchi - .data = (void *)RK_PDM_RK3308 }, - { .compatible = "rockchip,rk3308-pdm", - .data = (void *)RK_PDM_RK3308 }, -+ { .compatible = "rockchip,rv1126-pdm", -+ .data = (void *)RK_PDM_RV1126 }, - {}, - }; - MODULE_DEVICE_TABLE(of, rockchip_pdm_match); ---- a/sound/soc/rockchip/rockchip_pdm.h -+++ b/sound/soc/rockchip/rockchip_pdm.h -@@ -41,6 +41,8 @@ - #define PDM_PATH1_EN BIT(28) - #define PDM_PATH0_EN BIT(27) - #define PDM_HWT_EN BIT(26) -+#define PDM_SAMPLERATE_MSK GENMASK(7, 5) -+#define PDM_SAMPLERATE(x) ((x) << 5) - #define PDM_VDW_MSK (0x1f << 0) - #define PDM_VDW(X) ((X - 1) << 0) - -@@ -66,6 +68,7 @@ - #define PDM_CLK_1280FS (0x2 << 0) - #define PDM_CLK_2560FS (0x3 << 0) - #define PDM_CLK_5120FS (0x4 << 0) -+#define PDM_CIC_RATIO_MSK (0x3 << 0) - - /* PDM HPF CTRL */ - #define PDM_HPF_LE BIT(3) diff --git a/target/linux/rockchip/patches-5.15/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch b/target/linux/rockchip/patches-5.15/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch deleted file mode 100644 index 7eef2b8a7..000000000 --- a/target/linux/rockchip/patches-5.15/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d00d1cd4ab42f92d4d871deb9cdea1d7c262a213 Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:26 +0800 -Subject: [PATCH] ASoC: rockchip: pdm: Add support for rk3568 pdm - -This patch adds compatible for rk3568 which is the same -with rv1126. - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-3-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -531,6 +531,8 @@ static const struct of_device_id rockchi - .data = (void *)RK_PDM_RK3308 }, - { .compatible = "rockchip,rk3308-pdm", - .data = (void *)RK_PDM_RK3308 }, -+ { .compatible = "rockchip,rk3568-pdm", -+ .data = (void *)RK_PDM_RV1126 }, - { .compatible = "rockchip,rv1126-pdm", - .data = (void *)RK_PDM_RV1126 }, - {}, diff --git a/target/linux/rockchip/patches-5.15/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch b/target/linux/rockchip/patches-5.15/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch deleted file mode 100644 index b280723b6..000000000 --- a/target/linux/rockchip/patches-5.15/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 13e6e042a6f9c2be676f421935e026308de3303c Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:28 +0800 -Subject: [PATCH] ASoC: rockchip: pdm: Add support for path map - -This patch adds property 'rockchip,path-map' for path mapping. - -e.g. - -"rockchip,path-map = <3 2 1 0>" means the mapping as follows: - - path0 <-- sdi3 - path1 <-- sdi2 - path2 <-- sdi1 - path3 <-- sdi0 - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-5-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 34 +++++++++++++++++++++++++++++++ - sound/soc/rockchip/rockchip_pdm.h | 3 +++ - 2 files changed, 37 insertions(+) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -20,6 +20,7 @@ - - #define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */ - #define PDM_SIGNOFF_CLK_RATE (100000000) -+#define PDM_PATH_MAX (4) - - enum rk_pdm_version { - RK_PDM_RK3229, -@@ -539,8 +540,36 @@ static const struct of_device_id rockchi - }; - MODULE_DEVICE_TABLE(of, rockchip_pdm_match); - -+static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node) -+{ -+ unsigned int path[PDM_PATH_MAX]; -+ int cnt = 0, ret = 0, i = 0, val = 0, msk = 0; -+ -+ cnt = of_count_phandle_with_args(node, "rockchip,path-map", -+ NULL); -+ if (cnt != PDM_PATH_MAX) -+ return cnt; -+ -+ ret = of_property_read_u32_array(node, "rockchip,path-map", -+ path, cnt); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < cnt; i++) { -+ if (path[i] >= PDM_PATH_MAX) -+ return -EINVAL; -+ msk |= PDM_PATH_MASK(i); -+ val |= PDM_PATH(i, path[i]); -+ } -+ -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val); -+ -+ return 0; -+} -+ - static int rockchip_pdm_probe(struct platform_device *pdev) - { -+ struct device_node *node = pdev->dev.of_node; - const struct of_device_id *match; - struct rk_pdm_dev *pdm; - struct resource *res; -@@ -606,6 +635,11 @@ static int rockchip_pdm_probe(struct pla - } - - rockchip_pdm_rxctrl(pdm, 0); -+ -+ ret = rockchip_pdm_path_parse(pdm, node); -+ if (ret != 0 && ret != -ENOENT) -+ goto err_suspend; -+ - ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); - if (ret) { - dev_err(&pdev->dev, "could not register pcm: %d\n", ret); ---- a/sound/soc/rockchip/rockchip_pdm.h -+++ b/sound/soc/rockchip/rockchip_pdm.h -@@ -53,6 +53,9 @@ - #define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0) - - /* PDM CLK CTRL */ -+#define PDM_PATH_SHIFT(x) (8 + (x) * 2) -+#define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x)) -+#define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x)) - #define PDM_CLK_FD_RATIO_MSK BIT(6) - #define PDM_CLK_FD_RATIO_40 (0X0 << 6) - #define PDM_CLK_FD_RATIO_35 BIT(6) diff --git a/target/linux/rockchip/patches-5.15/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch b/target/linux/rockchip/patches-5.15/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch deleted file mode 100644 index fdf559c5a..000000000 --- a/target/linux/rockchip/patches-5.15/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 28 Jul 2021 14:00:31 -0400 -Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes - -Add the thermal and tsadc nodes to the rk3568 device tree. -There are two sensors, one for the cpu, one for the gpu. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++ - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++ - 2 files changed, 79 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi -@@ -3108,4 +3108,13 @@ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; -+ -+ tsadc { -+ /omit-if-no-ref/ -+ tsadc_pin: tsadc-pin { -+ rockchip,pins = -+ /* tsadc_pin */ -+ <0 RK_PA1 0 &pcfg_pull_none>; -+ }; -+ }; - }; diff --git a/target/linux/rockchip/patches-5.15/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch b/target/linux/rockchip/patches-5.15/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch deleted file mode 100644 index c63c7f020..000000000 --- a/target/linux/rockchip/patches-5.15/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Thu, 30 Sep 2021 13:05:16 +0200 -Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc - node - -The tsadc node in rk356x.dtsi has more resets then currently supported -by the rockchip_thermal.c driver, so use -devm_reset_control_array_get() to reset them all. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/rockchip_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/rockchip_thermal.c -+++ b/drivers/thermal/rockchip_thermal.c -@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct - if (IS_ERR(thermal->regs)) - return PTR_ERR(thermal->regs); - -- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); -+ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); - if (IS_ERR(thermal->reset)) { - error = PTR_ERR(thermal->reset); - dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); diff --git a/target/linux/rockchip/patches-5.15/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch b/target/linux/rockchip/patches-5.15/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch deleted file mode 100644 index 74f99511d..000000000 --- a/target/linux/rockchip/patches-5.15/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 29 Aug 2021 04:51:53 +0200 -Subject: [PATCH] mfd: rk808: Add support for power off on RK817 - -RK817 has a power-off bit in SYS_CFG3. Add support for powering -off the PMIC. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Lee Jones ---- - drivers/mfd/rk808.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void) - reg = RK808_DEVCTRL_REG, - bit = DEV_OFF_RST; - break; -+ case RK817_ID: -+ reg = RK817_SYS_CFG(3); -+ bit = DEV_OFF; -+ break; - case RK818_ID: - reg = RK818_DEVCTRL_REG; - bit = DEV_OFF; diff --git a/target/linux/rockchip/patches-5.15/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch b/target/linux/rockchip/patches-5.15/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch deleted file mode 100644 index 8ee043d5d..000000000 --- a/target/linux/rockchip/patches-5.15/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:47 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2 - -New Rockchip devices have the usb phy nodes as standalone devices. -These nodes have register nodes with #address_cells = 2, but only use 32 -bit addresses. - -Adjust the driver to check if the returned address is "0", and adjust -the index in that case. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1098,12 +1098,21 @@ static int rockchip_usb2phy_probe(struct - rphy->usbgrf = NULL; - } - -- if (of_property_read_u32(np, "reg", ®)) { -+ if (of_property_read_u32_index(np, "reg", 0, ®)) { - dev_err(dev, "the reg property is not assigned in %pOFn node\n", - np); - return -EINVAL; - } - -+ /* support address_cells=2 */ -+ if (reg == 0) { -+ if (of_property_read_u32_index(np, "reg", 1, ®)) { -+ dev_err(dev, "the reg property is not assigned in %pOFn node\n", -+ np); -+ return -EINVAL; -+ } -+ } -+ - rphy->dev = dev; - phy_cfgs = match->data; - rphy->chg_state = USB_CHG_STATE_UNDEFINED; diff --git a/target/linux/rockchip/patches-5.15/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch b/target/linux/rockchip/patches-5.15/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch deleted file mode 100644 index 13614e9ae..000000000 --- a/target/linux/rockchip/patches-5.15/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch +++ /dev/null @@ -1,237 +0,0 @@ -From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:49 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts - -The rk3568 usb2phy has a single muxed interrupt that handles all -interrupts. -Allow the driver to plug in only a single interrupt as necessary. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++----- - 1 file changed, 119 insertions(+), 49 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port { - * @dcd_retries: The retry count used to track Data contact - * detection process. - * @edev: extcon device for notification registration -+ * @irq: muxed interrupt for single irq configuration - * @phy_cfg: phy register configuration, assigned by driver data. - * @ports: phy port instance. - */ -@@ -218,6 +219,7 @@ struct rockchip_usb2phy { - enum power_supply_type chg_type; - u8 dcd_retries; - struct extcon_dev *edev; -+ int irq; - const struct rockchip_usb2phy_cfg *phy_cfg; - struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; - }; -@@ -934,6 +936,102 @@ static irqreturn_t rockchip_usb2phy_otg_ - return IRQ_NONE; - } - -+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) -+{ -+ struct rockchip_usb2phy *rphy = data; -+ struct rockchip_usb2phy_port *rport; -+ irqreturn_t ret = IRQ_NONE; -+ unsigned int index; -+ -+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) { -+ rport = &rphy->ports[index]; -+ if (!rport->phy) -+ continue; -+ -+ /* Handle linestate irq for both otg port and host port */ -+ ret = rockchip_usb2phy_linestate_irq(irq, rport); -+ } -+ -+ return ret; -+} -+ -+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy, -+ struct rockchip_usb2phy_port *rport, -+ struct device_node *child_np) -+{ -+ int ret; -+ -+ /* -+ * If the usb2 phy used combined irq for otg and host port, -+ * don't need to init otg and host port irq separately. -+ */ -+ if (rphy->irq > 0) -+ return 0; -+ -+ switch (rport->port_id) { -+ case USB2PHY_PORT_HOST: -+ rport->ls_irq = of_irq_get_byname(child_np, "linestate"); -+ if (rport->ls_irq < 0) { -+ dev_err(rphy->dev, "no linestate irq provided\n"); -+ return rport->ls_irq; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, -+ rockchip_usb2phy_linestate_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy", rport); -+ if (ret) { -+ dev_err(rphy->dev, "failed to request linestate irq handle\n"); -+ return ret; -+ } -+ break; -+ case USB2PHY_PORT_OTG: -+ /* -+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate -+ * interrupts muxed together, so probe the otg-mux interrupt first, -+ * if not found, then look for the regular interrupts one by one. -+ */ -+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); -+ if (rport->otg_mux_irq > 0) { -+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, -+ NULL, -+ rockchip_usb2phy_otg_mux_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_otg", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-mux irq handle\n"); -+ return ret; -+ } -+ } else { -+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); -+ if (rport->bvalid_irq < 0) { -+ dev_err(rphy->dev, "no vbus valid irq provided\n"); -+ ret = rport->bvalid_irq; -+ return ret; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, -+ NULL, -+ rockchip_usb2phy_bvalid_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_bvalid", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-bvalid irq handle\n"); -+ return ret; -+ } -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, - struct rockchip_usb2phy_port *rport, - struct device_node *child_np) -@@ -947,18 +1045,9 @@ static int rockchip_usb2phy_host_port_in - mutex_init(&rport->mutex); - INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); - -- rport->ls_irq = of_irq_get_byname(child_np, "linestate"); -- if (rport->ls_irq < 0) { -- dev_err(rphy->dev, "no linestate irq provided\n"); -- return rport->ls_irq; -- } -- -- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, -- rockchip_usb2phy_linestate_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy", rport); -+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); - if (ret) { -- dev_err(rphy->dev, "failed to request linestate irq handle\n"); -+ dev_err(rphy->dev, "failed to setup host irq\n"); - return ret; - } - -@@ -1007,44 +1096,10 @@ static int rockchip_usb2phy_otg_port_ini - INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); - INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); - -- /* -- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate -- * interrupts muxed together, so probe the otg-mux interrupt first, -- * if not found, then look for the regular interrupts one by one. -- */ -- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); -- if (rport->otg_mux_irq > 0) { -- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, -- NULL, -- rockchip_usb2phy_otg_mux_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy_otg", -- rport); -- if (ret) { -- dev_err(rphy->dev, -- "failed to request otg-mux irq handle\n"); -- goto out; -- } -- } else { -- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); -- if (rport->bvalid_irq < 0) { -- dev_err(rphy->dev, "no vbus valid irq provided\n"); -- ret = rport->bvalid_irq; -- goto out; -- } -- -- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, -- NULL, -- rockchip_usb2phy_bvalid_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy_bvalid", -- rport); -- if (ret) { -- dev_err(rphy->dev, -- "failed to request otg-bvalid irq handle\n"); -- goto out; -- } -- } -+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); -+ if (ret) { -+ dev_err(rphy->dev, "failed to init irq for host port\n"); -+ goto out; - - if (!IS_ERR(rphy->edev)) { - rport->event_nb.notifier_call = rockchip_otg_event; -@@ -1117,6 +1172,7 @@ static int rockchip_usb2phy_probe(struct - phy_cfgs = match->data; - rphy->chg_state = USB_CHG_STATE_UNDEFINED; - rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; -+ rphy->irq = platform_get_irq_optional(pdev, 0); - platform_set_drvdata(pdev, rphy); - - ret = rockchip_usb2phy_extcon_register(rphy); -@@ -1196,6 +1252,20 @@ next_child: - } - - provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ if (rphy->irq > 0) { -+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL, -+ rockchip_usb2phy_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy", -+ rphy); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request usb2phy irq handle\n"); -+ goto put_child; -+ } -+ } -+ - return PTR_ERR_OR_ZERO(provider); - - put_child: diff --git a/target/linux/rockchip/patches-5.15/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch b/target/linux/rockchip/patches-5.15/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch deleted file mode 100644 index 4a6f282c6..000000000 --- a/target/linux/rockchip/patches-5.15/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch +++ /dev/null @@ -1,44 +0,0 @@ -From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:48 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes - -New Rockchip devices have the usb2 phy devices as standalone nodes -instead of children of the grf node. -Allow the driver to find the grf node from a phandle. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++----- - 1 file changed, 12 insertions(+), 5 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1136,12 +1136,19 @@ static int rockchip_usb2phy_probe(struct - return -EINVAL; - } - -- if (!dev->parent || !dev->parent->of_node) -- return -EINVAL; -+ if (!dev->parent || !dev->parent->of_node) { -+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); -+ if (IS_ERR(rphy->grf)) { -+ dev_err(dev, "failed to locate usbgrf\n"); -+ return PTR_ERR(rphy->grf); -+ } -+ } - -- rphy->grf = syscon_node_to_regmap(dev->parent->of_node); -- if (IS_ERR(rphy->grf)) -- return PTR_ERR(rphy->grf); -+ else { -+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node); -+ if (IS_ERR(rphy->grf)) -+ return PTR_ERR(rphy->grf); -+ } - - if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { - rphy->usbgrf = diff --git a/target/linux/rockchip/patches-5.15/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch b/target/linux/rockchip/patches-5.15/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch deleted file mode 100644 index 8de87e138..000000000 --- a/target/linux/rockchip/patches-5.15/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:50 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support - -The rk3568 usb2phy is a standalone device with a single muxed interrupt. -Add support for the registers to the usb2phy driver. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1100,6 +1100,7 @@ static int rockchip_usb2phy_otg_port_ini - if (ret) { - dev_err(rphy->dev, "failed to init irq for host port\n"); - goto out; -+ } - - if (!IS_ERR(rphy->edev)) { - rport->event_nb.notifier_call = rockchip_otg_event; -@@ -1511,6 +1512,69 @@ static const struct rockchip_usb2phy_cfg - { /* sentinel */ } - }; - -+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { -+ { -+ .reg = 0xfe8a0000, -+ .num_ports = 2, -+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, -+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, -+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, -+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, -+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, -+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, -+ }, -+ [USB2PHY_PORT_HOST] = { -+ /* Select suspend control from controller */ -+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 }, -+ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } -+ } -+ }, -+ .chg_det = { -+ .opmode = { 0x0000, 3, 0, 5, 1 }, -+ .cp_det = { 0x00c0, 24, 24, 0, 1 }, -+ .dcp_det = { 0x00c0, 23, 23, 0, 1 }, -+ .dp_det = { 0x00c0, 25, 25, 0, 1 }, -+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, -+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, -+ .idp_src_en = { 0x0008, 9, 9, 0, 1 }, -+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, -+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, -+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, -+ }, -+ }, -+ { -+ .reg = 0xfe8b0000, -+ .num_ports = 2, -+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } -+ }, -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, -+ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } -+ } -+ }, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { - { - .reg = 0x100, -@@ -1560,6 +1624,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, - { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, - { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, -+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, - { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, - {} - }; diff --git a/target/linux/rockchip/patches-5.15/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch b/target/linux/rockchip/patches-5.15/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch deleted file mode 100644 index 93323ff6b..000000000 --- a/target/linux/rockchip/patches-5.15/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Wed, 26 Jan 2022 15:55:33 +0100 -Subject: [PATCH] clk: rockchip: Add more PLL rates for rk3568 - -This adds a few more PLL settings needed for some standard resolutions: - -297MHz 3840x2160-30.00 -241.5MHz 2560x1440-59.95 -135MHz 1280x1024-75.02 -119MHz 1680x1050-59.88 -108MHz 1280x1024-60.02 - 78.75MHz 1024x768-75.03 - -Changes since v3: -- new patch - -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk - RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), - RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), - RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), -+ RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), -+ RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), - RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), - RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), - RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), -+ RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), -+ RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), -+ RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), - RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), - RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), -+ RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), - { /* sentinel */ }, - }; diff --git a/target/linux/rockchip/patches-5.15/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch b/target/linux/rockchip/patches-5.15/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch deleted file mode 100644 index 890fe0897..000000000 --- a/target/linux/rockchip/patches-5.15/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Wed, 26 Jan 2022 15:55:47 +0100 -Subject: [PATCH] clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference - clock on rk3568 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On the rk3568 we have this (simplified) situation: - - .--------. .-----. .---------. --| hpll |--.--| /n |----|dclk_vop0|- - `--------´ | `-----´ `---------´ - | .-----. .---------. - `--| /m |----|dclk_vop1|- - | `-----´ `---------´ - | .---------. - `-------------|hdmi_ref |- - `---------´ - -For the HDMI to work the HDMI reference clock needs to be the same as the -pixel clock which means the dividers have be set to one. The last patch removed -the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not -changed on pixel clock changes. In order to allow the HDMI controller to -set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the -HDMI reference clock. With this the flow becomes: - -1) HDMI controller driver sets the rate to its pixel clock which means - hpll is set to the pixel clock -2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change - the hpll clock anymore this means only the divider is adjusted to the - desired value of dividing by one. - -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568 - RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), - GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), -- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, -+ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), - }; - diff --git a/target/linux/rockchip/patches-5.15/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch b/target/linux/rockchip/patches-5.15/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch deleted file mode 100644 index f4ae6cb7b..000000000 --- a/target/linux/rockchip/patches-5.15/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001 -From: Yifeng Zhao -Date: Tue, 8 Feb 2022 17:13:25 +0800 -Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568 - -This patch implements a combo phy driver for Rockchip SoCs -with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, -sata-phy or sgmii-phy. - -Signed-off-by: Yifeng Zhao -Signed-off-by: Johan Jonker -Tested-by: Peter Geis -Tested-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/Kconfig | 8 + - drivers/phy/rockchip/Makefile | 1 + - .../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++ - 3 files changed, 590 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY - Enable this to support the Rockchip MIPI/LVDS/TTL PHY with - Innosilicon IP block. - -+config PHY_ROCKCHIP_NANENG_COMBO_PHY -+ tristate "Rockchip NANENG COMBO PHY Driver" -+ depends on ARCH_ROCKCHIP && OF -+ select GENERIC_PHY -+ help -+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII -+ combo PHY with NaNeng IP block. -+ - config PHY_ROCKCHIP_PCIE - tristate "Rockchip PCIe PHY Driver" - depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) - obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o -+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/target/linux/rockchip/patches-5.15/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch b/target/linux/rockchip/patches-5.15/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch deleted file mode 100644 index 6588068cf..000000000 --- a/target/linux/rockchip/patches-5.15/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch +++ /dev/null @@ -1,54 +0,0 @@ -From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 5 Mar 2022 16:58:34 -0500 -Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers - -Host drivers may not be able to support frequencies as low as dw-mmc -supports. Unfortunately f_min isn't available when the drv_data->init -function is called, as the mmc_host struct hasn't been set up yet. - -Support the host drivers saving the requested minimum frequency, so we -can later set f_min when it is available. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/dw_mmc.c | 7 ++++++- - drivers/mmc/host/dw_mmc.h | 2 ++ - 2 files changed, 8 insertions(+), 1 deletion(-) - ---- a/drivers/mmc/host/dw_mmc.c -+++ b/drivers/mmc/host/dw_mmc.c -@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct - if (host->pdata->caps2) - mmc->caps2 = host->pdata->caps2; - -- mmc->f_min = DW_MCI_FREQ_MIN; -+ /* if host has set a minimum_freq, we should respect it */ -+ if (host->minimum_speed) -+ mmc->f_min = host->minimum_speed; -+ else -+ mmc->f_min = DW_MCI_FREQ_MIN; -+ - if (!mmc->f_max) - mmc->f_max = DW_MCI_FREQ_MAX; - ---- a/drivers/mmc/host/dw_mmc.h -+++ b/drivers/mmc/host/dw_mmc.h -@@ -99,6 +99,7 @@ struct dw_mci_dma_slave { - * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus - * rate and timeout calculations. - * @current_speed: Configured rate of the controller. -+ * @minimum_speed: Stored minimum rate of the controller. - * @fifoth_val: The value of FIFOTH register. - * @verid: Denote Version ID. - * @dev: Device associated with the MMC controller. -@@ -200,6 +201,7 @@ struct dw_mci { - - u32 bus_hz; - u32 current_speed; -+ u32 minimum_speed; - u32 fifoth_val; - u16 verid; - struct device *dev; diff --git a/target/linux/rockchip/patches-5.15/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch b/target/linux/rockchip/patches-5.15/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch deleted file mode 100644 index f86a6cdf0..000000000 --- a/target/linux/rockchip/patches-5.15/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 5 Mar 2022 16:58:35 -0500 -Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates - -The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc -hardware supports. This leads to a situation during card initialization -where the clock is set lower than the clock driver can support. The -dw-mmc-rockchip driver spews errors when this happens. -For normal operation this only happens a few times during boot, but when -cd-broken is enabled (in cases such as the SoQuartz module) this fires -multiple times each poll cycle. - -Fix this by testing the lowest possible frequency that the clock driver -can support which is within the mmc specification. Divide that rate by -the internal divider and set f_min to this. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++---- - 1 file changed, 23 insertions(+), 4 deletions(-) - ---- a/drivers/mmc/host/dw_mmc-rockchip.c -+++ b/drivers/mmc/host/dw_mmc-rockchip.c -@@ -15,7 +15,9 @@ - #include "dw_mmc.h" - #include "dw_mmc-pltfm.h" - --#define RK3288_CLKGEN_DIV 2 -+#define RK3288_CLKGEN_DIV 2 -+ -+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; - - struct dw_mci_rockchip_priv_data { - struct clk *drv_clk; -@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct - - ret = clk_set_rate(host->ciu_clk, cclkin); - if (ret) -- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); -+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret); - - bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; - if (bus_hz != host->bus_hz) { -@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct - - static int dw_mci_rockchip_init(struct dw_mci *host) - { -+ int ret, i; -+ - /* It is slot 8 on Rockchip SoCs */ - host->sdio_id0 = 8; - -- if (of_device_is_compatible(host->dev->of_node, -- "rockchip,rk3288-dw-mshc")) -+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) { - host->bus_hz /= RK3288_CLKGEN_DIV; - -+ /* clock driver will fail if the clock is less than the lowest source clock -+ * divided by the internal clock divider. Test for the lowest available -+ * clock and set the minimum freq to clock / clock divider. -+ */ -+ -+ for (i = 0; i < ARRAY_SIZE(freqs); i++) { -+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV); -+ if (ret > 0) { -+ host->minimum_speed = ret / RK3288_CLKGEN_DIV; -+ break; -+ } -+ } -+ if (ret < 0) -+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret); -+ } -+ - return 0; - } - diff --git a/target/linux/rockchip/patches-5.15/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch b/target/linux/rockchip/patches-5.15/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch deleted file mode 100644 index f4de9b7a1..000000000 --- a/target/linux/rockchip/patches-5.15/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 8 Feb 2022 14:40:23 -0500 -Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c - -This adds reboot support to the rk808 pmic driver and enables it for -the rk809 and rk817 devices. -This only enables if the rockchip,system-power-controller flag is set. - -Signed-off-by: Peter Geis -Signed-off-by: Frank Wunderlich -Reviewed-by: Dmitry Osipenko -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com ---- - drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++ - include/linux/mfd/rk808.h | 1 + - 2 files changed, 45 insertions(+) - ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - struct rk808_reg_data { - int addr; -@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void) - reg = RK808_DEVCTRL_REG, - bit = DEV_OFF_RST; - break; -+ case RK809_ID: - case RK817_ID: - reg = RK817_SYS_CFG(3); - bit = DEV_OFF; -@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void) - dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); - } - -+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd) -+{ -+ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); -+ unsigned int reg, bit; -+ int ret; -+ -+ switch (rk808->variant) { -+ case RK809_ID: -+ case RK817_ID: -+ reg = RK817_SYS_CFG(3); -+ bit = DEV_RST; -+ break; -+ -+ default: -+ return NOTIFY_DONE; -+ } -+ ret = regmap_update_bits(rk808->regmap, reg, bit, bit); -+ if (ret) -+ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n"); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block rk808_restart_handler = { -+ .notifier_call = rk808_restart_notify, -+ .priority = 192, -+}; -+ - static void rk8xx_shutdown(struct i2c_client *client) - { - struct rk808 *rk808 = i2c_get_clientdata(client); -@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client - if (of_property_read_bool(np, "rockchip,system-power-controller")) { - rk808_i2c_client = client; - pm_power_off = rk808_pm_power_off; -+ -+ switch (rk808->variant) { -+ case RK809_ID: -+ case RK817_ID: -+ ret = register_restart_handler(&rk808_restart_handler); -+ if (ret) -+ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); -+ break; -+ default: -+ dev_dbg(&client->dev, "pmic controlled board reset not supported\n"); -+ break; -+ } - } - - return 0; -@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_clien - if (pm_power_off == rk808_pm_power_off) - pm_power_off = NULL; - -+ unregister_restart_handler(&rk808_restart_handler); -+ - return 0; - } - ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -373,6 +373,7 @@ enum rk805_reg { - #define SWITCH2_EN BIT(6) - #define SWITCH1_EN BIT(5) - #define DEV_OFF_RST BIT(3) -+#define DEV_RST BIT(2) - #define DEV_OFF BIT(0) - #define RTC_STOP BIT(0) - diff --git a/target/linux/rockchip/patches-5.15/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch b/target/linux/rockchip/patches-5.15/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch deleted file mode 100644 index f2288c752..000000000 --- a/target/linux/rockchip/patches-5.15/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 8 Apr 2022 11:12:34 -0400 -Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566 - -The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to -the combophy as the clock source. As combophy0 doesn't exist on rk3566, -we need to set the clock source to the usb2 phy instead. - -Add handling to the grf driver to handle this on boot. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/grf.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/soc/rockchip/grf.c -+++ b/drivers/soc/rockchip/grf.c -@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk - .num_values = ARRAY_SIZE(rk3399_defaults), - }; - -+#define RK3566_GRF_USB3OTG0_CON1 0x0104 -+ -+static const struct rockchip_grf_value rk3566_defaults[] __initconst = { -+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) }, -+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) }, -+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) }, -+}; -+ -+static const struct rockchip_grf_info rk3566_pipegrf __initconst = { -+ .values = rk3566_defaults, -+ .num_values = ARRAY_SIZE(rk3566_defaults), -+}; -+ -+ - static const struct of_device_id rockchip_grf_dt_match[] __initconst = { - { - .compatible = "rockchip,rk3036-grf", -@@ -130,6 +144,9 @@ static const struct of_device_id rockchi - }, { - .compatible = "rockchip,rk3399-grf", - .data = (void *)&rk3399_grf, -+ }, { -+ .compatible = "rockchip,rk3566-pipe-grf", -+ .data = (void *)&rk3566_pipegrf, - }, - { /* sentinel */ }, - }; diff --git a/target/linux/rockchip/patches-5.15/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch b/target/linux/rockchip/patches-5.15/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch deleted file mode 100644 index 2717ad539..000000000 --- a/target/linux/rockchip/patches-5.15/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 5f6bfab6da6531238e899fdf29efd6d0185adc3e Mon Sep 17 00:00:00 2001 -From: Piotr Oniszczuk -Date: Mon, 14 Feb 2022 21:29:53 +0000 -Subject: [PATCH] media: hantro: Add support for Hantro G1 on RK356x - -RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 -video formats. - -This patch adds support for RK356x family in existing Hantro -video decoder kernel driver. - -Tested on [1] with FFmpeg v4l2_request code taken from [2] -with MPEG2, H.642 and VP8 samples with results [3]. - -[1] https://github.com/warpme/minimyth2 -[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch -[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt - -Signed-off-by: Piotr Oniszczuk -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_drv.c | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 ++++++++++++++ - 3 files changed, 16 insertions(+) - ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -588,6 +588,7 @@ static const struct of_device_id of_hant - { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, - { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, -+ { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M - { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -215,6 +215,7 @@ extern const struct hantro_variant rk306 - extern const struct hantro_variant rk3288_vpu_variant; - extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; -+extern const struct hantro_variant rk3568_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - - extern const struct hantro_postproc_regs hantro_g1_postproc_regs; ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -551,6 +551,20 @@ const struct hantro_variant rk3399_vpu_v - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - -+const struct hantro_variant rk3568_vpu_variant = { -+ .dec_offset = 0x400, -+ .dec_fmts = rk3399_vpu_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .codec = HANTRO_MPEG2_DECODER | -+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, -+ .codec_ops = rk3399_vpu_codec_ops, -+ .irqs = rockchip_vdpu2_irqs, -+ .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), -+ .init = rockchip_vpu_hw_init, -+ .clk_names = rockchip_vpu_clk_names, -+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -+}; -+ - const struct hantro_variant px30_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, diff --git a/target/linux/rockchip/patches-5.15/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch b/target/linux/rockchip/patches-5.15/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch deleted file mode 100644 index ba6b6c5ea..000000000 --- a/target/linux/rockchip/patches-5.15/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6a98df08ccd55e87947d253b19925691763e755c Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:52 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Fix muxed interrupt support - -This commit fixes two issues with the muxed interrupt handler. First, -the OTG port has the "bvalid" interrupt enabled, not "linestate". Since -only the linestate interrupt was handled, and not the bvalid interrupt, -plugging in a cable to the OTG port caused an interrupt storm. - -Second, the return values from the individual port IRQ handlers need to -be OR-ed together. Otherwise, the lack of an interrupt from the last -port would cause the handler to erroneously return IRQ_NONE. - -Fixes: ed2b5a8e6b98 ("phy: phy-rockchip-inno-usb2: support muxed interrupts") -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-2-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -948,8 +948,14 @@ static irqreturn_t rockchip_usb2phy_irq( - if (!rport->phy) - continue; - -- /* Handle linestate irq for both otg port and host port */ -- ret = rockchip_usb2phy_linestate_irq(irq, rport); -+ switch (rport->port_id) { -+ case USB2PHY_PORT_OTG: -+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); -+ break; -+ case USB2PHY_PORT_HOST: -+ ret |= rockchip_usb2phy_linestate_irq(irq, rport); -+ break; -+ } - } - - return ret; diff --git a/target/linux/rockchip/patches-5.15/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch b/target/linux/rockchip/patches-5.15/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch deleted file mode 100644 index 8ee9bccde..000000000 --- a/target/linux/rockchip/patches-5.15/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 656f7fcb1272df590e10cb82e07cd2b79bbf60d1 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:53 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Do not check bvalid twice - -The bvalid interrupt handler already checks bvalid status. The muxed IRQ -handler just needs to call the other handler (plus any other handlers -that will be added). - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-3-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -927,13 +927,11 @@ static irqreturn_t rockchip_usb2phy_bval - - static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) - { -- struct rockchip_usb2phy_port *rport = data; -- struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -+ irqreturn_t ret = IRQ_NONE; - -- if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) -- return rockchip_usb2phy_bvalid_irq(irq, data); -- else -- return IRQ_NONE; -+ ret |= rockchip_usb2phy_bvalid_irq(irq, data); -+ -+ return ret; - } - - static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) diff --git a/target/linux/rockchip/patches-5.15/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch b/target/linux/rockchip/patches-5.15/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch deleted file mode 100644 index b6652143c..000000000 --- a/target/linux/rockchip/patches-5.15/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 5a709a46e4270a6130877c052260d9a6d14ac685 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:54 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Do not lock in bvalid IRQ handler - -Clearing the IRQ is atomic, so there is no need to hold the mutex. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-4-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ---- - 1 file changed, 4 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -913,13 +913,9 @@ static irqreturn_t rockchip_usb2phy_bval - if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) - return IRQ_NONE; - -- mutex_lock(&rport->mutex); -- - /* clear bvalid detect irq pending status */ - property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); - -- mutex_unlock(&rport->mutex); -- - rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); - - return IRQ_HANDLED; diff --git a/target/linux/rockchip/patches-5.15/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch b/target/linux/rockchip/patches-5.15/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch deleted file mode 100644 index 03538c5b8..000000000 --- a/target/linux/rockchip/patches-5.15/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ffe597d04db2b75d9c547a2d2e07c268c2a33117 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:55 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Support multi-bit mask properties - -The "bvalid" and "id" interrupts can trigger on either the rising edge -or the falling edge, so each interrupt has two enable bits and two -status bits. This change allows using a single property for both bits, -checking whether either bit is set. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-5-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -253,7 +253,7 @@ static inline bool property_enabled(stru - return false; - - tmp = (orig & mask) >> reg->bitstart; -- return tmp == reg->enable; -+ return tmp != reg->disable; - } - - static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) diff --git a/target/linux/rockchip/patches-5.15/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch b/target/linux/rockchip/patches-5.15/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch deleted file mode 100644 index 2e0b96e89..000000000 --- a/target/linux/rockchip/patches-5.15/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 21a470606ed5e8b14980f34cd360595d1cba737f Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:56 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Handle bvalid falling - -Some SoCs have a bvalid falling interrupt, in addition to bvalid rising. -This interrupt can detect OTG cable plugout immediately, so it can avoid -the delay until the next scheduled work. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-6-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1353,9 +1353,9 @@ static const struct rockchip_usb2phy_cfg - .port_cfgs = { - [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, -- .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, -- .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, -- .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, -+ .bvalid_det_en = { 0x3020, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x3024, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 }, - .ls_det_en = { 0x3020, 0, 0, 0, 1 }, - .ls_det_st = { 0x3024, 0, 0, 0, 1 }, - .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, -@@ -1396,9 +1396,9 @@ static const struct rockchip_usb2phy_cfg - .port_cfgs = { - [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, -- .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, -- .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, -- .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, -+ .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, - .ls_det_en = { 0x0110, 0, 0, 0, 1 }, - .ls_det_st = { 0x0114, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, -@@ -1520,9 +1520,9 @@ static const struct rockchip_usb2phy_cfg - .port_cfgs = { - [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, -- .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, -- .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, -- .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, -+ .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, - .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, - }, diff --git a/target/linux/rockchip/patches-5.15/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch b/target/linux/rockchip/patches-5.15/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch deleted file mode 100644 index f5855af91..000000000 --- a/target/linux/rockchip/patches-5.15/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch +++ /dev/null @@ -1,230 +0,0 @@ -From 51a9b2c03dd3fddc56c2f68740fade2e38a066d0 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:57 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Handle ID IRQ - -This supports detecting host mode for the OTG port without an extcon. - -The rv1108 properties are not updated due to lack of documentation. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-7-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 85 +++++++++++++++++++ - 1 file changed, 85 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -116,11 +116,15 @@ struct rockchip_chg_det_reg { - * @bvalid_det_en: vbus valid rise detection enable register. - * @bvalid_det_st: vbus valid rise detection status register. - * @bvalid_det_clr: vbus valid rise detection clear register. -+ * @id_det_en: id detection enable register. -+ * @id_det_st: id detection state register. -+ * @id_det_clr: id detection clear register. - * @ls_det_en: linestate detection enable register. - * @ls_det_st: linestate detection state register. - * @ls_det_clr: linestate detection clear register. - * @utmi_avalid: utmi vbus avalid status register. - * @utmi_bvalid: utmi vbus bvalid status register. -+ * @utmi_id: utmi id state register. - * @utmi_ls: utmi linestate state register. - * @utmi_hstdet: utmi host disconnect register. - */ -@@ -129,11 +133,15 @@ struct rockchip_usb2phy_port_cfg { - struct usb2phy_reg bvalid_det_en; - struct usb2phy_reg bvalid_det_st; - struct usb2phy_reg bvalid_det_clr; -+ struct usb2phy_reg id_det_en; -+ struct usb2phy_reg id_det_st; -+ struct usb2phy_reg id_det_clr; - struct usb2phy_reg ls_det_en; - struct usb2phy_reg ls_det_st; - struct usb2phy_reg ls_det_clr; - struct usb2phy_reg utmi_avalid; - struct usb2phy_reg utmi_bvalid; -+ struct usb2phy_reg utmi_id; - struct usb2phy_reg utmi_ls; - struct usb2phy_reg utmi_hstdet; - }; -@@ -161,6 +169,7 @@ struct rockchip_usb2phy_cfg { - * @suspended: phy suspended flag. - * @vbus_attached: otg device vbus status. - * @bvalid_irq: IRQ number assigned for vbus valid rise detection. -+ * @id_irq: IRQ number assigned for ID pin detection. - * @ls_irq: IRQ number assigned for linestate detection. - * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate - * irqs to one irq in otg-port. -@@ -179,6 +188,7 @@ struct rockchip_usb2phy_port { - bool suspended; - bool vbus_attached; - int bvalid_irq; -+ int id_irq; - int ls_irq; - int otg_mux_irq; - struct mutex mutex; -@@ -426,6 +436,19 @@ static int rockchip_usb2phy_init(struct - if (ret) - goto out; - -+ /* clear id status and enable id detect irq */ -+ ret = property_enable(rphy->grf, -+ &rport->port_cfg->id_det_clr, -+ true); -+ if (ret) -+ goto out; -+ -+ ret = property_enable(rphy->grf, -+ &rport->port_cfg->id_det_en, -+ true); -+ if (ret) -+ goto out; -+ - schedule_delayed_work(&rport->otg_sm_work, - OTG_SCHEDULE_DELAY * 3); - } else { -@@ -921,11 +944,30 @@ static irqreturn_t rockchip_usb2phy_bval - return IRQ_HANDLED; - } - -+static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data) -+{ -+ struct rockchip_usb2phy_port *rport = data; -+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -+ bool id; -+ -+ if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st)) -+ return IRQ_NONE; -+ -+ /* clear id detect irq pending status */ -+ property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true); -+ -+ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); -+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) - { - irqreturn_t ret = IRQ_NONE; - - ret |= rockchip_usb2phy_bvalid_irq(irq, data); -+ ret |= rockchip_usb2phy_id_irq(irq, data); - - return ret; - } -@@ -1023,6 +1065,25 @@ static int rockchip_usb2phy_port_irq_ini - "failed to request otg-bvalid irq handle\n"); - return ret; - } -+ -+ rport->id_irq = of_irq_get_byname(child_np, "otg-id"); -+ if (rport->id_irq < 0) { -+ dev_err(rphy->dev, "no otg-id irq provided\n"); -+ ret = rport->id_irq; -+ return ret; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, -+ NULL, -+ rockchip_usb2phy_id_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_id", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-id irq handle\n"); -+ return ret; -+ } - } - break; - default: -@@ -1297,10 +1358,14 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, - .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, - .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, -+ .id_det_en = { 0x0680, 6, 5, 0, 3 }, -+ .id_det_st = { 0x0690, 6, 5, 0, 3 }, -+ .id_det_clr = { 0x06a0, 6, 5, 0, 3 }, - .ls_det_en = { 0x0680, 2, 2, 0, 1 }, - .ls_det_st = { 0x0690, 2, 2, 0, 1 }, - .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, - .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, -+ .utmi_id = { 0x0480, 1, 1, 0, 1 }, - .utmi_ls = { 0x0480, 3, 2, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { -@@ -1356,11 +1421,15 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x3020, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x3024, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 }, -+ .id_det_en = { 0x3020, 5, 4, 0, 3 }, -+ .id_det_st = { 0x3024, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x3028, 5, 4, 0, 3 }, - .ls_det_en = { 0x3020, 0, 0, 0, 1 }, - .ls_det_st = { 0x3024, 0, 0, 0, 1 }, - .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, - .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, -+ .utmi_id = { 0x0120, 6, 6, 0, 1 }, - .utmi_ls = { 0x0120, 5, 4, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { -@@ -1399,11 +1468,15 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, -+ .id_det_en = { 0x0110, 5, 4, 0, 3 }, -+ .id_det_st = { 0x0114, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x0118, 5, 4, 0, 3 }, - .ls_det_en = { 0x0110, 0, 0, 0, 1 }, - .ls_det_st = { 0x0114, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, - .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, -+ .utmi_id = { 0x0120, 6, 6, 0, 1 }, - .utmi_ls = { 0x0120, 5, 4, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { -@@ -1461,8 +1534,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, -+ .id_det_en = { 0xe3c0, 5, 4, 0, 3 }, -+ .id_det_st = { 0xe3e0, 5, 4, 0, 3 }, -+ .id_det_clr = { 0xe3d0, 5, 4, 0, 3 }, - .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, -+ .utmi_id = { 0xe2ac, 8, 8, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, -@@ -1496,8 +1573,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, -+ .id_det_en = { 0xe3c0, 10, 9, 0, 3 }, -+ .id_det_st = { 0xe3e0, 10, 9, 0, 3 }, -+ .id_det_clr = { 0xe3d0, 10, 9, 0, 3 }, - .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, -+ .utmi_id = { 0xe2ac, 11, 11, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, -@@ -1523,8 +1604,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, -+ .id_det_en = { 0x0080, 5, 4, 0, 3 }, -+ .id_det_st = { 0x0084, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x0088, 5, 4, 0, 3 }, - .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, -+ .utmi_id = { 0x00c0, 6, 6, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - /* Select suspend control from controller */ diff --git a/target/linux/rockchip/patches-5.15/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch b/target/linux/rockchip/patches-5.15/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch deleted file mode 100644 index c49bac1b5..000000000 --- a/target/linux/rockchip/patches-5.15/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 6931f85c29d5a0261219cf8a73773d3165806d84 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:18 +0200 -Subject: [PATCH] clk: rockchip: Mark hclk_vo as critical on rk3568 - -Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is -described in the Reference Manual as: - -| 2.8.6 NIU Clock gating reliance -| -| A part of niu clocks have a dependence on another niu clock in order to -| sharing the internal bus. When these clocks are in use, another niu -| clock must be opened, and cannot be gated. These clocks and the special -| clock on which they are relied are as following: -| -| Clocks which have dependency The clock which can not be gated -| ----------------------------------------------------------------- -| ... -| pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu -| ... - -The clock framework doesn't offer a way to enable clock B whenever clock A is -enabled, at least not when B is not an ancestor of A. Workaround this by -marking hclk_vo as critical so it is never disabled. This is suboptimal in -terms of power consumption, but a stop gap solution until the clock framework -has a way to deal with this. - -We have this clock tree: - -| aclk_vo 2 2 0 300000000 0 0 50000 Y -| aclk_hdcp 0 0 0 300000000 0 0 50000 N -| pclk_vo 2 3 0 75000000 0 0 50000 Y -| pclk_edp_ctrl 0 0 0 75000000 0 0 50000 N -| pclk_dsitx_1 0 0 0 75000000 0 0 50000 N -| pclk_dsitx_0 1 2 0 75000000 0 0 50000 Y -| pclk_hdmi_host 1 2 0 75000000 0 0 50000 Y -| pclk_hdcp 0 0 0 75000000 0 0 50000 N -| hclk_vo 2 5 0 150000000 0 0 50000 Y -| hclk_hdcp 0 0 0 150000000 0 0 50000 N -| hclk_vop 0 2 0 150000000 0 0 50000 N - -Without this patch the edp, dsitx, hdmi and hdcp driver would enable their -clocks which then enables pclk_vo, but hclk_vo stays disabled and register -accesses just hang. hclk_vo is enabled by the VOP2 driver, so reproducibility -of this issue depends on the probe order. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Reviewed-by: Robin Murphy -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220422072841.2206452-2-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_crit - "hclk_php", - "pclk_php", - "hclk_usb", -+ "hclk_vo", - }; - - static const char *const rk3568_pmucru_critical_clocks[] __initconst = { diff --git a/target/linux/rockchip/patches-5.15/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch b/target/linux/rockchip/patches-5.15/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch deleted file mode 100644 index 238172be7..000000000 --- a/target/linux/rockchip/patches-5.15/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch +++ /dev/null @@ -1,601 +0,0 @@ -From 540b8f271e53362a308f6bf288d38b630cf3fbd2 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:19 +0200 -Subject: [PATCH] drm/rockchip: Embed drm_encoder into rockchip_decoder - -The VOP2 driver needs rockchip specific information for a drm_encoder. - -This patch creates a struct rockchip_encoder with a struct drm_encoder -embedded in it. This is used throughout the rockchip driver instead of -struct drm_encoder directly. - -The information the VOP2 drivers needs is the of_graph endpoint node -of the encoder. To ease bisectability this is added here. - -While at it convert the different encoder-to-driverdata macros to -static inline functions in order to gain type safety and readability. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-3-s.hauer@pengutronix.de ---- - .../gpu/drm/rockchip/analogix_dp-rockchip.c | 32 +++++++++++------ - drivers/gpu/drm/rockchip/cdn-dp-core.c | 18 ++++++---- - drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +- - .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 ++++++---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 11 ++++-- - drivers/gpu/drm/rockchip/inno_hdmi.c | 32 +++++++++++------ - drivers/gpu/drm/rockchip/rk3066_hdmi.c | 34 ++++++++++++------- - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 10 ++++++ - drivers/gpu/drm/rockchip/rockchip_lvds.c | 26 ++++++++------ - 9 files changed, 122 insertions(+), 60 deletions(-) - ---- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -@@ -40,8 +40,6 @@ - - #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 - --#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) -- - /** - * struct rockchip_dp_chip_data - splite the grf setting of kind of chips - * @lcdsel_grf_reg: grf register offset of lcdc select -@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data { - struct rockchip_dp_device { - struct drm_device *drm_dev; - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - - struct clk *pclk; -@@ -73,6 +71,18 @@ struct rockchip_dp_device { - struct analogix_dp_plat_data plat_data; - }; - -+static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_dp_device, encoder); -+} -+ -+static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) -+{ -+ return container_of(plat_data, struct rockchip_dp_device, plat_data); -+} -+ - static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) - { - reset_control_assert(dp->rst); -@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct r - - static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - int ret; - - ret = clk_prepare_enable(dp->pclk); -@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(str - - static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - - clk_disable_unprepare(dp->pclk); - -@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new - static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state; - int ret; -@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enab - static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *new_crtc_state = NULL; - int ret; -@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct r - - static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) - { -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_device *drm_dev = dp->drm_dev; - struct device *dev = dp->dev; - int ret; -@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct devic - return ret; - } - -- dp->plat_data.encoder = &dp->encoder; -+ dp->plat_data.encoder = &dp->encoder.encoder; - - ret = analogix_dp_bind(dp->adp, drm_dev); - if (ret) -@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct devic - - return 0; - err_cleanup_encoder: -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - return ret; - } - -@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct de - struct rockchip_dp_device *dp = dev_get_drvdata(dev); - - analogix_dp_unbind(dp->adp); -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - } - - static const struct component_ops rockchip_dp_component_ops = { ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.c -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -26,11 +26,17 @@ - #include "cdn-dp-reg.h" - #include "rockchip_drm_vop.h" - --#define connector_to_dp(c) \ -- container_of(c, struct cdn_dp_device, connector) -+static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) -+{ -+ return container_of(connector, struct cdn_dp_device, connector); -+} - --#define encoder_to_dp(c) \ -- container_of(c, struct cdn_dp_device, encoder) -+static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct cdn_dp_device, encoder); -+} - - #define GRF_SOC_CON9 0x6224 - #define DP_SEL_VOP_LIT BIT(12) -@@ -1024,7 +1030,7 @@ static int cdn_dp_bind(struct device *de - - INIT_WORK(&dp->event_work, cdn_dp_pd_event_work); - -- encoder = &dp->encoder; -+ encoder = &dp->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); -@@ -1089,7 +1095,7 @@ err_free_encoder: - static void cdn_dp_unbind(struct device *dev, struct device *master, void *data) - { - struct cdn_dp_device *dp = dev_get_drvdata(dev); -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_connector *connector = &dp->connector; - - cancel_work_sync(&dp->event_work); ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.h -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h -@@ -65,7 +65,7 @@ struct cdn_dp_device { - struct device *dev; - struct drm_device *drm_dev; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - struct platform_device *audio_pdev; - struct work_struct event_work; ---- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -@@ -182,8 +182,6 @@ - - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - --#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) -- - enum { - DW_DSI_USAGE_IDLE, - DW_DSI_USAGE_DSI, -@@ -237,7 +235,7 @@ struct rockchip_dw_dsi_chip_data { - - struct dw_mipi_dsi_rockchip { - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - void __iomem *base; - - struct regmap *grf_regmap; -@@ -272,6 +270,13 @@ struct dw_mipi_dsi_rockchip { - bool dsi_bound; - }; - -+static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); -+} -+ - struct dphy_pll_parameter_map { - unsigned int max_mbps; - u8 hsfreqrange; -@@ -771,7 +776,7 @@ static void dw_mipi_dsi_encoder_enable(s - int ret, mux; - - mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, -- &dsi->encoder); -+ &dsi->encoder.encoder); - if (mux < 0) - return; - -@@ -802,7 +807,7 @@ dw_mipi_dsi_encoder_helper_funcs = { - static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, - struct drm_device *drm_dev) - { -- struct drm_encoder *encoder = &dsi->encoder; -+ struct drm_encoder *encoder = &dsi->encoder.encoder; - int ret; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, -@@ -960,7 +965,7 @@ static int dw_mipi_dsi_rockchip_bind(str - goto out_pll_clk; - } - -- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); -+ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); - if (ret) { - DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); - goto out_pll_clk; ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data { - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *vpll_clk; - struct clk *grf_clk; -@@ -75,7 +75,12 @@ struct rockchip_hdmi { - struct phy *phy; - }; - --#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) -+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_hdmi, encoder); -+} - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct - hdmi->dev = &pdev->dev; - hdmi->chip_data = plat_data->phy_data; - plat_data->phy_data = hdmi; -- encoder = &hdmi->encoder; -+ encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - /* ---- a/drivers/gpu/drm/rockchip/inno_hdmi.c -+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c -@@ -26,8 +26,6 @@ - - #include "inno_hdmi.h" - --#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) -- - struct hdmi_data_info { - int vic; - bool sink_is_hdmi; -@@ -56,7 +54,7 @@ struct inno_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct inno_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -67,6 +65,18 @@ struct inno_hdmi { - struct drm_display_mode previous_mode; - }; - -+static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct inno_hdmi, encoder); -+} -+ -+static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct inno_hdmi, connector); -+} -+ - enum { - CSC_ITU601_16_235_TO_RGB_0_255_8BIT, - CSC_ITU601_0_255_TO_RGB_0_255_8BIT, -@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(s - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_setup(hdmi, adj_mode); - -@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(s - - static void inno_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, NORMAL); - } - - static void inno_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR); - } -@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs i - static enum drm_connector_status - inno_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? - connector_status_connected : connector_status_disconnected; -@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_co - - static int inno_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs - - static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -@@ -881,7 +891,7 @@ static int inno_hdmi_bind(struct device - return 0; - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_put_adapter: - i2c_put_adapter(hdmi->ddc); - err_disable_clk: -@@ -895,7 +905,7 @@ static void inno_hdmi_unbind(struct devi - struct inno_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->pclk); ---- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c -+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c -@@ -47,7 +47,7 @@ struct rk3066_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct rk3066_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -58,7 +58,17 @@ struct rk3066_hdmi { - struct drm_display_mode previous_mode; - }; - --#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x) -+static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rk3066_hdmi, encoder); -+} -+ -+static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rk3066_hdmi, connector); -+} - - static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) - { -@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_ - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - /* Store the display mode for plugin/DPMS poweron events. */ - memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); -@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_ - - static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - int mux, val; - - mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); -@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(s - - static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); - -@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_h - static enum drm_connector_status - rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? - connector_status_connected : connector_status_disconnected; -@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_ - - static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct - static struct drm_encoder * - rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - -- return &hdmi->encoder; -+ return &hdmi->encoder.encoder; - } - - static int -@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066 - static int - rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = -@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct devic - - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_disable_i2c: - i2c_put_adapter(hdmi->ddc); - err_disable_hclk: -@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct de - struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->hclk); ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -52,6 +52,10 @@ struct rockchip_drm_private { - struct mutex psr_list_lock; - }; - -+struct rockchip_encoder { -+ struct drm_encoder encoder; -+}; -+ - int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, - struct device *dev); - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, -@@ -67,4 +71,10 @@ extern struct platform_driver rockchip_d - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+ -+static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) -+{ -+ return container_of(encoder, struct rockchip_encoder, encoder); -+} -+ - #endif /* _ROCKCHIP_DRM_DRV_H_ */ ---- a/drivers/gpu/drm/rockchip/rockchip_lvds.c -+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c -@@ -35,12 +35,6 @@ - - struct rockchip_lvds; - --#define connector_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, connector) -- --#define encoder_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, encoder) -- - /** - * struct rockchip_lvds_soc_data - rockchip lvds Soc private data - * @probe: LVDS platform probe function -@@ -64,10 +58,22 @@ struct rockchip_lvds { - struct drm_panel *panel; - struct drm_bridge *bridge; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct dev_pin_info *pins; - }; - -+static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rockchip_lvds, connector); -+} -+ -+static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_lvds, encoder); -+} -+ - static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, - u32 val) - { -@@ -600,7 +606,7 @@ static int rockchip_lvds_bind(struct dev - goto err_put_remote; - } - -- encoder = &lvds->encoder; -+ encoder = &lvds->encoder.encoder; - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); - -@@ -665,10 +671,10 @@ static void rockchip_lvds_unbind(struct - const struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = lvds->soc_data->helper_funcs; -- encoder_funcs->disable(&lvds->encoder); -+ encoder_funcs->disable(&lvds->encoder.encoder); - pm_runtime_disable(dev); - drm_connector_cleanup(&lvds->connector); -- drm_encoder_cleanup(&lvds->encoder); -+ drm_encoder_cleanup(&lvds->encoder.encoder); - } - - static const struct component_ops rockchip_lvds_component_ops = { diff --git a/target/linux/rockchip/patches-5.15/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch b/target/linux/rockchip/patches-5.15/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch deleted file mode 100644 index e80ecfddf..000000000 --- a/target/linux/rockchip/patches-5.15/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch +++ /dev/null @@ -1,88 +0,0 @@ -From cf544c6a885c52d79e4d8bf139fb8cb63a878512 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:20 +0200 -Subject: [PATCH] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder - -The VOP2 has an interface mux which decides to which encoder(s) a CRTC -is routed to. The encoders and CRTCs are connected via of_graphs in the -device tree. When given an encoder the VOP2 driver needs to know to -which internal register setting this encoder matches. For this the VOP2 -binding offers different endpoints, one for each possible encoder. The -endpoint ids of these endpoints are used as a key from an encoders -device tree description to the internal register setting. - -This patch adds the key aka endpoint id to struct rockchip_encoder plus -a function to read the endpoint id starting from the encoders device -node. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-4-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 33 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 4 ++- - 2 files changed, 36 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -255,6 +255,39 @@ static struct platform_driver *rockchip_ - static int num_rockchip_sub_drivers; - - /* -+ * Get the endpoint id of the remote endpoint of the given encoder. This -+ * information is used by the VOP2 driver to identify the encoder. -+ * -+ * @rkencoder: The encoder to get the remote endpoint id from -+ * @np: The encoder device node -+ * @port: The number of the port leading to the VOP2 -+ * @reg: The endpoint number leading to the VOP2 -+ */ -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder, -+ struct device_node *np, int port, int reg) -+{ -+ struct of_endpoint ep; -+ struct device_node *en, *ren; -+ int ret; -+ -+ en = of_graph_get_endpoint_by_regs(np, port, reg); -+ if (!en) -+ return -ENOENT; -+ -+ ren = of_graph_get_remote_endpoint(en); -+ if (!ren) -+ return -ENOENT; -+ -+ ret = of_graph_parse_endpoint(ren, &ep); -+ if (ret) -+ return ret; -+ -+ rkencoder->crtc_endpoint_id = ep.id; -+ -+ return 0; -+} -+ -+/* - * Check if a vop endpoint is leading to a rockchip subdriver or bridge. - * Should be called from the component bind stage of the drivers - * to ensure that all subdrivers are probed. ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -53,6 +53,7 @@ struct rockchip_drm_private { - }; - - struct rockchip_encoder { -+ int crtc_endpoint_id; - struct drm_encoder encoder; - }; - -@@ -61,7 +62,8 @@ int rockchip_drm_dma_attach_device(struc - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, - struct device *dev); - int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); -- -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder, -+ struct device_node *np, int port, int reg); - int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); - extern struct platform_driver cdn_dp_driver; - extern struct platform_driver dw_hdmi_rockchip_pltfm_driver; diff --git a/target/linux/rockchip/patches-5.15/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch b/target/linux/rockchip/patches-5.15/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch deleted file mode 100644 index dce5b3797..000000000 --- a/target/linux/rockchip/patches-5.15/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch +++ /dev/null @@ -1,93 +0,0 @@ -From a9d37e684492ab5db1cce28b655e20c01191873f Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:21 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: rename vpll clock to reference clock - -"vpll" is a misnomer. A clock input to a device should be named after -the usage in the device, not after the clock that drives it. On the -rk3568 the same clock is driven by the HPLL. -To fix that, this patch renames the vpll clock to ref clock. The clock -name "vpll" is left for compatibility to old device trees. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-5-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++---------- - 1 file changed, 14 insertions(+), 13 deletions(-) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -69,7 +69,7 @@ struct rockchip_hdmi { - struct regmap *regmap; - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; -- struct clk *vpll_clk; -+ struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; - struct phy *phy; -@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct - return PTR_ERR(hdmi->regmap); - } - -- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); -- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { -- hdmi->vpll_clk = NULL; -- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); -+ if (!hdmi->ref_clk) -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); -+ -+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { - return -EPROBE_DEFER; -- } else if (IS_ERR(hdmi->vpll_clk)) { -- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n"); -- return PTR_ERR(hdmi->vpll_clk); -+ } else if (IS_ERR(hdmi->ref_clk)) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); -+ return PTR_ERR(hdmi->ref_clk); - } - - hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); -@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mod - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - -- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); -+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); - } - - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -- ret = clk_prepare_enable(hdmi->vpll_clk); -+ ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); - return ret; - } -@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); - drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - return ret; -@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(stru - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/target/linux/rockchip/patches-5.15/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch b/target/linux/rockchip/patches-5.15/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch deleted file mode 100644 index 799f159ca..000000000 --- a/target/linux/rockchip/patches-5.15/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 28bbb5ffbe32741e65d798070986d212cc11e1bb Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:24 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: add rk3568 support - -Add a new dw_hdmi_plat_data struct and new compatible for rk3568. - -Signed-off-by: Benjamin Gaignard -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-8-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++ - 1 file changed, 31 insertions(+) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -50,6 +50,10 @@ - #define RK3399_GRF_SOC_CON20 0x6250 - #define RK3399_HDMI_LCDC_SEL BIT(6) - -+#define RK3568_GRF_VO_CON1 0x0364 -+#define RK3568_HDMI_SDAIN_MSK BIT(15) -+#define RK3568_HDMI_SCLIN_MSK BIT(14) -+ - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - - /** -@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk - .use_drm_infoframe = true, - }; - -+static struct rockchip_hdmi_chip_data rk3568_chip_data = { -+ .lcdsel_grf_reg = -1, -+}; -+ -+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { -+ .mode_valid = dw_hdmi_rockchip_mode_valid, -+ .mpll_cfg = rockchip_mpll_cfg, -+ .cur_ctr = rockchip_cur_ctr, -+ .phy_config = rockchip_phy_config, -+ .phy_data = &rk3568_chip_data, -+ .use_drm_infoframe = true, -+}; -+ - static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3228-dw-hdmi", - .data = &rk3228_hdmi_drv_data -@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi - { .compatible = "rockchip,rk3399-dw-hdmi", - .data = &rk3399_hdmi_drv_data - }, -+ { .compatible = "rockchip,rk3568-dw-hdmi", -+ .data = &rk3568_hdmi_drv_data -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); -@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct - encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -+ dev->of_node, 0, 0); -+ - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has -@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -+ if (hdmi->chip_data == &rk3568_chip_data) { -+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, -+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK, -+ RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK)); -+ } -+ - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - diff --git a/target/linux/rockchip/patches-5.15/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch b/target/linux/rockchip/patches-5.15/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch deleted file mode 100644 index 4a67db21d..000000000 --- a/target/linux/rockchip/patches-5.15/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From ca80c4eb4b01a7f1c2f333d0a329937ef9c7f03a Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:26 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: add regulator support - -The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed -for the HDMI port. add support for these to the driver for boards which -have them supplied by switchable regulators. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-10-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++-- - 1 file changed, 38 insertions(+), 3 deletions(-) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -76,6 +77,8 @@ struct rockchip_hdmi { - struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; -+ struct regulator *avdd_0v9; -+ struct regulator *avdd_1v8; - struct phy *phy; - }; - -@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct - return PTR_ERR(hdmi->grf_clk); - } - -+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); -+ if (IS_ERR(hdmi->avdd_0v9)) -+ return PTR_ERR(hdmi->avdd_0v9); -+ -+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); -+ if (IS_ERR(hdmi->avdd_1v8)) -+ return PTR_ERR(hdmi->avdd_1v8); -+ - return 0; - } - -@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -+ ret = regulator_enable(hdmi->avdd_0v9); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -+ goto err_avdd_0v9; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_1v8); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -+ goto err_avdd_1v8; -+ } -+ - ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); -- return ret; -+ goto err_clk; - } - - if (hdmi->chip_data == &rk3568_chip_data) { -@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct - */ - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); -- drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->ref_clk); -+ goto err_bind; - } - -+ return 0; -+ -+err_bind: -+ drm_encoder_cleanup(encoder); -+ clk_disable_unprepare(hdmi->ref_clk); -+err_clk: -+ regulator_disable(hdmi->avdd_1v8); -+err_avdd_1v8: -+ regulator_disable(hdmi->avdd_0v9); -+err_avdd_0v9: - return ret; - } - -@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(stru - - dw_hdmi_unbind(hdmi->hdmi); - clk_disable_unprepare(hdmi->ref_clk); -+ -+ regulator_disable(hdmi->avdd_1v8); -+ regulator_disable(hdmi->avdd_0v9); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/target/linux/rockchip/patches-5.15/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch b/target/linux/rockchip/patches-5.15/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch deleted file mode 100644 index 0f92c0774..000000000 --- a/target/linux/rockchip/patches-5.15/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch +++ /dev/null @@ -1,65 +0,0 @@ -From b382406a2cf4afaa7320a7ad4b298ed6e2675437 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:38 +0200 -Subject: [PATCH] drm/rockchip: Make VOP driver optional - -With upcoming VOP2 support VOP won't be the only choice anymore, so make -the VOP driver optional. - -This also adds a dependency from ROCKCHIP_ANALOGIX_DP to ROCKCHIP_VOP, -because that driver currently only links and works with the VOP driver. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-22-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/Kconfig | 8 ++++++++ - drivers/gpu/drm/rockchip/Makefile | 3 ++- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- - 3 files changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -22,8 +22,16 @@ config DRM_ROCKCHIP - - if DRM_ROCKCHIP - -+config ROCKCHIP_VOP -+ bool "Rockchip VOP driver" -+ default y -+ help -+ This selects support for the VOP driver. You should enable it -+ on older SoCs. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" -+ depends on ROCKCHIP_VOP - help - This selects support for Rockchip SoC specific extensions - for the Analogix Core DP driver. If you want to enable DP ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -4,9 +4,10 @@ - # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. - - rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ -- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o -+ rockchip_drm_gem.o - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -502,7 +502,7 @@ static int __init rockchip_drm_init(void - int ret; - - num_rockchip_sub_drivers = 0; -- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, diff --git a/target/linux/rockchip/patches-5.15/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch b/target/linux/rockchip/patches-5.15/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch deleted file mode 100644 index c33f9a572..000000000 --- a/target/linux/rockchip/patches-5.15/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 604be85547ce4d61b89292d2f9a78c721b778c16 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Fri, 22 Apr 2022 09:28:39 +0200 -Subject: [PATCH] drm/rockchip: Add VOP2 driver - -The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568. -It replaces the VOP unit found in the older Rockchip SoCs. - -This driver has been derived from the downstream Rockchip Kernel and -heavily modified: - -- All nonstandard DRM properties have been removed -- dropped struct vop2_plane_state and pass around less data between - functions -- Dropped all DRM_FORMAT_* not known on upstream -- rework register access to get rid of excessively used macros -- Drop all waiting for framesyncs - -The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB -board. Overlay support is tested with the modetest utility. AFBC support -on the cluster windows is tested with weston-simple-dmabuf-egl on -weston using the (yet to be upstreamed) panfrost driver support. - -Signed-off-by: Andy Yan -Co-Developed-by: Sascha Hauer -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -[dt-binding-header:] -Acked-by: Rob Herring -[moved dt-binding header from dt-nodes patch to here - and made checkpatch --strict happier] -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/Kconfig | 6 + - drivers/gpu/drm/rockchip/Makefile | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 6 +- - drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 + - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 + - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++ - drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++ - include/dt-bindings/soc/rockchip,vop2.h | 14 + - 10 files changed, 3507 insertions(+), 1 deletion(-) - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h - create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c - create mode 100644 include/dt-bindings/soc/rockchip,vop2.h - ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -29,6 +29,12 @@ config ROCKCHIP_VOP - This selects support for the VOP driver. You should enable it - on older SoCs. - -+config ROCKCHIP_VOP2 -+ bool "Rockchip VOP2 driver" -+ help -+ This selects support for the VOP2 driver. The VOP2 hardware is -+ first found on the RK3568. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" - depends on ROCKCHIP_VOP ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rock - rockchip_drm_gem.o - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -503,6 +503,7 @@ static int __init rockchip_drm_init(void - - num_rockchip_sub_drivers = 0; - ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -18,7 +18,7 @@ - - #define ROCKCHIP_MAX_FB_BUFFER 3 - #define ROCKCHIP_MAX_CONNECTOR 2 --#define ROCKCHIP_MAX_CRTC 2 -+#define ROCKCHIP_MAX_CRTC 4 - - struct drm_device; - struct drm_connector; -@@ -31,6 +31,9 @@ struct rockchip_crtc_state { - int output_bpc; - int output_flags; - bool enable_afbc; -+ u32 bus_format; -+ u32 bus_flags; -+ int color_space; - }; - #define to_rockchip_crtc_state(s) \ - container_of(s, struct rockchip_crtc_state, base) -@@ -73,6 +76,7 @@ extern struct platform_driver rockchip_d - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+extern struct platform_driver vop2_platform_driver; - - static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) - { ---- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struc - - dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; - dev->mode_config.helper_private = &rockchip_mode_config_helpers; -+ -+ dev->mode_config.normalize_zpos = true; - } ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -54,9 +54,23 @@ struct vop_afbc { - struct vop_reg enable; - struct vop_reg win_sel; - struct vop_reg format; -+ struct vop_reg rb_swap; -+ struct vop_reg uv_swap; -+ struct vop_reg auto_gating_en; -+ struct vop_reg block_split_en; -+ struct vop_reg pic_vir_width; -+ struct vop_reg tile_num; - struct vop_reg hreg_block_split; -+ struct vop_reg pic_offset; - struct vop_reg pic_size; -+ struct vop_reg dsp_offset; -+ struct vop_reg transform_offset; - struct vop_reg hdr_ptr; -+ struct vop_reg half_block_en; -+ struct vop_reg xmirror; -+ struct vop_reg ymirror; -+ struct vop_reg rotate_270; -+ struct vop_reg rotate_90; - struct vop_reg rstn; - }; - diff --git a/target/linux/rockchip/patches-5.15/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch b/target/linux/rockchip/patches-5.15/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch deleted file mode 100644 index fd380befd..000000000 --- a/target/linux/rockchip/patches-5.15/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:28 -0400 -Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe - -The PCIe controller is in an unknown state at driver probe. This can -lead to undesireable effects when the driver attempts to configure the -controller. - -Prevent issues in the future by resetting the core during probe. - -Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com -Tested-by: Nicolas Frattaroli -Signed-off-by: Peter Geis -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++----------- - 1 file changed, 10 insertions(+), 13 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(st - if (IS_ERR(rockchip->rst_gpio)) - return PTR_ERR(rockchip->rst_gpio); - -+ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev); -+ if (IS_ERR(rockchip->rst)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), -+ "failed to get reset lines\n"); -+ - return 0; - } - -@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(str - phy_power_off(rockchip->phy); - } - --static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip) --{ -- struct device *dev = rockchip->pci.dev; -- -- rockchip->rst = devm_reset_control_array_get_exclusive(dev); -- if (IS_ERR(rockchip->rst)) -- return dev_err_probe(dev, PTR_ERR(rockchip->rst), -- "failed to get reset lines\n"); -- -- return reset_control_deassert(rockchip->rst); --} -- - static const struct dw_pcie_ops dw_pcie_ops = { - .link_up = rockchip_pcie_link_up, - .start_link = rockchip_pcie_start_link, -@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct pl - if (ret) - return ret; - -+ ret = reset_control_assert(rockchip->rst); -+ if (ret) -+ return ret; -+ - /* DON'T MOVE ME: must be enable before PHY init */ - rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); - if (IS_ERR(rockchip->vpcie3v3)) { -@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct pl - if (ret) - goto disable_regulator; - -- ret = rockchip_pcie_reset_control_release(rockchip); -+ ret = reset_control_deassert(rockchip->rst); - if (ret) - goto deinit_phy; - diff --git a/target/linux/rockchip/patches-5.15/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch b/target/linux/rockchip/patches-5.15/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch deleted file mode 100644 index 05b762ff5..000000000 --- a/target/linux/rockchip/patches-5.15/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch +++ /dev/null @@ -1,163 +0,0 @@ -From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:29 -0400 -Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support - -The legacy interrupts on the rk356x PCIe controller are handled by a -single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip -driver to support the virtual domain. - -Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com -Signed-off-by: Peter Geis -Signed-off-by: Lorenzo Pieralisi -Reviewed-by: Marc Zyngier ---- - drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++- - 1 file changed, 94 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -10,9 +10,12 @@ - - #include - #include -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -26,6 +29,7 @@ - */ - #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) - #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) -+#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val) - - #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) - -@@ -36,10 +40,12 @@ - #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) - #define PCIE_L0S_ENTRY 0x11 - #define PCIE_CLIENT_GENERAL_CONTROL 0x0 -+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 -+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c - #define PCIE_CLIENT_GENERAL_DEBUG 0x104 --#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 -+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 - #define PCIE_CLIENT_LTSSM_STATUS 0x300 --#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) - #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) - - struct rockchip_pcie { -@@ -51,6 +57,7 @@ struct rockchip_pcie { - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; -+ struct irq_domain *irq_domain; - }; - - static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, -@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(str - writel_relaxed(val, rockchip->apb_base + reg); - } - -+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); -+ unsigned long reg, hwirq; -+ -+ chained_irq_enter(chip, desc); -+ -+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); -+ -+ for_each_set_bit(hwirq, ®, 4) -+ generic_handle_domain_irq(rockchip->irq_domain, hwirq); -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void rockchip_intx_mask(struct irq_data *data) -+{ -+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), -+ HIWORD_UPDATE_BIT(BIT(data->hwirq)), -+ PCIE_CLIENT_INTR_MASK_LEGACY); -+}; -+ -+static void rockchip_intx_unmask(struct irq_data *data) -+{ -+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), -+ HIWORD_DISABLE_BIT(BIT(data->hwirq)), -+ PCIE_CLIENT_INTR_MASK_LEGACY); -+}; -+ -+static struct irq_chip rockchip_intx_irq_chip = { -+ .name = "INTx", -+ .irq_mask = rockchip_intx_mask, -+ .irq_unmask = rockchip_intx_unmask, -+ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, -+}; -+ -+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops intx_domain_ops = { -+ .map = rockchip_pcie_intx_map, -+}; -+ -+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) -+{ -+ struct device *dev = rockchip->pci.dev; -+ struct device_node *intc; -+ -+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); -+ if (!intc) { -+ dev_err(dev, "missing child interrupt-controller node\n"); -+ return -EINVAL; -+ } -+ -+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, -+ &intx_domain_ops, rockchip); -+ of_node_put(intc); -+ if (!rockchip->irq_domain) { -+ dev_err(dev, "failed to get a INTx IRQ domain\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) - { - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, -@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struc - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); -+ struct device *dev = rockchip->pci.dev; - u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); -+ int irq, ret; -+ -+ irq = of_irq_get_byname(dev->of_node, "legacy"); -+ if (irq < 0) -+ return irq; -+ -+ ret = rockchip_pcie_init_irq_domain(rockchip); -+ if (ret < 0) -+ dev_err(dev, "failed to init irq domain\n"); -+ -+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, -+ rockchip); - - /* LTSSM enable control mode */ - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); diff --git a/target/linux/rockchip/patches-5.15/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch b/target/linux/rockchip/patches-5.15/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch deleted file mode 100644 index bf17aa7ff..000000000 --- a/target/linux/rockchip/patches-5.15/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 98526c5bbe3267d447ddd076b685439e3e1396c6 Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Mon, 9 May 2022 12:05:05 +0300 -Subject: [PATCH] drm/rockchip: vop2: unlock on error path in - vop2_crtc_atomic_enable() - -This error path needs an unlock before returning. - -Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") -Signed-off-by: Dan Carpenter -Acked-by: Sascha Hauer -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/YnjZQRV9lpub2ET8@kili ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -1524,6 +1524,7 @@ static void vop2_crtc_atomic_enable(stru - if (ret < 0) { - drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", - vp->id, ret); -+ vop2_unlock(vop2); - return; - } - diff --git a/target/linux/rockchip/patches-5.15/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch b/target/linux/rockchip/patches-5.15/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch deleted file mode 100644 index 33b2544bd..000000000 --- a/target/linux/rockchip/patches-5.15/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 6f1ae821a6c4aa9d5b8f437b27ec86fb569219fd Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Sun, 12 Jun 2022 16:53:45 +0100 -Subject: [PATCH] media: hantro: Add support for RK356x encoder - -The RK3566 and RK3568 SoCs come with a small Hantro instance which is -solely dedicated to encoding. This patch adds the necessary structs to -the Hantro driver to allow the JPEG encoder of it to function. - -Through some sleuthing through the vendor's MPP source code and after -closer inspection of the TRM, it was determined that the hardware likely -supports VP8 and H.264 as well. - -Tested with the following GStreamer command: - -gst-launch-1.0 videotestsrc ! v4l2jpegenc ! matroskamux ! \ - filesink location=foo.mkv - -Signed-off-by: Nicolas Frattaroli -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_drv.c | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../staging/media/hantro/rockchip_vpu_hw.c | 25 +++++++++++++++++++ - 3 files changed, 27 insertions(+) - ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -588,6 +588,7 @@ static const struct of_device_id of_hant - { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, - { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, -+ { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -215,6 +215,7 @@ extern const struct hantro_variant rk306 - extern const struct hantro_variant rk3288_vpu_variant; - extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; -+extern const struct hantro_variant rk3568_vepu_variant; - extern const struct hantro_variant rk3568_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -423,6 +423,14 @@ static const struct hantro_codec_ops rk3 - }, - }; - -+static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = { -+ [HANTRO_MODE_JPEG_ENC] = { -+ .run = rockchip_vpu2_jpeg_enc_run, -+ .reset = rockchip_vpu2_enc_reset, -+ .done = rockchip_vpu2_jpeg_enc_done, -+ }, -+}; -+ - /* - * VPU variant. - */ -@@ -445,6 +453,10 @@ static const struct hantro_irq rockchip_ - { "vdpu", rockchip_vpu2_vdpu_irq }, - }; - -+static const struct hantro_irq rk3568_vepu_irqs[] = { -+ { "vepu", rockchip_vpu2_vepu_irq }, -+}; -+ - static const char * const rk3066_vpu_clk_names[] = { - "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu" -@@ -549,6 +561,19 @@ const struct hantro_variant rk3399_vpu_v - .init = rockchip_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -+}; -+ -+const struct hantro_variant rk3568_vepu_variant = { -+ .enc_offset = 0x0, -+ .enc_fmts = rockchip_vpu_enc_fmts, -+ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), -+ .codec = HANTRO_JPEG_ENCODER, -+ .codec_ops = rk3568_vepu_codec_ops, -+ .irqs = rk3568_vepu_irqs, -+ .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs), -+ .init = rockchip_vpu_hw_init, -+ .clk_names = rockchip_vpu_clk_names, -+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - - const struct hantro_variant rk3568_vpu_variant = { diff --git a/target/linux/rockchip/patches-5.15/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch b/target/linux/rockchip/patches-5.15/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch deleted file mode 100644 index b850bbcf5..000000000 --- a/target/linux/rockchip/patches-5.15/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fd7d47484125c7d04578de9294faa7fec6e5df0a Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 8 Jul 2022 01:14:34 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode - -When the OTG port is fixed to host mode, the driver does not request its -IRQs, nor does it enable those IRQs in hardware. Similarly, the driver -should ignore the OTG port IRQs when handling the shared interrupt. - -Otherwise, it would update the extcon based on an ID pin which may be in -an undefined state, or try to queue a uninitialized work item. - -Fixes: 6a98df08ccd5 ("phy: rockchip-inno-usb2: Fix muxed interrupt support") -Reported-by: Frank Wunderlich -Signed-off-by: Samuel Holland -Tested-by: Peter Geis -Tested-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220708061434.38115-1-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -986,7 +986,9 @@ static irqreturn_t rockchip_usb2phy_irq( - - switch (rport->port_id) { - case USB2PHY_PORT_OTG: -- ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); -+ if (rport->mode != USB_DR_MODE_HOST && -+ rport->mode != USB_DR_MODE_UNKNOWN) -+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); - break; - case USB2PHY_PORT_HOST: - ret |= rockchip_usb2phy_linestate_irq(irq, rport); diff --git a/target/linux/rockchip/patches-5.15/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch b/target/linux/rockchip/patches-5.15/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch deleted file mode 100644 index 22e33fca3..000000000 --- a/target/linux/rockchip/patches-5.15/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 177d841fa19542eb35aa5ec9579c4abb989c9255 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Wed, 29 Jun 2022 20:56:23 +0100 -Subject: [PATCH] media: hantro: Fix RK3399 H.264 format advertising - -Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2") -enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect -of exposing H.264 coded format as supported on RK3399. - -Fix this and clarify how the codec is explicitly disabled on RK3399 on -this driver. - -Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2") -Signed-off-by: Ezequiel Garcia -Tested-by: Nicolas Dufresne -Reviewed-by: Nicolas Dufresne -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/rockchip_vpu_hw.c | 60 ++++++++++++++++--- - 1 file changed, 53 insertions(+), 7 deletions(-) - ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -158,7 +158,7 @@ static const struct hantro_fmt rk3288_vp - }, - }; - --static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { -+static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, -@@ -204,6 +204,47 @@ static const struct hantro_fmt rk3399_vp - }, - }; - -+static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_FHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_FHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, -+ .codec_mode = HANTRO_MODE_MPEG2_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_FHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_FHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP8_FRAME, -+ .codec_mode = HANTRO_MODE_VP8_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_UHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_UHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+}; -+ - static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id) - { - struct hantro_dev *vpu = dev_id; -@@ -534,8 +575,8 @@ const struct hantro_variant rk3288_vpu_v - - const struct hantro_variant rk3328_vpu_variant = { - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, -@@ -546,6 +587,11 @@ const struct hantro_variant rk3328_vpu_v - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names), - }; - -+/* -+ * H.264 decoding explicitly disabled in RK3399. -+ * This ensures userspace applications use the Rockchip VDEC core, -+ * which has better performance. -+ */ - const struct hantro_variant rk3399_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, -@@ -578,8 +624,8 @@ const struct hantro_variant rk3568_vepu_ - - const struct hantro_variant rk3568_vpu_variant = { - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, -@@ -595,8 +641,8 @@ const struct hantro_variant px30_vpu_var - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, diff --git a/target/linux/rockchip/patches-5.15/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch b/target/linux/rockchip/patches-5.15/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch deleted file mode 100644 index f65056fe2..000000000 --- a/target/linux/rockchip/patches-5.15/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch +++ /dev/null @@ -1,27 +0,0 @@ -From b113e55913e7f7f031d6cbf9d7b585c6b112f55a Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 25 Jun 2022 17:27:11 -0400 -Subject: [PATCH] phy: rockchip-inno-usb2: Prevent incorrect error on probe - -If a phy supply is designated but isn't available at probe time, an -EPROBE_DEFER is returned. Use dev_err_probe to prevent this from -incorrectly printing during boot. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1293,7 +1293,7 @@ static int rockchip_usb2phy_probe(struct - - phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); - if (IS_ERR(phy)) { -- dev_err(dev, "failed to create phy\n"); -+ dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n"); - ret = PTR_ERR(phy); - goto put_child; - } diff --git a/target/linux/rockchip/patches-5.15/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch b/target/linux/rockchip/patches-5.15/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch deleted file mode 100644 index 666c31539..000000000 --- a/target/linux/rockchip/patches-5.15/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8dc60f8da22fdbaa1fafcfb5ff6d24bc9eff56aa Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 21 Jun 2022 20:31:40 -0400 -Subject: [PATCH] phy: rockchip-inno-usb2: Sync initial otg state - -The initial otg state for the phy defaults to device mode. The actual -state isn't detected until an ID IRQ fires. Fix this by syncing the ID -state during initialization. - -Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") -Signed-off-by: Peter Geis -Reviewed-by: Samuel Holland -Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1172,6 +1172,12 @@ static int rockchip_usb2phy_otg_port_ini - EXTCON_USB_HOST, &rport->event_nb); - if (ret) - dev_err(rphy->dev, "register USB HOST notifier failed\n"); -+ -+ if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { -+ /* do initial sync of usb state */ -+ ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); -+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret); -+ } - } - - out: diff --git a/target/linux/rockchip/patches-5.15/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch b/target/linux/rockchip/patches-5.15/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch deleted file mode 100644 index 036a87b4f..000000000 --- a/target/linux/rockchip/patches-5.15/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch +++ /dev/null @@ -1,123 +0,0 @@ -From d0637c505f8a1d8c4088642f1f3e9e3b22da14f6 Mon Sep 17 00:00:00 2001 -From: Barry Song -Date: Wed, 20 Jul 2022 21:37:37 +1200 -Subject: [PATCH] arm64: enable THP_SWAP for arm64 - -THP_SWAP has been proven to improve the swap throughput significantly -on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay -splitting THP after swapped out"). -As long as arm64 uses 4K page size, it is quite similar with x86_64 -by having 2MB PMD THP. THP_SWAP is architecture-independent, thus, -enabling it on arm64 will benefit arm64 as well. -A corner case is that MTE has an assumption that only base pages -can be swapped. We won't enable THP_SWAP for ARM64 hardware with -MTE support until MTE is reworked to coexist with THP_SWAP. - -A micro-benchmark is written to measure thp swapout throughput as -below, - - unsigned long long tv_to_ms(struct timeval tv) - { - return tv.tv_sec * 1000 + tv.tv_usec / 1000; - } - - main() - { - struct timeval tv_b, tv_e;; - #define SIZE 400*1024*1024 - volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - if (!p) { - perror("fail to get memory"); - exit(-1); - } - - madvise(p, SIZE, MADV_HUGEPAGE); - memset(p, 0x11, SIZE); /* write to get mem */ - - gettimeofday(&tv_b, NULL); - madvise(p, SIZE, MADV_PAGEOUT); - gettimeofday(&tv_e, NULL); - - printf("swp out bandwidth: %ld bytes/ms\n", - SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b))); - } - -Testing is done on rk3568 64bit Quad Core Cortex-A55 platform - -ROCK 3A. -thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests) -thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests) - -Cc: "Huang, Ying" -Cc: Minchan Kim -Cc: Johannes Weiner -Cc: Hugh Dickins -Cc: Andrea Arcangeli -Cc: Steven Price -Cc: Yang Shi -Reviewed-by: Anshuman Khandual -Signed-off-by: Barry Song -Link: https://lore.kernel.org/r/20220720093737.133375-1-21cnbao@gmail.com -Signed-off-by: Will Deacon ---- - arch/arm64/Kconfig | 1 + - arch/arm64/include/asm/pgtable.h | 6 ++++++ - include/linux/huge_mm.h | 12 ++++++++++++ - mm/swap_slots.c | 2 +- - 4 files changed, 20 insertions(+), 1 deletion(-) - ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -95,6 +95,7 @@ config ARM64 - select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) - select ARCH_WANT_LD_ORPHAN_WARN - select ARCH_WANTS_NO_INSTR -+ select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES - select ARCH_HAS_UBSAN_SANITIZE_ALL - select ARM_AMBA - select ARM_ARCH_TIMER ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -44,6 +44,12 @@ - __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) - #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ - -+static inline bool arch_thp_swp_supported(void) -+{ -+ return !system_supports_mte(); -+} -+#define arch_thp_swp_supported arch_thp_swp_supported -+ - /* - * Outside of a few very special situations (e.g. hibernation), we always - * use broadcast TLB invalidation instructions, therefore a spurious page ---- a/include/linux/huge_mm.h -+++ b/include/linux/huge_mm.h -@@ -495,4 +495,16 @@ static inline unsigned long thp_size(str - return PAGE_SIZE << thp_order(page); - } - -+/* -+ * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to -+ * limitations in the implementation like arm64 MTE can override this to -+ * false -+ */ -+#ifndef arch_thp_swp_supported -+static inline bool arch_thp_swp_supported(void) -+{ -+ return true; -+} -+#endif -+ - #endif /* _LINUX_HUGE_MM_H */ ---- a/mm/swap_slots.c -+++ b/mm/swap_slots.c -@@ -308,7 +308,7 @@ swp_entry_t get_swap_page(struct page *p - entry.val = 0; - - if (PageTransHuge(page)) { -- if (IS_ENABLED(CONFIG_THP_SWAP)) -+ if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported()) - get_swap_pages(1, &entry, HPAGE_PMD_NR); - goto out; - } diff --git a/target/linux/rockchip/patches-5.15/105-rockchip-rock-pi-4.patch b/target/linux/rockchip/patches-5.15/105-rockchip-rock-pi-4.patch new file mode 100644 index 000000000..7bc671604 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/105-rockchip-rock-pi-4.patch @@ -0,0 +1,18 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb +@@ -42,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pi + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb diff --git a/target/linux/rockchip/patches-5.15/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.15/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch index 624b993de..d76563efc 100644 --- a/target/linux/rockchip/patches-5.15/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.15/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -96,6 +96,19 @@ +@@ -101,6 +101,19 @@ max-link-speed = <1>; num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; @@ -11,7 +11,7 @@ + #size-cells = <2>; + + pcie-eth@0,0 { -+ compatible = "realtek,r8168"; ++ compatible = "pci10ec,8168"; + reg = <0x000000 0 0 0 0>; + + realtek,led-data = <0x870>; diff --git a/target/linux/rockchip/patches-5.15/108-phy-rockchip-Support-PCIe-v3.patch b/target/linux/rockchip/patches-5.15/108-phy-rockchip-Support-PCIe-v3.patch deleted file mode 100644 index e0080d379..000000000 --- a/target/linux/rockchip/patches-5.15/108-phy-rockchip-Support-PCIe-v3.patch +++ /dev/null @@ -1,106 +0,0 @@ -From: Frank Wunderlich -To: linux-rockchip@lists.infradead.org -Cc: Frank Wunderlich , - Kishon Vijay Abraham I , - Vinod Koul , Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Johan Jonker , - Yifeng Zhao , - Peter Geis , - Michael Riesch , - Liang Chen , Simon Xue , - Shawn Lin , - linux-phy@lists.infradead.org, devicetree@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org -Subject: [PATCH v4 3/5] phy: rockchip: Support PCIe v3 -Date: Sun, 19 Jun 2022 10:26:03 +0200 [thread overview] -Message-ID: <20220619082605.7935-4-linux@fw-web.de> (raw) -In-Reply-To: <20220619082605.7935-1-linux@fw-web.de> - -From: Shawn Lin - -RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. -It use a dedicated PCIe-phy. Add support for this. - -Initial support by Shawn Lin, modifications by Peter Geis and Frank -Wunderlich. - -Add data-lanes property for splitting pcie-lanes across controllers. - -The data-lanes is an array where x=0 means lane is disabled and x > 0 -means controller x is assigned to phy lane. - -Signed-off-by: Shawn Lin -Suggested-by: Peter Geis -Signed-off-by: Frank Wunderlich ---- -v4: -- change u8 lane-map to u32 data-lanes - -v3: -- change dt-binding include -- change reset to devm_reset_control_get_optional_exclusive - exit on error and lower severity of message if unset -- fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe -- move bifurcation/lane-map support from PCIe to phy driver - -v2: -- move dt-bindings header into separate patch -- use BIT-macro -- make constants better readable -- use dev_err instead of pr_* -- change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) -- use exclusive variant of devm_reset_control_get{,_exclusive} -- fix semicolon.cocci warnings reported by kernel test robot - ---- -driver was taken from linux 5.10 based on in -https://github.com/JeffyCN/mirrors -which now has disappeared - -Update phy-rockchip-snps-pcie3.c - -Fix messages for data-lanes - -Update phy-rockchip-snps-pcie3.c - -Fix comment for data-lanes ---- - drivers/phy/rockchip/Kconfig | 9 + - drivers/phy/rockchip/Makefile | 1 + - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ - include/linux/phy/pcie.h | 12 + - 4 files changed, 339 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c - create mode 100644 include/linux/phy/pcie.h - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE - help - Enable this to support the Rockchip PCIe PHY. - -+config PHY_ROCKCHIP_SNPS_PCIE3 -+ tristate "Rockchip Snps PCIe3 PHY Driver" -+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST -+ depends on HAS_IOMEM -+ select GENERIC_PHY -+ select MFD_SYSCON -+ help -+ Enable this to support the Rockchip snps PCIe3 PHY. -+ - config PHY_ROCKCHIP_TYPEC - tristate "Rockchip TYPEC PHY Driver" - depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o -+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/target/linux/rockchip/patches-5.15/108-rockchip-rock-pi-4.patch b/target/linux/rockchip/patches-5.15/108-rockchip-rock-pi-4.patch deleted file mode 100644 index 24336dc57..000000000 --- a/target/linux/rockchip/patches-5.15/108-rockchip-rock-pi-4.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pi - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb diff --git a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch deleted file mode 100644 index 6513c17c3..000000000 --- a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch +++ /dev/null @@ -1,174 +0,0 @@ -From: Frank Wunderlich -To: linux-rockchip@lists.infradead.org -Cc: Frank Wunderlich , - Kishon Vijay Abraham I , - Vinod Koul , Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Johan Jonker , - Yifeng Zhao , - Peter Geis , - Michael Riesch , - Liang Chen , Simon Xue , - Shawn Lin , - linux-phy@lists.infradead.org, devicetree@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org -Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes -Date: Sun, 19 Jun 2022 10:26:04 +0200 [thread overview] -Message-ID: <20220619082605.7935-5-linux@fw-web.de> (raw) -In-Reply-To: <20220619082605.7935-1-linux@fw-web.de> - -From: Frank Wunderlich - -Add nodes to rk356x devicetree to support PCIe v3. - -Co-developed-by: Peter Geis -Signed-off-by: Frank Wunderlich ---- -v4: -- update pcie3 reg/ranges - -v3: -- fix from Peter: change bus-range and msi-map, msi-map needs - to start from 0x0 - -v2: -- change to compatible with soc-part -- change rockchip,bifurcation to vendor unspecific bifurcation ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ - 1 file changed, 122 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -42,6 +42,128 @@ - reg = <0x0 0xfe190200 0x0 0x20>; - }; - -+ pcie30_phy_grf: syscon@fdcb8000 { -+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfdcb8000 0x0 0x10000>; -+ }; -+ -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie3x1: pcie@fe270000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, -+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, -+ <&cru CLK_PCIE30X1_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, -+ <0 0 0 2 &pcie3x1_intc 1>, -+ <0 0 0 3 &pcie3x1_intc 2>, -+ <0 0 0 4 &pcie3x1_intc 3>; -+ linux,pci-domain = <1>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x1000 0x1000>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0400000 0x0 0x00400000>, -+ <0x0 0xfe270000 0x0 0x00010000>, -+ <0x3 0x7f000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X1_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane1 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe280000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, -+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, -+ <&cru CLK_PCIE30X2_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <2>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x2000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0800000 0x0 0x00400000>, -+ <0x0 0xfe280000 0x0 0x00010000>, -+ <0x3 0xbf000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X2_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane0 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.15/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch b/target/linux/rockchip/patches-5.15/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch new file mode 100644 index 000000000..216667683 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch @@ -0,0 +1,52 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus:green:lan"; ++}; ++ ++&spi0 { ++ max-freq = <48000000>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ }; ++}; ++ ++&sys_led { ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ label = "orangepi-r1-plus:red:sys"; ++}; ++ ++&sys_led_pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch b/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch deleted file mode 100644 index b0757624d..000000000 --- a/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch +++ /dev/null @@ -1,509 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -@@ -0,0 +1,495 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 EmbedFire -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3328-dram-nanopi2-timing.dtsi" -+#include "rk3328.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet1"; -+ compatible = "embedfire,doornet1", "rockchip,rk3328"; -+ -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ // mmc1 = &sdmmc; -+ // mmc0 = &emmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&reset_button_pin>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ vcc_rtl8153: vcc-rtl8153-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtl8153_en_drv>; -+ regulator-always-on; -+ regulator-name = "vcc_rtl8153"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ }; -+ -+ dmc: dmc { -+ compatible = "rockchip,rk3328-dmc"; -+ devfreq-events = <&dfi>; -+ center-supply = <&vdd_log>; -+ clocks = <&cru SCLK_DDRCLK>; -+ clock-names = "dmc_clk"; -+ operating-points-v2 = <&dmc_opp_table>; -+ ddr_timing = <&ddr_timing>; -+ upthreshold = <40>; -+ downdifferential = <20>; -+ auto-min-freq = <786000>; -+ auto-freq-en = <1>; -+ #cooling-cells = <2>; -+ status = "okay"; -+ -+ ddr_power_model: ddr_power_model { -+ compatible = "ddr_power_model"; -+ dynamic-power-coefficient = <120>; -+ static-power-coefficient = <200>; -+ ts = <32000 4700 (-80) 2>; -+ thermal-zone = "soc-thermal"; -+ }; -+ }; -+ -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ rockchip,leakage-voltage-sel = < -+ 1 10 0 -+ 11 254 1 -+ >; -+ nvmem-cells = <&logic_leakage>; -+ nvmem-cell-names = "ddr_leakage"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000>; -+ opp-microvolt-L0 = <1100000>; -+ opp-microvolt-L1 = <1075000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000>; -+ opp-microvolt-L0 = <1175000>; -+ opp-microvolt-L1 = <1150000>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ lan_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "doornet1:green:wan"; -+ }; -+ -+ wifi_enable: wifi_enable { -+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ label = "wifi-enable"; -+ }; -+ }; -+ -+ vcc_io_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_io_sdio"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ startup-delay-us = <2000>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&dfi { -+ status = "okay"; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io_33>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-delays-us = <0 1000000 50000>; -+ snps,reset-active-low; -+ tx_delay = <0x18>; -+ rx_delay = <0x24>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vdd_5v>; -+ vcc2-supply = <&vdd_5v>; -+ vcc3-supply = <&vdd_5v>; -+ vcc4-supply = <&vdd_5v>; -+ vcc5-supply = <&vcc_io_33>; -+ vcc6-supply = <&vdd_5v>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <1075000>; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <1225000>; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io_33: DCDC_REG4 { -+ regulator-name = "vcc_io_33"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+ usb { -+ rtl8153_en_drv: rtl8153-en-drv { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io_33>; -+ vccio1-supply = <&vcc_io_33>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io_sdio>; -+ vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io_33>; -+ vccio6-supply = <&vcc_io_33>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ button { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_pin: wifi_pin{ -+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sd { -+ sdio_vcc_pin: sdio-vcc-pin { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io_33>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Second port is for USB 3.0 */ -+ rtl8153: device@2 { -+ compatible = "usbbda,8153"; -+ reg = <2>; -+ -+ realtek,led-data = <0x87>; -+ }; -+}; -\ No newline at end of file diff --git a/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 000000000..3b31dff85 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,79 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021 Tianling Shen ++ */ ++ ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&dmc_opp_table { ++ opp-798000000 { ++ status = "disabled"; ++ }; ++ opp-840000000 { ++ status = "disabled"; ++ }; ++ opp-924000000 { ++ status = "disabled"; ++ }; ++ opp-1056000000 { ++ status = "disabled"; ++ }; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-id4f51.e91b", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus-lts:green:lan"; ++}; ++ ++&rtl8153 { ++ realtek,led-data = <0x78>; ++}; ++ ++&sys_led { ++ label = "orangepi-r1-plus-lts:red:sys"; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus-lts:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.15/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.15/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 000000000..61027fd21 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,64 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2021 Tianling Shen ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8521s>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8521s: ethernet-phy@3 { ++ compatible = "ethernet-phy-id0000.011a", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&lan_led { ++ label = "nanopi-r2c:green:lan"; ++}; ++ ++&rtl8153 { ++ realtek,led-data = <0x78>; ++}; ++ ++&sys_led { ++ label = "nanopi-r2c:red:sys"; ++}; ++ ++&wan_led { ++ label = "nanopi-r2c:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.15/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-5.15/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch similarity index 92% rename from target/linux/rockchip/patches-5.15/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch rename to target/linux/rockchip/patches-5.15/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch index 40c3f61ce..5c3fa8923 100644 --- a/target/linux/rockchip/patches-5.15/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch +++ b/target/linux/rockchip/patches-5.15/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch @@ -33,6 +33,21 @@ to status_led in accordance with the board schematics. 2 files changed, 397 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 479906f3a..5f6ffb496 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -3,6 +3,7 @@ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +new file mode 100644 +index 000000000..1eb7fd5f7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts @@ -0,0 +1,394 @@ @@ -430,3 +445,6 @@ to status_led in accordance with the board schematics. + realtek,led-data = <0x87>; + }; +}; +-- +2.34.1 + diff --git a/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch deleted file mode 100644 index 0eb5e6bde..000000000 --- a/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch +++ /dev/null @@ -1,768 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3399-doornet2.dtsi" -+ -+/ { -+ model = "EmbedFire DoorNet2 1GB"; -+ compatible = "embedfire,doornet2", "rockchip,rk3399"; -+ -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ -+ /delete-node/ display-subsystem; -+ -+ gpio-leds { -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ -+ /delete-node/ status; -+ -+ lan_led: led-lan { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ sys_led: led-sys { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "red:sys"; -+ default-state = "on"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+ -+ gpio-keys { -+ pinctrl-0 = <&reset_button_pin>; -+ -+ /delete-node/ power; -+ -+ reset { -+ debounce-interval = <50>; -+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ }; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ -+ pcie@0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ pcie-eth@0,0 { -+ compatible = "realtek,r8168"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x870>; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ /delete-node/ leds-gpio; -+ -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rockchip-key { -+ /delete-node/ power-key; -+ -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -@@ -0,0 +1,637 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc5v0_sys"; -+ vin-supply = <&vdd_5v>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_s3"; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vbus_typec: vbus-typec { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vbus_typec"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_key>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&leds_gpio>; -+ -+ status { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc3v3_s3>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 100000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c7>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "xin32k", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_cam: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_cam"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_touch"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmupll: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_pmupll"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <3000000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcca3v0_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <200000>; -+ i2c-scl-rising-time-ns = <150>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ status = "okay"; -+}; -+ -+&i2c7 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <2>; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-leds { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ power_key: power-key { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_reg_on_h: wifi-reg_on-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -+ diff --git a/target/linux/rockchip/patches-5.15/208-rockchip-rk3399-add-support-for-GuangMiao-G4C.patch b/target/linux/rockchip/patches-5.15/208-rockchip-rk3399-add-support-for-GuangMiao-G4C.patch deleted file mode 100644 index 592793802..000000000 --- a/target/linux/rockchip/patches-5.15/208-rockchip-rk3399-add-support-for-GuangMiao-G4C.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb diff --git a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 7157acd2a..8eea25381 100644 --- a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -48,22 +48,3 @@ Signed-off-by: wevsty gpu: gpu@ff9a0000 { compatible = "rockchip,rk3399-mali", "arm,mali-t860"; reg = <0x0 0xff9a0000 0x0 0x10000>; ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -211,6 +211,16 @@ - }; - }; - -+ rng: rng@fe388000 { -+ compatible = "rockchip,cryptov2-rng"; -+ reg = <0x0 0xfe388000 0x0 0x2000>; -+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; -+ clock-names = "clk_trng", "hclk_trng"; -+ resets = <&cru SRST_TRNG_NS>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - combphy0: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-5.15/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch b/target/linux/rockchip/patches-5.15/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch index ef06b0d59..12d519fd0 100644 --- a/target/linux/rockchip/patches-5.15/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch +++ b/target/linux/rockchip/patches-5.15/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch @@ -13,7 +13,7 @@ Signed-off-by: hmz007 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig -@@ -120,6 +120,18 @@ config ARM_TEGRA_DEVFREQ +@@ -120,6 +120,18 @@ config ARM_TEGRA20_DEVFREQ It reads ACTMON counters of memory controllers and adjusts the operating frequencies and voltages with OPP support. @@ -34,7 +34,7 @@ Signed-off-by: hmz007 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += gov +@@ -11,6 +11,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o diff --git a/target/linux/rockchip/patches-5.15/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.15/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch index f195f2aa3..722391f1d 100644 --- a/target/linux/rockchip/patches-5.15/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch +++ b/target/linux/rockchip/patches-5.15/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch @@ -20,11 +20,11 @@ Signed-off-by: hmz007 #include #include -+#include "rk3328-dram-nanopi2-timing.dtsi" ++#include "rk3328-dram-default-timing.dtsi" #include "rk3328.dtsi" / { -@@ -119,6 +120,72 @@ +@@ -114,6 +115,72 @@ regulator-boot-on; vin-supply = <&vdd_5v>; }; @@ -97,7 +97,7 @@ Signed-off-by: hmz007 }; &cpu0 { -@@ -137,6 +204,10 @@ +@@ -132,6 +199,10 @@ cpu-supply = <&vdd_arm>; }; @@ -108,7 +108,7 @@ Signed-off-by: hmz007 &display_subsystem { status = "disabled"; }; -@@ -206,6 +277,7 @@ +@@ -195,6 +266,7 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; @@ -116,7 +116,7 @@ Signed-off-by: hmz007 regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; -@@ -220,6 +292,7 @@ +@@ -209,6 +281,7 @@ regulator-name = "vdd_arm"; regulator-always-on; regulator-boot-on; diff --git a/target/linux/rockchip/patches-5.15/900-arm64-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.15/900-arm64-boot-add-dts-files.patch deleted file mode 100644 index 0da660510..000000000 --- a/target/linux/rockchip/patches-5.15/900-arm64-boot-add-dts-files.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -9,7 +9,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb -@@ -51,4 +54,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-station-p2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch deleted file mode 100644 index 9f0e480d9..000000000 --- a/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch +++ /dev/null @@ -1,193 +0,0 @@ -From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 19 Dec 2020 12:42:27 +0000 -Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices - -It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, -and for better performance. - -Signed-off-by: Tianling Shen -Co-authored-by: gzelvis ---- - .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++ - .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- - 2 files changed, 157 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi -@@ -0,0 +1,152 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * Copyright (c) 2020 Tianling Shen -+ * Copyright (c) 2020 gzelvis -+ */ -+ -+/ { -+ cluster0_opp: opp-table0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <800000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <925000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1000000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1125000>; -+ }; -+ opp06 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1225000>; -+ }; -+ opp07 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1275000>; -+ }; -+ }; -+ -+ cluster1_opp: opp-table1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <800000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <825000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <875000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <950000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1025000>; -+ }; -+ opp06 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1100000>; -+ }; -+ opp07 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1200000>; -+ }; -+ opp08 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <1250000>; -+ }; -+ opp09 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <1325000>; -+ }; -+ }; -+ -+ gpu_opp_table: opp-table2 { -+ compatible = "operating-points-v2"; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <297000000>; -+ opp-microvolt = <800000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <825000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <875000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <925000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1100000>; -+ }; -+ }; -+}; -+ -+&cpu_l0 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l1 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l2 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l3 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_b0 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&cpu_b1 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&gpu { -+ operating-points-v2 = <&gpu_opp_table>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -@@ -14,7 +14,7 @@ - /dts-v1/; - #include - #include "rk3399.dtsi" --#include "rk3399-opp.dtsi" -+#include "rk3399-nanopi4-opp.dtsi" - - / { - aliases { ---- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi -@@ -3,7 +3,7 @@ - /dts-v1/; - #include - #include "rk3399.dtsi" --#include "rk3399-opp.dtsi" -+#include "rk3399-nanopi4-opp.dtsi" - - / { - chosen { diff --git a/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch b/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch new file mode 100644 index 000000000..12cb932d1 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch @@ -0,0 +1,46 @@ +From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon, 18 Oct 2021 12:47:30 +0800 +Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz + +It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, +and for better performance. + +Co-development-by: gzelvis +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi +@@ -33,6 +33,14 @@ + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000>; + }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1225000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1275000>; ++ }; + }; + + cluster1_opp: opp-table1 { +@@ -72,6 +80,14 @@ + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp09 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1325000>; ++ }; + }; + + gpu_opp_table: opp-table2 { diff --git a/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch deleted file mode 100644 index 792028b29..000000000 --- a/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ /dev/null @@ -1,31 +0,0 @@ -From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 7 Jun 2021 15:45:37 +0800 -Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S - -NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which -stores the MAC address. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,15 @@ - status = "disabled"; - }; - -+&i2c2 { -+ eeprom@51 { -+ compatible = "microchip,24c02", "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ read-only; /* This holds our MAC */ -+ }; -+}; -+ - &i2c4 { - status = "disabled"; - }; diff --git a/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch b/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch deleted file mode 100644 index e430e6972..000000000 --- a/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 2c26cd88f13382b6965bbf5a8fc1c56384c6c3f6 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 11 May 2022 11:01:15 -0400 -Subject: [PATCH 01/51] arm64: dts: rockchip: add Quartz64-A fan pinctrl - -The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl -issues in the future by binding the pinctrl assignment for the gpio. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220511150117.113070-5-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -32,6 +32,8 @@ - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fan_en_h>; - #cooling-cells = <2>; - }; - -@@ -524,6 +526,12 @@ - }; - }; - -+ fan { -+ fan_en_h: fan-en-h { -+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - leds { - work_led_enable_h: work-led-enable-h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch b/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch deleted file mode 100644 index 87e3c6866..000000000 --- a/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch +++ /dev/null @@ -1,32 +0,0 @@ -From eda045fa2ca7b1567457048a389cda854a3a01e5 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 11 May 2022 11:01:16 -0400 -Subject: [PATCH 02/51] arm64: dts: rockchip: enable sdr-104 for sdmmc on - Quartz A - -Now that we have working io-domain support, we can enable higher date -rates on the sdmmc card. - -Before: -Timing buffered disk reads: 68 MB in 3.08 seconds = 22.07 MB/sec - -After: -Timing buffered disk reads: 188 MB in 3.02 seconds = 62.29 MB/sec - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220511150117.113070-6-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -596,6 +596,7 @@ - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; diff --git a/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch b/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch deleted file mode 100644 index 48ee02187..000000000 --- a/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 591f44f27342906ccd58eb7e63ec3ef5810bd7eb Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 11 May 2022 11:01:17 -0400 -Subject: [PATCH 03/51] arm64: dts: rockchip: enable sfc controller on Quartz64 - Model A - -Add the sfc controller binding for the Quartz64 Model A. This is not -populated by default, so leave it disabled. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -617,6 +617,22 @@ - status = "okay"; - }; - -+&sfc { -+ pinctrl-0 = <&fspi_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <24000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - /* spdif is exposed on con40 pin 18 */ - &spdif { - status = "okay"; diff --git a/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch b/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch deleted file mode 100644 index cea47965f..000000000 --- a/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 83729931332a2f15b0452f7dc8ea7a2e1b431842 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:30 -0400 -Subject: [PATCH 04/51] arm64: dts: rockchip: Add rk3568 PCIe2x1 controller - -The PCIe2x1 controller is common between the rk3568 and rk3566. It is a -single lane PCIe2 compliant controller. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220429123832.2376381-5-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -752,6 +752,56 @@ - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; - -+ pcie2x1: pcie@fe260000 { -+ compatible = "rockchip,rk3568-pcie"; -+ reg = <0x3 0xc0000000 0x0 0x00400000>, -+ <0x0 0xfe260000 0x0 0x00010000>, -+ <0x3 0x3f000000 0x0 0x01000000>; -+ reg-names = "dbi", "apb", "config"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, -+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, -+ <&cru CLK_PCIE20_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ linux,pci-domain = <0>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <2>; -+ msi-map = <0x0 &gic 0x0 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy2 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 -+ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; -+ resets = <&cru SRST_PCIE20_POWERUP>; -+ reset-names = "pipe"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ status = "disabled"; -+ -+ pcie_intc: legacy-interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch b/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch deleted file mode 100644 index 0980512db..000000000 --- a/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 5b1b78762d3fb4cf20aec4b22fbfab33960a6fdc Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:31 -0400 -Subject: [PATCH 05/51] arm64: dts: rockchip: Enable PCIe controller on - quartz64-a - -Add the nodes to enable the PCIe controller on the Quartz64 Model A -board. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220429123832.2376381-6-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++ - 1 file changed, 34 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -127,6 +127,18 @@ - vin-supply = <&vcc12v_dcin>; - }; - -+ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie_p"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; -+ }; -+ - vcc5v0_usb: vcc5v0_usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; -@@ -203,6 +215,10 @@ - status = "okay"; - }; - -+&combphy2 { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_cpu>; - }; -@@ -511,6 +527,14 @@ - }; - }; - -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie_p>; -+ status = "okay"; -+}; -+ - &pinctrl { - bt { - bt_enable_h: bt-enable-h { -@@ -542,6 +566,16 @@ - }; - }; - -+ pcie { -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch b/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch deleted file mode 100644 index e714d89bb..000000000 --- a/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 175ce006fe4ebf077322e5818127acfade41296f Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 11 May 2022 07:35:16 -0400 -Subject: [PATCH 06/51] arm64: dts: rockchip: add pine64 touch panel display to - rockpro64 - -The Pine64 touch panel is a panel consisting of the Feiyang fy07024di26a30d -panel with a Goodix gt911 touch screen. Add the device tree nodes to the -rockpro64 to permit attaching this display to the device. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220511113517.4172962-4-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 70 +++++++++++++++++-- - 1 file changed, 66 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -20,6 +20,15 @@ - stdout-path = "serial2:1500000n8"; - }; - -+ /* enable for panel backlight support */ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <5>; -+ pwms = <&pwm0 0 1000000 0>; -+ status = "disabled"; -+ }; -+ - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; -@@ -107,6 +116,14 @@ - }; - }; - -+ avdd: avdd-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "avdd"; -+ regulator-min-microvolt = <11000000>; -+ regulator-max-microvolt = <11000000>; -+ vin-supply = <&vcc3v3_s0>; -+ }; -+ - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -400,8 +417,6 @@ - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; -- regulator-always-on; -- regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { -@@ -490,8 +505,6 @@ - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; -- regulator-always-on; -- regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; -@@ -565,6 +578,19 @@ - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -+ -+ /* enable for pine64 touch screen support */ -+ touch: touchscreen@5d { -+ compatible = "goodix,gt911"; -+ reg = <0x5d>; -+ interrupt-parent = <&gpio4>; -+ interrupts = ; -+ AVDD28-supply = <&vcc3v0_touch>; -+ VDDIO-supply = <&vcc3v0_touch>; -+ irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; -+ }; - }; - - &i2s0 { -@@ -600,6 +626,42 @@ - gpio1830-supply = <&vcc_3v0>; - }; - -+/* enable for pine64 panel display support */ -+&mipi_dsi { -+ clock-master; -+ status = "disabled"; -+ -+ ports { -+ mipi_out: port@1 { -+ reg = <1>; -+ -+ mipi_out_panel: endpoint { -+ remote-endpoint = <&mipi_in_panel>; -+ }; -+ }; -+ }; -+ -+ mipi_panel: panel@0 { -+ compatible = "feiyang,fy07024di26a30d"; -+ reg = <0>; -+ avdd-supply = <&avdd>; -+ backlight = <&backlight>; -+ dvdd-supply = <&vcc3v3_s0>; -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ mipi_in_panel: endpoint { -+ remote-endpoint = <&mipi_out_panel>; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &pcie0 { - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; diff --git a/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch b/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch deleted file mode 100644 index 8105f0840..000000000 --- a/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch +++ /dev/null @@ -1,106 +0,0 @@ -From ec7cbc7e9111d3d655f25807e8511492359bb0fd Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:33 +0200 -Subject: [PATCH 07/51] arm64: dts: rockchip: rk356x: Add VOP2 nodes - -The VOP2 is the display output controller on the RK3568. Add the node -for it to the dtsi file along with the required display-subsystem node -and the iommu node. - -Signed-off-by: Sascha Hauer -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20220422072841.2206452-17-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++ - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++ - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++ - 3 files changed, 59 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -@@ -29,3 +29,7 @@ - extcon = <&usb2phy0>; - maximum-speed = "high-speed"; - }; -+ -+&vop { -+ compatible = "rockchip,rk3566-vop"; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -137,3 +137,7 @@ - phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - }; -+ -+&vop { -+ compatible = "rockchip,rk3568-vop"; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -129,6 +129,11 @@ - }; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; -@@ -632,6 +637,52 @@ - }; - }; - -+ vop: vop@fe040000 { -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ reg-names = "vop", "gamma-lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; -+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3568_PD_VO>; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp2: port@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fe043e00 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ status = "disabled"; -+ }; -+ - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch b/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch deleted file mode 100644 index eed468bdf..000000000 --- a/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 98180f4652c2c994cc2cc6088932086ee5c6e4d9 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:34 +0200 -Subject: [PATCH 08/51] arm64: dts: rockchip: rk356x: Add HDMI nodes - -Add support for the HDMI port found on RK3568. - -Signed-off-by: Sascha Hauer -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220422072841.2206452-18-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++++++++++++++ - 1 file changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -683,6 +683,38 @@ - status = "disabled"; - }; - -+ hdmi: hdmi@fe0a0000 { -+ compatible = "rockchip,rk3568-dw-hdmi"; -+ reg = <0x0 0xfe0a0000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&cru PCLK_HDMI_HOST>, -+ <&cru CLK_HDMI_SFR>, -+ <&cru CLK_HDMI_CEC>, -+ <&pmucru CLK_HDMI_REF>, -+ <&cru HCLK_VO>; -+ clock-names = "iahb", "isfr", "cec", "ref"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; -+ power-domains = <&power RK3568_PD_VO>; -+ reg-io-width = <4>; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch b/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch deleted file mode 100644 index c4316b5d1..000000000 --- a/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 7ccf41205a3deb146e7cc4fffb59fb1eb490a649 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:35 +0200 -Subject: [PATCH 09/51] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi - -This enabled the VOP2 display controller along with hdmi and the -required port routes which is enough to get a picture out of the -hdmi port of the board. - -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220422072841.2206452-19-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-evb1-v10.dts | 47 +++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include "rk3568.dtsi" - - / { -@@ -34,6 +35,17 @@ - regulator-max-microvolt = <12000000>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -209,6 +221,24 @@ - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -635,3 +665,20 @@ - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch b/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch deleted file mode 100644 index 3b4489aa9..000000000 --- a/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch +++ /dev/null @@ -1,91 +0,0 @@ -From d6eb924b01522decb987cb8c70d66c6b732a91e4 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Fri, 22 Apr 2022 09:28:36 +0200 -Subject: [PATCH 10/51] arm64: dts: rockchip: enable vop2 and hdmi tx on - quartz64a - -Enable the RK356x Video Output Processor (VOP) 2 on the Pine64 -Quartz64 Model A. - -Signed-off-by: Michael Riesch -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220422072841.2206452-20-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3566-quartz64-a.dts | 47 +++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3566.dtsi" - - / { -@@ -37,6 +38,17 @@ - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -280,6 +292,24 @@ - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda_0v9>; -+ avdd-1v8-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -782,3 +812,20 @@ - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch b/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch deleted file mode 100644 index 2896d4254..000000000 --- a/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 6ca0fc50d82e4ee0c1f5a2ba35cc692cfb4eeeec Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Thu, 26 May 2022 22:42:16 +0200 -Subject: [PATCH 13/51] arm64: dts: rockchip: adjust whitespace around '=' - -Fix whitespace coding style: use single space instead of tabs or -multiple spaces around '=' sign in property assignment. No functional -changes (same DTB). - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220526204218.832029-1-krzysztof.kozlowski@linaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 +++--- - arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 2 +- - 6 files changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -528,7 +528,7 @@ - i2c0: i2c@ff180000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; -- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; -+ clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; ---- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi -@@ -1084,7 +1084,7 @@ - - gmac { - rgmii_pins: rgmii-pins { -- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, -+ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PB0 1 &pcfg_pull_none_12ma>, -@@ -1102,7 +1102,7 @@ - }; - - rmii_pins: rmii-pins { -- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, -+ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PB0 1 &pcfg_pull_none_12ma>, -@@ -1257,7 +1257,7 @@ - - spdif { - spdif_tx: spdif-tx { -- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; -+ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts -@@ -55,7 +55,7 @@ - }; - - edp_panel: edp-panel { -- compatible ="lg,lp079qx1-sp0v"; -+ compatible = "lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - power-supply = <&vcc3v3_s0>; ---- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts -@@ -49,7 +49,7 @@ - sgtl5000_clk: sgtl5000-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; -- clock-frequency = <24576000>; -+ clock-frequency = <24576000>; - }; - - dc_12v: dc-12v { ---- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts -@@ -88,7 +88,7 @@ - }; - - edp_panel: edp-panel { -- compatible ="lg,lp079qx1-sp0v"; -+ compatible = "lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -347,7 +347,7 @@ - - pcie { - pcie_pwr: pcie-pwr { -- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - diff --git a/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch b/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch deleted file mode 100644 index 5f5d06dd4..000000000 --- a/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 7a32752d0d94ea613092aaa45db136626a55a1ab Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Sat, 11 Jun 2022 08:52:59 +0200 -Subject: [PATCH 14/51] arm64: dts: rockchip: Add HDMI audio nodes to rk356x - -This adds the i2s0 node and an hdmi-sound sound device to the -rk356x device tree. On the rk356[68], the i2s0 controller is -connected to HDMI audio. - -Tested-by: Michael Riesch -Tested-by: Peter Geis -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20220611065300.885212-2-frattaroli.nicolas@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 33 ++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -183,6 +183,22 @@ - }; - }; - -+ hdmi_sound: hdmi-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "HDMI"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ }; -+ }; -+ - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , -@@ -950,6 +966,23 @@ - #sound-dai-cells = <0>; - status = "disabled"; - }; -+ -+ i2s0_8ch: i2s@fe400000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe400000 0x0 0x1000>; -+ interrupts = ; -+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; -+ assigned-clock-rates = <1188000000>, <1188000000>; -+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 0>; -+ dma-names = "tx"; -+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; - - i2s1_8ch: i2s@fe410000 { - compatible = "rockchip,rk3568-i2s-tdm"; diff --git a/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch b/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch deleted file mode 100644 index 09369e3d8..000000000 --- a/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 2d330dcbbb5f3ce5ff55a2642aac4fb0d0e0a79e Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Sat, 11 Jun 2022 08:53:00 +0200 -Subject: [PATCH 15/51] arm64: dts: rockchip: Enable HDMI audio on Quartz64 A - -This enables the i2s0 controller and the hdmi-sound node on -the PINE64 Quartz64 Model A single-board computer. - -Tested-by: Peter Geis -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20220611065300.885212-3-frattaroli.nicolas@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -310,6 +310,10 @@ - }; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -540,6 +544,10 @@ - status = "okay"; - }; - -+&i2s0_8ch { -+ status = "okay"; -+}; -+ - &i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx diff --git a/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch deleted file mode 100644 index e7609aef6..000000000 --- a/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0a691542952f6706436e383f984c38b361c986ee Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 8 Jun 2022 18:11:49 +0200 -Subject: [PATCH 17/51] arm64: dts: rockchip: add RTC to BPI-R2 Pro - -Add devicetree node for hym8563 rtc to Bananapi R2 Pro board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220608161150.58919-3-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -389,6 +389,23 @@ - }; - }; - -+&i2c3 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "rtcic_32kout"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ - &i2c5 { - /* pin 3 (SDA) + 4 (SCL) of header con2 */ - status = "disabled"; -@@ -411,6 +428,12 @@ - }; - }; - -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int: pmic_int { - rockchip,pins = diff --git a/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch b/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch deleted file mode 100644 index 902ccaa14..000000000 --- a/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 032baf8d6c3493e0dcad2c780361faa7ac4f9dde Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Mon, 6 Jun 2022 19:07:59 +0200 -Subject: [PATCH 19/51] arm64: dts: rockchip: set display regulators to - always-on on BPI-R2-Pro - -The gpu power supply needs to stay always on until the issues with power- -domains not being regulator aware is resolved. Otherwise we run into -issues where the gpu-regulator gets shut down and we start getting mmu -faults. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220606170803.478082-2-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -215,6 +215,7 @@ - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; -+ regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; -@@ -264,6 +265,7 @@ - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; -+ regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - -@@ -359,6 +361,7 @@ - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; -+ regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - diff --git a/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch b/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch deleted file mode 100644 index 725f46306..000000000 --- a/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch +++ /dev/null @@ -1,90 +0,0 @@ -From ffb2555c106a820acc90d31c201d9879b4400623 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Mon, 6 Jun 2022 19:08:00 +0200 -Subject: [PATCH 20/51] arm64: dts: rockchip: enable vop2 and hdmi tx on - BPI-R2-Pro - -Enable the RK356x Video Output Processor (VOP) 2 on the -BananaPi R2 Pro board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220606170803.478082-3-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include "rk3568.dtsi" - - / { -@@ -54,6 +55,17 @@ - regulator-max-microvolt = <12000000>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; -@@ -174,6 +186,24 @@ - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -613,3 +643,20 @@ - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch deleted file mode 100644 index 65ca0a5f6..000000000 --- a/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 16fa52e8e2aae8debb651ac5f84a8d49499a301e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Mon, 6 Jun 2022 19:08:01 +0200 -Subject: [PATCH 21/51] arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro - -This enables the i2s0 controller and the hdmi-sound node on -the Bananapi R2 Pro single-board computer. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220606170803.478082-4-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -204,6 +204,10 @@ - }; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -444,6 +448,11 @@ - status = "disabled"; - }; - -+&i2s0_8ch { -+ /* hdmi sound */ -+ status = "okay"; -+}; -+ - &mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch b/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch deleted file mode 100644 index 7238aabbf..000000000 --- a/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 6976a5970ca53ac9dba444f4929528c3400152a5 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Mon, 6 Jun 2022 19:08:02 +0200 -Subject: [PATCH 22/51] arm64: dts: rockchip: configure thermal shutdown for - BPI-R2-Pro - -Add thermal shutdown configuration for use of GPU. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220606170803.478082-5-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -588,6 +588,8 @@ - }; - - &tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch deleted file mode 100644 index 8a8613708..000000000 --- a/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 92e9e89c7fe9178cb56dba0faf4b0fabbc19d97d Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Mon, 6 Jun 2022 19:08:03 +0200 -Subject: [PATCH 23/51] arm64: dts: rockchip: enable the gpu on BPI-R2-Pro - -Enable the GPU core on the Rockchip RK3568 BananaPi R2 Pro - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220606170803.478082-6-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -186,6 +186,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ - &hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; diff --git a/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch b/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch deleted file mode 100644 index 41a6973b8..000000000 --- a/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch +++ /dev/null @@ -1,31 +0,0 @@ -From fe99ab9113e33c825d1efb8d66f79e217e3108bf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= - -Date: Mon, 13 Jun 2022 00:31:57 +0200 -Subject: [PATCH 24/51] arm64: dts: rockchip: Add missing space around - regulator-name on rk3368-orion-r68 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add the missing space around the regulator-name property before the typo -spreads to other files. - -Signed-off-by: Niklas Söderlund -Link: https://lore.kernel.org/r/20220612223201.2740248-3-niklas.soderlund+renesas@ragnatech.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts -@@ -134,7 +134,7 @@ - - vccio_sd: vcc-io-sd-regulator { - compatible = "regulator-fixed"; -- regulator-name= "vccio_sd"; -+ regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; diff --git a/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch b/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch deleted file mode 100644 index f787cd228..000000000 --- a/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch +++ /dev/null @@ -1,245 +0,0 @@ -From 50373d43ecd2504c240f0048087bf0a1fd6e8b4c Mon Sep 17 00:00:00 2001 -From: Akash Gajjar -Date: Tue, 14 Jun 2022 08:48:56 +0200 -Subject: [PATCH 25/51] arm64: dts: rockchip: add ROCK Pi S DTS support - -ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, -- 256MB/512MB DDR3 RAM -- SD, NAND flash (optional on board 1/2/4/8Gb) -- 100MB ethernet, PoE (optional) -- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module -- USB2.0 Type-A HOST x1 -- USB3.0 Type-C OTG x1 -- 26-pin expansion header -- USB Type-C DC 5V Power Supply - -This patch enables -- Console -- NAND Flash -- SD Card - -Signed-off-by: Akash Gajjar -[sjoerd: Sort dt nodes, drop properties duplicated from dtsi] -Signed-off-by: Sjoerd Simons -Link: https://lore.kernel.org/r/20220614064858.1445817-3-sjoerd@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 201 ++++++++++++++++++ - 2 files changed, 202 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engi - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -0,0 +1,201 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2019 Akash Gajjar -+ * Copyright (c) 2019 Jagan Teki -+ */ -+ -+/dts-v1/; -+#include "rk3308.dtsi" -+ -+/ { -+ model = "Radxa ROCK Pi S"; -+ compatible = "radxa,rockpis", "rockchip,rk3308"; -+ -+ chosen { -+ stdout-path = "serial0:1500000n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; -+ -+ green-led { -+ default-state = "on"; -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ label = "rockpis:green:power"; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ blue-led { -+ default-state = "on"; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ label = "rockpis:blue:user"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-0 = <&wifi_enable_h>; -+ pinctrl-names = "default"; -+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ vcc_1v8: vcc-1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_io: vcc-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_io"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc_ddr: vcc-ddr { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_otg: vcc5v0-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&otg_vbus_drv>; -+ regulator-name = "vcc5v0_otg"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vdd_core: vdd-core { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm0 0 5000 1>; -+ pwm-supply = <&vcc5v0_sys>; -+ regulator-name = "vdd_core"; -+ regulator-min-microvolt = <827000>; -+ regulator-max-microvolt = <1340000>; -+ regulator-init-microvolt = <1015000>; -+ regulator-settling-time-up-us = <250>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_core>; -+}; -+ -+&emmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ non-removable; -+ vmmc-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtc_32k>; -+ -+ leds { -+ green_led_gio: green-led-gpio { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ heartbeat_led_gpio: heartbeat-led-gpio { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ otg_vbus_drv: otg-vbus-drv { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_host_wake: wifi-host-wake { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+}; -+ -+&pwm0 { -+ status = "okay"; -+ pinctrl-0 = <&pwm0_pin_pull_down>; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ max-frequency = <1000000>; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ cap-sd-highspeed; -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart4 { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch b/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch deleted file mode 100644 index 20b5695fe..000000000 --- a/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch +++ /dev/null @@ -1,100 +0,0 @@ -From a1bee6a014cf68d8298c370115f7036f0dcb4f59 Mon Sep 17 00:00:00 2001 -From: Sjoerd Simons -Date: Tue, 14 Jun 2022 08:48:57 +0200 -Subject: [PATCH 26/51] arm64: dts: rockchip: rock-pi-s add more peripherals - -This enables the following peripherals: -* Onboard ethernet support -* Bluetooth -* USB 2 port -* OTG port via type-c connector -* Hardware watchog - -Also add aliases for the mmc devices and the ethernet interface - -Signed-off-by: Sjoerd Simons -Link: https://lore.kernel.org/r/20220614064858.1445817-4-sjoerd@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 52 +++++++++++++++++++ - 1 file changed, 52 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -11,6 +11,12 @@ - model = "Radxa ROCK Pi S"; - compatible = "radxa,rockpis", "rockchip,rk3308"; - -+ aliases { -+ ethernet0 = &gmac; -+ mmc0 = &emmc; -+ mmc1 = &sdmmc; -+ }; -+ - chosen { - stdout-path = "serial0:1500000n8"; - }; -@@ -129,6 +135,15 @@ - status = "okay"; - }; - -+&gmac { -+ clock_in_out = "output"; -+ phy-supply = <&vcc_io>; -+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 50000 50000>; -+ status = "okay"; -+}; -+ - &i2c1 { - status = "okay"; - }; -@@ -192,10 +207,47 @@ - status = "okay"; - }; - -+&u2phy { -+ status = "okay"; -+ -+ u2phy_host: host-port { -+ phy-supply = <&vcc5v0_otg>; -+ status = "okay"; -+ }; -+ -+ u2phy_otg: otg-port { -+ phy-supply = <&vcc5v0_otg>; -+ status = "okay"; -+ }; -+}; -+ - &uart0 { - status = "okay"; - }; - - &uart4 { - status = "okay"; -+ -+ bluetooth { -+ compatible = "realtek,rtl8723bs-bt"; -+ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&usb_host_ehci { -+ status = "okay"; -+}; -+ -+&usb_host_ohci { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&wdt { -+ status = "okay"; - }; diff --git a/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch b/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch deleted file mode 100644 index 3df5bf71f..000000000 --- a/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch +++ /dev/null @@ -1,369 +0,0 @@ -From deefbffc188d3b0c9e08fa1ce31bb098839a9995 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 15 Jun 2022 17:53:19 -0700 -Subject: [PATCH 27/51] arm64: dts: rockchip: align gpio-key node names with - dtschema - -The node names should be generic and DT schema expects certain pattern -(e.g. with key/button/switch). - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220616005333.18491-26-krzysztof.kozlowski@linaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 2 +- - .../boot/dts/rockchip/rk3326-odroid-go2.dts | 32 +++++++++---------- - .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 2 +- - .../boot/dts/rockchip/rk3368-geekbox.dts | 2 +- - .../dts/rockchip/rk3368-orion-r68-meta.dts | 2 +- - .../boot/dts/rockchip/rk3368-px5-evb.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 2 +- - .../boot/dts/rockchip/rk3399-firefly.dts | 2 +- - .../dts/rockchip/rk3399-gru-chromebook.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-gru-kevin.dts | 2 +- - .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-khadas-edge.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 4 +-- - .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-orangepi.dts | 2 +- - .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 +-- - .../boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- - .../boot/dts/rockchip/rk3399-sapphire.dtsi | 2 +- - .../boot/dts/rockchip/rk3566-pinenote.dtsi | 2 +- - 21 files changed, 38 insertions(+), 38 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts -@@ -75,7 +75,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -@@ -71,82 +71,82 @@ - * |------------------------------------------------| - */ - -- sw1 { -+ button-sw1 { - gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; - label = "DPAD-UP"; - linux,code = ; - }; -- sw2 { -+ button-sw2 { - gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; - label = "DPAD-DOWN"; - linux,code = ; - }; -- sw3 { -+ button-sw3 { - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - label = "DPAD-LEFT"; - linux,code = ; - }; -- sw4 { -+ button-sw4 { - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - label = "DPAD-RIGHT"; - linux,code = ; - }; -- sw5 { -+ button-sw5 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; - label = "BTN-A"; - linux,code = ; - }; -- sw6 { -+ button-sw6 { - gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - label = "BTN-B"; - linux,code = ; - }; -- sw7 { -+ button-sw7 { - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - label = "BTN-Y"; - linux,code = ; - }; -- sw8 { -+ button-sw8 { - gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; - label = "BTN-X"; - linux,code = ; - }; -- sw9 { -+ button-sw9 { - gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; - label = "F1"; - linux,code = ; - }; -- sw10 { -+ button-sw10 { - gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; - label = "F2"; - linux,code = ; - }; -- sw11 { -+ button-sw11 { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - label = "F3"; - linux,code = ; - }; -- sw12 { -+ button-sw12 { - gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; - label = "F4"; - linux,code = ; - }; -- sw13 { -+ button-sw13 { - gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; - label = "F5"; - linux,code = ; - }; -- sw14 { -+ button-sw14 { - gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; - label = "F6"; - linux,code = ; - }; -- sw15 { -+ button-sw15 { - gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; - label = "TOP-LEFT"; - linux,code = ; - }; -- sw16 { -+ button-sw16 { - gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; - label = "TOP-RIGHT"; - linux,code = ; ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -34,7 +34,7 @@ - pinctrl-0 = <&reset_button_pin>; - pinctrl-names = "default"; - -- reset { -+ key-reset { - label = "reset"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - linux,code = ; ---- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi -@@ -76,7 +76,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - wakeup-source; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts -@@ -43,7 +43,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; ---- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts -@@ -44,7 +44,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - label = "GPIO Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts -@@ -30,7 +30,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; ---- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts -@@ -37,7 +37,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - -- power { -+ key-power { - wakeup-source; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts -@@ -87,7 +87,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi -@@ -206,7 +206,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - -- wake_on_bt: wake-on-bt { -+ wake_on_bt: key-wake-on-bt { - label = "Wake-on-Bluetooth"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - linux,code = ; ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts -@@ -92,7 +92,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; - -- pen-insert { -+ switch-pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -@@ -183,7 +183,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - -- pen-insert { -+ switch-pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ---- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi -@@ -136,7 +136,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -46,9 +46,9 @@ - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - -- /delete-node/ power; -+ /delete-node/ key-power; - -- reset { -+ key-reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -@@ -111,7 +111,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -@@ -78,7 +78,7 @@ - compatible = "gpio-keys"; - autorepeat; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts -@@ -76,7 +76,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&lidbtn_pin>; - -- lid { -+ switch-lid { - debounce-interval = <20>; - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; - label = "Lid"; -@@ -92,7 +92,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn_pin>; - -- power { -+ key-power { - debounce-interval = <20>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -@@ -54,7 +54,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -42,7 +42,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi -@@ -53,7 +53,7 @@ - compatible = "gpio-keys"; - autorepeat; - -- power { -+ key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; ---- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi -@@ -49,7 +49,7 @@ - pinctrl-0 = <&hall_int_l>; - pinctrl-names = "default"; - -- cover { -+ switch-cover { - label = "cover"; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; - linux,input-type = ; diff --git a/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch b/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch deleted file mode 100644 index ed38b3cc6..000000000 --- a/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch +++ /dev/null @@ -1,40 +0,0 @@ -From ff2aa1ec6f09917d03959bc2250eccf5f9c24f0c Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Wed, 15 Jun 2022 01:03:53 +0200 -Subject: [PATCH 28/51] arm64: dts: rockchip: enable hdmi tx audio on - rk3568-evb1-v10 - -Enable the I2S0 controller and the hdmi-sound node on the Rockchip -RK3568 EVB1. - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220614230354.3756364-1-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -@@ -239,6 +239,10 @@ - }; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -496,6 +500,10 @@ - }; - }; - -+&i2s0_8ch { -+ status = "okay"; -+}; -+ - &i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; diff --git a/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch b/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch deleted file mode 100644 index d8ce2ae08..000000000 --- a/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch +++ /dev/null @@ -1,39 +0,0 @@ -From f33757d7c1a25febc85546f9a398e23ad449de05 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Wed, 15 Jun 2022 01:03:54 +0200 -Subject: [PATCH 29/51] arm64: dts: rockchip: enable hdmi tx audio on rock-3a - -Enable the I2S0 controller and the hdmi-sound node on the Radxa -ROCK3 Model A. - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220614230354.3756364-2-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -200,6 +200,10 @@ - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -441,6 +445,10 @@ - }; - - &i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s0_8ch { - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch deleted file mode 100644 index 797c4538b..000000000 --- a/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch +++ /dev/null @@ -1,72 +0,0 @@ -From a502eafcfbed31cb01e71e23553f9348a08c3cfe Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 10 Jun 2022 19:05:41 +0200 -Subject: [PATCH 30/51] arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro - board - -Add Device Tree node for mt7531 switch connected to gmac0. - -Signed-off-by: Frank Wunderlich -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -458,6 +458,54 @@ - status = "okay"; - }; - -+&mdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch@0 { -+ compatible = "mediatek,mt7531"; -+ reg = <0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan0"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan1"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan3"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "rgmii"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch deleted file mode 100644 index ba2983041..000000000 --- a/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch +++ /dev/null @@ -1,87 +0,0 @@ -From fd0e3d705a8ee61e822c9f4e74c34567a9a31335 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 10 Jun 2022 19:05:37 +0200 -Subject: [PATCH 31/51] net: dsa: mt7530: rework mt7530_hw_vlan_{add,del} - -Rework vlan_add/vlan_del functions in preparation for dynamic cpu port. - -Currently BIT(MT7530_CPU_PORT) is added to new_members, even though -mt7530_port_vlan_add() will be called on the CPU port too. - -Let DSA core decide when to call port_vlan_add for the CPU port, rather -than doing it implicitly. - -We can do autonomous forwarding in a certain VLAN, but not add br0 to that -VLAN and avoid flooding the CPU with those packets, if software knows it -doesn't need to process them. - -Suggested-by: Vladimir Oltean -Signed-off-by: Frank Wunderlich -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 30 ++++++++++++------------------ - 1 file changed, 12 insertions(+), 18 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1527,11 +1527,11 @@ static void - mt7530_hw_vlan_add(struct mt7530_priv *priv, - struct mt7530_hw_vlan_entry *entry) - { -+ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); - u8 new_members; - u32 val; - -- new_members = entry->old_members | BIT(entry->port) | -- BIT(MT7530_CPU_PORT); -+ new_members = entry->old_members | BIT(entry->port); - - /* Validate the entry with independent learning, create egress tag per - * VLAN and joining the port as one of the port members. -@@ -1542,22 +1542,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p - - /* Decide whether adding tag or not for those outgoing packets from the - * port inside the VLAN. -- */ -- val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : -- MT7530_VLAN_EGRESS_TAG; -- mt7530_rmw(priv, MT7530_VAWD2, -- ETAG_CTRL_P_MASK(entry->port), -- ETAG_CTRL_P(entry->port, val)); -- -- /* CPU port is always taken as a tagged port for serving more than one -+ * CPU port is always taken as a tagged port for serving more than one - * VLANs across and also being applied with egress type stack mode for - * that VLAN tags would be appended after hardware special tag used as - * DSA tag. - */ -+ if (dsa_port_is_cpu(dp)) -+ val = MT7530_VLAN_EGRESS_STACK; -+ else if (entry->untagged) -+ val = MT7530_VLAN_EGRESS_UNTAG; -+ else -+ val = MT7530_VLAN_EGRESS_TAG; - mt7530_rmw(priv, MT7530_VAWD2, -- ETAG_CTRL_P_MASK(MT7530_CPU_PORT), -- ETAG_CTRL_P(MT7530_CPU_PORT, -- MT7530_VLAN_EGRESS_STACK)); -+ ETAG_CTRL_P_MASK(entry->port), -+ ETAG_CTRL_P(entry->port, val)); - } - - static void -@@ -1576,11 +1574,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p - return; - } - -- /* If certain member apart from CPU port is still alive in the VLAN, -- * the entry would be kept valid. Otherwise, the entry is got to be -- * disabled. -- */ -- if (new_members && new_members != BIT(MT7530_CPU_PORT)) { -+ if (new_members) { - val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | - VLAN_VALID; - mt7530_write(priv, MT7530_VAWD1, val); diff --git a/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch b/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch deleted file mode 100644 index 0ce93ecd6..000000000 --- a/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 65046fea942259fb22ae9cdfb86971d8c4e4237b Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 10 Jun 2022 19:05:38 +0200 -Subject: [PATCH 32/51] net: dsa: mt7530: rework mt753[01]_setup - -Enumerate available cpu-ports instead of using hardcoded constant. - -Suggested-by: Vladimir Oltean -Signed-off-by: Frank Wunderlich -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 25 +++++++++++++++++++++---- - 1 file changed, 21 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2092,11 +2092,12 @@ static int - mt7530_setup(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; -+ struct device_node *dn = NULL; - struct device_node *phy_node; - struct device_node *mac_np; - struct mt7530_dummy_poll p; - phy_interface_t interface; -- struct device_node *dn; -+ struct dsa_port *cpu_dp; - u32 id, val; - int ret, i; - -@@ -2104,7 +2105,19 @@ mt7530_setup(struct dsa_switch *ds) - * controller also is the container for two GMACs nodes representing - * as two netdev instances. - */ -- dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; -+ dsa_switch_for_each_cpu_port(cpu_dp, ds) { -+ dn = cpu_dp->master->dev.of_node->parent; -+ /* It doesn't matter which CPU port is found first, -+ * their masters should share the same parent OF node -+ */ -+ break; -+ } -+ -+ if (!dn) { -+ dev_err(ds->dev, "parent OF node of DSA master not found"); -+ return -EINVAL; -+ } -+ - ds->assisted_learning_on_cpu_port = true; - ds->mtu_enforcement_ingress = true; - -@@ -2266,6 +2279,7 @@ mt7531_setup(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; - struct mt7530_dummy_poll p; -+ struct dsa_port *cpu_dp; - u32 val, id; - int ret, i; - -@@ -2338,8 +2352,11 @@ mt7531_setup(struct dsa_switch *ds) - CORE_PLL_GROUP4, val); - - /* BPDU to CPU port */ -- mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, -- BIT(MT7530_CPU_PORT)); -+ dsa_switch_for_each_cpu_port(cpu_dp, ds) { -+ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, -+ BIT(cpu_dp->index)); -+ break; -+ } - mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); - diff --git a/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch deleted file mode 100644 index d06f4703f..000000000 --- a/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 28650c65d8ca16a1b607a06fd0bce67371143069 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 10 Jun 2022 19:05:39 +0200 -Subject: [PATCH 33/51] net: dsa: mt7530: get cpu-port via dp->cpu_dp instead - of constant - -Replace last occurences of hardcoded cpu-port by cpu_dp member of -dsa_port struct. - -Now the constant can be dropped. - -Suggested-by: Vladimir Oltean -Signed-off-by: Frank Wunderlich -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 27 ++++++++++++++++++++------- - drivers/net/dsa/mt7530.h | 1 - - 2 files changed, 20 insertions(+), 8 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1038,6 +1038,7 @@ static int - mt7530_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) - { -+ struct dsa_port *dp = dsa_to_port(ds, port); - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1046,7 +1047,11 @@ mt7530_port_enable(struct dsa_switch *ds - * restore the port matrix if the port is the member of a certain - * bridge. - */ -- priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); -+ if (dsa_port_is_user(dp)) { -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ -+ priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); -+ } - priv->ports[port].enable = true; - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, - priv->ports[port].pm); -@@ -1195,7 +1200,8 @@ mt7530_port_bridge_join(struct dsa_switc - struct netlink_ext_ack *extack) - { - struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; -- u32 port_bitmap = BIT(MT7530_CPU_PORT); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ u32 port_bitmap = BIT(cpu_dp->index); - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1272,9 +1278,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ - * the CPU port get out of VLAN filtering mode. - */ - if (all_user_ports_removed) { -- mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), -+ struct dsa_port *dp = dsa_to_port(ds, port); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ -+ mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), - PCR_MATRIX(dsa_user_ports(priv->ds))); -- mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG -+ mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG - | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); - } - } -@@ -1312,6 +1321,7 @@ mt7530_port_bridge_leave(struct dsa_swit - struct dsa_bridge bridge) - { - struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; -+ struct dsa_port *cpu_dp = dp->cpu_dp; - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1340,8 +1350,8 @@ mt7530_port_bridge_leave(struct dsa_swit - */ - if (priv->ports[port].enable) - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, -- PCR_MATRIX(BIT(MT7530_CPU_PORT))); -- priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); -+ PCR_MATRIX(BIT(cpu_dp->index))); -+ priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); - - /* When a port is removed from the bridge, the port would be set up - * back to the default as is at initial boot which is a VLAN-unaware -@@ -1508,6 +1518,9 @@ static int - mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, - struct netlink_ext_ack *extack) - { -+ struct dsa_port *dp = dsa_to_port(ds, port); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ - if (vlan_filtering) { - /* The port is being kept as VLAN-unaware port when bridge is - * set up with vlan_filtering not being set, Otherwise, the -@@ -1515,7 +1528,7 @@ mt7530_port_vlan_filtering(struct dsa_sw - * for becoming a VLAN-aware port. - */ - mt7530_port_set_vlan_aware(ds, port); -- mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); -+ mt7530_port_set_vlan_aware(ds, cpu_dp->index); - } else { - mt7530_port_set_vlan_unaware(ds, port); - } ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -8,7 +8,6 @@ - - #define MT7530_NUM_PORTS 7 - #define MT7530_NUM_PHYS 5 --#define MT7530_CPU_PORT 6 - #define MT7530_NUM_FDB_RECORDS 2048 - #define MT7530_ALL_MEMBERS 0xff - diff --git a/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch b/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch deleted file mode 100644 index 47cb28b7b..000000000 --- a/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 83aef06999a8ee66444ef52986834780f5e4f94a Mon Sep 17 00:00:00 2001 -From: Ren Zhijie -Date: Sat, 7 May 2022 18:09:10 +0800 -Subject: [PATCH 34/51] drm/rockchip: Fix Kconfig dependencies for display-port - encoders - -The DP-helper module has been replaced by the display-helper module. -So the driver have to select it. - -Reported-by: Hulk Robot -Fixes: 1e0f66420b13("drm/display: Introduce a DRM display-helper module") -Signed-off-by: Ren Zhijie -Reviewed-by: Andy Yan -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220507100910.93705-1-renzhijie2@huawei.com ---- - drivers/gpu/drm/rockchip/Kconfig | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -2,7 +2,6 @@ - config DRM_ROCKCHIP - tristate "DRM Support for Rockchip" - depends on DRM && ROCKCHIP_IOMMU -- select DRM_DISPLAY_HELPER if ROCKCHIP_ANALOGIX_DP - select DRM_GEM_CMA_HELPER - select DRM_KMS_HELPER - select DRM_PANEL -@@ -38,6 +37,7 @@ config ROCKCHIP_VOP2 - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" - depends on ROCKCHIP_VOP -+ select DRM_DISPLAY_HELPER - select DRM_DISPLAY_DP_HELPER - help - This selects support for Rockchip SoC specific extensions -@@ -47,6 +47,8 @@ config ROCKCHIP_ANALOGIX_DP - config ROCKCHIP_CDN_DP - bool "Rockchip cdn DP" - depends on EXTCON=y || (EXTCON=m && DRM_ROCKCHIP=m) -+ select DRM_DISPLAY_HELPER -+ select DRM_DISPLAY_DP_HELPER - help - This selects support for Rockchip SoC specific extensions - for the cdn DP driver. If you want to enable Dp on diff --git a/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch b/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch deleted file mode 100644 index 86923bcc3..000000000 --- a/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 9226222a72f2a336495728d24cd9bff7685f1cbe Mon Sep 17 00:00:00 2001 -From: Yang Li -Date: Fri, 6 May 2022 07:26:59 +0800 -Subject: [PATCH 35/51] drm/rockchip: remove unneeded semicolon from vop2 - driver - -Eliminate the following coccicheck warning: -./drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:1476:2-3: Unneeded -semicolon - -Reported-by: Abaci Robot -Signed-off-by: Yang Li -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220505232659.4405-1-yang.lee@linux.alibaba.com ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -1473,7 +1473,7 @@ static void rk3568_set_intf_mux(struct v - default: - drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); - return; -- }; -+ } - - dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; - diff --git a/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch b/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch deleted file mode 100644 index 0b3925a69..000000000 --- a/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch +++ /dev/null @@ -1,26 +0,0 @@ -From c130c07b62dd4cc18c9b10ab65da6c6a5d41fcfa Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Thu, 5 May 2022 12:10:44 +0100 -Subject: [PATCH 36/51] drm/rockchip: Fix spelling mistake "aligened" -> - "aligned" - -There is a spelling mistake in a drm_err message. Fix it. - -Signed-off-by: Colin Ian King -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220505111044.374174-1-colin.i.king@gmail.com ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -1202,7 +1202,7 @@ static void vop2_plane_atomic_update(str - */ - stride = (fb->pitches[0] << 3) / bpp; - if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) -- drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n", -+ drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", - vp->id, win->data->name, stride); - - rb_swap = vop2_afbc_rb_swap(fb->format->format); diff --git a/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch b/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch deleted file mode 100644 index 95eb69b22..000000000 --- a/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch +++ /dev/null @@ -1,569 +0,0 @@ -From 38666f6a53492c98e2224bb292b89671bc2ed866 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= -Date: Tue, 14 Jun 2022 12:02:45 +0300 -Subject: [PATCH 38/51] drm: Drop drm_edid.h from drm_crtc.h -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -drm_crtc.h has no need for drm_edid.h, so don't include it. -Avoids useless rebuilds of the entire universe when -touching drm_edid.h. - -Quite a few placs do currently depend on drm_edid.h without -actually including it directly. All of those need to be fixed -up. - -v2: Fix up i915 and msm some more -v3: Fix alphabetical ordering (Sam) - -Signed-off-by: Ville Syrjälä -Link: https://patchwork.freedesktop.org/patch/msgid/20220614090245.30283-1-ville.syrjala@linux.intel.com -Acked-by: Sam Ravnborg -Acked-by: Jani Nikula ---- - drivers/gpu/drm/arm/malidp_mw.c | 1 + - drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 1 + - drivers/gpu/drm/ast/ast_mode.c | 1 + - drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1 + - drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 1 + - drivers/gpu/drm/bridge/lontium-lt8912b.c | 1 + - drivers/gpu/drm/bridge/parade-ps8640.c | 1 + - drivers/gpu/drm/bridge/simple-bridge.c | 1 + - drivers/gpu/drm/bridge/ti-tfp410.c | 1 + - drivers/gpu/drm/display/drm_dp_helper.c | 1 + - drivers/gpu/drm/display/drm_dp_mst_topology.c | 1 + - drivers/gpu/drm/drm_client_modeset.c | 1 + - drivers/gpu/drm/drm_kms_helper_common.c | 1 + - drivers/gpu/drm/drm_modes.c | 1 + - drivers/gpu/drm/exynos/exynos_mixer.c | 1 + - drivers/gpu/drm/gma500/cdv_intel_dp.c | 1 + - drivers/gpu/drm/gma500/oaktrail_hdmi.c | 1 + - drivers/gpu/drm/gma500/oaktrail_lvds.c | 1 + - drivers/gpu/drm/gma500/psb_intel_modes.c | 2 ++ - drivers/gpu/drm/gud/gud_connector.c | 1 + - drivers/gpu/drm/i915/display/intel_bios.c | 1 + - drivers/gpu/drm/i915/display/intel_dp.c | 1 + - drivers/gpu/drm/i915/display/intel_lspcon.c | 1 + - drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++ - drivers/gpu/drm/imx/imx-ldb.c | 1 + - drivers/gpu/drm/imx/imx-tve.c | 1 + - drivers/gpu/drm/imx/parallel-display.c | 1 + - drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 2 ++ - drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 1 + - drivers/gpu/drm/omapdrm/dss/hdmi4.c | 1 + - drivers/gpu/drm/omapdrm/dss/hdmi5.c | 1 + - drivers/gpu/drm/panel/panel-edp.c | 1 + - drivers/gpu/drm/panel/panel-simple.c | 1 + - drivers/gpu/drm/qxl/qxl_display.c | 1 + - drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 1 + - drivers/gpu/drm/rockchip/rk3066_hdmi.c | 1 + - drivers/gpu/drm/solomon/ssd130x.c | 1 + - drivers/gpu/drm/stm/ltdc.c | 1 + - drivers/gpu/drm/tiny/arcpgu.c | 1 + - drivers/gpu/drm/tiny/bochs.c | 1 + - drivers/gpu/drm/tiny/cirrus.c | 1 + - drivers/gpu/drm/tiny/gm12u320.c | 1 + - drivers/gpu/drm/udl/udl_connector.c | 1 + - drivers/gpu/drm/vboxvideo/vbox_mode.c | 1 + - drivers/gpu/drm/virtio/virtgpu_display.c | 1 + - drivers/gpu/drm/virtio/virtgpu_vq.c | 2 ++ - drivers/gpu/drm/vkms/vkms_output.c | 1 + - drivers/gpu/drm/vkms/vkms_writeback.c | 1 + - include/drm/drm_crtc.h | 1 - - 49 files changed, 52 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/arm/malidp_mw.c -+++ b/drivers/gpu/drm/arm/malidp_mw.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c -+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_out.c -@@ -4,6 +4,7 @@ - #include - #include - #include -+#include - #include - - #include "aspeed_gfx.h" ---- a/drivers/gpu/drm/ast/ast_mode.c -+++ b/drivers/gpu/drm/ast/ast_mode.c -@@ -36,6 +36,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c -+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c -@@ -43,6 +43,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/bridge/lontium-lt8912b.c -+++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c -@@ -11,6 +11,7 @@ - - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/bridge/parade-ps8640.c -+++ b/drivers/gpu/drm/bridge/parade-ps8640.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/bridge/simple-bridge.c -+++ b/drivers/gpu/drm/bridge/simple-bridge.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/bridge/ti-tfp410.c -+++ b/drivers/gpu/drm/bridge/ti-tfp410.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/display/drm_dp_helper.c -+++ b/drivers/gpu/drm/display/drm_dp_helper.c -@@ -32,6 +32,7 @@ - - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/display/drm_dp_mst_topology.c -+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c -@@ -42,6 +42,7 @@ - #include - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/drm_client_modeset.c -+++ b/drivers/gpu/drm/drm_client_modeset.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/drm_kms_helper_common.c -+++ b/drivers/gpu/drm/drm_kms_helper_common.c -@@ -27,6 +27,7 @@ - - #include - -+#include - #include - - #include "drm_crtc_helper_internal.h" ---- a/drivers/gpu/drm/drm_modes.c -+++ b/drivers/gpu/drm/drm_modes.c -@@ -41,6 +41,7 @@ - - #include - #include -+#include - #include - #include - ---- a/drivers/gpu/drm/exynos/exynos_mixer.c -+++ b/drivers/gpu/drm/exynos/exynos_mixer.c -@@ -25,6 +25,7 @@ - #include - #include - -+#include - #include - #include - #include ---- a/drivers/gpu/drm/gma500/cdv_intel_dp.c -+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - #include - - #include "gma_display.h" ---- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c -+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c -@@ -27,6 +27,7 @@ - #include - - #include -+#include - #include - - #include "psb_drv.h" ---- a/drivers/gpu/drm/gma500/oaktrail_lvds.c -+++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c -@@ -13,6 +13,7 @@ - - #include - -+#include - #include - - #include "intel_bios.h" ---- a/drivers/gpu/drm/gma500/psb_intel_modes.c -+++ b/drivers/gpu/drm/gma500/psb_intel_modes.c -@@ -7,6 +7,8 @@ - - #include - -+#include -+ - #include "psb_intel_drv.h" - - /** ---- a/drivers/gpu/drm/gud/gud_connector.c -+++ b/drivers/gpu/drm/gud/gud_connector.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/i915/display/intel_bios.c -+++ b/drivers/gpu/drm/i915/display/intel_bios.c -@@ -25,6 +25,7 @@ - * - */ - -+#include - #include - #include - ---- a/drivers/gpu/drm/i915/display/intel_dp.c -+++ b/drivers/gpu/drm/i915/display/intel_dp.c -@@ -40,6 +40,7 @@ - #include - #include - #include -+#include - #include - - #include "g4x_dp.h" ---- a/drivers/gpu/drm/i915/display/intel_lspcon.c -+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - - #include "intel_de.h" - #include "intel_display_types.h" ---- a/drivers/gpu/drm/i915/display/intel_opregion.c -+++ b/drivers/gpu/drm/i915/display/intel_opregion.c -@@ -30,6 +30,8 @@ - #include - #include - -+#include -+ - #include "i915_drv.h" - #include "intel_acpi.h" - #include "intel_backlight.h" ---- a/drivers/gpu/drm/imx/imx-ldb.c -+++ b/drivers/gpu/drm/imx/imx-ldb.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/drivers/gpu/drm/imx/imx-tve.c -+++ b/drivers/gpu/drm/imx/imx-tve.c -@@ -18,6 +18,7 @@ - #include