mirror of
https://github.com/coolsnowwolf/lede.git
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127 lines
3.4 KiB
Diff
127 lines
3.4 KiB
Diff
From 217fbbc122663c5a3dac752cebef44fb3e0cc179 Mon Sep 17 00:00:00 2001
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From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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Date: Fri, 10 Nov 2023 14:49:35 +0530
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Subject: [PATCH] firmware: qcom_scm: ipq5332: add msa lock/unlock
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support
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IPQ5332 user pd remoteproc firmwares need to be locked
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with MSA(modem secure access) features. This patch add
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support to lock/unlock MSA features.
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Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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---
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drivers/firmware/qcom_scm.c | 78 ++++++++++++++++++++++++++
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drivers/firmware/qcom_scm.h | 2 +
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include/linux/firmware/qcom/qcom_scm.h | 2 +
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3 files changed, 82 insertions(+)
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--- a/drivers/firmware/qcom_scm.c
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+++ b/drivers/firmware/qcom_scm.c
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@@ -712,6 +712,84 @@ bool qcom_scm_pas_supported(u32 peripher
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}
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EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
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+/**
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+ * qcom_scm_msa_lock() - Lock given peripheral firmware region as MSA
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+ *
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+ * @peripheral: peripheral id
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+ *
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+ * Return 0 on success.
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+ */
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+int qcom_scm_msa_lock(u32 peripheral)
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+{
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+ int ret;
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+ struct qcom_scm_desc desc = {
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+ .svc = QCOM_SCM_SVC_PIL,
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+ .cmd = QCOM_SCM_MSA_LOCK,
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+ .arginfo = QCOM_SCM_ARGS(1),
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+ .args[0] = peripheral,
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+ .owner = ARM_SMCCC_OWNER_SIP,
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+ };
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+ struct qcom_scm_res res;
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+
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+ if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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+ QCOM_SCM_MSA_LOCK))
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+ return 0;
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+
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+ ret = qcom_scm_clk_enable();
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+ if (ret)
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+ return ret;
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+
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+ ret = qcom_scm_bw_enable();
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+ if (ret)
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+ return ret;
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+
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+ ret = qcom_scm_call(__scm->dev, &desc, &res);
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+ qcom_scm_bw_disable();
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+ qcom_scm_clk_disable();
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+
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+ return ret ? : res.result[0];
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+}
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+EXPORT_SYMBOL_GPL(qcom_scm_msa_lock);
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+
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+/**
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+ * qcom_scm_msa_unlock() - Unlock given peripheral MSA firmware region
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+ *
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+ * @peripheral: peripheral id
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+ *
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+ * Return 0 on success.
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+ */
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+int qcom_scm_msa_unlock(u32 peripheral)
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+{
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+ int ret;
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+ struct qcom_scm_desc desc = {
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+ .svc = QCOM_SCM_SVC_PIL,
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+ .cmd = QCOM_SCM_MSA_UNLOCK,
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+ .arginfo = QCOM_SCM_ARGS(1),
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+ .args[0] = peripheral,
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+ .owner = ARM_SMCCC_OWNER_SIP,
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+ };
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+ struct qcom_scm_res res;
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+
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+ if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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+ QCOM_SCM_MSA_UNLOCK))
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+ return 0;
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+
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+ ret = qcom_scm_clk_enable();
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+ if (ret)
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+ return ret;
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+
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+ ret = qcom_scm_bw_enable();
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+ if (ret)
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+ return ret;
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+
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+ ret = qcom_scm_call(__scm->dev, &desc, &res);
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+ qcom_scm_bw_disable();
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+ qcom_scm_clk_disable();
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+
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+ return ret ? : res.result[0];
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+}
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+EXPORT_SYMBOL_GPL(qcom_scm_msa_unlock);
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+
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static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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{
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struct qcom_scm_desc desc = {
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--- a/drivers/firmware/qcom_scm.h
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+++ b/drivers/firmware/qcom_scm.h
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@@ -98,6 +98,8 @@ extern int scm_legacy_call(struct device
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
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+#define QCOM_SCM_MSA_LOCK 0x24
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+#define QCOM_SCM_MSA_UNLOCK 0x25
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#define QCOM_SCM_SVC_IO 0x05
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#define QCOM_SCM_IO_READ 0x01
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--- a/include/linux/firmware/qcom/qcom_scm.h
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+++ b/include/linux/firmware/qcom/qcom_scm.h
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@@ -81,6 +81,8 @@ extern int qcom_scm_pas_mem_setup(u32 pe
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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+extern int qcom_scm_msa_lock(u32 peripheral);
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+extern int qcom_scm_msa_unlock(u32 peripheral);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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