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114 lines
3.5 KiB
Diff
114 lines
3.5 KiB
Diff
From 7b89dbf5c7dcd8a9c131721e93c1292e5993968b Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 20 Aug 2024 22:02:42 +0800
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Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL clock controller
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for IPQ SoC
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The CMN PLL controller provides clocks to networking hardware blocks
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on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi,
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and produces output clocks at fixed rates. These output rates are
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predetermined, and are unrelated to the input clock rate. The output
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clocks are supplied to the Ethernet hardware such as PPE (packet
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process engine) and the externally connected switch or PHY device.
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 +++++++++++++++++++
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include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 ++++
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2 files changed, 85 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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@@ -0,0 +1,70 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
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+
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+maintainers:
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+ - Bjorn Andersson <andersson@kernel.org>
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+ - Luo Jie <quic_luoj@quicinc.com>
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+
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+description:
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+ The CMN PLL clock controller expects a reference input clock.
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+ This reference clock is from the on-board Wi-Fi. The CMN PLL
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+ supplies a number of fixed rate output clocks to the Ethernet
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+ devices including PPE (packet process engine) and the connected
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+ switch or PHY device.
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq9574-cmn-pll
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: The reference clock. The supported clock rates include
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+ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
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+ - description: The AHB clock
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+ - description: The SYS clock
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+ description:
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+ The reference clock is the source clock of CMN PLL, which is from the
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+ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
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+ clock registers.
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+
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+ clock-names:
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+ items:
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+ - const: ref
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+ - const: ahb
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+ - const: sys
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+
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+ "#clock-cells":
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - "#clock-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+
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+ clock-controller@9b000 {
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+ compatible = "qcom,ipq9574-cmn-pll";
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+ reg = <0x0009b000 0x800>;
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+ clocks = <&cmn_pll_ref_clk>,
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+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
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+ clock-names = "ref", "ahb", "sys";
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+ #clock-cells = <1>;
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+ };
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+...
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--- /dev/null
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+++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
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@@ -0,0 +1,15 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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+
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+/* The output clocks from CMN PLL of IPQ9574. */
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+#define PPE_353MHZ_CLK 0
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+#define ETH0_50MHZ_CLK 1
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+#define ETH1_50MHZ_CLK 2
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+#define ETH2_50MHZ_CLK 3
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+#define ETH_25MHZ_CLK 4
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+#endif
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