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201 lines
4.0 KiB
Diff
201 lines
4.0 KiB
Diff
From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add tsens node
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Date: Fri, 22 Sep 2023 17:21:16 +0530
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IPQ5018 has tsens V1.0 IP with 4 sensors.
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There is no RPM, so tsens has to be manually enabled. Adding the tsens
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and nvmem node and IPQ5018 has 4 thermal sensors (zones). With the
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critical temperature being 120'C and action is to reboot. Adding all
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the 4 zones here.
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
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1 file changed, 169 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -254,6 +254,117 @@
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status = "disabled";
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};
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+ qfprom: qfprom@a0000 {
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+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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+ reg = <0xa0000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ tsens_mode: mode@249 {
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+ reg = <0x249 1>;
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+ bits = <0 3>;
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+ };
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+
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+ tsens_base1: base1@249 {
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+ reg = <0x249 2>;
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+ bits = <3 8>;
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+ };
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+
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+ tsens_base2: base2@24a {
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+ reg = <0x24a 2>;
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+ bits = <3 8>;
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+ };
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+
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+ tsens_s0_p1: s0-p1@24b {
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+ reg = <0x24b 0x2>;
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+ bits = <2 6>;
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+ };
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+
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+ tsens_s0_p2: s0-p2@24c {
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+ reg = <0x24c 0x1>;
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+ bits = <1 6>;
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+ };
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+
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+ tsens_s1_p1: s1-p1@24c {
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+ reg = <0x24c 0x2>;
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+ bits = <7 6>;
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+ };
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+
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+ tsens_s1_p2: s1-p2@24d {
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+ reg = <0x24d 0x2>;
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+ bits = <5 6>;
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+ };
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+
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+ tsens_s2_p1: s2-p1@24e {
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+ reg = <0x24e 0x2>;
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+ bits = <3 6>;
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+ };
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+
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+ tsens_s2_p2: s2-p2@24f {
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+ reg = <0x24f 0x1>;
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+ bits = <1 6>;
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+ };
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+
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+ tsens_s3_p1: s3-p1@24f {
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+ reg = <0x24f 0x2>;
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+ bits = <7 6>;
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+ };
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+
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+ tsens_s3_p2: s3-p2@250 {
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+ reg = <0x250 0x2>;
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+ bits = <5 6>;
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+ };
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+
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+ tsens_s4_p1: s4-p1@251 {
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+ reg = <0x251 0x2>;
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+ bits = <3 6>;
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+ };
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+
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+ tsens_s4_p2: s4-p2@254 {
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+ reg = <0x254 0x1>;
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+ bits = <0 6>;
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+ };
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+ };
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+
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+ tsens: thermal-sensor@4a9000 {
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+ compatible = "qcom,ipq5018-tsens";
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+ reg = <0x4a9000 0x1000>, /* TM */
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+ <0x4a8000 0x1000>; /* SROT */
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+
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+ nvmem-cells = <&tsens_mode>,
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+ <&tsens_base1>,
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+ <&tsens_base2>,
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+ <&tsens_s0_p1>,
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+ <&tsens_s0_p2>,
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+ <&tsens_s1_p1>,
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+ <&tsens_s1_p2>,
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+ <&tsens_s2_p1>,
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+ <&tsens_s2_p2>,
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+ <&tsens_s3_p1>,
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+ <&tsens_s3_p2>,
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+ <&tsens_s4_p1>,
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+ <&tsens_s4_p2>;
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+
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+ nvmem-cell-names = "mode",
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+ "base1",
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+ "base2",
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+ "s0_p1",
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+ "s0_p2",
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+ "s1_p1",
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+ "s1_p2",
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+ "s2_p1",
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+ "s2_p2",
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+ "s3_p1",
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+ "s3_p2",
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+ "s4_p1",
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+ "s4_p2";
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+
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+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
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+ interrupt-names = "uplow";
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+ #qcom,sensors = <5>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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@@ -651,6 +762,64 @@
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};
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};
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+ thermal-zones {
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+ cpu-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 2>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <120000>;
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+ hysteresis = <2>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ gephy-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 4>;
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+
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+ trips {
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+ gephy-critical {
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+ temperature = <120000>;
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+ hysteresis = <2>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ top-glue-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 3>;
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+
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+ trips {
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+ top_glue-critical {
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+ temperature = <120000>;
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+ hysteresis = <2>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ ubi32-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 1>;
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+
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+ trips {
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+ ubi32-critical {
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+ temperature = <120000>;
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+ hysteresis = <2>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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