mirror of
https://github.com/coolsnowwolf/lede.git
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137 lines
4.1 KiB
Diff
137 lines
4.1 KiB
Diff
From 0245360f8e118b67f4015533cfc79314f2d848d5 Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Tue, 13 Jun 2017 15:30:39 +0530
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Subject: [PATCH 2/3] clk: qcom: add support for hw controlled RCG
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The current driver generates stack trace during RCG update if
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the RCG is off and new parent source is also disabled. For
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hardware controlled RCG’s, clock is forced on during update
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process and goes back to off status once switch is completed.
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Since the new parent is in disabled state so update bit won’t
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be cleared in this case. The check for update bit can be
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skipped in this case.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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(cherry picked from commit 84dd0e12f10eebff44a464eb8455205abc4b4178)
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
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---
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drivers/clk/qcom/clk-rcg.h | 4 ++++
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drivers/clk/qcom/clk-rcg2.c | 27 +++++++++++++++++++++------
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2 files changed, 25 insertions(+), 6 deletions(-)
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--- a/drivers/clk/qcom/clk-rcg.h
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+++ b/drivers/clk/qcom/clk-rcg.h
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@@ -135,6 +135,7 @@ extern const struct clk_ops clk_dyn_rcg_
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* @mnd_width: number of bits in m/n/d values
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* @hid_width: number of bits in half integer divider
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* @safe_src_index: safe src index value
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+ * @flags: RCG2 specific clock flags
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* @parent_map: map from software's parent index to hardware's src_sel field
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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@@ -145,6 +146,9 @@ struct clk_rcg2 {
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u8 mnd_width;
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u8 hid_width;
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u8 safe_src_index;
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+
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+#define CLK_RCG2_HW_CONTROLLED BIT(0)
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+ u8 flags;
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const struct parent_map *parent_map;
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -97,7 +97,7 @@ err:
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return 0;
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}
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-static int update_config(struct clk_rcg2 *rcg)
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+static int update_config(struct clk_rcg2 *rcg, bool check_update_clear)
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{
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int count, ret;
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u32 cmd;
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@@ -109,6 +109,9 @@ static int update_config(struct clk_rcg2
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if (ret)
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return ret;
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+ if (!check_update_clear)
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+ return 0;
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+
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/* Wait for update to take effect */
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for (count = 500; count > 0; count--) {
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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@@ -127,14 +130,19 @@ static int clk_rcg2_set_parent(struct cl
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int ret;
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+ bool check_update_clear = true;
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u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
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+ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) &&
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+ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index)))
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+ check_update_clear = false;
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+
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ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
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CFG_SRC_SEL_MASK, cfg);
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if (ret)
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return ret;
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- return update_config(rcg);
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+ return update_config(rcg, check_update_clear);
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}
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/*
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@@ -305,12 +313,19 @@ static int __clk_rcg2_configure(struct c
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static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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{
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int ret;
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+ bool check_update_clear = true;
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+ struct clk_hw *hw = &rcg->clkr.hw;
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+ int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
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ret = __clk_rcg2_configure(rcg, f);
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if (ret)
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return ret;
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- return update_config(rcg);
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+ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) &&
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+ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index)))
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+ check_update_clear = false;
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+
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+ return update_config(rcg, check_update_clear);
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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@@ -790,7 +805,7 @@ static int clk_gfx3d_set_rate_and_parent
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if (ret)
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return ret;
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- return update_config(rcg);
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+ return update_config(rcg, true);
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}
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static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
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@@ -902,7 +917,7 @@ static int clk_rcg2_shared_enable(struct
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if (ret)
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return ret;
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- ret = update_config(rcg);
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+ ret = update_config(rcg, true);
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if (ret)
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return ret;
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@@ -933,7 +948,7 @@ static void clk_rcg2_shared_disable(stru
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regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
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- update_config(rcg);
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+ update_config(rcg, true);
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clk_rcg2_clear_force_enable(hw);
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