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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
148 lines
4.6 KiB
Diff
148 lines
4.6 KiB
Diff
From a9179aeead3fe0737b47d11ef687edc2dc15c964 Mon Sep 17 00:00:00 2001
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From: Kathiravan T <kathirav@codeaurora.org>
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Date: Fri, 6 Nov 2020 12:18:37 +0530
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Subject: [PATCH 1003/1011] clk: qcom: ipq6018: add missing clock flags
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The downstream QCA 5.4 kernel sets several extra clock flags. From
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their reasoning:
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Add the CLK_IS_CRITICAL, CLK_RCG2_HW_CONTROLLED for the required clocks.
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Without the critical flag, below warning is seen when QDSS
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components are enabled.
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[ 1.712722] ------------[ cut here ]------------
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[ 1.719039] gcc_qdss_dap_clk status stuck at 'on'
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[ 1.719084] WARNING: CPU: 1 PID: 1 at drivers/clk/qcom/clk-branch.c:92 clk_branch_toggle+0x160/0x178
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Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq6018.c | 19 +++++++++++++++----
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1 file changed, 15 insertions(+), 4 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -62,6 +62,7 @@ static struct clk_alpha_pll gpll0_main =
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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},
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};
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@@ -150,6 +151,7 @@ static struct clk_alpha_pll gpll6_main =
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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},
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};
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@@ -181,6 +183,7 @@ static struct clk_alpha_pll gpll4_main =
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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},
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};
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@@ -211,6 +214,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
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.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
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+ .flags = CLK_RCG2_HW_CONTROLLED,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcnoc_bfdcd_clk_src",
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.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
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@@ -232,6 +236,7 @@ static struct clk_alpha_pll gpll2_main =
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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},
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};
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@@ -456,6 +461,7 @@ static struct clk_branch gcc_sleep_clk_s
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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},
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};
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@@ -960,6 +966,7 @@ static struct clk_rcg2 nss_crypto_clk_sr
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
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+ .flags = CLK_RCG2_HW_CONTROLLED,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_crypto_clk_src",
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.parent_data = gcc_xo_nss_crypto_pll_gpll0,
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@@ -1131,6 +1138,7 @@ static struct clk_rcg2 nss_ubi0_clk_src
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.freq_tbl = ftbl_nss_ubi_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
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+ .flags = CLK_RCG2_HW_CONTROLLED,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_ubi0_clk_src",
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.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
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@@ -1869,7 +1877,7 @@ static struct clk_branch gcc_apss_ahb_cl
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.parent_hws = (const struct clk_hw *[]){
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&apss_ahb_postdiv_clk_src.clkr.hw },
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@@ -1891,11 +1899,13 @@ static struct clk_rcg2 system_noc_bfdcd_
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.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
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+ .flags = CLK_RCG2_HW_CONTROLLED,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "system_noc_bfdcd_clk_src",
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.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
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.num_parents = 4,
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.ops = &clk_rcg2_ops,
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+ .flags = CLK_IS_CRITICAL,
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},
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};
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@@ -1945,7 +1955,7 @@ static struct clk_branch gcc_apss_axi_cl
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.parent_hws = (const struct clk_hw *[]){
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&apss_axi_clk_src.clkr.hw },
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@@ -2314,7 +2324,7 @@ static struct clk_branch gcc_xo_clk = {
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.parent_hws = (const struct clk_hw *[]){
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&gcc_xo_clk_src.clkr.hw },
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@@ -3163,6 +3173,7 @@ static struct clk_branch gcc_nssnoc_ppe_
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.name = "gcc_nssnoc_ppe_cfg_clk",
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.parent_hws = (const struct clk_hw *[]){
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&nss_ppe_clk_src.clkr.hw },
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+ .num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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@@ -3521,7 +3532,7 @@ static struct clk_branch gcc_qdss_dap_cl
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.parent_hws = (const struct clk_hw *[]){
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&qdss_dap_sync_clk_src.hw },
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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