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https://github.com/coolsnowwolf/lede.git
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62 lines
1.8 KiB
Diff
62 lines
1.8 KiB
Diff
From f05295ef5e58a042f3a66490f6e75c6af83a329f Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 13 Mar 2022 12:46:28 +0100
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Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
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The built-in PPE engine has a dedicated clock for the EIP-197 crypto
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engine.
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So, since the required clock currently missing add support for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
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2 files changed, 20 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref
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},
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};
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+static struct clk_branch gcc_crypto_ppe_clk = {
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+ .halt_reg = 0x68310,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x68310,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_crypto_ppe_clk",
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+ .parent_names = (const char *[]){
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+ "nss_ppe_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_branch gcc_nssnoc_ce_apb_clk = {
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.halt_reg = 0x6830c,
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.clkr = {
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@@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_cl
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[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
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[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
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[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
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+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq8074_resets[] = {
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--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@@ -233,6 +233,7 @@
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
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#define GCC_PCIE0_RCHNG_CLK_SRC 225
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#define GCC_PCIE0_RCHNG_CLK 226
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+#define GCC_CRYPTO_PPE_CLK 227
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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