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65 lines
2.5 KiB
Diff
65 lines
2.5 KiB
Diff
From 7cb389923931167cc772f36fabe5f140abb28053 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 1 Jan 2022 19:29:48 +0100
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Subject: [PATCH] clk: qcom: ipq8074: fix NSS port frequency tables
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NSS port 5 and 6 frequency tables are currently broken and are causing a
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wide ranges of issue like 1G not working at all on port 6 or port 5 being
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clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.
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So, update the frequency tables with the ones from the downstream QCA 5.4
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based kernel which has already fixed this.
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Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_t
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static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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+ F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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+ F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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@@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_r
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static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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+ F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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+ F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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{ }
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@@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_t
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static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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+ F(25000000, P_UNIPHY2_RX, 5, 0, 0),
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F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
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F(78125000, P_UNIPHY2_RX, 4, 0, 0),
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+ F(125000000, P_UNIPHY2_RX, 1, 0, 0),
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F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
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F(156250000, P_UNIPHY2_RX, 2, 0, 0),
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F(312500000, P_UNIPHY2_RX, 1, 0, 0),
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@@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_r
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static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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+ F(25000000, P_UNIPHY2_TX, 5, 0, 0),
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F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
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F(78125000, P_UNIPHY2_TX, 4, 0, 0),
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+ F(125000000, P_UNIPHY2_TX, 1, 0, 0),
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F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
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F(156250000, P_UNIPHY2_TX, 2, 0, 0),
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F(312500000, P_UNIPHY2_TX, 1, 0, 0),
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