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81 lines
2.4 KiB
Diff
81 lines
2.4 KiB
Diff
From 73344249026d524544e2f86c737759737c962e28 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 1 Jan 2022 18:48:56 +0100
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Subject: [PATCH] clk: qcom: ipq8074: fix NSS core PLL-s
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration
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to work.
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So, obtain the regmap that is required for the Alpha PLL configuration
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and thus utilize the qcom_cc_really_probe() as we already have the regmap.
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Then utilize the Alpha PLL configs from the downstream QCA 5.4 based
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kernel to configure them.
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This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the
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kernel.
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Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++-
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1 file changed, 38 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s
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},
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};
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+static const struct alpha_pll_config ubi32_pll_config = {
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+ .l = 0x4e,
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+ .config_ctl_val = 0x200d4aa8,
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+ .config_ctl_hi_val = 0x3c2,
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+ .main_output_mask = BIT(0),
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+ .aux_output_mask = BIT(1),
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+ .pre_div_val = 0x0,
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+ .pre_div_mask = BIT(12),
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+ .post_div_val = 0x0,
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+ .post_div_mask = GENMASK(9, 8),
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+};
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+
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+static const struct alpha_pll_config nss_crypto_pll_config = {
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+ .l = 0x3e,
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+ .alpha = 0x0,
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+ .alpha_hi = 0x80,
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+ .config_ctl_val = 0x4001055b,
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+ .main_output_mask = BIT(0),
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+ .pre_div_val = 0x0,
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+ .pre_div_mask = GENMASK(14, 12),
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+ .post_div_val = 0x1 << 8,
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+ .post_div_mask = GENMASK(11, 8),
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+ .vco_mask = GENMASK(21, 20),
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+ .vco_val = 0x0,
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+ .alpha_en_mask = BIT(24),
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+};
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+
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static struct clk_hw *gcc_ipq8074_hws[] = {
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&gpll0_out_main_div2.hw,
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&gpll6_out_main_div2.hw,
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@@ -4787,7 +4814,17 @@ static const struct qcom_cc_desc gcc_ipq
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static int gcc_ipq8074_probe(struct platform_device *pdev)
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{
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- return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
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+ struct regmap *regmap;
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+
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+ regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
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+ clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
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+ &nss_crypto_pll_config);
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+
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+ return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
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}
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static struct platform_driver gcc_ipq8074_driver = {
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