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https://github.com/coolsnowwolf/lede.git
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67 lines
1.7 KiB
Diff
67 lines
1.7 KiB
Diff
From c8cda381dfd1fd083d6d2f56f71d33144c042a43 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 31 Dec 2021 17:56:14 +0100
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Subject: [PATCH] arm64: dts: ipq8074: add CPU clock and regulator
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Now that we have drivers for both the CPU voltage regulator and clock
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controller, add the required DT properties to CPU cores.
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OPP tables are not added as they are different for the IPQ8072/4/6/8 and
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IPQ8070/1 SoC-s
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -4,6 +4,7 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/qcom,apss-ipq8074.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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#include <dt-bindings/spmi/spmi.h>
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@@ -35,6 +36,9 @@
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ cpu-supply = <&s3>;
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};
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CPU1: cpu@1 {
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@@ -43,6 +47,9 @@
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ cpu-supply = <&s3>;
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};
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CPU2: cpu@2 {
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@@ -51,6 +58,9 @@
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ cpu-supply = <&s3>;
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};
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CPU3: cpu@3 {
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@@ -59,6 +69,9 @@
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ cpu-supply = <&s3>;
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};
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L2_0: l2-cache {
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