mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-15 18:03:30 +00:00
43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
|
@@ -225,6 +225,7 @@
|
|
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_PIPEPHY0>;
|
|
+ reset-names = "phy";
|
|
rockchip,pipe-grf = <&pipegrf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
|
#phy-cells = <1>;
|
|
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
|
@@ -1719,6 +1719,7 @@
|
|
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_PIPEPHY1>;
|
|
+ reset-names = "phy";
|
|
rockchip,pipe-grf = <&pipegrf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
|
#phy-cells = <1>;
|
|
@@ -1735,6 +1736,7 @@
|
|
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_PIPEPHY2>;
|
|
+ reset-names = "phy";
|
|
rockchip,pipe-grf = <&pipegrf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
|
#phy-cells = <1>;
|
|
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
|
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
|
@@ -324,7 +324,10 @@ static int rockchip_combphy_parse_dt(str
|
|
|
|
priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
|
|
|
|
- priv->phy_rst = devm_reset_control_get(dev, "phy");
|
|
+ priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
|
|
+ /* fallback to old behaviour */
|
|
+ if (PTR_ERR(priv->phy_rst) == -ENOENT)
|
|
+ priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
|
|
if (IS_ERR(priv->phy_rst))
|
|
return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
|
|
|