mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-07 14:52:04 +08:00
71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From: Gabor Juhos <j4g8y7@gmail.com>
|
|
Date: Fri, 02 May 2025 21:31:16 +0200
|
|
Subject: [PATCH next 1/2] mtd: nand: qpic-common: add defines for ECC_MODE
|
|
values
|
|
|
|
Add defines for the values of the ECC_MODE field of the NAND_DEV0_ECC_CFG
|
|
register and change both the 'qcom-nandc' and 'spi-qpic-snand' drivers to
|
|
use those instead of magic numbers.
|
|
|
|
No functional changes. This is in preparation for adding 8 bit ECC strength
|
|
support for the 'spi-qpic-snand' driver.
|
|
|
|
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
|
|
---
|
|
drivers/mtd/nand/raw/qcom_nandc.c | 6 +++---
|
|
drivers/spi/spi-qpic-snand.c | 2 +-
|
|
include/linux/mtd/nand-qpic-common.h | 2 ++
|
|
3 files changed, 6 insertions(+), 4 deletions(-)
|
|
|
|
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
|
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
|
@@ -1379,7 +1379,7 @@ static int qcom_nand_attach_chip(struct
|
|
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
|
int cwperpage, bad_block_byte, ret;
|
|
bool wide_bus;
|
|
- int ecc_mode = 1;
|
|
+ int ecc_mode = ECC_MODE_8BIT;
|
|
|
|
/* controller only supports 512 bytes data steps */
|
|
ecc->size = NANDC_STEP_SIZE;
|
|
@@ -1400,7 +1400,7 @@ static int qcom_nand_attach_chip(struct
|
|
if (ecc->strength >= 8) {
|
|
/* 8 bit ECC defaults to BCH ECC on all platforms */
|
|
host->bch_enabled = true;
|
|
- ecc_mode = 1;
|
|
+ ecc_mode = ECC_MODE_8BIT;
|
|
|
|
if (wide_bus) {
|
|
host->ecc_bytes_hw = 14;
|
|
@@ -1420,7 +1420,7 @@ static int qcom_nand_attach_chip(struct
|
|
if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
|
|
/* BCH */
|
|
host->bch_enabled = true;
|
|
- ecc_mode = 0;
|
|
+ ecc_mode = ECC_MODE_4BIT;
|
|
|
|
if (wide_bus) {
|
|
host->ecc_bytes_hw = 8;
|
|
--- a/drivers/spi/spi-qpic-snand.c
|
|
+++ b/drivers/spi/spi-qpic-snand.c
|
|
@@ -349,7 +349,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
|
|
FIELD_PREP(ECC_SW_RESET, 0) |
|
|
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
|
|
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
|
|
- FIELD_PREP(ECC_MODE_MASK, 0) |
|
|
+ FIELD_PREP(ECC_MODE_MASK, ECC_MODE_4BIT) |
|
|
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
|
|
|
|
ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
|
|
--- a/include/linux/mtd/nand-qpic-common.h
|
|
+++ b/include/linux/mtd/nand-qpic-common.h
|
|
@@ -101,6 +101,8 @@
|
|
#define ECC_SW_RESET BIT(1)
|
|
#define ECC_MODE 4
|
|
#define ECC_MODE_MASK GENMASK(5, 4)
|
|
+#define ECC_MODE_4BIT 0
|
|
+#define ECC_MODE_8BIT 1
|
|
#define ECC_PARITY_SIZE_BYTES_BCH 8
|
|
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
|
|
#define ECC_NUM_DATA_BYTES 16
|