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https://github.com/coolsnowwolf/lede.git
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404209f6c4
kernel: bump to 4.14.193, 4.19.138, 5.4.59 (#5350) 431fb8c mac80211: add AQL improvements 6bdd4c9 mac80211: add missing backports for building with 4.14 kernels 0106820 mac80211: add missing return code checks in AQL improvements e7f7101 mac80211: rework encapsulation offload support [package] base-files: add function for generating random MAC dnsmasq: abort dhcp_check on interface state boot: sync upstream source code ath10k-ct-firmware/mt76/sch_cake: update to latest git HEAD [script] download: add China Mirror Station [target] Sync: arc770, ath79, bcm63xx, kirkwood, lantiq, layerscape, mediatek, mvebu, octeon, oxnas, pistachio, uml Sync most of the target patches. Run-compiled-on: ipq40xx (4.19 & 5.4), ramips
28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
--- a/drivers/crypto/inside-secure/safexcel.c
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+++ b/drivers/crypto/inside-secure/safexcel.c
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@@ -595,6 +595,14 @@ static int safexcel_hw_init(struct safex
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val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
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writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
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}
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+ /*
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+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
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+ */
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+ else {
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+ val = 0;
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+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
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+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
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+ }
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/* Configure wr/rd cache values */
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writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
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--- a/drivers/crypto/inside-secure/safexcel.h
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+++ b/drivers/crypto/inside-secure/safexcel.h
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@@ -306,6 +306,7 @@
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#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
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#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
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#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
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+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
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#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
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#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
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#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
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