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150 lines
4.1 KiB
Diff
150 lines
4.1 KiB
Diff
From 25e4cf1178f49d975a6fa0c50debeec42c1f98cf Mon Sep 17 00:00:00 2001
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From: Hector Martin <marcan@marcan.st>
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Date: Mon, 2 May 2022 23:21:00 +0900
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Subject: [PATCH 157/171] dt-bindings: cpufreq: apple,soc-cpufreq: Add binding
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for Apple SoC cpufreq
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This binding represents the cpufreq/DVFS hardware present in Apple SoCs.
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The hardware has an independent controller per CPU cluster, but we
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represent them as a single cpufreq node since there can only be one
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systemwide cpufreq device (and since in the future, interactions with
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memory controller performance states will also involve cooperation
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between multiple frequency domains).
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Signed-off-by: Hector Martin <marcan@marcan.st>
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---
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.../bindings/cpufreq/apple,soc-cpufreq.yaml | 121 ++++++++++++++++++
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1 file changed, 121 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml
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diff --git a/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml
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new file mode 100644
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index 000000000000..f398c1bd5de5
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml
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@@ -0,0 +1,121 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/cpufreq/apple,soc-cpufreq.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Apple SoC cpufreq device
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+
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+maintainers:
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+ - Hector Martin <marcan@marcan.st>
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+
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+description: |
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+ Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
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+ the cluster management register block. This binding uses the standard
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+ operating-points-v2 table to define the CPU performance states, with the
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+ opp-level property specifying the hardware p-state index for that level.
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - apple,t8103-soc-cpufreq
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+ - apple,t6000-soc-cpufreq
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+ - const: apple,soc-cpufreq
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+
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+ reg:
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+ minItems: 1
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+ maxItems: 6
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+ description: One register region per CPU cluster DVFS controller
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+
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+ reg-names:
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+ minItems: 1
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+ items:
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+ - const: cluster0
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+ - const: cluster1
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+ - const: cluster2
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+ - const: cluster3
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+ - const: cluster4
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+ - const: cluster5
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+
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+ '#freq-domain-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - reg-names
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+ - '#freq-domain-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ // This example shows a single CPU per domain and 2 domains,
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+ // with two p-states per domain.
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+ // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
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+ cpus {
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ compatible = "apple,icestorm";
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+ device_type = "cpu";
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+ reg = <0x0 0x0>;
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+ operating-points-v2 = <&ecluster_opp>;
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+ apple,freq-domain = <&cpufreq_hw 0>;
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+ };
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+
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+ cpu@10100 {
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+ compatible = "apple,firestorm";
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+ device_type = "cpu";
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+ reg = <0x0 0x10100>;
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+ operating-points-v2 = <&pcluster_opp>;
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+ apple,freq-domain = <&cpufreq_hw 1>;
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+ };
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+ };
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+
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+ ecluster_opp: opp-table-0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-level = <1>;
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+ clock-latency-ns = <7500>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <972000000>;
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+ opp-level = <2>;
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+ clock-latency-ns = <22000>;
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+ };
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+ };
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+
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+ pcluster_opp: opp-table-1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-level = <1>;
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+ clock-latency-ns = <8000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <828000000>;
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+ opp-level = <2>;
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+ clock-latency-ns = <19000>;
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+ };
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+ };
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+
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ cpufreq_hw: cpufreq@210e20000 {
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+ compatible = "apple,t8103-soc-cpufreq", "apple,soc-cpufreq";
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+ reg = <0x2 0x10e20000 0 0x1000>,
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+ <0x2 0x11e20000 0 0x1000>;
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+ reg-names = "cluster0", "cluster1";
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+ #freq-domain-cells = <1>;
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+ };
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+ };
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--
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2.34.1
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