mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-07-18 15:46:59 +08:00
75 lines
2.6 KiB
Diff
75 lines
2.6 KiB
Diff
From 7ab58741bf0d62ff5600dffaf34d06634403f465 Mon Sep 17 00:00:00 2001
|
|
From: Hector Martin <marcan@marcan.st>
|
|
Date: Tue, 21 Dec 2021 17:14:59 +0900
|
|
Subject: [PATCH 103/171] brcmfmac: chip: Handle 1024-unit sizes for TCM blocks
|
|
|
|
BCM4387 has trailing odd-sized blocks as part of TCM which have
|
|
their size described as a multiple of 1024 instead of 8192. Handle this
|
|
so we can compute the TCM size properly.
|
|
|
|
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Signed-off-by: Hector Martin <marcan@marcan.st>
|
|
---
|
|
.../wireless/broadcom/brcm80211/brcmfmac/chip.c | 17 ++++++++++++-----
|
|
1 file changed, 12 insertions(+), 5 deletions(-)
|
|
|
|
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
|
index 8266466283e4..78d835dea8d2 100644
|
|
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
|
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
|
@@ -212,8 +212,8 @@ struct sbsocramregs {
|
|
#define ARMCR4_TCBANB_MASK 0xf
|
|
#define ARMCR4_TCBANB_SHIFT 0
|
|
|
|
-#define ARMCR4_BSZ_MASK 0x3f
|
|
-#define ARMCR4_BSZ_MULT 8192
|
|
+#define ARMCR4_BSZ_MASK 0x7f
|
|
+#define ARMCR4_BLK_1K_MASK 0x200
|
|
|
|
struct brcmf_core_priv {
|
|
struct brcmf_core pub;
|
|
@@ -675,7 +675,8 @@ static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
|
|
}
|
|
|
|
/** Return the TCM-RAM size of the ARMCR4 core. */
|
|
-static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
|
|
+static u32 brcmf_chip_tcm_ramsize(struct brcmf_chip_priv *ci,
|
|
+ struct brcmf_core_priv *cr4)
|
|
{
|
|
u32 corecap;
|
|
u32 memsize = 0;
|
|
@@ -683,6 +684,7 @@ static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
|
|
u32 nbb;
|
|
u32 totb;
|
|
u32 bxinfo;
|
|
+ u32 blksize;
|
|
u32 idx;
|
|
|
|
corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
|
|
@@ -694,7 +696,12 @@ static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
|
|
for (idx = 0; idx < totb; idx++) {
|
|
brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
|
|
bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
|
|
- memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
|
|
+ if (bxinfo & ARMCR4_BLK_1K_MASK)
|
|
+ blksize = 1024;
|
|
+ else
|
|
+ blksize = 8192;
|
|
+
|
|
+ memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * blksize;
|
|
}
|
|
|
|
return memsize;
|
|
@@ -753,7 +760,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
|
|
mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
|
|
if (mem) {
|
|
mem_core = container_of(mem, struct brcmf_core_priv, pub);
|
|
- ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
|
|
+ ci->pub.ramsize = brcmf_chip_tcm_ramsize(ci, mem_core);
|
|
ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
|
|
if (ci->pub.rambase == INVALID_RAMBASE) {
|
|
brcmf_err("RAM base not provided with ARM CR4 core\n");
|
|
--
|
|
2.34.1
|
|
|