mirror of
https://github.com/coolsnowwolf/lede.git
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100 lines
3.5 KiB
Diff
100 lines
3.5 KiB
Diff
From 539a79c58042c7902bfff6453a589d5dc2e0230c Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Fri, 20 Oct 2023 11:49:32 +0530
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Subject: [PATCH 36/41] clk: qcom: clk-alpha-pll: introduce stromer plus ops
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Stromer plus APSS PLL does not support dynamic frequency scaling.
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To switch between frequencies, we have to shut down the PLL,
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configure the L and ALPHA values and turn on again. So introduce the
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separate set of ops for Stromer Plus PLL.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/2affa6c63ff0c4342230623a7d4eef02ec7c02d4.1697781921.git.quic_varada@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/clk-alpha-pll.c | 63 ++++++++++++++++++++++++++++++++
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drivers/clk/qcom/clk-alpha-pll.h | 1 +
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2 files changed, 64 insertions(+)
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--- a/drivers/clk/qcom/clk-alpha-pll.c
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+++ b/drivers/clk/qcom/clk-alpha-pll.c
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@@ -2486,3 +2486,66 @@ const struct clk_ops clk_alpha_pll_strom
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.set_rate = clk_alpha_pll_stromer_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
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+
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+static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
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+ unsigned long rate,
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+ unsigned long prate)
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+{
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+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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+ u32 l, alpha_width = pll_alpha_width(pll);
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+ int ret, pll_mode;
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+ u64 a;
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+
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+ rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
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+
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+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
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+ if (ret)
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+ return ret;
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+
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+ regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
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+
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+ /* Delay of 2 output clock ticks required until output is disabled */
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+ udelay(1);
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+
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+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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+
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+ if (alpha_width > ALPHA_BITWIDTH)
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+ a <<= alpha_width - ALPHA_BITWIDTH;
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+
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
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+ a >> ALPHA_BITWIDTH);
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+
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+ regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
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+
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+ /* Wait five micro seconds or more */
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+ udelay(5);
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+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
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+ PLL_RESET_N);
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+
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+ /* The lock time should be less than 50 micro seconds worst case */
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+ usleep_range(50, 60);
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+
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+ ret = wait_for_pll_enable_lock(pll);
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+ if (ret) {
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+ pr_err("Wait for PLL enable lock failed [%s] %d\n",
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+ clk_hw_get_name(hw), ret);
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+ return ret;
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+ }
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+
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+ if (pll_mode & PLL_OUTCTRL)
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+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
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+ PLL_OUTCTRL);
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+
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+ return 0;
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+}
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+
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+const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
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+ .prepare = clk_alpha_pll_enable,
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+ .unprepare = clk_alpha_pll_disable,
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+ .is_enabled = clk_alpha_pll_is_enabled,
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+ .recalc_rate = clk_alpha_pll_recalc_rate,
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+ .determine_rate = clk_alpha_pll_stromer_determine_rate,
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+ .set_rate = clk_alpha_pll_stromer_plus_set_rate,
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+};
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+EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
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--- a/drivers/clk/qcom/clk-alpha-pll.h
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+++ b/drivers/clk/qcom/clk-alpha-pll.h
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@@ -145,6 +145,7 @@ extern const struct clk_ops clk_alpha_pl
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extern const struct clk_ops clk_alpha_pll_huayra_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
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extern const struct clk_ops clk_alpha_pll_stromer_ops;
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+extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
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extern const struct clk_ops clk_alpha_pll_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
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