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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
92 lines
3.0 KiB
Diff
92 lines
3.0 KiB
Diff
From 14caaa7a23404cfee65a0d74b61d7998f762c70f Mon Sep 17 00:00:00 2001
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From: Pavithra R <quic_pavir@quicinc.com>
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Date: Wed, 6 Mar 2024 22:29:41 +0530
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Subject: [PATCH 16/17] arm64: dts: qcom: Add EDMA node for IPQ9574
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Add EDMA (Ethernet DMA) device tree node for IPQ9574 to
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enable ethernet support.
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Change-Id: I87d7c50f2485c8670948dce305000337f6499f8b
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Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 68 +++++++++++++++++++++++++++
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1 file changed, 68 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -989,6 +989,74 @@
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"nssnoc_memnoc",
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"memnoc_nssnoc",
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"memnoc_nssnoc_1";
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+
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+ edma {
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+ compatible = "qcom,ipq9574-edma";
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+ clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>,
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+ <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>;
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+ clock-names = "edma",
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+ "edma-cfg";
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+ resets = <&nsscc EDMA_HW_RESET>;
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+ reset-names = "edma_rst";
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+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "edma_txcmpl_8",
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+ "edma_txcmpl_9",
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+ "edma_txcmpl_10",
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+ "edma_txcmpl_11",
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+ "edma_txcmpl_12",
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+ "edma_txcmpl_13",
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+ "edma_txcmpl_14",
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+ "edma_txcmpl_15",
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+ "edma_txcmpl_16",
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+ "edma_txcmpl_17",
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+ "edma_txcmpl_18",
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+ "edma_txcmpl_19",
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+ "edma_txcmpl_20",
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+ "edma_txcmpl_21",
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+ "edma_txcmpl_22",
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+ "edma_txcmpl_23",
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+ "edma_txcmpl_24",
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+ "edma_txcmpl_25",
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+ "edma_txcmpl_26",
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+ "edma_txcmpl_27",
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+ "edma_txcmpl_28",
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+ "edma_txcmpl_29",
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+ "edma_txcmpl_30",
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+ "edma_txcmpl_31",
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+ "edma_rxdesc_20",
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+ "edma_rxdesc_21",
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+ "edma_rxdesc_22",
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+ "edma_rxdesc_23",
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+ "edma_misc";
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+ };
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};
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};
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