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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
63 lines
1.9 KiB
Diff
63 lines
1.9 KiB
Diff
From ff847b8692e877e660b64ff2de4f26c6f7ce932e Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Fri, 1 Mar 2024 14:46:45 +0800
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Subject: [PATCH 14/17] arm64: dts: qcom: Add IPQ9574 PPE base device node
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PPE is the packet process engine on the Qualcomm IPQ platform,
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which is connected with the external switch or PHY device via
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the UNIPHY (PCS).
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Change-Id: I254bd48c218aa4eab54f697a2ad149f5a93b682c
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 38 +++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -952,6 +952,44 @@
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"ch_tx";
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};
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};
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+
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+ ethernet@3a000000 {
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+ compatible = "qcom,ipq9574-ppe";
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+ reg = <0x3a000000 0xbef800>;
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+ ranges;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
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+ clock-names = "ppe",
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+ "ppe_cfg",
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+ "ppe_ipe",
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+ "ppe_btq";
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+ resets = <&nsscc PPE_FULL_RESET>;
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+ interconnects = <&nsscc MASTER_NSSNOC_PPE
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+ &nsscc SLAVE_NSSNOC_PPE>,
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+ <&nsscc MASTER_NSSNOC_PPE_CFG
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+ &nsscc SLAVE_NSSNOC_PPE_CFG>,
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+ <&gcc MASTER_NSSNOC_QOSGEN_REF
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+ &gcc SLAVE_NSSNOC_QOSGEN_REF>,
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+ <&gcc MASTER_NSSNOC_TIMEOUT_REF
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+ &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
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+ <&gcc MASTER_MEM_NOC_NSSNOC
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+ &gcc SLAVE_MEM_NOC_NSSNOC>,
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+ <&gcc MASTER_NSSNOC_MEMNOC
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+ &gcc SLAVE_NSSNOC_MEMNOC>,
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+ <&gcc MASTER_NSSNOC_MEM_NOC_1
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+ &gcc SLAVE_NSSNOC_MEM_NOC_1>;
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+ interconnect-names = "ppe",
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+ "ppe_cfg",
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+ "qos_gen",
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+ "timeout_ref",
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+ "nssnoc_memnoc",
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+ "memnoc_nssnoc",
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+ "memnoc_nssnoc_1";
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+ };
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};
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thermal-zones {
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