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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
50 lines
1.3 KiB
Diff
50 lines
1.3 KiB
Diff
From 3e98aaf9e5c6b2206edce3309beb1adeb2b61b60 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Thu, 23 Nov 2023 15:41:20 +0800
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Subject: [PATCH 15/17] arm64: dts: qcom: Add IPQ9574 MDIO device node
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The MDIO bus master block is used to accessing the MDIO slave
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device (such as PHY device), the dedicated MDIO PINs needs to
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be configured.
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Change-Id: Ia64083529e693256dbd8f8af4071c02afdded8f9
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -251,6 +251,8 @@
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mdio: mdio@90000 {
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compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
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reg = <0x00090000 0x64>;
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+ pinctrl-0 = <&mdio_pins>;
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+ pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_MDIO_AHB_CLK>;
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@@ -322,6 +324,22 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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+ mdio_pins: mdio-pins {
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+ mdc-state {
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+ pins = "gpio38";
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+ function = "mdc";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ mdio-state {
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+ pins = "gpio39";
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+ function = "mdio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ };
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+
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uart2_pins: uart2-state {
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pins = "gpio34", "gpio35";
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function = "blsp2_uart";
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