mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
148 lines
4.3 KiB
Diff
148 lines
4.3 KiB
Diff
From 3105ff9d7111d15b686b8d14e8b4413a5c2a88ce Mon Sep 17 00:00:00 2001
|
|
From: Lei Wei <quic_leiwei@quicinc.com>
|
|
Date: Thu, 1 Feb 2024 13:03:14 +0800
|
|
Subject: [PATCH 13/17] arm64: dts: qcom: ipq9574: Add PCS UNIPHY device tree
|
|
support
|
|
|
|
The UNIPHY block in the IPQ SoC enables PCS/XPCS functions and helps in
|
|
interfacing the Ethernet MAC to external PHYs.
|
|
|
|
There are three PCS UNIPHY instances available in the IPQ9574 SoC. The
|
|
first UNIPHY has four PCS channels which can connect to QCA8075 Quad
|
|
PHYs in QSGMII mode or QCA8085 PHYs with 10G-QXGMII mode. The second
|
|
and third UNIPHYs each has one PCS channel which can connect with single
|
|
10G capable PHY such as Aquantia 113c PHY in USXGMII mode.
|
|
|
|
Change-Id: I7832a71b12730d5bd7926a25f4feda371c09b58e
|
|
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 110 +++++++++++++++++++++++++-
|
|
1 file changed, 109 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
@@ -3,7 +3,7 @@
|
|
* IPQ9574 SoC device tree source
|
|
*
|
|
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
|
|
- * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
|
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/qcom,apss-ipq.h>
|
|
@@ -826,6 +826,114 @@
|
|
#power-domain-cells = <1>;
|
|
#interconnect-cells = <1>;
|
|
};
|
|
+
|
|
+ pcsuniphy0: ethernet-uniphy@7a00000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "qcom,ipq9574-uniphy";
|
|
+ reg = <0x7a00000 0x10000>;
|
|
+ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
|
|
+ <&gcc GCC_UNIPHY0_AHB_CLK>;
|
|
+ clock-names = "sys",
|
|
+ "ahb";
|
|
+ resets = <&gcc GCC_UNIPHY0_SYS_RESET>,
|
|
+ <&gcc GCC_UNIPHY0_AHB_RESET>,
|
|
+ <&gcc GCC_UNIPHY0_XPCS_RESET>;
|
|
+ reset-names = "sys",
|
|
+ "ahb",
|
|
+ "xpcs";
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "uniphy0_nss_rx_clk",
|
|
+ "uniphy0_nss_tx_clk";
|
|
+
|
|
+ pcsuniphy0_ch0: uniphy-ch@0 {
|
|
+ reg = <0>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+
|
|
+ pcsuniphy0_ch1: uniphy-ch@1 {
|
|
+ reg = <1>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+
|
|
+ pcsuniphy0_ch2: uniphy-ch@2 {
|
|
+ reg = <2>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+
|
|
+ pcsuniphy0_ch3: uniphy-ch@3 {
|
|
+ reg = <3>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcsuniphy1: ethernet-uniphy@7a10000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "qcom,ipq9574-uniphy";
|
|
+ reg = <0x7a10000 0x10000>;
|
|
+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
|
|
+ <&gcc GCC_UNIPHY1_AHB_CLK>;
|
|
+ clock-names = "sys",
|
|
+ "ahb";
|
|
+ resets = <&gcc GCC_UNIPHY1_SYS_RESET>,
|
|
+ <&gcc GCC_UNIPHY1_AHB_RESET>,
|
|
+ <&gcc GCC_UNIPHY1_XPCS_RESET>;
|
|
+ reset-names = "sys",
|
|
+ "ahb",
|
|
+ "xpcs";
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "uniphy1_nss_rx_clk",
|
|
+ "uniphy1_nss_tx_clk";
|
|
+
|
|
+ pcsuniphy1_ch0: uniphy-ch@0 {
|
|
+ reg = <0>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcsuniphy2: ethernet-uniphy@7a20000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "qcom,ipq9574-uniphy";
|
|
+ reg = <0x7a20000 0x10000>;
|
|
+ clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
|
|
+ <&gcc GCC_UNIPHY2_AHB_CLK>;
|
|
+ clock-names = "sys",
|
|
+ "ahb";
|
|
+ resets = <&gcc GCC_UNIPHY2_SYS_RESET>,
|
|
+ <&gcc GCC_UNIPHY2_AHB_RESET>,
|
|
+ <&gcc GCC_UNIPHY2_XPCS_RESET>;
|
|
+ reset-names = "sys",
|
|
+ "ahb",
|
|
+ "xpcs";
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "uniphy2_nss_rx_clk",
|
|
+ "uniphy2_nss_tx_clk";
|
|
+
|
|
+ pcsuniphy2_ch0: uniphy-ch@0 {
|
|
+ reg = <0>;
|
|
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>,
|
|
+ <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>;
|
|
+ clock-names = "ch_rx",
|
|
+ "ch_tx";
|
|
+ };
|
|
+ };
|
|
};
|
|
|
|
thermal-zones {
|