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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
171 lines
5.1 KiB
Diff
171 lines
5.1 KiB
Diff
From 172dc9a0d7704051c63407af6b39939c43801a99 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Fri, 1 Mar 2024 13:36:26 +0800
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Subject: [PATCH 34/50] net: ethernet: qualcomm: Add PPE port MAC address and
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EEE functions
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Add PPE port MAC address set and EEE set API functions which
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will be used by netdev ops and ethtool.
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Change-Id: Id2b3b06ae940b3b6f5227d927316329cdf3caeaa
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 75 ++++++++++++++++++++
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drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 3 +
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 29 ++++++++
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3 files changed, 107 insertions(+)
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
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@@ -462,6 +462,81 @@ void ppe_port_get_stats64(struct ppe_por
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}
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}
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+/**
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+ * ppe_port_set_mac_address() - Set PPE port MAC address
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+ * @ppe_port: PPE port
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+ * @addr: MAC address
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+ *
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+ * Description: Set MAC address for the given PPE port.
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+ *
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+ * Return: 0 upon success or a negative error upon failure.
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+ */
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+int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr)
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+{
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+ struct ppe_device *ppe_dev = ppe_port->ppe_dev;
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+ int port = ppe_port->port_id;
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+ u32 reg, val;
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+ int ret;
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+
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+ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) {
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+ reg = PPE_PORT_GMAC_ADDR(port);
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+ val = (addr[5] << 8) | addr[4];
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+ ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR0_ADDR, val);
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+ if (ret)
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+ return ret;
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+
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+ val = (addr[0] << 24) | (addr[1] << 16) |
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+ (addr[2] << 8) | addr[3];
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+ ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR1_ADDR, val);
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+ if (ret)
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+ return ret;
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+ } else {
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+ reg = PPE_PORT_XGMAC_ADDR(port);
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+ val = (addr[5] << 8) | addr[4] | XGMAC_ADDR_EN;
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+ ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_H_ADDR, val);
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+ if (ret)
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+ return ret;
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+
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+ val = (addr[3] << 24) | (addr[2] << 16) |
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+ (addr[1] << 8) | addr[0];
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+ ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_L_ADDR, val);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * ppe_port_set_mac_eee() - Set EEE configuration for PPE port MAC
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+ * @ppe_port: PPE port
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+ * @eee: EEE settings
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+ *
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+ * Description: Set port MAC EEE settings for the given PPE port.
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+ *
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+ * Return: 0 upon success or a negative error upon failure.
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+ */
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+int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee)
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+{
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+ struct ppe_device *ppe_dev = ppe_port->ppe_dev;
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+ int port = ppe_port->port_id;
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+ u32 val;
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+ int ret;
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+
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+ ret = regmap_read(ppe_dev->regmap, PPE_LPI_EN_ADDR, &val);
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+ if (ret)
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+ return ret;
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+
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+ if (eee->tx_lpi_enabled)
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+ val |= PPE_LPI_PORT_EN(port);
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+ else
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+ val &= ~PPE_LPI_PORT_EN(port);
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+
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+ ret = regmap_write(ppe_dev->regmap, PPE_LPI_EN_ADDR, val);
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+
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+ return ret;
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+}
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+
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/* PPE port and MAC reset */
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static int ppe_port_mac_reset(struct ppe_port *ppe_port)
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{
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
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@@ -8,6 +8,7 @@
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#include <linux/phylink.h>
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+struct ethtool_eee;
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struct rtnl_link_stats64;
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/**
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@@ -86,4 +87,6 @@ void ppe_port_get_strings(struct ppe_por
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void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data);
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void ppe_port_get_stats64(struct ppe_port *ppe_port,
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struct rtnl_link_stats64 *s);
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+int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr);
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+int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee);
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#endif
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -18,6 +18,16 @@
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#define PPE_PORT5_SEL_PCS1 BIT(4)
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#define PPE_PORT_SEL_XGMAC(x) (BIT(8) << ((x) - 1))
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+/* PPE port LPI enable register */
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+#define PPE_LPI_EN_ADDR 0x400
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+#define PPE_LPI_PORT1_EN BIT(0)
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+#define PPE_LPI_PORT2_EN BIT(1)
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+#define PPE_LPI_PORT3_EN BIT(2)
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+#define PPE_LPI_PORT4_EN BIT(3)
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+#define PPE_LPI_PORT5_EN BIT(4)
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+#define PPE_LPI_PORT6_EN BIT(5)
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+#define PPE_LPI_PORT_EN(x) (BIT(0) << ((x) - 1))
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+
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/* There are 15 BM ports and 4 BM groups supported by PPE,
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* BM port (0-7) is matched to EDMA port 0, BM port (8-13) is matched
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* to PPE physical port 1-6, BM port 14 is matched to EIP.
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@@ -580,6 +590,17 @@
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#define GMAC_SPEED_100 1
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#define GMAC_SPEED_1000 2
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+/* GMAC MAC address register */
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+#define GMAC_GOL_ADDR0_ADDR 0x8
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+#define GMAC_ADDR_BYTE5 GENMASK(15, 8)
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+#define GMAC_ADDR_BYTE4 GENMASK(7, 0)
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+
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+#define GMAC_GOL_ADDR1_ADDR 0xC
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+#define GMAC_ADDR_BYTE0 GENMASK(31, 24)
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+#define GMAC_ADDR_BYTE1 GENMASK(23, 16)
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+#define GMAC_ADDR_BYTE2 GENMASK(15, 8)
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+#define GMAC_ADDR_BYTE3 GENMASK(7, 0)
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+
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/* GMAC control register */
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#define GMAC_CTRL_ADDR 0x18
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#define GMAC_TX_THD_M GENMASK(27, 24)
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@@ -705,6 +726,14 @@
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#define XGMAC_RX_FLOW_CTRL_ADDR 0x90
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#define XGMAC_RXFCEN BIT(0)
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+/* XGMAC MAC address register */
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+#define XGMAC_ADDR0_H_ADDR 0x300
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+#define XGMAC_ADDR_EN BIT(31)
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+#define XGMAC_ADDRH GENMASK(15, 0)
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+
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+#define XGMAC_ADDR0_L_ADDR 0x304
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+#define XGMAC_ADDRL GENMASK(31, 0)
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+
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/* XGMAC management counters control register */
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#define XGMAC_MMC_CTRL_ADDR 0x800
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#define XGMAC_MCF BIT(3)
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